2 * INCA-IP internal switch ethernet driver.
4 * (C) Copyright 2003-2004
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/inca-ip.h>
32 #include <asm/addrspace.h>
35 #define NUM_RX_DESC PKTBUFSRX
37 #define TOUT_LOOP 1000000
40 #define DELAY udelay(10000)
41 /* Sometimes the store word instruction hangs while writing to one
42 * of the Switch registers. Moving the instruction into a separate
43 * function somehow makes the problem go away.
45 static void SWORD(volatile u32 * reg, u32 value)
50 #define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value;
51 #define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
52 #define SW_WRITE_REG(reg, value) \
57 #define SW_READ_REG(reg, value) \
58 value = (u32)*((volatile u32*)reg);\
60 value = (u32)*((volatile u32*)reg);
62 #define INCA_DMA_TX_POLLING_TIME 0x07
63 #define INCA_DMA_RX_POLLING_TIME 0x07
65 #define INCA_DMA_TX_HOLD 0x80000000
66 #define INCA_DMA_TX_EOP 0x40000000
67 #define INCA_DMA_TX_SOP 0x20000000
68 #define INCA_DMA_TX_ICPT 0x10000000
69 #define INCA_DMA_TX_IEOP 0x08000000
71 #define INCA_DMA_RX_C 0x80000000
72 #define INCA_DMA_RX_SOP 0x40000000
73 #define INCA_DMA_RX_EOP 0x20000000
75 #define INCA_SWITCH_PHY_SPEED_10H 0x1
76 #define INCA_SWITCH_PHY_SPEED_10F 0x5
77 #define INCA_SWITCH_PHY_SPEED_100H 0x2
78 #define INCA_SWITCH_PHY_SPEED_100F 0x6
80 /************************ Auto MDIX settings ************************/
81 #define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR
82 #define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL
83 #define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT
84 #define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16
86 #define WAIT_SIGNAL_RETRIES 100
87 #define WAIT_LINK_RETRIES 100
88 #define LINK_RETRY_DELAY 2000 /* ms */
89 /********************************************************************/
98 volatile u32 offset :3;
99 volatile u32 reserved0 :4;
100 volatile u32 NFB :22;
106 volatile u32 nextRxDescPtr;
108 volatile u32 RxDataPtr;
115 volatile u32 reserved3 :12;
116 volatile u32 NBT :17;
122 } inca_rx_descriptor_t;
129 volatile u32 HOLD :1;
132 volatile u32 ICpt :1;
133 volatile u32 IEop :1;
134 volatile u32 reserved0 :5;
135 volatile u32 NBA :22;
141 volatile u32 nextTxDescPtr;
143 volatile u32 TxDataPtr;
146 volatile u32 reserved3 :31;
148 } inca_tx_descriptor_t;
151 static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16)));
152 static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16)));
154 static int tx_new, rx_new, tx_hold, rx_hold;
155 static int tx_old_hold = -1;
156 static int initialized = 0;
159 static int inca_switch_init(struct eth_device *dev, bd_t * bis);
160 static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length);
161 static int inca_switch_recv(struct eth_device *dev);
162 static void inca_switch_halt(struct eth_device *dev);
163 static void inca_init_switch_chip(void);
164 static void inca_dma_init(void);
165 static int inca_amdix(void);
168 int inca_switch_initialize(bd_t * bis)
170 struct eth_device *dev;
173 printf("Entered inca_switch_initialize()\n");
176 if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
177 printf("Failed to allocate memory\n");
180 memset(dev, 0, sizeof(*dev));
184 inca_init_switch_chip();
186 #if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
190 sprintf(dev->name, "INCA-IP Switch");
191 dev->init = inca_switch_init;
192 dev->halt = inca_switch_halt;
193 dev->send = inca_switch_send;
194 dev->recv = inca_switch_recv;
199 printf("Leaving inca_switch_initialize()\n");
206 static int inca_switch_init(struct eth_device *dev, bd_t * bis)
213 printf("Entering inca_switch_init()\n");
218 wTmp = (u16)dev->enetaddr[0];
219 regValue = (wTmp << 8) | dev->enetaddr[1];
221 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue);
223 wTmp = (u16)dev->enetaddr[2];
224 regValue = (wTmp << 8) | dev->enetaddr[3];
225 regValue = regValue << 16;
226 wTmp = (u16)dev->enetaddr[4];
227 regValue |= (wTmp<<8) | dev->enetaddr[5];
229 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue);
231 /* Initialize the descriptor rings.
233 for (i = 0; i < NUM_RX_DESC; i++) {
234 inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]);
235 memset(rx_desc, 0, sizeof(rx_ring[i]));
237 /* Set maximum size of receive buffer.
239 rx_desc->params.field.NFB = PKTSIZE_ALIGN;
241 /* Set the offset of the receive buffer. Zero means
242 * that the offset mechanism is not used.
244 rx_desc->params.field.offset = 0;
246 /* Check if it is the last descriptor.
248 if (i == (NUM_RX_DESC - 1)) {
249 /* Let the last descriptor point to the first
252 rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring);
254 /* Set the address of the next descriptor.
256 rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]);
259 rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]);
263 printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]);
264 printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]);
267 for (i = 0; i < NUM_TX_DESC; i++) {
268 inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]);
270 memset(tx_desc, 0, sizeof(tx_ring[i]));
272 tx_desc->params.word = 0;
273 tx_desc->params.field.HOLD = 1;
276 /* Check if it is the last descriptor.
278 if (i == (NUM_TX_DESC - 1)) {
279 /* Let the last descriptor point to the
282 tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring);
284 /* Set the address of the next descriptor.
286 tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]);
292 DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
294 printf("RX status = 0x%08X\n", v);
297 /* Writing to the FRDA of CHANNEL.
299 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring);
301 /* Writing to the COMMAND REG.
303 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT);
307 DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
309 printf("TX status = 0x%08X\n", v);
312 /* Writing to the FRDA of CHANNEL.
314 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring);
318 tx_hold = NUM_TX_DESC - 1;
319 rx_hold = NUM_RX_DESC - 1;
322 rx_ring[rx_hold].params.field.HOLD = 1;
324 /* enable spanning tree forwarding, enable the CPU port */
326 * CPS (CPU port status) 0x3 (forwarding)
327 * LPS (LAN port status) 0x3 (forwarding)
328 * PPS (PC port status) 0x3 (forwarding)
330 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
333 printf("Leaving inca_switch_init()\n");
340 static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length)
346 inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]);
349 printf("Entered inca_switch_send()\n");
353 printf ("%s: bad packet size: %d\n", dev->name, length);
357 for(i = 0; tx_desc->C == 0; i++) {
358 if (i >= TOUT_LOOP) {
359 printf("%s: tx error buffer not ready\n", dev->name);
364 if (tx_old_hold >= 0) {
365 ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1;
367 tx_old_hold = tx_hold;
369 tx_desc->params.word =
370 (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD);
373 tx_desc->TxDataPtr = (u32)packet;
374 tx_desc->params.field.NBA = length;
376 ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0;
379 tx_new = (tx_new + 1) % NUM_TX_DESC;
383 command = INCA_IP_DMA_DMA_TXCCR0_INIT;
386 command = INCA_IP_DMA_DMA_TXCCR0_HR;
389 DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
392 printf("regValue = 0x%x\n", regValue);
394 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
397 for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) {
398 if (i >= TOUT_LOOP) {
399 printf("%s: tx buffer not ready\n", dev->name);
407 printf("Leaving inca_switch_send()\n");
413 static int inca_switch_recv(struct eth_device *dev)
416 inca_rx_descriptor_t * rx_desc;
419 printf("Entered inca_switch_recv()\n");
423 rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]);
425 if (rx_desc->status.field.C == 0) {
430 rx_ring[rx_new].params.field.HOLD = 1;
433 if (! rx_desc->status.field.Eop) {
434 printf("Partly received packet!!!\n");
438 length = rx_desc->status.field.NBT;
439 rx_desc->status.word &=
440 ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C);
444 for (i=0;i<length - 4;i++) {
445 if (i % 16 == 0) printf("\n%04x: ", i);
446 printf("%02X ", NetRxPackets[rx_new][i]);
454 printf("Received %d bytes\n", length);
456 NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4);
459 printf("Zero length!!!\n");
464 ((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0;
468 rx_new = (rx_new + 1) % NUM_RX_DESC;
472 printf("Leaving inca_switch_recv()\n");
479 static void inca_switch_halt(struct eth_device *dev)
482 printf("Entered inca_switch_halt()\n");
489 /* Disable forwarding to the CPU port.
491 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
493 /* Close RxDMA channel.
495 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
497 /* Close TxDMA channel.
499 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF);
504 printf("Leaving inca_switch_halt()\n");
509 static void inca_init_switch_chip(void)
513 /* To workaround a problem with collision counter
514 * (see Errata sheet).
516 SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
517 SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
520 /* init MDIO configuration:
521 * MDS (Poll speed): 0x01 (4ms)
524 * UEP (Use External PHY): 0x00 (Internal PHY is used)
525 * PS (Port Select): 0x00 (PT/UMM for LAN)
526 * PT (PHY Test): 0x00 (no test mode)
527 * UMM (Use MDIO Mode): 0x00 (state machine is disabled)
529 SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
532 * SL (Auto Neg. Speed for LAN)
533 * SP (Auto Neg. Speed for PC)
534 * LL (Link Status for LAN)
535 * LP (Link Status for PC)
536 * DL (Duplex Status for LAN)
537 * DP (Duplex Status for PC)
538 * PL (Auto Neg. Pause Status for LAN)
539 * PP (Auto Neg. Pause Status for PC)
541 SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
544 * RA (Request/Ack) 0x01 (Request)
545 * RW (Read/Write) 0x01 (Write)
547 * REG_ADDR 0x00 (PHY_BCR: basic control register)
549 * Reset - software reset
550 * LB (loop back) - normal
551 * SS (speed select) - 10 Mbit/s
552 * ANE (auto neg. enable) - enable
553 * PD (power down) - normal
554 * ISO (isolate) - normal
555 * RAN (restart auto neg.) - normal
556 * DM (duplex mode) - half duplex
557 * CT (collision test) - enable
559 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
562 * RA (Request/Ack) 0x01 (Request)
563 * RW (Read/Write) 0x01 (Write)
564 * PHY_ADDR 0x06 (LAN)
565 * REG_ADDR 0x00 (PHY_BCR: basic control register)
567 * Reset - software reset
568 * LB (loop back) - normal
569 * SS (speed select) - 10 Mbit/s
570 * ANE (auto neg. enable) - enable
571 * PD (power down) - normal
572 * ISO (isolate) - normal
573 * RAN (restart auto neg.) - normal
574 * DM (duplex mode) - half duplex
575 * CT (collision test) - enable
577 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
581 /* Make sure the CPU port is disabled for now. We
582 * don't want packets to get stacked for us until
583 * we enable DMA and are prepared to receive them.
585 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
587 SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
589 /* CRC GEN is enabled.
591 regValue |= 0x00000200;
592 SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
594 /* ADD TAG is disabled.
596 SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
597 regValue &= ~0x00000002;
598 SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
602 static void inca_dma_init(void)
604 /* Switch off all DMA channels.
606 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
607 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF);
609 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
610 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF);
611 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF);
613 /* Setup TX channel polling time.
615 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME);
617 /* Setup RX channel polling time.
619 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME);
621 /* ERRATA: write reset value into the DMA RX IMR register.
623 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF);
625 /* Just in case: disable all transmit interrupts also.
627 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF);
629 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF);
630 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF);
633 #if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
634 static int inca_amdix(void)
647 *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
648 *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
653 retries = WAIT_SIGNAL_RETRIES;
655 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
656 (0x1 << 31) | /* RA */
657 (0x0 << 30) | /* Read */
658 (0x6 << 21) | /* LAN */
659 (17 << 16)); /* PHY_MCSR */
661 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
662 } while (phyReg1 & (1 << 31));
664 if (phyReg1 & (1 << 1)) {
665 /* Signal detected */
676 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
681 retries = WAIT_LINK_RETRIES;
683 udelay(LINK_RETRY_DELAY * 1000);
684 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
685 (0x1 << 31) | /* RA */
686 (0x0 << 30) | /* Read */
687 (0x6 << 21) | /* LAN */
688 (1 << 16)); /* PHY_BSR */
690 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
691 } while (phyReg1 & (1 << 31));
693 if (phyReg1 & (1 << 2)) {
696 } else if (mdi_flag) {
698 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
702 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
710 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
711 (0x1 << 31) | /* RA */
712 (0x0 << 30) | /* Read */
713 (0x6 << 21) | /* LAN */
714 (1 << 16)); /* PHY_BSR */
716 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
717 } while (phyReg1 & (1 << 31));
719 /* Auto-negotiation / Parallel detection complete
721 if (phyReg1 & (1 << 5)) {
722 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
723 (0x1 << 31) | /* RA */
724 (0x0 << 30) | /* Read */
725 (0x6 << 21) | /* LAN */
726 (31 << 16)); /* PHY_SCSR */
728 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31);
729 } while (phyReg31 & (1 << 31));
731 switch ((phyReg31 >> 2) & 0x7) {
732 case INCA_SWITCH_PHY_SPEED_10H:
733 /* 10Base-T Half-duplex */
736 case INCA_SWITCH_PHY_SPEED_10F:
737 /* 10Base-T Full-duplex */
738 regEphy = INCA_IP_Switch_EPHY_DL;
740 case INCA_SWITCH_PHY_SPEED_100H:
741 /* 100Base-TX Half-duplex */
742 regEphy = INCA_IP_Switch_EPHY_SL;
744 case INCA_SWITCH_PHY_SPEED_100F:
745 /* 100Base-TX Full-duplex */
746 regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL;
750 /* In case of Auto-negotiation,
751 * update the negotiated PAUSE support status
753 if (phyReg1 & (1 << 3)) {
754 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
755 (0x1 << 31) | /* RA */
756 (0x0 << 30) | /* Read */
757 (0x6 << 21) | /* LAN */
758 (6 << 16)); /* PHY_ANER */
760 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
761 } while (phyReg6 & (1 << 31));
763 /* We are Autoneg-able.
764 * Is Link partner also able to autoneg?
766 if (phyReg6 & (1 << 0)) {
767 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
768 (0x1 << 31) | /* RA */
769 (0x0 << 30) | /* Read */
770 (0x6 << 21) | /* LAN */
771 (4 << 16)); /* PHY_ANAR */
773 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
774 } while (phyReg4 & (1 << 31));
776 /* We advertise PAUSE capab.
777 * Does link partner also advertise it?
779 if (phyReg4 & (1 << 10)) {
780 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
781 (0x1 << 31) | /* RA */
782 (0x0 << 30) | /* Read */
783 (0x6 << 21) | /* LAN */
784 (5 << 16)); /* PHY_ANLPAR */
786 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
787 } while (phyReg5 & (1 << 31));
789 /* Link partner is PAUSE capab.
791 if (phyReg5 & (1 << 10)) {
792 regEphy |= INCA_IP_Switch_EPHY_PL;
800 regEphy |= INCA_IP_Switch_EPHY_LL;
802 SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy);
809 printf("No Link on LAN port\n");
812 #endif /* CONFIG_INCA_IP_SWITCH_AMDIX */