drivers/net/higmacv300.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019, Linaro Limited
   4  */
   5
   6 #include <cpu_func.h>
   7 #include <malloc.h>
   8 #include <asm/cache.h>
   9 #include <asm/io.h>
  10 #include <common.h>
  11 #include <console.h>
  12 #include <linux/bug.h>
  13 #include <linux/mii.h>
  14 #include <miiphy.h>
  15 #include <net.h>
  16 #include <reset.h>
  17 #include <wait_bit.h>
  18
  19 #define STATION_ADDR_LOW                0x0000
  20 #define STATION_ADDR_HIGH               0x0004
  21 #define MAC_DUPLEX_HALF_CTRL            0x0008
  22 #define PORT_MODE                       0x0040
  23 #define PORT_EN                         0x0044
  24 #define BIT_TX_EN                       BIT(2)
  25 #define BIT_RX_EN                       BIT(1)
  26 #define MODE_CHANGE_EN                  0x01b4
  27 #define BIT_MODE_CHANGE_EN              BIT(0)
  28 #define MDIO_SINGLE_CMD                 0x03c0
  29 #define BIT_MDIO_BUSY                   BIT(20)
  30 #define MDIO_READ                       (BIT(17) | BIT_MDIO_BUSY)
  31 #define MDIO_WRITE                      (BIT(16) | BIT_MDIO_BUSY)
  32 #define MDIO_SINGLE_DATA                0x03c4
  33 #define MDIO_RDATA_STATUS               0x03d0
  34 #define BIT_MDIO_RDATA_INVALID          BIT(0)
  35 #define RX_FQ_START_ADDR                0x0500
  36 #define RX_FQ_DEPTH                     0x0504
  37 #define RX_FQ_WR_ADDR                   0x0508
  38 #define RX_FQ_RD_ADDR                   0x050c
  39 #define RX_FQ_REG_EN                    0x0518
  40 #define RX_BQ_START_ADDR                0x0520
  41 #define RX_BQ_DEPTH                     0x0524
  42 #define RX_BQ_WR_ADDR                   0x0528
  43 #define RX_BQ_RD_ADDR                   0x052c
  44 #define RX_BQ_REG_EN                    0x0538
  45 #define TX_BQ_START_ADDR                0x0580
  46 #define TX_BQ_DEPTH                     0x0584
  47 #define TX_BQ_WR_ADDR                   0x0588
  48 #define TX_BQ_RD_ADDR                   0x058c
  49 #define TX_BQ_REG_EN                    0x0598
  50 #define TX_RQ_START_ADDR                0x05a0
  51 #define TX_RQ_DEPTH                     0x05a4
  52 #define TX_RQ_WR_ADDR                   0x05a8
  53 #define TX_RQ_RD_ADDR                   0x05ac
  54 #define TX_RQ_REG_EN                    0x05b8
  55 #define BIT_START_ADDR_EN               BIT(2)
  56 #define BIT_DEPTH_EN                    BIT(1)
  57 #define DESC_WR_RD_ENA                  0x05cc
  58 #define BIT_RX_OUTCFF_WR                BIT(3)
  59 #define BIT_RX_CFF_RD                   BIT(2)
  60 #define BIT_TX_OUTCFF_WR                BIT(1)
  61 #define BIT_TX_CFF_RD                   BIT(0)
  62 #define BITS_DESC_ENA                   (BIT_RX_OUTCFF_WR | BIT_RX_CFF_RD | \
  63                                          BIT_TX_OUTCFF_WR | BIT_TX_CFF_RD)
  64
  65 /* MACIF_CTRL */
  66 #define RGMII_SPEED_1000                0x2c
  67 #define RGMII_SPEED_100                 0x2f
  68 #define RGMII_SPEED_10                  0x2d
  69 #define MII_SPEED_100                   0x0f
  70 #define MII_SPEED_10                    0x0d
  71 #define GMAC_SPEED_1000                 0x05
  72 #define GMAC_SPEED_100                  0x01
  73 #define GMAC_SPEED_10                   0x00
  74 #define GMAC_FULL_DUPLEX                BIT(4)
  75
  76 #define RX_DESC_NUM                     64
  77 #define TX_DESC_NUM                     2
  78 #define DESC_SIZE                       32
  79 #define DESC_WORD_SHIFT                 3
  80 #define DESC_BYTE_SHIFT                 5
  81 #define DESC_CNT(n)                     ((n) >> DESC_BYTE_SHIFT)
  82 #define DESC_BYTE(n)                    ((n) << DESC_BYTE_SHIFT)
  83 #define DESC_VLD_FREE                   0
  84 #define DESC_VLD_BUSY                   1
  85
  86 #define MAC_MAX_FRAME_SIZE              1600
  87
  88 enum higmac_queue {
  89         RX_FQ,
  90         RX_BQ,
  91         TX_BQ,
  92         TX_RQ,
  93 };
  94
  95 struct higmac_desc {
  96         unsigned int buf_addr;
  97         unsigned int buf_len:11;
  98         unsigned int reserve0:5;
  99         unsigned int data_len:11;
 100         unsigned int reserve1:2;
 101         unsigned int fl:2;
 102         unsigned int descvid:1;
 103         unsigned int reserve2[6];
 104 };
 105
 106 struct higmac_priv {
 107         void __iomem *base;
 108         void __iomem *macif_ctrl;
 109         struct reset_ctl rst_phy;
 110         struct higmac_desc *rxfq;
 111         struct higmac_desc *rxbq;
 112         struct higmac_desc *txbq;
 113         struct higmac_desc *txrq;
 114         int rxdesc_in_use;
 115         struct mii_dev *bus;
 116         struct phy_device *phydev;
 117         int phyintf;
 118         int phyaddr;
 119 };
 120
 121 #define flush_desc(d) flush_cache((unsigned long)(d), sizeof(*(d)))
 122 #define invalidate_desc(d) \
 123         invalidate_dcache_range((unsigned long)(d), \
 124                                 (unsigned long)(d) + sizeof(*(d)))
 125
 126 static int higmac_write_hwaddr(struct udevice *dev)
 127 {
 128         struct eth_pdata *pdata = dev_get_platdata(dev);
 129         struct higmac_priv *priv = dev_get_priv(dev);
 130         unsigned char *mac = pdata->enetaddr;
 131         u32 val;
 132
 133         val = mac[1] | (mac[0] << 8);
 134         writel(val, priv->base + STATION_ADDR_HIGH);
 135
 136         val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
 137         writel(val, priv->base + STATION_ADDR_LOW);
 138
 139         return 0;
 140 }
 141
 142 static int higmac_free_pkt(struct udevice *dev, uchar *packet, int length)
 143 {
 144         struct higmac_priv *priv = dev_get_priv(dev);
 145
 146         /* Inform GMAC that the RX descriptor is no longer in use */
 147         writel(DESC_BYTE(priv->rxdesc_in_use), priv->base + RX_BQ_RD_ADDR);
 148
 149         return 0;
 150 }
 151
 152 static int higmac_recv(struct udevice *dev, int flags, uchar **packetp)
 153 {
 154         struct higmac_priv *priv = dev_get_priv(dev);
 155         struct higmac_desc *fqd = priv->rxfq;
 156         struct higmac_desc *bqd = priv->rxbq;
 157         int fqw_pos, fqr_pos, bqw_pos, bqr_pos;
 158         int timeout = 100000;
 159         int len = 0;
 160         int space;
 161         int i;
 162
 163         fqw_pos = DESC_CNT(readl(priv->base + RX_FQ_WR_ADDR));
 164         fqr_pos = DESC_CNT(readl(priv->base + RX_FQ_RD_ADDR));
 165
 166         if (fqw_pos >= fqr_pos)
 167                 space = RX_DESC_NUM - (fqw_pos - fqr_pos);
 168         else
 169                 space = fqr_pos - fqw_pos;
 170
 171         /* Leave one free to distinguish full filled from empty buffer */
 172         for (i = 0; i < space - 1; i++) {
 173                 fqd = priv->rxfq + fqw_pos;
 174                 invalidate_dcache_range(fqd->buf_addr,
 175                                         fqd->buf_addr + MAC_MAX_FRAME_SIZE);
 176
 177                 if (++fqw_pos >= RX_DESC_NUM)
 178                         fqw_pos = 0;
 179
 180                 writel(DESC_BYTE(fqw_pos), priv->base + RX_FQ_WR_ADDR);
 181         }
 182
 183         bqr_pos = DESC_CNT(readl(priv->base + RX_BQ_RD_ADDR));
 184         bqd += bqr_pos;
 185         /* BQ is only ever written by GMAC */
 186         invalidate_desc(bqd);
 187
 188         do {
 189                 bqw_pos = DESC_CNT(readl(priv->base + RX_BQ_WR_ADDR));
 190                 udelay(1);
 191         } while (--timeout && bqw_pos == bqr_pos);
 192
 193         if (!timeout)
 194                 return -ETIMEDOUT;
 195
 196         if (++bqr_pos >= RX_DESC_NUM)
 197                 bqr_pos = 0;
 198
 199         len = bqd->data_len;
 200
 201         /* CPU should not have touched this buffer since we added it to FQ */
 202         invalidate_dcache_range(bqd->buf_addr, bqd->buf_addr + len);
 203         *packetp = (void *)(unsigned long)bqd->buf_addr;
 204
 205         /* Record the RX_BQ descriptor that is holding RX data */
 206         priv->rxdesc_in_use = bqr_pos;
 207
 208         return len;
 209 }
 210
 211 static int higmac_send(struct udevice *dev, void *packet, int length)
 212 {
 213         struct higmac_priv *priv = dev_get_priv(dev);
 214         struct higmac_desc *bqd = priv->txbq;
 215         int bqw_pos, rqw_pos, rqr_pos;
 216         int timeout = 1000;
 217
 218         flush_cache((unsigned long)packet, length);
 219
 220         bqw_pos = DESC_CNT(readl(priv->base + TX_BQ_WR_ADDR));
 221         bqd += bqw_pos;
 222         bqd->buf_addr = (unsigned long)packet;
 223         bqd->descvid = DESC_VLD_BUSY;
 224         bqd->data_len = length;
 225         flush_desc(bqd);
 226
 227         if (++bqw_pos >= TX_DESC_NUM)
 228                 bqw_pos = 0;
 229
 230         writel(DESC_BYTE(bqw_pos), priv->base + TX_BQ_WR_ADDR);
 231
 232         rqr_pos = DESC_CNT(readl(priv->base + TX_RQ_RD_ADDR));
 233         if (++rqr_pos >= TX_DESC_NUM)
 234                 rqr_pos = 0;
 235
 236         do {
 237                 rqw_pos = DESC_CNT(readl(priv->base + TX_RQ_WR_ADDR));
 238                 udelay(1);
 239         } while (--timeout && rqr_pos != rqw_pos);
 240
 241         if (!timeout)
 242                 return -ETIMEDOUT;
 243
 244         writel(DESC_BYTE(rqr_pos), priv->base + TX_RQ_RD_ADDR);
 245
 246         return 0;
 247 }
 248
 249 static int higmac_adjust_link(struct higmac_priv *priv)
 250 {
 251         struct phy_device *phydev = priv->phydev;
 252         int interface = priv->phyintf;
 253         u32 val;
 254
 255         switch (interface) {
 256         case PHY_INTERFACE_MODE_RGMII:
 257                 if (phydev->speed == SPEED_1000)
 258                         val = RGMII_SPEED_1000;
 259                 else if (phydev->speed == SPEED_100)
 260                         val = RGMII_SPEED_100;
 261                 else
 262                         val = RGMII_SPEED_10;
 263                 break;
 264         case PHY_INTERFACE_MODE_MII:
 265                 if (phydev->speed == SPEED_100)
 266                         val = MII_SPEED_100;
 267                 else
 268                         val = MII_SPEED_10;
 269                 break;
 270         default:
 271                 debug("unsupported mode: %d\n", interface);
 272                 return -EINVAL;
 273         }
 274
 275         if (phydev->duplex)
 276                 val |= GMAC_FULL_DUPLEX;
 277
 278         writel(val, priv->macif_ctrl);
 279
 280         if (phydev->speed == SPEED_1000)
 281                 val = GMAC_SPEED_1000;
 282         else if (phydev->speed == SPEED_100)
 283                 val = GMAC_SPEED_100;
 284         else
 285                 val = GMAC_SPEED_10;
 286
 287         writel(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
 288         writel(val, priv->base + PORT_MODE);
 289         writel(0, priv->base + MODE_CHANGE_EN);
 290         writel(phydev->duplex, priv->base + MAC_DUPLEX_HALF_CTRL);
 291
 292         return 0;
 293 }
 294
 295 static int higmac_start(struct udevice *dev)
 296 {
 297         struct higmac_priv *priv = dev_get_priv(dev);
 298         struct phy_device *phydev = priv->phydev;
 299         int ret;
 300
 301         ret = phy_startup(phydev);
 302         if (ret)
 303                 return ret;
 304
 305         if (!phydev->link) {
 306                 debug("%s: link down\n", phydev->dev->name);
 307                 return -ENODEV;
 308         }
 309
 310         ret = higmac_adjust_link(priv);
 311         if (ret)
 312                 return ret;
 313
 314         /* Enable port */
 315         writel(BITS_DESC_ENA, priv->base + DESC_WR_RD_ENA);
 316         writel(BIT_TX_EN | BIT_RX_EN, priv->base + PORT_EN);
 317
 318         return 0;
 319 }
 320
 321 static void higmac_stop(struct udevice *dev)
 322 {
 323         struct higmac_priv *priv = dev_get_priv(dev);
 324
 325         /* Disable port */
 326         writel(0, priv->base + PORT_EN);
 327         writel(0, priv->base + DESC_WR_RD_ENA);
 328 }
 329
 330 static const struct eth_ops higmac_ops = {
 331         .start          = higmac_start,
 332         .send           = higmac_send,
 333         .recv           = higmac_recv,
 334         .free_pkt       = higmac_free_pkt,
 335         .stop           = higmac_stop,
 336         .write_hwaddr   = higmac_write_hwaddr,
 337 };
 338
 339 static int higmac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 340 {
 341         struct higmac_priv *priv = bus->priv;
 342         int ret;
 343
 344         ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
 345                                 false, 1000, false);
 346         if (ret)
 347                 return ret;
 348
 349         writel(MDIO_READ | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
 350
 351         ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
 352                                 false, 1000, false);
 353         if (ret)
 354                 return ret;
 355
 356         if (readl(priv->base + MDIO_RDATA_STATUS) & BIT_MDIO_RDATA_INVALID)
 357                 return -EINVAL;
 358
 359         return readl(priv->base + MDIO_SINGLE_DATA) >> 16;
 360 }
 361
 362 static int higmac_mdio_write(struct mii_dev *bus, int addr, int devad,
 363                              int reg, u16 value)
 364 {
 365         struct higmac_priv *priv = bus->priv;
 366         int ret;
 367
 368         ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
 369                                 false, 1000, false);
 370         if (ret)
 371                 return ret;
 372
 373         writel(value, priv->base + MDIO_SINGLE_DATA);
 374         writel(MDIO_WRITE | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
 375
 376         return 0;
 377 }
 378
 379 static int higmac_init_rx_descs(struct higmac_desc *descs, int num)
 380 {
 381         int i;
 382
 383         for (i = 0; i < num; i++) {
 384                 struct higmac_desc *desc = &descs[i];
 385
 386                 desc->buf_addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
 387                                                          MAC_MAX_FRAME_SIZE);
 388                 if (!desc->buf_addr)
 389                         goto free_bufs;
 390
 391                 desc->descvid = DESC_VLD_FREE;
 392                 desc->buf_len = MAC_MAX_FRAME_SIZE - 1;
 393                 flush_desc(desc);
 394         }
 395
 396         return 0;
 397
 398 free_bufs:
 399         while (--i > 0)
 400                 free((void *)(unsigned long)descs[i].buf_addr);
 401         return -ENOMEM;
 402 }
 403
 404 static int higmac_init_hw_queue(struct higmac_priv *priv,
 405                                 enum higmac_queue queue)
 406 {
 407         struct higmac_desc *desc, **pdesc;
 408         u32 regaddr, regen, regdep;
 409         int depth;
 410         int len;
 411
 412         switch (queue) {
 413         case RX_FQ:
 414                 regaddr = RX_FQ_START_ADDR;
 415                 regen = RX_FQ_REG_EN;
 416                 regdep = RX_FQ_DEPTH;
 417                 depth = RX_DESC_NUM;
 418                 pdesc = &priv->rxfq;
 419                 break;
 420         case RX_BQ:
 421                 regaddr = RX_BQ_START_ADDR;
 422                 regen = RX_BQ_REG_EN;
 423                 regdep = RX_BQ_DEPTH;
 424                 depth = RX_DESC_NUM;
 425                 pdesc = &priv->rxbq;
 426                 break;
 427         case TX_BQ:
 428                 regaddr = TX_BQ_START_ADDR;
 429                 regen = TX_BQ_REG_EN;
 430                 regdep = TX_BQ_DEPTH;
 431                 depth = TX_DESC_NUM;
 432                 pdesc = &priv->txbq;
 433                 break;
 434         case TX_RQ:
 435                 regaddr = TX_RQ_START_ADDR;
 436                 regen = TX_RQ_REG_EN;
 437                 regdep = TX_RQ_DEPTH;
 438                 depth = TX_DESC_NUM;
 439                 pdesc = &priv->txrq;
 440                 break;
 441         }
 442
 443         /* Enable depth */
 444         writel(BIT_DEPTH_EN, priv->base + regen);
 445         writel(depth << DESC_WORD_SHIFT, priv->base + regdep);
 446         writel(0, priv->base + regen);
 447
 448         len = depth * sizeof(*desc);
 449         desc = memalign(ARCH_DMA_MINALIGN, len);
 450         if (!desc)
 451                 return -ENOMEM;
 452         memset(desc, 0, len);
 453         flush_cache((unsigned long)desc, len);
 454         *pdesc = desc;
 455
 456         /* Set up RX_FQ descriptors */
 457         if (queue == RX_FQ)
 458                 higmac_init_rx_descs(desc, depth);
 459
 460         /* Enable start address */
 461         writel(BIT_START_ADDR_EN, priv->base + regen);
 462         writel((unsigned long)desc, priv->base + regaddr);
 463         writel(0, priv->base + regen);
 464
 465         return 0;
 466 }
 467
 468 static int higmac_hw_init(struct higmac_priv *priv)
 469 {
 470         int ret;
 471
 472         /* Initialize hardware queues */
 473         ret = higmac_init_hw_queue(priv, RX_FQ);
 474         if (ret)
 475                 return ret;
 476
 477         ret = higmac_init_hw_queue(priv, RX_BQ);
 478         if (ret)
 479                 goto free_rx_fq;
 480
 481         ret = higmac_init_hw_queue(priv, TX_BQ);
 482         if (ret)
 483                 goto free_rx_bq;
 484
 485         ret = higmac_init_hw_queue(priv, TX_RQ);
 486         if (ret)
 487                 goto free_tx_bq;
 488
 489         /* Reset phy */
 490         reset_deassert(&priv->rst_phy);
 491         mdelay(10);
 492         reset_assert(&priv->rst_phy);
 493         mdelay(30);
 494         reset_deassert(&priv->rst_phy);
 495         mdelay(30);
 496
 497         return 0;
 498
 499 free_tx_bq:
 500         free(priv->txbq);
 501 free_rx_bq:
 502         free(priv->rxbq);
 503 free_rx_fq:
 504         free(priv->rxfq);
 505         return ret;
 506 }
 507
 508 static int higmac_probe(struct udevice *dev)
 509 {
 510         struct higmac_priv *priv = dev_get_priv(dev);
 511         struct phy_device *phydev;
 512         struct mii_dev *bus;
 513         int ret;
 514
 515         ret = higmac_hw_init(priv);
 516         if (ret)
 517                 return ret;
 518
 519         bus = mdio_alloc();
 520         if (!bus)
 521                 return -ENOMEM;
 522
 523         bus->read = higmac_mdio_read;
 524         bus->write = higmac_mdio_write;
 525         bus->priv = priv;
 526         priv->bus = bus;
 527
 528         ret = mdio_register_seq(bus, dev->seq);
 529         if (ret)
 530                 return ret;
 531
 532         phydev = phy_connect(bus, priv->phyaddr, dev, priv->phyintf);
 533         if (!phydev)
 534                 return -ENODEV;
 535
 536         phydev->supported &= PHY_GBIT_FEATURES;
 537         phydev->advertising = phydev->supported;
 538         priv->phydev = phydev;
 539
 540         return phy_config(phydev);
 541 }
 542
 543 static int higmac_remove(struct udevice *dev)
 544 {
 545         struct higmac_priv *priv = dev_get_priv(dev);
 546         int i;
 547
 548         mdio_unregister(priv->bus);
 549         mdio_free(priv->bus);
 550
 551         /* Free RX packet buffers */
 552         for (i = 0; i < RX_DESC_NUM; i++)
 553                 free((void *)(unsigned long)priv->rxfq[i].buf_addr);
 554
 555         return 0;
 556 }
 557
 558 static int higmac_ofdata_to_platdata(struct udevice *dev)
 559 {
 560         struct higmac_priv *priv = dev_get_priv(dev);
 561         int phyintf = PHY_INTERFACE_MODE_NONE;
 562         const char *phy_mode;
 563         ofnode phy_node;
 564
 565         priv->base = dev_remap_addr_index(dev, 0);
 566         priv->macif_ctrl = dev_remap_addr_index(dev, 1);
 567
 568         phy_mode = dev_read_string(dev, "phy-mode");
 569         if (phy_mode)
 570                 phyintf = phy_get_interface_by_name(phy_mode);
 571         if (phyintf == PHY_INTERFACE_MODE_NONE)
 572                 return -ENODEV;
 573         priv->phyintf = phyintf;
 574
 575         phy_node = dev_read_subnode(dev, "phy");
 576         if (!ofnode_valid(phy_node)) {
 577                 debug("failed to find phy node\n");
 578                 return -ENODEV;
 579         }
 580         priv->phyaddr = ofnode_read_u32_default(phy_node, "reg", 0);
 581
 582         return reset_get_by_name(dev, "phy", &priv->rst_phy);
 583 }
 584
 585 static const struct udevice_id higmac_ids[] = {
 586         { .compatible = "hisilicon,hi3798cv200-gmac" },
 587         { }
 588 };
 589
 590 U_BOOT_DRIVER(eth_higmac) = {
 591         .name   = "eth_higmac",
 592         .id     = UCLASS_ETH,
 593         .of_match = higmac_ids,
 594         .ofdata_to_platdata = higmac_ofdata_to_platdata,
 595         .probe  = higmac_probe,
 596         .remove = higmac_remove,
 597         .ops    = &higmac_ops,
 598         .priv_auto_alloc_size = sizeof(struct higmac_priv),
 599         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 600 };