1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2019, Linaro Limited
10 #include <linux/bug.h>
11 #include <linux/mii.h>
17 #define STATION_ADDR_LOW 0x0000
18 #define STATION_ADDR_HIGH 0x0004
19 #define MAC_DUPLEX_HALF_CTRL 0x0008
20 #define PORT_MODE 0x0040
21 #define PORT_EN 0x0044
22 #define BIT_TX_EN BIT(2)
23 #define BIT_RX_EN BIT(1)
24 #define MODE_CHANGE_EN 0x01b4
25 #define BIT_MODE_CHANGE_EN BIT(0)
26 #define MDIO_SINGLE_CMD 0x03c0
27 #define BIT_MDIO_BUSY BIT(20)
28 #define MDIO_READ (BIT(17) | BIT_MDIO_BUSY)
29 #define MDIO_WRITE (BIT(16) | BIT_MDIO_BUSY)
30 #define MDIO_SINGLE_DATA 0x03c4
31 #define MDIO_RDATA_STATUS 0x03d0
32 #define BIT_MDIO_RDATA_INVALID BIT(0)
33 #define RX_FQ_START_ADDR 0x0500
34 #define RX_FQ_DEPTH 0x0504
35 #define RX_FQ_WR_ADDR 0x0508
36 #define RX_FQ_RD_ADDR 0x050c
37 #define RX_FQ_REG_EN 0x0518
38 #define RX_BQ_START_ADDR 0x0520
39 #define RX_BQ_DEPTH 0x0524
40 #define RX_BQ_WR_ADDR 0x0528
41 #define RX_BQ_RD_ADDR 0x052c
42 #define RX_BQ_REG_EN 0x0538
43 #define TX_BQ_START_ADDR 0x0580
44 #define TX_BQ_DEPTH 0x0584
45 #define TX_BQ_WR_ADDR 0x0588
46 #define TX_BQ_RD_ADDR 0x058c
47 #define TX_BQ_REG_EN 0x0598
48 #define TX_RQ_START_ADDR 0x05a0
49 #define TX_RQ_DEPTH 0x05a4
50 #define TX_RQ_WR_ADDR 0x05a8
51 #define TX_RQ_RD_ADDR 0x05ac
52 #define TX_RQ_REG_EN 0x05b8
53 #define BIT_START_ADDR_EN BIT(2)
54 #define BIT_DEPTH_EN BIT(1)
55 #define DESC_WR_RD_ENA 0x05cc
56 #define BIT_RX_OUTCFF_WR BIT(3)
57 #define BIT_RX_CFF_RD BIT(2)
58 #define BIT_TX_OUTCFF_WR BIT(1)
59 #define BIT_TX_CFF_RD BIT(0)
60 #define BITS_DESC_ENA (BIT_RX_OUTCFF_WR | BIT_RX_CFF_RD | \
61 BIT_TX_OUTCFF_WR | BIT_TX_CFF_RD)
64 #define RGMII_SPEED_1000 0x2c
65 #define RGMII_SPEED_100 0x2f
66 #define RGMII_SPEED_10 0x2d
67 #define MII_SPEED_100 0x0f
68 #define MII_SPEED_10 0x0d
69 #define GMAC_SPEED_1000 0x05
70 #define GMAC_SPEED_100 0x01
71 #define GMAC_SPEED_10 0x00
72 #define GMAC_FULL_DUPLEX BIT(4)
74 #define RX_DESC_NUM 64
77 #define DESC_WORD_SHIFT 3
78 #define DESC_BYTE_SHIFT 5
79 #define DESC_CNT(n) ((n) >> DESC_BYTE_SHIFT)
80 #define DESC_BYTE(n) ((n) << DESC_BYTE_SHIFT)
81 #define DESC_VLD_FREE 0
82 #define DESC_VLD_BUSY 1
84 #define MAC_MAX_FRAME_SIZE 1600
94 unsigned int buf_addr;
95 unsigned int buf_len:11;
96 unsigned int reserve0:5;
97 unsigned int data_len:11;
98 unsigned int reserve1:2;
100 unsigned int descvid:1;
101 unsigned int reserve2[6];
106 void __iomem *macif_ctrl;
107 struct reset_ctl rst_phy;
108 struct higmac_desc *rxfq;
109 struct higmac_desc *rxbq;
110 struct higmac_desc *txbq;
111 struct higmac_desc *txrq;
114 struct phy_device *phydev;
119 #define flush_desc(d) flush_cache((unsigned long)(d), sizeof(*(d)))
120 #define invalidate_desc(d) \
121 invalidate_dcache_range((unsigned long)(d), \
122 (unsigned long)(d) + sizeof(*(d)))
124 static int higmac_write_hwaddr(struct udevice *dev)
126 struct eth_pdata *pdata = dev_get_platdata(dev);
127 struct higmac_priv *priv = dev_get_priv(dev);
128 unsigned char *mac = pdata->enetaddr;
131 val = mac[1] | (mac[0] << 8);
132 writel(val, priv->base + STATION_ADDR_HIGH);
134 val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
135 writel(val, priv->base + STATION_ADDR_LOW);
140 static int higmac_free_pkt(struct udevice *dev, uchar *packet, int length)
142 struct higmac_priv *priv = dev_get_priv(dev);
144 /* Inform GMAC that the RX descriptor is no longer in use */
145 writel(DESC_BYTE(priv->rxdesc_in_use), priv->base + RX_BQ_RD_ADDR);
150 static int higmac_recv(struct udevice *dev, int flags, uchar **packetp)
152 struct higmac_priv *priv = dev_get_priv(dev);
153 struct higmac_desc *fqd = priv->rxfq;
154 struct higmac_desc *bqd = priv->rxbq;
155 int fqw_pos, fqr_pos, bqw_pos, bqr_pos;
156 int timeout = 100000;
161 fqw_pos = DESC_CNT(readl(priv->base + RX_FQ_WR_ADDR));
162 fqr_pos = DESC_CNT(readl(priv->base + RX_FQ_RD_ADDR));
164 if (fqw_pos >= fqr_pos)
165 space = RX_DESC_NUM - (fqw_pos - fqr_pos);
167 space = fqr_pos - fqw_pos;
169 /* Leave one free to distinguish full filled from empty buffer */
170 for (i = 0; i < space - 1; i++) {
171 fqd = priv->rxfq + fqw_pos;
172 invalidate_dcache_range(fqd->buf_addr,
173 fqd->buf_addr + MAC_MAX_FRAME_SIZE);
175 if (++fqw_pos >= RX_DESC_NUM)
178 writel(DESC_BYTE(fqw_pos), priv->base + RX_FQ_WR_ADDR);
181 bqr_pos = DESC_CNT(readl(priv->base + RX_BQ_RD_ADDR));
183 /* BQ is only ever written by GMAC */
184 invalidate_desc(bqd);
187 bqw_pos = DESC_CNT(readl(priv->base + RX_BQ_WR_ADDR));
189 } while (--timeout && bqw_pos == bqr_pos);
194 if (++bqr_pos >= RX_DESC_NUM)
199 /* CPU should not have touched this buffer since we added it to FQ */
200 invalidate_dcache_range(bqd->buf_addr, bqd->buf_addr + len);
201 *packetp = (void *)(unsigned long)bqd->buf_addr;
203 /* Record the RX_BQ descriptor that is holding RX data */
204 priv->rxdesc_in_use = bqr_pos;
209 static int higmac_send(struct udevice *dev, void *packet, int length)
211 struct higmac_priv *priv = dev_get_priv(dev);
212 struct higmac_desc *bqd = priv->txbq;
213 int bqw_pos, rqw_pos, rqr_pos;
216 flush_cache((unsigned long)packet, length);
218 bqw_pos = DESC_CNT(readl(priv->base + TX_BQ_WR_ADDR));
220 bqd->buf_addr = (unsigned long)packet;
221 bqd->descvid = DESC_VLD_BUSY;
222 bqd->data_len = length;
225 if (++bqw_pos >= TX_DESC_NUM)
228 writel(DESC_BYTE(bqw_pos), priv->base + TX_BQ_WR_ADDR);
230 rqr_pos = DESC_CNT(readl(priv->base + TX_RQ_RD_ADDR));
231 if (++rqr_pos >= TX_DESC_NUM)
235 rqw_pos = DESC_CNT(readl(priv->base + TX_RQ_WR_ADDR));
237 } while (--timeout && rqr_pos != rqw_pos);
242 writel(DESC_BYTE(rqr_pos), priv->base + TX_RQ_RD_ADDR);
247 static int higmac_adjust_link(struct higmac_priv *priv)
249 struct phy_device *phydev = priv->phydev;
250 int interface = priv->phyintf;
254 case PHY_INTERFACE_MODE_RGMII:
255 if (phydev->speed == SPEED_1000)
256 val = RGMII_SPEED_1000;
257 else if (phydev->speed == SPEED_100)
258 val = RGMII_SPEED_100;
260 val = RGMII_SPEED_10;
262 case PHY_INTERFACE_MODE_MII:
263 if (phydev->speed == SPEED_100)
269 debug("unsupported mode: %d\n", interface);
274 val |= GMAC_FULL_DUPLEX;
276 writel(val, priv->macif_ctrl);
278 if (phydev->speed == SPEED_1000)
279 val = GMAC_SPEED_1000;
280 else if (phydev->speed == SPEED_100)
281 val = GMAC_SPEED_100;
285 writel(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
286 writel(val, priv->base + PORT_MODE);
287 writel(0, priv->base + MODE_CHANGE_EN);
288 writel(phydev->duplex, priv->base + MAC_DUPLEX_HALF_CTRL);
293 static int higmac_start(struct udevice *dev)
295 struct higmac_priv *priv = dev_get_priv(dev);
296 struct phy_device *phydev = priv->phydev;
299 ret = phy_startup(phydev);
304 debug("%s: link down\n", phydev->dev->name);
308 ret = higmac_adjust_link(priv);
313 writel(BITS_DESC_ENA, priv->base + DESC_WR_RD_ENA);
314 writel(BIT_TX_EN | BIT_RX_EN, priv->base + PORT_EN);
319 static void higmac_stop(struct udevice *dev)
321 struct higmac_priv *priv = dev_get_priv(dev);
324 writel(0, priv->base + PORT_EN);
325 writel(0, priv->base + DESC_WR_RD_ENA);
328 static const struct eth_ops higmac_ops = {
329 .start = higmac_start,
332 .free_pkt = higmac_free_pkt,
334 .write_hwaddr = higmac_write_hwaddr,
337 static int higmac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
339 struct higmac_priv *priv = bus->priv;
342 ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
347 writel(MDIO_READ | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
349 ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
354 if (readl(priv->base + MDIO_RDATA_STATUS) & BIT_MDIO_RDATA_INVALID)
357 return readl(priv->base + MDIO_SINGLE_DATA) >> 16;
360 static int higmac_mdio_write(struct mii_dev *bus, int addr, int devad,
363 struct higmac_priv *priv = bus->priv;
366 ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
371 writel(value, priv->base + MDIO_SINGLE_DATA);
372 writel(MDIO_WRITE | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
377 static int higmac_init_rx_descs(struct higmac_desc *descs, int num)
381 for (i = 0; i < num; i++) {
382 struct higmac_desc *desc = &descs[i];
384 desc->buf_addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
389 desc->descvid = DESC_VLD_FREE;
390 desc->buf_len = MAC_MAX_FRAME_SIZE - 1;
398 free((void *)(unsigned long)descs[i].buf_addr);
402 static int higmac_init_hw_queue(struct higmac_priv *priv,
403 enum higmac_queue queue)
405 struct higmac_desc *desc, **pdesc;
406 u32 regaddr, regen, regdep;
412 regaddr = RX_FQ_START_ADDR;
413 regen = RX_FQ_REG_EN;
414 regdep = RX_FQ_DEPTH;
419 regaddr = RX_BQ_START_ADDR;
420 regen = RX_BQ_REG_EN;
421 regdep = RX_BQ_DEPTH;
426 regaddr = TX_BQ_START_ADDR;
427 regen = TX_BQ_REG_EN;
428 regdep = TX_BQ_DEPTH;
433 regaddr = TX_RQ_START_ADDR;
434 regen = TX_RQ_REG_EN;
435 regdep = TX_RQ_DEPTH;
442 writel(BIT_DEPTH_EN, priv->base + regen);
443 writel(depth << DESC_WORD_SHIFT, priv->base + regdep);
444 writel(0, priv->base + regen);
446 len = depth * sizeof(*desc);
447 desc = memalign(ARCH_DMA_MINALIGN, len);
450 memset(desc, 0, len);
451 flush_cache((unsigned long)desc, len);
454 /* Set up RX_FQ descriptors */
456 higmac_init_rx_descs(desc, depth);
458 /* Enable start address */
459 writel(BIT_START_ADDR_EN, priv->base + regen);
460 writel((unsigned long)desc, priv->base + regaddr);
461 writel(0, priv->base + regen);
466 static int higmac_hw_init(struct higmac_priv *priv)
470 /* Initialize hardware queues */
471 ret = higmac_init_hw_queue(priv, RX_FQ);
475 ret = higmac_init_hw_queue(priv, RX_BQ);
479 ret = higmac_init_hw_queue(priv, TX_BQ);
483 ret = higmac_init_hw_queue(priv, TX_RQ);
488 reset_deassert(&priv->rst_phy);
490 reset_assert(&priv->rst_phy);
492 reset_deassert(&priv->rst_phy);
506 static int higmac_probe(struct udevice *dev)
508 struct higmac_priv *priv = dev_get_priv(dev);
509 struct phy_device *phydev;
513 ret = higmac_hw_init(priv);
521 bus->read = higmac_mdio_read;
522 bus->write = higmac_mdio_write;
526 ret = mdio_register_seq(bus, dev->seq);
530 phydev = phy_connect(bus, priv->phyaddr, dev, priv->phyintf);
534 phydev->supported &= PHY_GBIT_FEATURES;
535 phydev->advertising = phydev->supported;
536 priv->phydev = phydev;
538 return phy_config(phydev);
541 static int higmac_remove(struct udevice *dev)
543 struct higmac_priv *priv = dev_get_priv(dev);
546 mdio_unregister(priv->bus);
547 mdio_free(priv->bus);
549 /* Free RX packet buffers */
550 for (i = 0; i < RX_DESC_NUM; i++)
551 free((void *)(unsigned long)priv->rxfq[i].buf_addr);
556 static int higmac_ofdata_to_platdata(struct udevice *dev)
558 struct higmac_priv *priv = dev_get_priv(dev);
559 int phyintf = PHY_INTERFACE_MODE_NONE;
560 const char *phy_mode;
563 priv->base = dev_remap_addr_index(dev, 0);
564 priv->macif_ctrl = dev_remap_addr_index(dev, 1);
566 phy_mode = dev_read_string(dev, "phy-mode");
568 phyintf = phy_get_interface_by_name(phy_mode);
569 if (phyintf == PHY_INTERFACE_MODE_NONE)
571 priv->phyintf = phyintf;
573 phy_node = dev_read_subnode(dev, "phy");
574 if (!ofnode_valid(phy_node)) {
575 debug("failed to find phy node\n");
578 priv->phyaddr = ofnode_read_u32_default(phy_node, "reg", 0);
580 return reset_get_by_name(dev, "phy", &priv->rst_phy);
583 static const struct udevice_id higmac_ids[] = {
584 { .compatible = "hisilicon,hi3798cv200-gmac" },
588 U_BOOT_DRIVER(eth_higmac) = {
589 .name = "eth_higmac",
591 .of_match = higmac_ids,
592 .ofdata_to_platdata = higmac_ofdata_to_platdata,
593 .probe = higmac_probe,
594 .remove = higmac_remove,
596 .priv_auto_alloc_size = sizeof(struct higmac_priv),
597 .platdata_auto_alloc_size = sizeof(struct eth_pdata),