drivers/net/higmacv300.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019, Linaro Limited
   4  */
   5
   6 #include <asm/io.h>
   7 #include <common.h>
   8 #include <console.h>
   9 #include <linux/bug.h>
  10 #include <linux/mii.h>
  11 #include <miiphy.h>
  12 #include <net.h>
  13 #include <reset.h>
  14 #include <wait_bit.h>
  15
  16 #define STATION_ADDR_LOW                0x0000
  17 #define STATION_ADDR_HIGH               0x0004
  18 #define MAC_DUPLEX_HALF_CTRL            0x0008
  19 #define PORT_MODE                       0x0040
  20 #define PORT_EN                         0x0044
  21 #define BIT_TX_EN                       BIT(2)
  22 #define BIT_RX_EN                       BIT(1)
  23 #define MODE_CHANGE_EN                  0x01b4
  24 #define BIT_MODE_CHANGE_EN              BIT(0)
  25 #define MDIO_SINGLE_CMD                 0x03c0
  26 #define BIT_MDIO_BUSY                   BIT(20)
  27 #define MDIO_READ                       (BIT(17) | BIT_MDIO_BUSY)
  28 #define MDIO_WRITE                      (BIT(16) | BIT_MDIO_BUSY)
  29 #define MDIO_SINGLE_DATA                0x03c4
  30 #define MDIO_RDATA_STATUS               0x03d0
  31 #define BIT_MDIO_RDATA_INVALID          BIT(0)
  32 #define RX_FQ_START_ADDR                0x0500
  33 #define RX_FQ_DEPTH                     0x0504
  34 #define RX_FQ_WR_ADDR                   0x0508
  35 #define RX_FQ_RD_ADDR                   0x050c
  36 #define RX_FQ_REG_EN                    0x0518
  37 #define RX_BQ_START_ADDR                0x0520
  38 #define RX_BQ_DEPTH                     0x0524
  39 #define RX_BQ_WR_ADDR                   0x0528
  40 #define RX_BQ_RD_ADDR                   0x052c
  41 #define RX_BQ_REG_EN                    0x0538
  42 #define TX_BQ_START_ADDR                0x0580
  43 #define TX_BQ_DEPTH                     0x0584
  44 #define TX_BQ_WR_ADDR                   0x0588
  45 #define TX_BQ_RD_ADDR                   0x058c
  46 #define TX_BQ_REG_EN                    0x0598
  47 #define TX_RQ_START_ADDR                0x05a0
  48 #define TX_RQ_DEPTH                     0x05a4
  49 #define TX_RQ_WR_ADDR                   0x05a8
  50 #define TX_RQ_RD_ADDR                   0x05ac
  51 #define TX_RQ_REG_EN                    0x05b8
  52 #define BIT_START_ADDR_EN               BIT(2)
  53 #define BIT_DEPTH_EN                    BIT(1)
  54 #define DESC_WR_RD_ENA                  0x05cc
  55 #define BIT_RX_OUTCFF_WR                BIT(3)
  56 #define BIT_RX_CFF_RD                   BIT(2)
  57 #define BIT_TX_OUTCFF_WR                BIT(1)
  58 #define BIT_TX_CFF_RD                   BIT(0)
  59 #define BITS_DESC_ENA                   (BIT_RX_OUTCFF_WR | BIT_RX_CFF_RD | \
  60                                          BIT_TX_OUTCFF_WR | BIT_TX_CFF_RD)
  61
  62 /* MACIF_CTRL */
  63 #define RGMII_SPEED_1000                0x2c
  64 #define RGMII_SPEED_100                 0x2f
  65 #define RGMII_SPEED_10                  0x2d
  66 #define MII_SPEED_100                   0x0f
  67 #define MII_SPEED_10                    0x0d
  68 #define GMAC_SPEED_1000                 0x05
  69 #define GMAC_SPEED_100                  0x01
  70 #define GMAC_SPEED_10                   0x00
  71 #define GMAC_FULL_DUPLEX                BIT(4)
  72
  73 #define RX_DESC_NUM                     64
  74 #define TX_DESC_NUM                     2
  75 #define DESC_SIZE                       32
  76 #define DESC_WORD_SHIFT                 3
  77 #define DESC_BYTE_SHIFT                 5
  78 #define DESC_CNT(n)                     ((n) >> DESC_BYTE_SHIFT)
  79 #define DESC_BYTE(n)                    ((n) << DESC_BYTE_SHIFT)
  80 #define DESC_VLD_FREE                   0
  81 #define DESC_VLD_BUSY                   1
  82
  83 #define MAC_MAX_FRAME_SIZE              1600
  84
  85 enum higmac_queue {
  86         RX_FQ,
  87         RX_BQ,
  88         TX_BQ,
  89         TX_RQ,
  90 };
  91
  92 struct higmac_desc {
  93         unsigned int buf_addr;
  94         unsigned int buf_len:11;
  95         unsigned int reserve0:5;
  96         unsigned int data_len:11;
  97         unsigned int reserve1:2;
  98         unsigned int fl:2;
  99         unsigned int descvid:1;
 100         unsigned int reserve2[6];
 101 };
 102
 103 struct higmac_priv {
 104         void __iomem *base;
 105         void __iomem *macif_ctrl;
 106         struct reset_ctl rst_phy;
 107         struct higmac_desc *rxfq;
 108         struct higmac_desc *rxbq;
 109         struct higmac_desc *txbq;
 110         struct higmac_desc *txrq;
 111         int rxdesc_in_use;
 112         struct mii_dev *bus;
 113         struct phy_device *phydev;
 114         int phyintf;
 115         int phyaddr;
 116 };
 117
 118 #define flush_desc(d) flush_cache((unsigned long)(d), sizeof(*(d)))
 119 #define invalidate_desc(d) \
 120         invalidate_dcache_range((unsigned long)(d), \
 121                                 (unsigned long)(d) + sizeof(*(d)))
 122
 123 static int higmac_write_hwaddr(struct udevice *dev)
 124 {
 125         struct eth_pdata *pdata = dev_get_platdata(dev);
 126         struct higmac_priv *priv = dev_get_priv(dev);
 127         unsigned char *mac = pdata->enetaddr;
 128         u32 val;
 129
 130         val = mac[1] | (mac[0] << 8);
 131         writel(val, priv->base + STATION_ADDR_HIGH);
 132
 133         val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
 134         writel(val, priv->base + STATION_ADDR_LOW);
 135
 136         return 0;
 137 }
 138
 139 static int higmac_free_pkt(struct udevice *dev, uchar *packet, int length)
 140 {
 141         struct higmac_priv *priv = dev_get_priv(dev);
 142
 143         /* Inform GMAC that the RX descriptor is no longer in use */
 144         writel(DESC_BYTE(priv->rxdesc_in_use), priv->base + RX_BQ_RD_ADDR);
 145
 146         return 0;
 147 }
 148
 149 static int higmac_recv(struct udevice *dev, int flags, uchar **packetp)
 150 {
 151         struct higmac_priv *priv = dev_get_priv(dev);
 152         struct higmac_desc *fqd = priv->rxfq;
 153         struct higmac_desc *bqd = priv->rxbq;
 154         int fqw_pos, fqr_pos, bqw_pos, bqr_pos;
 155         int timeout = 100000;
 156         int len = 0;
 157         int space;
 158         int i;
 159
 160         fqw_pos = DESC_CNT(readl(priv->base + RX_FQ_WR_ADDR));
 161         fqr_pos = DESC_CNT(readl(priv->base + RX_FQ_RD_ADDR));
 162
 163         if (fqw_pos >= fqr_pos)
 164                 space = RX_DESC_NUM - (fqw_pos - fqr_pos);
 165         else
 166                 space = fqr_pos - fqw_pos;
 167
 168         /* Leave one free to distinguish full filled from empty buffer */
 169         for (i = 0; i < space - 1; i++) {
 170                 fqd = priv->rxfq + fqw_pos;
 171                 invalidate_dcache_range(fqd->buf_addr,
 172                                         fqd->buf_addr + MAC_MAX_FRAME_SIZE);
 173
 174                 if (++fqw_pos >= RX_DESC_NUM)
 175                         fqw_pos = 0;
 176
 177                 writel(DESC_BYTE(fqw_pos), priv->base + RX_FQ_WR_ADDR);
 178         }
 179
 180         bqr_pos = DESC_CNT(readl(priv->base + RX_BQ_RD_ADDR));
 181         bqd += bqr_pos;
 182         /* BQ is only ever written by GMAC */
 183         invalidate_desc(bqd);
 184
 185         do {
 186                 bqw_pos = DESC_CNT(readl(priv->base + RX_BQ_WR_ADDR));
 187                 udelay(1);
 188         } while (--timeout && bqw_pos == bqr_pos);
 189
 190         if (!timeout)
 191                 return -ETIMEDOUT;
 192
 193         if (++bqr_pos >= RX_DESC_NUM)
 194                 bqr_pos = 0;
 195
 196         len = bqd->data_len;
 197
 198         /* CPU should not have touched this buffer since we added it to FQ */
 199         invalidate_dcache_range(bqd->buf_addr, bqd->buf_addr + len);
 200         *packetp = (void *)(unsigned long)bqd->buf_addr;
 201
 202         /* Record the RX_BQ descriptor that is holding RX data */
 203         priv->rxdesc_in_use = bqr_pos;
 204
 205         return len;
 206 }
 207
 208 static int higmac_send(struct udevice *dev, void *packet, int length)
 209 {
 210         struct higmac_priv *priv = dev_get_priv(dev);
 211         struct higmac_desc *bqd = priv->txbq;
 212         int bqw_pos, rqw_pos, rqr_pos;
 213         int timeout = 1000;
 214
 215         flush_cache((unsigned long)packet, length);
 216
 217         bqw_pos = DESC_CNT(readl(priv->base + TX_BQ_WR_ADDR));
 218         bqd += bqw_pos;
 219         bqd->buf_addr = (unsigned long)packet;
 220         bqd->descvid = DESC_VLD_BUSY;
 221         bqd->data_len = length;
 222         flush_desc(bqd);
 223
 224         if (++bqw_pos >= TX_DESC_NUM)
 225                 bqw_pos = 0;
 226
 227         writel(DESC_BYTE(bqw_pos), priv->base + TX_BQ_WR_ADDR);
 228
 229         rqr_pos = DESC_CNT(readl(priv->base + TX_RQ_RD_ADDR));
 230         if (++rqr_pos >= TX_DESC_NUM)
 231                 rqr_pos = 0;
 232
 233         do {
 234                 rqw_pos = DESC_CNT(readl(priv->base + TX_RQ_WR_ADDR));
 235                 udelay(1);
 236         } while (--timeout && rqr_pos != rqw_pos);
 237
 238         if (!timeout)
 239                 return -ETIMEDOUT;
 240
 241         writel(DESC_BYTE(rqr_pos), priv->base + TX_RQ_RD_ADDR);
 242
 243         return 0;
 244 }
 245
 246 static int higmac_adjust_link(struct higmac_priv *priv)
 247 {
 248         struct phy_device *phydev = priv->phydev;
 249         int interface = priv->phyintf;
 250         u32 val;
 251
 252         switch (interface) {
 253         case PHY_INTERFACE_MODE_RGMII:
 254                 if (phydev->speed == SPEED_1000)
 255                         val = RGMII_SPEED_1000;
 256                 else if (phydev->speed == SPEED_100)
 257                         val = RGMII_SPEED_100;
 258                 else
 259                         val = RGMII_SPEED_10;
 260                 break;
 261         case PHY_INTERFACE_MODE_MII:
 262                 if (phydev->speed == SPEED_100)
 263                         val = MII_SPEED_100;
 264                 else
 265                         val = MII_SPEED_10;
 266                 break;
 267         default:
 268                 debug("unsupported mode: %d\n", interface);
 269                 return -EINVAL;
 270         }
 271
 272         if (phydev->duplex)
 273                 val |= GMAC_FULL_DUPLEX;
 274
 275         writel(val, priv->macif_ctrl);
 276
 277         if (phydev->speed == SPEED_1000)
 278                 val = GMAC_SPEED_1000;
 279         else if (phydev->speed == SPEED_100)
 280                 val = GMAC_SPEED_100;
 281         else
 282                 val = GMAC_SPEED_10;
 283
 284         writel(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
 285         writel(val, priv->base + PORT_MODE);
 286         writel(0, priv->base + MODE_CHANGE_EN);
 287         writel(phydev->duplex, priv->base + MAC_DUPLEX_HALF_CTRL);
 288
 289         return 0;
 290 }
 291
 292 static int higmac_start(struct udevice *dev)
 293 {
 294         struct higmac_priv *priv = dev_get_priv(dev);
 295         struct phy_device *phydev = priv->phydev;
 296         int ret;
 297
 298         ret = phy_startup(phydev);
 299         if (ret)
 300                 return ret;
 301
 302         if (!phydev->link) {
 303                 debug("%s: link down\n", phydev->dev->name);
 304                 return -ENODEV;
 305         }
 306
 307         ret = higmac_adjust_link(priv);
 308         if (ret)
 309                 return ret;
 310
 311         /* Enable port */
 312         writel(BITS_DESC_ENA, priv->base + DESC_WR_RD_ENA);
 313         writel(BIT_TX_EN | BIT_RX_EN, priv->base + PORT_EN);
 314
 315         return 0;
 316 }
 317
 318 static void higmac_stop(struct udevice *dev)
 319 {
 320         struct higmac_priv *priv = dev_get_priv(dev);
 321
 322         /* Disable port */
 323         writel(0, priv->base + PORT_EN);
 324         writel(0, priv->base + DESC_WR_RD_ENA);
 325 }
 326
 327 static const struct eth_ops higmac_ops = {
 328         .start          = higmac_start,
 329         .send           = higmac_send,
 330         .recv           = higmac_recv,
 331         .free_pkt       = higmac_free_pkt,
 332         .stop           = higmac_stop,
 333         .write_hwaddr   = higmac_write_hwaddr,
 334 };
 335
 336 static int higmac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 337 {
 338         struct higmac_priv *priv = bus->priv;
 339         int ret;
 340
 341         ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
 342                                 false, 1000, false);
 343         if (ret)
 344                 return ret;
 345
 346         writel(MDIO_READ | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
 347
 348         ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
 349                                 false, 1000, false);
 350         if (ret)
 351                 return ret;
 352
 353         if (readl(priv->base + MDIO_RDATA_STATUS) & BIT_MDIO_RDATA_INVALID)
 354                 return -EINVAL;
 355
 356         return readl(priv->base + MDIO_SINGLE_DATA) >> 16;
 357 }
 358
 359 static int higmac_mdio_write(struct mii_dev *bus, int addr, int devad,
 360                              int reg, u16 value)
 361 {
 362         struct higmac_priv *priv = bus->priv;
 363         int ret;
 364
 365         ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
 366                                 false, 1000, false);
 367         if (ret)
 368                 return ret;
 369
 370         writel(value, priv->base + MDIO_SINGLE_DATA);
 371         writel(MDIO_WRITE | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
 372
 373         return 0;
 374 }
 375
 376 static int higmac_init_rx_descs(struct higmac_desc *descs, int num)
 377 {
 378         int i;
 379
 380         for (i = 0; i < num; i++) {
 381                 struct higmac_desc *desc = &descs[i];
 382
 383                 desc->buf_addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
 384                                                          MAC_MAX_FRAME_SIZE);
 385                 if (!desc->buf_addr)
 386                         goto free_bufs;
 387
 388                 desc->descvid = DESC_VLD_FREE;
 389                 desc->buf_len = MAC_MAX_FRAME_SIZE - 1;
 390                 flush_desc(desc);
 391         }
 392
 393         return 0;
 394
 395 free_bufs:
 396         while (--i > 0)
 397                 free((void *)(unsigned long)descs[i].buf_addr);
 398         return -ENOMEM;
 399 }
 400
 401 static int higmac_init_hw_queue(struct higmac_priv *priv,
 402                                 enum higmac_queue queue)
 403 {
 404         struct higmac_desc *desc, **pdesc;
 405         u32 regaddr, regen, regdep;
 406         int depth;
 407         int len;
 408
 409         switch (queue) {
 410         case RX_FQ:
 411                 regaddr = RX_FQ_START_ADDR;
 412                 regen = RX_FQ_REG_EN;
 413                 regdep = RX_FQ_DEPTH;
 414                 depth = RX_DESC_NUM;
 415                 pdesc = &priv->rxfq;
 416                 break;
 417         case RX_BQ:
 418                 regaddr = RX_BQ_START_ADDR;
 419                 regen = RX_BQ_REG_EN;
 420                 regdep = RX_BQ_DEPTH;
 421                 depth = RX_DESC_NUM;
 422                 pdesc = &priv->rxbq;
 423                 break;
 424         case TX_BQ:
 425                 regaddr = TX_BQ_START_ADDR;
 426                 regen = TX_BQ_REG_EN;
 427                 regdep = TX_BQ_DEPTH;
 428                 depth = TX_DESC_NUM;
 429                 pdesc = &priv->txbq;
 430                 break;
 431         case TX_RQ:
 432                 regaddr = TX_RQ_START_ADDR;
 433                 regen = TX_RQ_REG_EN;
 434                 regdep = TX_RQ_DEPTH;
 435                 depth = TX_DESC_NUM;
 436                 pdesc = &priv->txrq;
 437                 break;
 438         }
 439
 440         /* Enable depth */
 441         writel(BIT_DEPTH_EN, priv->base + regen);
 442         writel(depth << DESC_WORD_SHIFT, priv->base + regdep);
 443         writel(0, priv->base + regen);
 444
 445         len = depth * sizeof(*desc);
 446         desc = memalign(ARCH_DMA_MINALIGN, len);
 447         if (!desc)
 448                 return -ENOMEM;
 449         memset(desc, 0, len);
 450         flush_cache((unsigned long)desc, len);
 451         *pdesc = desc;
 452
 453         /* Set up RX_FQ descriptors */
 454         if (queue == RX_FQ)
 455                 higmac_init_rx_descs(desc, depth);
 456
 457         /* Enable start address */
 458         writel(BIT_START_ADDR_EN, priv->base + regen);
 459         writel((unsigned long)desc, priv->base + regaddr);
 460         writel(0, priv->base + regen);
 461
 462         return 0;
 463 }
 464
 465 static int higmac_hw_init(struct higmac_priv *priv)
 466 {
 467         int ret;
 468
 469         /* Initialize hardware queues */
 470         ret = higmac_init_hw_queue(priv, RX_FQ);
 471         if (ret)
 472                 return ret;
 473
 474         ret = higmac_init_hw_queue(priv, RX_BQ);
 475         if (ret)
 476                 goto free_rx_fq;
 477
 478         ret = higmac_init_hw_queue(priv, TX_BQ);
 479         if (ret)
 480                 goto free_rx_bq;
 481
 482         ret = higmac_init_hw_queue(priv, TX_RQ);
 483         if (ret)
 484                 goto free_tx_bq;
 485
 486         /* Reset phy */
 487         reset_deassert(&priv->rst_phy);
 488         mdelay(10);
 489         reset_assert(&priv->rst_phy);
 490         mdelay(30);
 491         reset_deassert(&priv->rst_phy);
 492         mdelay(30);
 493
 494         return 0;
 495
 496 free_tx_bq:
 497         free(priv->txbq);
 498 free_rx_bq:
 499         free(priv->rxbq);
 500 free_rx_fq:
 501         free(priv->rxfq);
 502         return ret;
 503 }
 504
 505 static int higmac_probe(struct udevice *dev)
 506 {
 507         struct higmac_priv *priv = dev_get_priv(dev);
 508         struct phy_device *phydev;
 509         struct mii_dev *bus;
 510         int ret;
 511
 512         ret = higmac_hw_init(priv);
 513         if (ret)
 514                 return ret;
 515
 516         bus = mdio_alloc();
 517         if (!bus)
 518                 return -ENOMEM;
 519
 520         bus->read = higmac_mdio_read;
 521         bus->write = higmac_mdio_write;
 522         bus->priv = priv;
 523         priv->bus = bus;
 524
 525         ret = mdio_register_seq(bus, dev->seq);
 526         if (ret)
 527                 return ret;
 528
 529         phydev = phy_connect(bus, priv->phyaddr, dev, priv->phyintf);
 530         if (!phydev)
 531                 return -ENODEV;
 532
 533         phydev->supported &= PHY_GBIT_FEATURES;
 534         phydev->advertising = phydev->supported;
 535         priv->phydev = phydev;
 536
 537         return phy_config(phydev);
 538 }
 539
 540 static int higmac_remove(struct udevice *dev)
 541 {
 542         struct higmac_priv *priv = dev_get_priv(dev);
 543         int i;
 544
 545         mdio_unregister(priv->bus);
 546         mdio_free(priv->bus);
 547
 548         /* Free RX packet buffers */
 549         for (i = 0; i < RX_DESC_NUM; i++)
 550                 free((void *)(unsigned long)priv->rxfq[i].buf_addr);
 551
 552         return 0;
 553 }
 554
 555 static int higmac_ofdata_to_platdata(struct udevice *dev)
 556 {
 557         struct higmac_priv *priv = dev_get_priv(dev);
 558         int phyintf = PHY_INTERFACE_MODE_NONE;
 559         const char *phy_mode;
 560         ofnode phy_node;
 561
 562         priv->base = dev_remap_addr_index(dev, 0);
 563         priv->macif_ctrl = dev_remap_addr_index(dev, 1);
 564
 565         phy_mode = dev_read_string(dev, "phy-mode");
 566         if (phy_mode)
 567                 phyintf = phy_get_interface_by_name(phy_mode);
 568         if (phyintf == PHY_INTERFACE_MODE_NONE)
 569                 return -ENODEV;
 570         priv->phyintf = phyintf;
 571
 572         phy_node = dev_read_subnode(dev, "phy");
 573         if (!ofnode_valid(phy_node)) {
 574                 debug("failed to find phy node\n");
 575                 return -ENODEV;
 576         }
 577         priv->phyaddr = ofnode_read_u32_default(phy_node, "reg", 0);
 578
 579         return reset_get_by_name(dev, "phy", &priv->rst_phy);
 580 }
 581
 582 static const struct udevice_id higmac_ids[] = {
 583         { .compatible = "hisilicon,hi3798cv200-gmac" },
 584         { }
 585 };
 586
 587 U_BOOT_DRIVER(eth_higmac) = {
 588         .name   = "eth_higmac",
 589         .id     = UCLASS_ETH,
 590         .of_match = higmac_ids,
 591         .ofdata_to_platdata = higmac_ofdata_to_platdata,
 592         .probe  = higmac_probe,
 593         .remove = higmac_remove,
 594         .ops    = &higmac_ops,
 595         .priv_auto_alloc_size = sizeof(struct higmac_priv),
 596         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 597 };