1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
5 * Rockchip GMAC ethernet IP driver for U-Boot
14 #include <asm/arch-rockchip/periph.h>
15 #include <asm/arch-rockchip/clock.h>
16 #include <asm/arch-rockchip/hardware.h>
17 #include <asm/arch-rockchip/grf_px30.h>
18 #include <asm/arch-rockchip/grf_rk322x.h>
19 #include <asm/arch-rockchip/grf_rk3288.h>
20 #include <asm/arch-rockchip/grf_rk3328.h>
21 #include <asm/arch-rockchip/grf_rk3368.h>
22 #include <asm/arch-rockchip/grf_rk3399.h>
23 #include <asm/arch-rockchip/grf_rv1108.h>
24 #include <dm/pinctrl.h>
25 #include <dt-bindings/clock/rk3288-cru.h>
26 #include "designware.h"
28 DECLARE_GLOBAL_DATA_PTR;
29 #define DELAY_ENABLE(soc, tx, rx) \
30 (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
31 ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
34 * Platform data for the gmac
36 * dw_eth_pdata: Required platform data for designware driver (must be first)
38 struct gmac_rockchip_platdata {
39 struct dw_eth_pdata dw_eth_pdata;
46 int (*fix_mac_speed)(struct dw_eth_dev *priv);
47 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
48 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
52 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
54 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
57 string = dev_read_string(dev, "clock_in_out");
58 if (!strcmp(string, "input"))
59 pdata->clock_input = true;
61 pdata->clock_input = false;
63 /* Check the new naming-style first... */
64 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
65 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
67 /* ... and fall back to the old naming style or default, if necessary */
68 if (pdata->tx_delay == -ENOENT)
69 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
70 if (pdata->rx_delay == -ENOENT)
71 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
73 return designware_eth_ofdata_to_platdata(dev);
76 static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
82 PX30_GMAC_SPEED_SHIFT = 0x2,
83 PX30_GMAC_SPEED_MASK = BIT(2),
84 PX30_GMAC_SPEED_10M = 0,
85 PX30_GMAC_SPEED_100M = BIT(2),
88 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
93 switch (priv->phydev->speed) {
95 speed = PX30_GMAC_SPEED_10M;
96 ret = clk_set_rate(&clk_speed, 2500000);
101 speed = PX30_GMAC_SPEED_100M;
102 ret = clk_set_rate(&clk_speed, 25000000);
107 debug("Unknown phy speed: %d\n", priv->phydev->speed);
111 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
112 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed);
117 static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
119 struct rk322x_grf *grf;
122 RK3228_GMAC_CLK_SEL_SHIFT = 8,
123 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8),
124 RK3228_GMAC_CLK_SEL_125M = 0 << 8,
125 RK3228_GMAC_CLK_SEL_25M = 3 << 8,
126 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8,
129 switch (priv->phydev->speed) {
131 clk = RK3228_GMAC_CLK_SEL_2_5M;
134 clk = RK3228_GMAC_CLK_SEL_25M;
137 clk = RK3228_GMAC_CLK_SEL_125M;
140 debug("Unknown phy speed: %d\n", priv->phydev->speed);
144 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
145 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
150 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
152 struct rk3288_grf *grf;
155 switch (priv->phydev->speed) {
157 clk = RK3288_GMAC_CLK_SEL_2_5M;
160 clk = RK3288_GMAC_CLK_SEL_25M;
163 clk = RK3288_GMAC_CLK_SEL_125M;
166 debug("Unknown phy speed: %d\n", priv->phydev->speed);
170 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
171 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
176 static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
178 struct rk3328_grf_regs *grf;
181 RK3328_GMAC_CLK_SEL_SHIFT = 11,
182 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11),
183 RK3328_GMAC_CLK_SEL_125M = 0 << 11,
184 RK3328_GMAC_CLK_SEL_25M = 3 << 11,
185 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11,
188 switch (priv->phydev->speed) {
190 clk = RK3328_GMAC_CLK_SEL_2_5M;
193 clk = RK3328_GMAC_CLK_SEL_25M;
196 clk = RK3328_GMAC_CLK_SEL_125M;
199 debug("Unknown phy speed: %d\n", priv->phydev->speed);
203 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
204 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
209 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
211 struct rk3368_grf *grf;
214 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
215 RK3368_GMAC_CLK_SEL_25M = 3 << 4,
216 RK3368_GMAC_CLK_SEL_125M = 0 << 4,
217 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
220 switch (priv->phydev->speed) {
222 clk = RK3368_GMAC_CLK_SEL_2_5M;
225 clk = RK3368_GMAC_CLK_SEL_25M;
228 clk = RK3368_GMAC_CLK_SEL_125M;
231 debug("Unknown phy speed: %d\n", priv->phydev->speed);
235 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
236 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
241 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
243 struct rk3399_grf_regs *grf;
246 switch (priv->phydev->speed) {
248 clk = RK3399_GMAC_CLK_SEL_2_5M;
251 clk = RK3399_GMAC_CLK_SEL_25M;
254 clk = RK3399_GMAC_CLK_SEL_125M;
257 debug("Unknown phy speed: %d\n", priv->phydev->speed);
261 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
262 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
267 static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
269 struct rv1108_grf *grf;
272 RV1108_GMAC_SPEED_MASK = BIT(2),
273 RV1108_GMAC_SPEED_10M = 0 << 2,
274 RV1108_GMAC_SPEED_100M = 1 << 2,
275 RV1108_GMAC_CLK_SEL_MASK = BIT(7),
276 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7,
277 RV1108_GMAC_CLK_SEL_25M = 1 << 7,
280 switch (priv->phydev->speed) {
282 clk = RV1108_GMAC_CLK_SEL_2_5M;
283 speed = RV1108_GMAC_SPEED_10M;
286 clk = RV1108_GMAC_CLK_SEL_25M;
287 speed = RV1108_GMAC_SPEED_100M;
290 debug("Unknown phy speed: %d\n", priv->phydev->speed);
294 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
295 rk_clrsetreg(&grf->gmac_con0,
296 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
302 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
304 struct px30_grf *grf;
306 PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
307 PX30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6),
308 PX30_GMAC_PHY_INTF_SEL_RMII = BIT(6),
311 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
313 rk_clrsetreg(&grf->mac_con1,
314 PX30_GMAC_PHY_INTF_SEL_MASK,
315 PX30_GMAC_PHY_INTF_SEL_RMII);
318 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
320 struct rk322x_grf *grf;
322 RK3228_RMII_MODE_SHIFT = 10,
323 RK3228_RMII_MODE_MASK = BIT(10),
325 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
326 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
327 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
329 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
330 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
331 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
333 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
334 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
335 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
338 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
339 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
341 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
342 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
345 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
346 rk_clrsetreg(&grf->mac_con[1],
347 RK3228_RMII_MODE_MASK |
348 RK3228_GMAC_PHY_INTF_SEL_MASK |
349 RK3228_RXCLK_DLY_ENA_GMAC_MASK |
350 RK3228_TXCLK_DLY_ENA_GMAC_MASK,
351 RK3228_GMAC_PHY_INTF_SEL_RGMII |
352 DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
354 rk_clrsetreg(&grf->mac_con[0],
355 RK3228_CLK_RX_DL_CFG_GMAC_MASK |
356 RK3228_CLK_TX_DL_CFG_GMAC_MASK,
357 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
358 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
361 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
363 struct rk3288_grf *grf;
365 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
366 rk_clrsetreg(&grf->soc_con1,
367 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
368 RK3288_GMAC_PHY_INTF_SEL_RGMII);
370 rk_clrsetreg(&grf->soc_con3,
371 RK3288_RXCLK_DLY_ENA_GMAC_MASK |
372 RK3288_TXCLK_DLY_ENA_GMAC_MASK |
373 RK3288_CLK_RX_DL_CFG_GMAC_MASK |
374 RK3288_CLK_TX_DL_CFG_GMAC_MASK,
375 DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) |
376 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
377 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
380 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
382 struct rk3328_grf_regs *grf;
384 RK3328_RMII_MODE_SHIFT = 9,
385 RK3328_RMII_MODE_MASK = BIT(9),
387 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
388 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
389 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
391 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
392 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
393 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
395 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
396 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
397 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
400 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
401 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
403 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
404 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
407 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
408 rk_clrsetreg(&grf->mac_con[1],
409 RK3328_RMII_MODE_MASK |
410 RK3328_GMAC_PHY_INTF_SEL_MASK |
411 RK3328_RXCLK_DLY_ENA_GMAC_MASK |
412 RK3328_TXCLK_DLY_ENA_GMAC_MASK,
413 RK3328_GMAC_PHY_INTF_SEL_RGMII |
414 DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
416 rk_clrsetreg(&grf->mac_con[0],
417 RK3328_CLK_RX_DL_CFG_GMAC_MASK |
418 RK3328_CLK_TX_DL_CFG_GMAC_MASK,
419 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
420 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
423 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
425 struct rk3368_grf *grf;
427 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
428 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
429 RK3368_RMII_MODE_MASK = BIT(6),
430 RK3368_RMII_MODE = BIT(6),
433 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
434 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
435 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
436 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
437 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
438 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
439 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
440 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
441 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
442 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
445 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
446 rk_clrsetreg(&grf->soc_con15,
447 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
448 RK3368_GMAC_PHY_INTF_SEL_RGMII);
450 rk_clrsetreg(&grf->soc_con16,
451 RK3368_RXCLK_DLY_ENA_GMAC_MASK |
452 RK3368_TXCLK_DLY_ENA_GMAC_MASK |
453 RK3368_CLK_RX_DL_CFG_GMAC_MASK |
454 RK3368_CLK_TX_DL_CFG_GMAC_MASK,
455 DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) |
456 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
457 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
460 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
462 struct rk3399_grf_regs *grf;
464 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
466 rk_clrsetreg(&grf->soc_con5,
467 RK3399_GMAC_PHY_INTF_SEL_MASK,
468 RK3399_GMAC_PHY_INTF_SEL_RGMII);
470 rk_clrsetreg(&grf->soc_con6,
471 RK3399_RXCLK_DLY_ENA_GMAC_MASK |
472 RK3399_TXCLK_DLY_ENA_GMAC_MASK |
473 RK3399_CLK_RX_DL_CFG_GMAC_MASK |
474 RK3399_CLK_TX_DL_CFG_GMAC_MASK,
475 DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) |
476 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
477 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
480 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
482 struct rv1108_grf *grf;
485 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
486 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,
489 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
490 rk_clrsetreg(&grf->gmac_con0,
491 RV1108_GMAC_PHY_INTF_SEL_MASK,
492 RV1108_GMAC_PHY_INTF_SEL_RMII);
495 static int gmac_rockchip_probe(struct udevice *dev)
497 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
498 struct rk_gmac_ops *ops =
499 (struct rk_gmac_ops *)dev_get_driver_data(dev);
500 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
501 struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
506 ret = clk_set_defaults(dev, 0);
508 debug("%s clk_set_defaults failed %d\n", __func__, ret);
510 ret = clk_get_by_index(dev, 0, &clk);
514 switch (eth_pdata->phy_interface) {
515 case PHY_INTERFACE_MODE_RGMII:
516 /* Set to RGMII mode */
517 if (ops->set_to_rgmii)
518 ops->set_to_rgmii(pdata);
523 * If the gmac clock is from internal pll, need to set and
524 * check the return value for gmac clock at RGMII mode. If
525 * the gmac clock is from external source, the clock rate
526 * is not set, because of it is bypassed.
529 if (!pdata->clock_input) {
530 rate = clk_set_rate(&clk, 125000000);
531 if (rate != 125000000)
536 case PHY_INTERFACE_MODE_RGMII_ID:
537 /* Set to RGMII mode */
538 if (ops->set_to_rgmii) {
541 ops->set_to_rgmii(pdata);
545 if (!pdata->clock_input) {
546 rate = clk_set_rate(&clk, 125000000);
547 if (rate != 125000000)
552 case PHY_INTERFACE_MODE_RMII:
553 /* Set to RMII mode */
554 if (ops->set_to_rmii)
555 ops->set_to_rmii(pdata);
559 if (!pdata->clock_input) {
560 rate = clk_set_rate(&clk, 50000000);
561 if (rate != 50000000)
566 case PHY_INTERFACE_MODE_RGMII_RXID:
567 /* Set to RGMII_RXID mode */
568 if (ops->set_to_rgmii) {
570 ops->set_to_rgmii(pdata);
574 if (!pdata->clock_input) {
575 rate = clk_set_rate(&clk, 125000000);
576 if (rate != 125000000)
581 case PHY_INTERFACE_MODE_RGMII_TXID:
582 /* Set to RGMII_TXID mode */
583 if (ops->set_to_rgmii) {
585 ops->set_to_rgmii(pdata);
589 if (!pdata->clock_input) {
590 rate = clk_set_rate(&clk, 125000000);
591 if (rate != 125000000)
597 debug("NO interface defined!\n");
601 return designware_eth_probe(dev);
604 static int gmac_rockchip_eth_start(struct udevice *dev)
606 struct eth_pdata *pdata = dev_get_platdata(dev);
607 struct dw_eth_dev *priv = dev_get_priv(dev);
608 struct rk_gmac_ops *ops =
609 (struct rk_gmac_ops *)dev_get_driver_data(dev);
612 ret = designware_eth_init(priv, pdata->enetaddr);
615 ret = ops->fix_mac_speed(priv);
618 ret = designware_eth_enable(priv);
625 const struct eth_ops gmac_rockchip_eth_ops = {
626 .start = gmac_rockchip_eth_start,
627 .send = designware_eth_send,
628 .recv = designware_eth_recv,
629 .free_pkt = designware_eth_free_pkt,
630 .stop = designware_eth_stop,
631 .write_hwaddr = designware_eth_write_hwaddr,
634 const struct rk_gmac_ops px30_gmac_ops = {
635 .fix_mac_speed = px30_gmac_fix_mac_speed,
636 .set_to_rmii = px30_gmac_set_to_rmii,
639 const struct rk_gmac_ops rk3228_gmac_ops = {
640 .fix_mac_speed = rk3228_gmac_fix_mac_speed,
641 .set_to_rgmii = rk3228_gmac_set_to_rgmii,
644 const struct rk_gmac_ops rk3288_gmac_ops = {
645 .fix_mac_speed = rk3288_gmac_fix_mac_speed,
646 .set_to_rgmii = rk3288_gmac_set_to_rgmii,
649 const struct rk_gmac_ops rk3328_gmac_ops = {
650 .fix_mac_speed = rk3328_gmac_fix_mac_speed,
651 .set_to_rgmii = rk3328_gmac_set_to_rgmii,
654 const struct rk_gmac_ops rk3368_gmac_ops = {
655 .fix_mac_speed = rk3368_gmac_fix_mac_speed,
656 .set_to_rgmii = rk3368_gmac_set_to_rgmii,
659 const struct rk_gmac_ops rk3399_gmac_ops = {
660 .fix_mac_speed = rk3399_gmac_fix_mac_speed,
661 .set_to_rgmii = rk3399_gmac_set_to_rgmii,
664 const struct rk_gmac_ops rv1108_gmac_ops = {
665 .fix_mac_speed = rv1108_set_rmii_speed,
666 .set_to_rmii = rv1108_gmac_set_to_rmii,
669 static const struct udevice_id rockchip_gmac_ids[] = {
670 { .compatible = "rockchip,px30-gmac",
671 .data = (ulong)&px30_gmac_ops },
672 { .compatible = "rockchip,rk3228-gmac",
673 .data = (ulong)&rk3228_gmac_ops },
674 { .compatible = "rockchip,rk3288-gmac",
675 .data = (ulong)&rk3288_gmac_ops },
676 { .compatible = "rockchip,rk3328-gmac",
677 .data = (ulong)&rk3328_gmac_ops },
678 { .compatible = "rockchip,rk3368-gmac",
679 .data = (ulong)&rk3368_gmac_ops },
680 { .compatible = "rockchip,rk3399-gmac",
681 .data = (ulong)&rk3399_gmac_ops },
682 { .compatible = "rockchip,rv1108-gmac",
683 .data = (ulong)&rv1108_gmac_ops },
687 U_BOOT_DRIVER(eth_gmac_rockchip) = {
688 .name = "gmac_rockchip",
690 .of_match = rockchip_gmac_ids,
691 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
692 .probe = gmac_rockchip_probe,
693 .ops = &gmac_rockchip_eth_ops,
694 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
695 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
696 .flags = DM_FLAG_ALLOC_PRIV_DMA,