1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
5 * Rockchip GMAC ethernet IP driver for U-Boot
14 #include <asm/arch-rockchip/periph.h>
15 #include <asm/arch-rockchip/clock.h>
16 #include <asm/arch-rockchip/hardware.h>
17 #include <asm/arch-rockchip/grf_px30.h>
18 #include <asm/arch-rockchip/grf_rk322x.h>
19 #include <asm/arch-rockchip/grf_rk3288.h>
20 #include <asm/arch-rk3308/grf_rk3308.h>
21 #include <asm/arch-rockchip/grf_rk3328.h>
22 #include <asm/arch-rockchip/grf_rk3368.h>
23 #include <asm/arch-rockchip/grf_rk3399.h>
24 #include <asm/arch-rockchip/grf_rv1108.h>
25 #include <dm/pinctrl.h>
26 #include <dt-bindings/clock/rk3288-cru.h>
27 #include "designware.h"
29 DECLARE_GLOBAL_DATA_PTR;
30 #define DELAY_ENABLE(soc, tx, rx) \
31 (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
32 ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
35 * Platform data for the gmac
37 * dw_eth_pdata: Required platform data for designware driver (must be first)
39 struct gmac_rockchip_platdata {
40 struct dw_eth_pdata dw_eth_pdata;
47 int (*fix_mac_speed)(struct dw_eth_dev *priv);
48 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
49 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
53 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
55 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
58 string = dev_read_string(dev, "clock_in_out");
59 if (!strcmp(string, "input"))
60 pdata->clock_input = true;
62 pdata->clock_input = false;
64 /* Check the new naming-style first... */
65 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
66 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
68 /* ... and fall back to the old naming style or default, if necessary */
69 if (pdata->tx_delay == -ENOENT)
70 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
71 if (pdata->rx_delay == -ENOENT)
72 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
74 return designware_eth_ofdata_to_platdata(dev);
77 static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
83 PX30_GMAC_SPEED_SHIFT = 0x2,
84 PX30_GMAC_SPEED_MASK = BIT(2),
85 PX30_GMAC_SPEED_10M = 0,
86 PX30_GMAC_SPEED_100M = BIT(2),
89 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
94 switch (priv->phydev->speed) {
96 speed = PX30_GMAC_SPEED_10M;
97 ret = clk_set_rate(&clk_speed, 2500000);
102 speed = PX30_GMAC_SPEED_100M;
103 ret = clk_set_rate(&clk_speed, 25000000);
108 debug("Unknown phy speed: %d\n", priv->phydev->speed);
112 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
113 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed);
118 static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
120 struct rk322x_grf *grf;
123 RK3228_GMAC_CLK_SEL_SHIFT = 8,
124 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8),
125 RK3228_GMAC_CLK_SEL_125M = 0 << 8,
126 RK3228_GMAC_CLK_SEL_25M = 3 << 8,
127 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8,
130 switch (priv->phydev->speed) {
132 clk = RK3228_GMAC_CLK_SEL_2_5M;
135 clk = RK3228_GMAC_CLK_SEL_25M;
138 clk = RK3228_GMAC_CLK_SEL_125M;
141 debug("Unknown phy speed: %d\n", priv->phydev->speed);
145 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
146 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
151 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
153 struct rk3288_grf *grf;
156 switch (priv->phydev->speed) {
158 clk = RK3288_GMAC_CLK_SEL_2_5M;
161 clk = RK3288_GMAC_CLK_SEL_25M;
164 clk = RK3288_GMAC_CLK_SEL_125M;
167 debug("Unknown phy speed: %d\n", priv->phydev->speed);
171 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
172 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
177 static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
179 struct rk3308_grf *grf;
180 struct clk clk_speed;
183 RK3308_GMAC_SPEED_SHIFT = 0x0,
184 RK3308_GMAC_SPEED_MASK = BIT(0),
185 RK3308_GMAC_SPEED_10M = 0,
186 RK3308_GMAC_SPEED_100M = BIT(0),
189 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
194 switch (priv->phydev->speed) {
196 speed = RK3308_GMAC_SPEED_10M;
197 ret = clk_set_rate(&clk_speed, 2500000);
202 speed = RK3308_GMAC_SPEED_100M;
203 ret = clk_set_rate(&clk_speed, 25000000);
208 debug("Unknown phy speed: %d\n", priv->phydev->speed);
212 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
213 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed);
218 static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
220 struct rk3328_grf_regs *grf;
223 RK3328_GMAC_CLK_SEL_SHIFT = 11,
224 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11),
225 RK3328_GMAC_CLK_SEL_125M = 0 << 11,
226 RK3328_GMAC_CLK_SEL_25M = 3 << 11,
227 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11,
230 switch (priv->phydev->speed) {
232 clk = RK3328_GMAC_CLK_SEL_2_5M;
235 clk = RK3328_GMAC_CLK_SEL_25M;
238 clk = RK3328_GMAC_CLK_SEL_125M;
241 debug("Unknown phy speed: %d\n", priv->phydev->speed);
245 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
246 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
251 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
253 struct rk3368_grf *grf;
256 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
257 RK3368_GMAC_CLK_SEL_25M = 3 << 4,
258 RK3368_GMAC_CLK_SEL_125M = 0 << 4,
259 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
262 switch (priv->phydev->speed) {
264 clk = RK3368_GMAC_CLK_SEL_2_5M;
267 clk = RK3368_GMAC_CLK_SEL_25M;
270 clk = RK3368_GMAC_CLK_SEL_125M;
273 debug("Unknown phy speed: %d\n", priv->phydev->speed);
277 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
278 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
283 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
285 struct rk3399_grf_regs *grf;
288 switch (priv->phydev->speed) {
290 clk = RK3399_GMAC_CLK_SEL_2_5M;
293 clk = RK3399_GMAC_CLK_SEL_25M;
296 clk = RK3399_GMAC_CLK_SEL_125M;
299 debug("Unknown phy speed: %d\n", priv->phydev->speed);
303 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
304 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
309 static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
311 struct rv1108_grf *grf;
314 RV1108_GMAC_SPEED_MASK = BIT(2),
315 RV1108_GMAC_SPEED_10M = 0 << 2,
316 RV1108_GMAC_SPEED_100M = 1 << 2,
317 RV1108_GMAC_CLK_SEL_MASK = BIT(7),
318 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7,
319 RV1108_GMAC_CLK_SEL_25M = 1 << 7,
322 switch (priv->phydev->speed) {
324 clk = RV1108_GMAC_CLK_SEL_2_5M;
325 speed = RV1108_GMAC_SPEED_10M;
328 clk = RV1108_GMAC_CLK_SEL_25M;
329 speed = RV1108_GMAC_SPEED_100M;
332 debug("Unknown phy speed: %d\n", priv->phydev->speed);
336 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
337 rk_clrsetreg(&grf->gmac_con0,
338 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
344 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
346 struct px30_grf *grf;
348 PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
349 PX30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6),
350 PX30_GMAC_PHY_INTF_SEL_RMII = BIT(6),
353 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
355 rk_clrsetreg(&grf->mac_con1,
356 PX30_GMAC_PHY_INTF_SEL_MASK,
357 PX30_GMAC_PHY_INTF_SEL_RMII);
360 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
362 struct rk322x_grf *grf;
364 RK3228_RMII_MODE_SHIFT = 10,
365 RK3228_RMII_MODE_MASK = BIT(10),
367 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
368 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
369 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
371 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
372 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
373 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
375 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
376 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
377 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
380 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
381 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
383 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
384 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
387 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
388 rk_clrsetreg(&grf->mac_con[1],
389 RK3228_RMII_MODE_MASK |
390 RK3228_GMAC_PHY_INTF_SEL_MASK |
391 RK3228_RXCLK_DLY_ENA_GMAC_MASK |
392 RK3228_TXCLK_DLY_ENA_GMAC_MASK,
393 RK3228_GMAC_PHY_INTF_SEL_RGMII |
394 DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
396 rk_clrsetreg(&grf->mac_con[0],
397 RK3228_CLK_RX_DL_CFG_GMAC_MASK |
398 RK3228_CLK_TX_DL_CFG_GMAC_MASK,
399 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
400 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
403 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
405 struct rk3288_grf *grf;
407 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
408 rk_clrsetreg(&grf->soc_con1,
409 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
410 RK3288_GMAC_PHY_INTF_SEL_RGMII);
412 rk_clrsetreg(&grf->soc_con3,
413 RK3288_RXCLK_DLY_ENA_GMAC_MASK |
414 RK3288_TXCLK_DLY_ENA_GMAC_MASK |
415 RK3288_CLK_RX_DL_CFG_GMAC_MASK |
416 RK3288_CLK_TX_DL_CFG_GMAC_MASK,
417 DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) |
418 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
419 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
422 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
424 struct rk3308_grf *grf;
426 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2,
427 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2),
428 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4),
431 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
433 rk_clrsetreg(&grf->mac_con0,
434 RK3308_GMAC_PHY_INTF_SEL_MASK,
435 RK3308_GMAC_PHY_INTF_SEL_RMII);
438 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
440 struct rk3328_grf_regs *grf;
442 RK3328_RMII_MODE_SHIFT = 9,
443 RK3328_RMII_MODE_MASK = BIT(9),
445 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
446 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
447 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
449 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
450 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
451 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
453 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
454 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
455 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
458 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
459 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
461 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
462 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
465 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
466 rk_clrsetreg(&grf->mac_con[1],
467 RK3328_RMII_MODE_MASK |
468 RK3328_GMAC_PHY_INTF_SEL_MASK |
469 RK3328_RXCLK_DLY_ENA_GMAC_MASK |
470 RK3328_TXCLK_DLY_ENA_GMAC_MASK,
471 RK3328_GMAC_PHY_INTF_SEL_RGMII |
472 DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
474 rk_clrsetreg(&grf->mac_con[0],
475 RK3328_CLK_RX_DL_CFG_GMAC_MASK |
476 RK3328_CLK_TX_DL_CFG_GMAC_MASK,
477 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
478 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
481 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
483 struct rk3368_grf *grf;
485 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
486 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
487 RK3368_RMII_MODE_MASK = BIT(6),
488 RK3368_RMII_MODE = BIT(6),
491 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
492 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
493 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
494 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
495 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
496 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
497 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
498 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
499 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
500 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
503 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
504 rk_clrsetreg(&grf->soc_con15,
505 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
506 RK3368_GMAC_PHY_INTF_SEL_RGMII);
508 rk_clrsetreg(&grf->soc_con16,
509 RK3368_RXCLK_DLY_ENA_GMAC_MASK |
510 RK3368_TXCLK_DLY_ENA_GMAC_MASK |
511 RK3368_CLK_RX_DL_CFG_GMAC_MASK |
512 RK3368_CLK_TX_DL_CFG_GMAC_MASK,
513 DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) |
514 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
515 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
518 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
520 struct rk3399_grf_regs *grf;
522 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
524 rk_clrsetreg(&grf->soc_con5,
525 RK3399_GMAC_PHY_INTF_SEL_MASK,
526 RK3399_GMAC_PHY_INTF_SEL_RGMII);
528 rk_clrsetreg(&grf->soc_con6,
529 RK3399_RXCLK_DLY_ENA_GMAC_MASK |
530 RK3399_TXCLK_DLY_ENA_GMAC_MASK |
531 RK3399_CLK_RX_DL_CFG_GMAC_MASK |
532 RK3399_CLK_TX_DL_CFG_GMAC_MASK,
533 DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) |
534 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
535 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
538 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
540 struct rv1108_grf *grf;
543 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
544 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,
547 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
548 rk_clrsetreg(&grf->gmac_con0,
549 RV1108_GMAC_PHY_INTF_SEL_MASK,
550 RV1108_GMAC_PHY_INTF_SEL_RMII);
553 static int gmac_rockchip_probe(struct udevice *dev)
555 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
556 struct rk_gmac_ops *ops =
557 (struct rk_gmac_ops *)dev_get_driver_data(dev);
558 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
559 struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
564 ret = clk_set_defaults(dev, 0);
566 debug("%s clk_set_defaults failed %d\n", __func__, ret);
568 ret = clk_get_by_index(dev, 0, &clk);
572 switch (eth_pdata->phy_interface) {
573 case PHY_INTERFACE_MODE_RGMII:
574 /* Set to RGMII mode */
575 if (ops->set_to_rgmii)
576 ops->set_to_rgmii(pdata);
581 * If the gmac clock is from internal pll, need to set and
582 * check the return value for gmac clock at RGMII mode. If
583 * the gmac clock is from external source, the clock rate
584 * is not set, because of it is bypassed.
587 if (!pdata->clock_input) {
588 rate = clk_set_rate(&clk, 125000000);
589 if (rate != 125000000)
594 case PHY_INTERFACE_MODE_RGMII_ID:
595 /* Set to RGMII mode */
596 if (ops->set_to_rgmii) {
599 ops->set_to_rgmii(pdata);
603 if (!pdata->clock_input) {
604 rate = clk_set_rate(&clk, 125000000);
605 if (rate != 125000000)
610 case PHY_INTERFACE_MODE_RMII:
611 /* Set to RMII mode */
612 if (ops->set_to_rmii)
613 ops->set_to_rmii(pdata);
617 if (!pdata->clock_input) {
618 rate = clk_set_rate(&clk, 50000000);
619 if (rate != 50000000)
624 case PHY_INTERFACE_MODE_RGMII_RXID:
625 /* Set to RGMII_RXID mode */
626 if (ops->set_to_rgmii) {
628 ops->set_to_rgmii(pdata);
632 if (!pdata->clock_input) {
633 rate = clk_set_rate(&clk, 125000000);
634 if (rate != 125000000)
639 case PHY_INTERFACE_MODE_RGMII_TXID:
640 /* Set to RGMII_TXID mode */
641 if (ops->set_to_rgmii) {
643 ops->set_to_rgmii(pdata);
647 if (!pdata->clock_input) {
648 rate = clk_set_rate(&clk, 125000000);
649 if (rate != 125000000)
655 debug("NO interface defined!\n");
659 return designware_eth_probe(dev);
662 static int gmac_rockchip_eth_start(struct udevice *dev)
664 struct eth_pdata *pdata = dev_get_platdata(dev);
665 struct dw_eth_dev *priv = dev_get_priv(dev);
666 struct rk_gmac_ops *ops =
667 (struct rk_gmac_ops *)dev_get_driver_data(dev);
670 ret = designware_eth_init(priv, pdata->enetaddr);
673 ret = ops->fix_mac_speed(priv);
676 ret = designware_eth_enable(priv);
683 const struct eth_ops gmac_rockchip_eth_ops = {
684 .start = gmac_rockchip_eth_start,
685 .send = designware_eth_send,
686 .recv = designware_eth_recv,
687 .free_pkt = designware_eth_free_pkt,
688 .stop = designware_eth_stop,
689 .write_hwaddr = designware_eth_write_hwaddr,
692 const struct rk_gmac_ops px30_gmac_ops = {
693 .fix_mac_speed = px30_gmac_fix_mac_speed,
694 .set_to_rmii = px30_gmac_set_to_rmii,
697 const struct rk_gmac_ops rk3228_gmac_ops = {
698 .fix_mac_speed = rk3228_gmac_fix_mac_speed,
699 .set_to_rgmii = rk3228_gmac_set_to_rgmii,
702 const struct rk_gmac_ops rk3288_gmac_ops = {
703 .fix_mac_speed = rk3288_gmac_fix_mac_speed,
704 .set_to_rgmii = rk3288_gmac_set_to_rgmii,
707 const struct rk_gmac_ops rk3308_gmac_ops = {
708 .fix_mac_speed = rk3308_gmac_fix_mac_speed,
709 .set_to_rmii = rk3308_gmac_set_to_rmii,
712 const struct rk_gmac_ops rk3328_gmac_ops = {
713 .fix_mac_speed = rk3328_gmac_fix_mac_speed,
714 .set_to_rgmii = rk3328_gmac_set_to_rgmii,
717 const struct rk_gmac_ops rk3368_gmac_ops = {
718 .fix_mac_speed = rk3368_gmac_fix_mac_speed,
719 .set_to_rgmii = rk3368_gmac_set_to_rgmii,
722 const struct rk_gmac_ops rk3399_gmac_ops = {
723 .fix_mac_speed = rk3399_gmac_fix_mac_speed,
724 .set_to_rgmii = rk3399_gmac_set_to_rgmii,
727 const struct rk_gmac_ops rv1108_gmac_ops = {
728 .fix_mac_speed = rv1108_set_rmii_speed,
729 .set_to_rmii = rv1108_gmac_set_to_rmii,
732 static const struct udevice_id rockchip_gmac_ids[] = {
733 { .compatible = "rockchip,px30-gmac",
734 .data = (ulong)&px30_gmac_ops },
735 { .compatible = "rockchip,rk3228-gmac",
736 .data = (ulong)&rk3228_gmac_ops },
737 { .compatible = "rockchip,rk3288-gmac",
738 .data = (ulong)&rk3288_gmac_ops },
739 { .compatible = "rockchip,rk3308-mac",
740 .data = (ulong)&rk3308_gmac_ops },
741 { .compatible = "rockchip,rk3328-gmac",
742 .data = (ulong)&rk3328_gmac_ops },
743 { .compatible = "rockchip,rk3368-gmac",
744 .data = (ulong)&rk3368_gmac_ops },
745 { .compatible = "rockchip,rk3399-gmac",
746 .data = (ulong)&rk3399_gmac_ops },
747 { .compatible = "rockchip,rv1108-gmac",
748 .data = (ulong)&rv1108_gmac_ops },
752 U_BOOT_DRIVER(eth_gmac_rockchip) = {
753 .name = "gmac_rockchip",
755 .of_match = rockchip_gmac_ids,
756 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
757 .probe = gmac_rockchip_probe,
758 .ops = &gmac_rockchip_eth_ops,
759 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
760 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
761 .flags = DM_FLAG_ALLOC_PRIV_DMA,