drivers/net/gmac_rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
   4  *
   5  * Rockchip GMAC ethernet IP driver for U-Boot
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <clk.h>
  11 #include <net.h>
  12 #include <phy.h>
  13 #include <syscon.h>
  14 #include <asm/io.h>
  15 #include <asm/arch-rockchip/periph.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/hardware.h>
  18 #include <asm/arch-rockchip/grf_px30.h>
  19 #include <asm/arch-rockchip/grf_rk322x.h>
  20 #include <asm/arch-rockchip/grf_rk3288.h>
  21 #include <asm/arch-rk3308/grf_rk3308.h>
  22 #include <asm/arch-rockchip/grf_rk3328.h>
  23 #include <asm/arch-rockchip/grf_rk3368.h>
  24 #include <asm/arch-rockchip/grf_rk3399.h>
  25 #include <asm/arch-rockchip/grf_rv1108.h>
  26 #include <dm/pinctrl.h>
  27 #include <dt-bindings/clock/rk3288-cru.h>
  28 #include "designware.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31 #define DELAY_ENABLE(soc, tx, rx) \
  32         (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
  33         ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
  34
  35 /*
  36  * Platform data for the gmac
  37  *
  38  * dw_eth_pdata: Required platform data for designware driver (must be first)
  39  */
  40 struct gmac_rockchip_platdata {
  41         struct dw_eth_pdata dw_eth_pdata;
  42         bool clock_input;
  43         int tx_delay;
  44         int rx_delay;
  45 };
  46
  47 struct rk_gmac_ops {
  48         int (*fix_mac_speed)(struct dw_eth_dev *priv);
  49         void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
  50         void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
  51 };
  52
  53
  54 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
  55 {
  56         struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
  57         const char *string;
  58
  59         string = dev_read_string(dev, "clock_in_out");
  60         if (!strcmp(string, "input"))
  61                 pdata->clock_input = true;
  62         else
  63                 pdata->clock_input = false;
  64
  65         /* Check the new naming-style first... */
  66         pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
  67         pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
  68
  69         /* ... and fall back to the old naming style or default, if necessary */
  70         if (pdata->tx_delay == -ENOENT)
  71                 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
  72         if (pdata->rx_delay == -ENOENT)
  73                 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
  74
  75         return designware_eth_ofdata_to_platdata(dev);
  76 }
  77
  78 static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  79 {
  80         struct px30_grf *grf;
  81         struct clk clk_speed;
  82         int speed, ret;
  83         enum {
  84                 PX30_GMAC_SPEED_SHIFT = 0x2,
  85                 PX30_GMAC_SPEED_MASK  = BIT(2),
  86                 PX30_GMAC_SPEED_10M   = 0,
  87                 PX30_GMAC_SPEED_100M  = BIT(2),
  88         };
  89
  90         ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
  91                               &clk_speed);
  92         if (ret)
  93                 return ret;
  94
  95         switch (priv->phydev->speed) {
  96         case 10:
  97                 speed = PX30_GMAC_SPEED_10M;
  98                 ret = clk_set_rate(&clk_speed, 2500000);
  99                 if (ret)
 100                         return ret;
 101                 break;
 102         case 100:
 103                 speed = PX30_GMAC_SPEED_100M;
 104                 ret = clk_set_rate(&clk_speed, 25000000);
 105                 if (ret)
 106                         return ret;
 107                 break;
 108         default:
 109                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 110                 return -EINVAL;
 111         }
 112
 113         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 114         rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed);
 115
 116         return 0;
 117 }
 118
 119 static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 120 {
 121         struct rk322x_grf *grf;
 122         int clk;
 123         enum {
 124                 RK3228_GMAC_CLK_SEL_SHIFT = 8,
 125                 RK3228_GMAC_CLK_SEL_MASK  = GENMASK(9, 8),
 126                 RK3228_GMAC_CLK_SEL_125M  = 0 << 8,
 127                 RK3228_GMAC_CLK_SEL_25M   = 3 << 8,
 128                 RK3228_GMAC_CLK_SEL_2_5M  = 2 << 8,
 129         };
 130
 131         switch (priv->phydev->speed) {
 132         case 10:
 133                 clk = RK3228_GMAC_CLK_SEL_2_5M;
 134                 break;
 135         case 100:
 136                 clk = RK3228_GMAC_CLK_SEL_25M;
 137                 break;
 138         case 1000:
 139                 clk = RK3228_GMAC_CLK_SEL_125M;
 140                 break;
 141         default:
 142                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 143                 return -EINVAL;
 144         }
 145
 146         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 147         rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
 148
 149         return 0;
 150 }
 151
 152 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 153 {
 154         struct rk3288_grf *grf;
 155         int clk;
 156
 157         switch (priv->phydev->speed) {
 158         case 10:
 159                 clk = RK3288_GMAC_CLK_SEL_2_5M;
 160                 break;
 161         case 100:
 162                 clk = RK3288_GMAC_CLK_SEL_25M;
 163                 break;
 164         case 1000:
 165                 clk = RK3288_GMAC_CLK_SEL_125M;
 166                 break;
 167         default:
 168                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 169                 return -EINVAL;
 170         }
 171
 172         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 173         rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
 174
 175         return 0;
 176 }
 177
 178 static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 179 {
 180         struct rk3308_grf *grf;
 181         struct clk clk_speed;
 182         int speed, ret;
 183         enum {
 184                 RK3308_GMAC_SPEED_SHIFT = 0x0,
 185                 RK3308_GMAC_SPEED_MASK  = BIT(0),
 186                 RK3308_GMAC_SPEED_10M   = 0,
 187                 RK3308_GMAC_SPEED_100M  = BIT(0),
 188         };
 189
 190         ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
 191                               &clk_speed);
 192         if (ret)
 193                 return ret;
 194
 195         switch (priv->phydev->speed) {
 196         case 10:
 197                 speed = RK3308_GMAC_SPEED_10M;
 198                 ret = clk_set_rate(&clk_speed, 2500000);
 199                 if (ret)
 200                         return ret;
 201                 break;
 202         case 100:
 203                 speed = RK3308_GMAC_SPEED_100M;
 204                 ret = clk_set_rate(&clk_speed, 25000000);
 205                 if (ret)
 206                         return ret;
 207                 break;
 208         default:
 209                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 210                 return -EINVAL;
 211         }
 212
 213         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 214         rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed);
 215
 216         return 0;
 217 }
 218
 219 static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 220 {
 221         struct rk3328_grf_regs *grf;
 222         int clk;
 223         enum {
 224                 RK3328_GMAC_CLK_SEL_SHIFT = 11,
 225                 RK3328_GMAC_CLK_SEL_MASK  = GENMASK(12, 11),
 226                 RK3328_GMAC_CLK_SEL_125M  = 0 << 11,
 227                 RK3328_GMAC_CLK_SEL_25M   = 3 << 11,
 228                 RK3328_GMAC_CLK_SEL_2_5M  = 2 << 11,
 229         };
 230
 231         switch (priv->phydev->speed) {
 232         case 10:
 233                 clk = RK3328_GMAC_CLK_SEL_2_5M;
 234                 break;
 235         case 100:
 236                 clk = RK3328_GMAC_CLK_SEL_25M;
 237                 break;
 238         case 1000:
 239                 clk = RK3328_GMAC_CLK_SEL_125M;
 240                 break;
 241         default:
 242                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 243                 return -EINVAL;
 244         }
 245
 246         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 247         rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
 248
 249         return 0;
 250 }
 251
 252 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 253 {
 254         struct rk3368_grf *grf;
 255         int clk;
 256         enum {
 257                 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
 258                 RK3368_GMAC_CLK_SEL_25M = 3 << 4,
 259                 RK3368_GMAC_CLK_SEL_125M = 0 << 4,
 260                 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
 261         };
 262
 263         switch (priv->phydev->speed) {
 264         case 10:
 265                 clk = RK3368_GMAC_CLK_SEL_2_5M;
 266                 break;
 267         case 100:
 268                 clk = RK3368_GMAC_CLK_SEL_25M;
 269                 break;
 270         case 1000:
 271                 clk = RK3368_GMAC_CLK_SEL_125M;
 272                 break;
 273         default:
 274                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 275                 return -EINVAL;
 276         }
 277
 278         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 279         rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
 280
 281         return 0;
 282 }
 283
 284 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 285 {
 286         struct rk3399_grf_regs *grf;
 287         int clk;
 288
 289         switch (priv->phydev->speed) {
 290         case 10:
 291                 clk = RK3399_GMAC_CLK_SEL_2_5M;
 292                 break;
 293         case 100:
 294                 clk = RK3399_GMAC_CLK_SEL_25M;
 295                 break;
 296         case 1000:
 297                 clk = RK3399_GMAC_CLK_SEL_125M;
 298                 break;
 299         default:
 300                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 301                 return -EINVAL;
 302         }
 303
 304         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 305         rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
 306
 307         return 0;
 308 }
 309
 310 static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
 311 {
 312         struct rv1108_grf *grf;
 313         int clk, speed;
 314         enum {
 315                 RV1108_GMAC_SPEED_MASK          = BIT(2),
 316                 RV1108_GMAC_SPEED_10M           = 0 << 2,
 317                 RV1108_GMAC_SPEED_100M          = 1 << 2,
 318                 RV1108_GMAC_CLK_SEL_MASK        = BIT(7),
 319                 RV1108_GMAC_CLK_SEL_2_5M        = 0 << 7,
 320                 RV1108_GMAC_CLK_SEL_25M         = 1 << 7,
 321         };
 322
 323         switch (priv->phydev->speed) {
 324         case 10:
 325                 clk = RV1108_GMAC_CLK_SEL_2_5M;
 326                 speed = RV1108_GMAC_SPEED_10M;
 327                 break;
 328         case 100:
 329                 clk = RV1108_GMAC_CLK_SEL_25M;
 330                 speed = RV1108_GMAC_SPEED_100M;
 331                 break;
 332         default:
 333                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 334                 return -EINVAL;
 335         }
 336
 337         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 338         rk_clrsetreg(&grf->gmac_con0,
 339                      RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
 340                      clk | speed);
 341
 342         return 0;
 343 }
 344
 345 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
 346 {
 347         struct px30_grf *grf;
 348         enum {
 349                 PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
 350                 PX30_GMAC_PHY_INTF_SEL_MASK  = GENMASK(4, 6),
 351                 PX30_GMAC_PHY_INTF_SEL_RMII  = BIT(6),
 352         };
 353
 354         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 355
 356         rk_clrsetreg(&grf->mac_con1,
 357                      PX30_GMAC_PHY_INTF_SEL_MASK,
 358                      PX30_GMAC_PHY_INTF_SEL_RMII);
 359 }
 360
 361 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 362 {
 363         struct rk322x_grf *grf;
 364         enum {
 365                 RK3228_RMII_MODE_SHIFT = 10,
 366                 RK3228_RMII_MODE_MASK  = BIT(10),
 367
 368                 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
 369                 RK3228_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
 370                 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
 371
 372                 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
 373                 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
 374                 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
 375
 376                 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
 377                 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
 378                 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
 379         };
 380         enum {
 381                 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
 382                 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
 383
 384                 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
 385                 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
 386         };
 387
 388         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 389         rk_clrsetreg(&grf->mac_con[1],
 390                      RK3228_RMII_MODE_MASK |
 391                      RK3228_GMAC_PHY_INTF_SEL_MASK |
 392                      RK3228_RXCLK_DLY_ENA_GMAC_MASK |
 393                      RK3228_TXCLK_DLY_ENA_GMAC_MASK,
 394                      RK3228_GMAC_PHY_INTF_SEL_RGMII |
 395                      DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
 396
 397         rk_clrsetreg(&grf->mac_con[0],
 398                      RK3228_CLK_RX_DL_CFG_GMAC_MASK |
 399                      RK3228_CLK_TX_DL_CFG_GMAC_MASK,
 400                      pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
 401                      pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
 402 }
 403
 404 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 405 {
 406         struct rk3288_grf *grf;
 407
 408         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 409         rk_clrsetreg(&grf->soc_con1,
 410                      RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
 411                      RK3288_GMAC_PHY_INTF_SEL_RGMII);
 412
 413         rk_clrsetreg(&grf->soc_con3,
 414                      RK3288_RXCLK_DLY_ENA_GMAC_MASK |
 415                      RK3288_TXCLK_DLY_ENA_GMAC_MASK |
 416                      RK3288_CLK_RX_DL_CFG_GMAC_MASK |
 417                      RK3288_CLK_TX_DL_CFG_GMAC_MASK,
 418                      DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) |
 419                      pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
 420                      pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
 421 }
 422
 423 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
 424 {
 425         struct rk3308_grf *grf;
 426         enum {
 427                 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2,
 428                 RK3308_GMAC_PHY_INTF_SEL_MASK  = GENMASK(4, 2),
 429                 RK3308_GMAC_PHY_INTF_SEL_RMII  = BIT(4),
 430         };
 431
 432         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 433
 434         rk_clrsetreg(&grf->mac_con0,
 435                      RK3308_GMAC_PHY_INTF_SEL_MASK,
 436                      RK3308_GMAC_PHY_INTF_SEL_RMII);
 437 }
 438
 439 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 440 {
 441         struct rk3328_grf_regs *grf;
 442         enum {
 443                 RK3328_RMII_MODE_SHIFT = 9,
 444                 RK3328_RMII_MODE_MASK  = BIT(9),
 445
 446                 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
 447                 RK3328_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
 448                 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
 449
 450                 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
 451                 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
 452                 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
 453
 454                 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
 455                 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
 456                 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
 457         };
 458         enum {
 459                 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
 460                 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
 461
 462                 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
 463                 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
 464         };
 465
 466         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 467         rk_clrsetreg(&grf->mac_con[1],
 468                      RK3328_RMII_MODE_MASK |
 469                      RK3328_GMAC_PHY_INTF_SEL_MASK |
 470                      RK3328_RXCLK_DLY_ENA_GMAC_MASK |
 471                      RK3328_TXCLK_DLY_ENA_GMAC_MASK,
 472                      RK3328_GMAC_PHY_INTF_SEL_RGMII |
 473                      DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
 474
 475         rk_clrsetreg(&grf->mac_con[0],
 476                      RK3328_CLK_RX_DL_CFG_GMAC_MASK |
 477                      RK3328_CLK_TX_DL_CFG_GMAC_MASK,
 478                      pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
 479                      pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
 480 }
 481
 482 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 483 {
 484         struct rk3368_grf *grf;
 485         enum {
 486                 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
 487                 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
 488                 RK3368_RMII_MODE_MASK  = BIT(6),
 489                 RK3368_RMII_MODE       = BIT(6),
 490         };
 491         enum {
 492                 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
 493                 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
 494                 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
 495                 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
 496                 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
 497                 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
 498                 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
 499                 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
 500                 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
 501                 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
 502         };
 503
 504         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 505         rk_clrsetreg(&grf->soc_con15,
 506                      RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
 507                      RK3368_GMAC_PHY_INTF_SEL_RGMII);
 508
 509         rk_clrsetreg(&grf->soc_con16,
 510                      RK3368_RXCLK_DLY_ENA_GMAC_MASK |
 511                      RK3368_TXCLK_DLY_ENA_GMAC_MASK |
 512                      RK3368_CLK_RX_DL_CFG_GMAC_MASK |
 513                      RK3368_CLK_TX_DL_CFG_GMAC_MASK,
 514                      DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) |
 515                      pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
 516                      pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
 517 }
 518
 519 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 520 {
 521         struct rk3399_grf_regs *grf;
 522
 523         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 524
 525         rk_clrsetreg(&grf->soc_con5,
 526                      RK3399_GMAC_PHY_INTF_SEL_MASK,
 527                      RK3399_GMAC_PHY_INTF_SEL_RGMII);
 528
 529         rk_clrsetreg(&grf->soc_con6,
 530                      RK3399_RXCLK_DLY_ENA_GMAC_MASK |
 531                      RK3399_TXCLK_DLY_ENA_GMAC_MASK |
 532                      RK3399_CLK_RX_DL_CFG_GMAC_MASK |
 533                      RK3399_CLK_TX_DL_CFG_GMAC_MASK,
 534                      DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) |
 535                      pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
 536                      pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
 537 }
 538
 539 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
 540 {
 541         struct rv1108_grf *grf;
 542
 543         enum {
 544                 RV1108_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
 545                 RV1108_GMAC_PHY_INTF_SEL_RMII  = 4 << 4,
 546         };
 547
 548         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 549         rk_clrsetreg(&grf->gmac_con0,
 550                      RV1108_GMAC_PHY_INTF_SEL_MASK,
 551                      RV1108_GMAC_PHY_INTF_SEL_RMII);
 552 }
 553
 554 static int gmac_rockchip_probe(struct udevice *dev)
 555 {
 556         struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
 557         struct rk_gmac_ops *ops =
 558                 (struct rk_gmac_ops *)dev_get_driver_data(dev);
 559         struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
 560         struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
 561         struct clk clk;
 562         ulong rate;
 563         int ret;
 564
 565         ret = clk_set_defaults(dev, 0);
 566         if (ret)
 567                 debug("%s clk_set_defaults failed %d\n", __func__, ret);
 568
 569         ret = clk_get_by_index(dev, 0, &clk);
 570         if (ret)
 571                 return ret;
 572
 573         switch (eth_pdata->phy_interface) {
 574         case PHY_INTERFACE_MODE_RGMII:
 575                 /* Set to RGMII mode */
 576                 if (ops->set_to_rgmii)
 577                         ops->set_to_rgmii(pdata);
 578                 else
 579                         return -EPERM;
 580
 581                 /*
 582                  * If the gmac clock is from internal pll, need to set and
 583                  * check the return value for gmac clock at RGMII mode. If
 584                  * the gmac clock is from external source, the clock rate
 585                  * is not set, because of it is bypassed.
 586                  */
 587
 588                 if (!pdata->clock_input) {
 589                         rate = clk_set_rate(&clk, 125000000);
 590                         if (rate != 125000000)
 591                                 return -EINVAL;
 592                 }
 593                 break;
 594
 595         case PHY_INTERFACE_MODE_RGMII_ID:
 596                 /* Set to RGMII mode */
 597                 if (ops->set_to_rgmii) {
 598                         pdata->tx_delay = 0;
 599                         pdata->rx_delay = 0;
 600                         ops->set_to_rgmii(pdata);
 601                 } else
 602                         return -EPERM;
 603
 604                 if (!pdata->clock_input) {
 605                         rate = clk_set_rate(&clk, 125000000);
 606                         if (rate != 125000000)
 607                                 return -EINVAL;
 608                 }
 609                 break;
 610
 611         case PHY_INTERFACE_MODE_RMII:
 612                 /* Set to RMII mode */
 613                 if (ops->set_to_rmii)
 614                         ops->set_to_rmii(pdata);
 615                 else
 616                         return -EPERM;
 617
 618                 if (!pdata->clock_input) {
 619                         rate = clk_set_rate(&clk, 50000000);
 620                         if (rate != 50000000)
 621                                 return -EINVAL;
 622                 }
 623                 break;
 624
 625         case PHY_INTERFACE_MODE_RGMII_RXID:
 626                  /* Set to RGMII_RXID mode */
 627                 if (ops->set_to_rgmii) {
 628                         pdata->tx_delay = 0;
 629                         ops->set_to_rgmii(pdata);
 630                 } else
 631                         return -EPERM;
 632
 633                 if (!pdata->clock_input) {
 634                         rate = clk_set_rate(&clk, 125000000);
 635                         if (rate != 125000000)
 636                                 return -EINVAL;
 637                 }
 638                 break;
 639
 640         case PHY_INTERFACE_MODE_RGMII_TXID:
 641                 /* Set to RGMII_TXID mode */
 642                 if (ops->set_to_rgmii) {
 643                         pdata->rx_delay = 0;
 644                         ops->set_to_rgmii(pdata);
 645                 } else
 646                         return -EPERM;
 647
 648                 if (!pdata->clock_input) {
 649                         rate = clk_set_rate(&clk, 125000000);
 650                         if (rate != 125000000)
 651                                 return -EINVAL;
 652                 }
 653                 break;
 654
 655         default:
 656                 debug("NO interface defined!\n");
 657                 return -ENXIO;
 658         }
 659
 660         return designware_eth_probe(dev);
 661 }
 662
 663 static int gmac_rockchip_eth_start(struct udevice *dev)
 664 {
 665         struct eth_pdata *pdata = dev_get_platdata(dev);
 666         struct dw_eth_dev *priv = dev_get_priv(dev);
 667         struct rk_gmac_ops *ops =
 668                 (struct rk_gmac_ops *)dev_get_driver_data(dev);
 669         int ret;
 670
 671         ret = designware_eth_init(priv, pdata->enetaddr);
 672         if (ret)
 673                 return ret;
 674         ret = ops->fix_mac_speed(priv);
 675         if (ret)
 676                 return ret;
 677         ret = designware_eth_enable(priv);
 678         if (ret)
 679                 return ret;
 680
 681         return 0;
 682 }
 683
 684 const struct eth_ops gmac_rockchip_eth_ops = {
 685         .start                  = gmac_rockchip_eth_start,
 686         .send                   = designware_eth_send,
 687         .recv                   = designware_eth_recv,
 688         .free_pkt               = designware_eth_free_pkt,
 689         .stop                   = designware_eth_stop,
 690         .write_hwaddr           = designware_eth_write_hwaddr,
 691 };
 692
 693 const struct rk_gmac_ops px30_gmac_ops = {
 694         .fix_mac_speed = px30_gmac_fix_mac_speed,
 695         .set_to_rmii = px30_gmac_set_to_rmii,
 696 };
 697
 698 const struct rk_gmac_ops rk3228_gmac_ops = {
 699         .fix_mac_speed = rk3228_gmac_fix_mac_speed,
 700         .set_to_rgmii = rk3228_gmac_set_to_rgmii,
 701 };
 702
 703 const struct rk_gmac_ops rk3288_gmac_ops = {
 704         .fix_mac_speed = rk3288_gmac_fix_mac_speed,
 705         .set_to_rgmii = rk3288_gmac_set_to_rgmii,
 706 };
 707
 708 const struct rk_gmac_ops rk3308_gmac_ops = {
 709         .fix_mac_speed = rk3308_gmac_fix_mac_speed,
 710         .set_to_rmii = rk3308_gmac_set_to_rmii,
 711 };
 712
 713 const struct rk_gmac_ops rk3328_gmac_ops = {
 714         .fix_mac_speed = rk3328_gmac_fix_mac_speed,
 715         .set_to_rgmii = rk3328_gmac_set_to_rgmii,
 716 };
 717
 718 const struct rk_gmac_ops rk3368_gmac_ops = {
 719         .fix_mac_speed = rk3368_gmac_fix_mac_speed,
 720         .set_to_rgmii = rk3368_gmac_set_to_rgmii,
 721 };
 722
 723 const struct rk_gmac_ops rk3399_gmac_ops = {
 724         .fix_mac_speed = rk3399_gmac_fix_mac_speed,
 725         .set_to_rgmii = rk3399_gmac_set_to_rgmii,
 726 };
 727
 728 const struct rk_gmac_ops rv1108_gmac_ops = {
 729         .fix_mac_speed = rv1108_set_rmii_speed,
 730         .set_to_rmii = rv1108_gmac_set_to_rmii,
 731 };
 732
 733 static const struct udevice_id rockchip_gmac_ids[] = {
 734         { .compatible = "rockchip,px30-gmac",
 735           .data = (ulong)&px30_gmac_ops },
 736         { .compatible = "rockchip,rk3228-gmac",
 737           .data = (ulong)&rk3228_gmac_ops },
 738         { .compatible = "rockchip,rk3288-gmac",
 739           .data = (ulong)&rk3288_gmac_ops },
 740         { .compatible = "rockchip,rk3308-mac",
 741           .data = (ulong)&rk3308_gmac_ops },
 742         { .compatible = "rockchip,rk3328-gmac",
 743           .data = (ulong)&rk3328_gmac_ops },
 744         { .compatible = "rockchip,rk3368-gmac",
 745           .data = (ulong)&rk3368_gmac_ops },
 746         { .compatible = "rockchip,rk3399-gmac",
 747           .data = (ulong)&rk3399_gmac_ops },
 748         { .compatible = "rockchip,rv1108-gmac",
 749           .data = (ulong)&rv1108_gmac_ops },
 750         { }
 751 };
 752
 753 U_BOOT_DRIVER(eth_gmac_rockchip) = {
 754         .name   = "gmac_rockchip",
 755         .id     = UCLASS_ETH,
 756         .of_match = rockchip_gmac_ids,
 757         .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
 758         .probe  = gmac_rockchip_probe,
 759         .ops    = &gmac_rockchip_eth_ops,
 760         .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
 761         .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
 762         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 763 };