1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
5 * Rockchip GMAC ethernet IP driver for U-Boot
14 #include <asm/arch/periph.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/grf_rk322x.h>
18 #include <asm/arch/grf_rk3288.h>
19 #include <asm/arch/grf_rk3328.h>
20 #include <asm/arch/grf_rk3368.h>
21 #include <asm/arch/grf_rk3399.h>
22 #include <asm/arch/grf_rv1108.h>
23 #include <dm/pinctrl.h>
24 #include <dt-bindings/clock/rk3288-cru.h>
25 #include "designware.h"
28 * Platform data for the gmac
30 * dw_eth_pdata: Required platform data for designware driver (must be first)
32 struct gmac_rockchip_platdata {
33 struct dw_eth_pdata dw_eth_pdata;
40 int (*fix_mac_speed)(struct dw_eth_dev *priv);
41 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
42 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
46 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
48 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
51 string = dev_read_string(dev, "clock_in_out");
52 if (!strcmp(string, "input"))
53 pdata->clock_input = true;
55 pdata->clock_input = false;
57 /* Check the new naming-style first... */
58 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
59 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
61 /* ... and fall back to the old naming style or default, if necessary */
62 if (pdata->tx_delay == -ENOENT)
63 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
64 if (pdata->rx_delay == -ENOENT)
65 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
67 return designware_eth_ofdata_to_platdata(dev);
70 static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
72 struct rk322x_grf *grf;
75 RK3228_GMAC_CLK_SEL_SHIFT = 8,
76 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8),
77 RK3228_GMAC_CLK_SEL_125M = 0 << 8,
78 RK3228_GMAC_CLK_SEL_25M = 3 << 8,
79 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8,
82 switch (priv->phydev->speed) {
84 clk = RK3228_GMAC_CLK_SEL_2_5M;
87 clk = RK3228_GMAC_CLK_SEL_25M;
90 clk = RK3228_GMAC_CLK_SEL_125M;
93 debug("Unknown phy speed: %d\n", priv->phydev->speed);
97 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
98 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
103 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
105 struct rk3288_grf *grf;
108 switch (priv->phydev->speed) {
110 clk = RK3288_GMAC_CLK_SEL_2_5M;
113 clk = RK3288_GMAC_CLK_SEL_25M;
116 clk = RK3288_GMAC_CLK_SEL_125M;
119 debug("Unknown phy speed: %d\n", priv->phydev->speed);
123 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
124 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
129 static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
131 struct rk3328_grf_regs *grf;
134 RK3328_GMAC_CLK_SEL_SHIFT = 11,
135 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11),
136 RK3328_GMAC_CLK_SEL_125M = 0 << 11,
137 RK3328_GMAC_CLK_SEL_25M = 3 << 11,
138 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11,
141 switch (priv->phydev->speed) {
143 clk = RK3328_GMAC_CLK_SEL_2_5M;
146 clk = RK3328_GMAC_CLK_SEL_25M;
149 clk = RK3328_GMAC_CLK_SEL_125M;
152 debug("Unknown phy speed: %d\n", priv->phydev->speed);
156 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
157 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
162 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
164 struct rk3368_grf *grf;
167 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
168 RK3368_GMAC_CLK_SEL_25M = 3 << 4,
169 RK3368_GMAC_CLK_SEL_125M = 0 << 4,
170 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
173 switch (priv->phydev->speed) {
175 clk = RK3368_GMAC_CLK_SEL_2_5M;
178 clk = RK3368_GMAC_CLK_SEL_25M;
181 clk = RK3368_GMAC_CLK_SEL_125M;
184 debug("Unknown phy speed: %d\n", priv->phydev->speed);
188 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
189 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
194 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
196 struct rk3399_grf_regs *grf;
199 switch (priv->phydev->speed) {
201 clk = RK3399_GMAC_CLK_SEL_2_5M;
204 clk = RK3399_GMAC_CLK_SEL_25M;
207 clk = RK3399_GMAC_CLK_SEL_125M;
210 debug("Unknown phy speed: %d\n", priv->phydev->speed);
214 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
215 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
220 static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
222 struct rv1108_grf *grf;
225 RV1108_GMAC_SPEED_MASK = BIT(2),
226 RV1108_GMAC_SPEED_10M = 0 << 2,
227 RV1108_GMAC_SPEED_100M = 1 << 2,
228 RV1108_GMAC_CLK_SEL_MASK = BIT(7),
229 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7,
230 RV1108_GMAC_CLK_SEL_25M = 1 << 7,
233 switch (priv->phydev->speed) {
235 clk = RV1108_GMAC_CLK_SEL_2_5M;
236 speed = RV1108_GMAC_SPEED_10M;
239 clk = RV1108_GMAC_CLK_SEL_25M;
240 speed = RV1108_GMAC_SPEED_100M;
243 debug("Unknown phy speed: %d\n", priv->phydev->speed);
247 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
248 rk_clrsetreg(&grf->gmac_con0,
249 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
255 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
257 struct rk322x_grf *grf;
259 RK3228_RMII_MODE_SHIFT = 10,
260 RK3228_RMII_MODE_MASK = BIT(10),
262 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
263 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
264 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
266 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
267 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
268 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
270 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
271 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
272 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
275 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
276 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
278 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
279 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
282 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
283 rk_clrsetreg(&grf->mac_con[1],
284 RK3228_RMII_MODE_MASK |
285 RK3228_GMAC_PHY_INTF_SEL_MASK |
286 RK3228_RXCLK_DLY_ENA_GMAC_MASK |
287 RK3228_TXCLK_DLY_ENA_GMAC_MASK,
288 RK3228_GMAC_PHY_INTF_SEL_RGMII |
289 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
290 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
292 rk_clrsetreg(&grf->mac_con[0],
293 RK3228_CLK_RX_DL_CFG_GMAC_MASK |
294 RK3228_CLK_TX_DL_CFG_GMAC_MASK,
295 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
296 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
299 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
301 struct rk3288_grf *grf;
303 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
304 rk_clrsetreg(&grf->soc_con1,
305 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
306 RK3288_GMAC_PHY_INTF_SEL_RGMII);
308 rk_clrsetreg(&grf->soc_con3,
309 RK3288_RXCLK_DLY_ENA_GMAC_MASK |
310 RK3288_TXCLK_DLY_ENA_GMAC_MASK |
311 RK3288_CLK_RX_DL_CFG_GMAC_MASK |
312 RK3288_CLK_TX_DL_CFG_GMAC_MASK,
313 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE |
314 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE |
315 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
316 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
319 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
321 struct rk3328_grf_regs *grf;
323 RK3328_RMII_MODE_SHIFT = 9,
324 RK3328_RMII_MODE_MASK = BIT(9),
326 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
327 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
328 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
330 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
331 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
332 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
334 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
335 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
336 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
339 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
340 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
342 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
343 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
346 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
347 rk_clrsetreg(&grf->mac_con[1],
348 RK3328_RMII_MODE_MASK |
349 RK3328_GMAC_PHY_INTF_SEL_MASK |
350 RK3328_RXCLK_DLY_ENA_GMAC_MASK |
351 RK3328_TXCLK_DLY_ENA_GMAC_MASK,
352 RK3328_GMAC_PHY_INTF_SEL_RGMII |
353 RK3328_RXCLK_DLY_ENA_GMAC_MASK |
354 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
356 rk_clrsetreg(&grf->mac_con[0],
357 RK3328_CLK_RX_DL_CFG_GMAC_MASK |
358 RK3328_CLK_TX_DL_CFG_GMAC_MASK,
359 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
360 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
363 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
365 struct rk3368_grf *grf;
367 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
368 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
369 RK3368_RMII_MODE_MASK = BIT(6),
370 RK3368_RMII_MODE = BIT(6),
373 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
374 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
375 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
376 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
377 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
378 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
379 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
380 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
381 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
382 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
385 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
386 rk_clrsetreg(&grf->soc_con15,
387 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
388 RK3368_GMAC_PHY_INTF_SEL_RGMII);
390 rk_clrsetreg(&grf->soc_con16,
391 RK3368_RXCLK_DLY_ENA_GMAC_MASK |
392 RK3368_TXCLK_DLY_ENA_GMAC_MASK |
393 RK3368_CLK_RX_DL_CFG_GMAC_MASK |
394 RK3368_CLK_TX_DL_CFG_GMAC_MASK,
395 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
396 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
397 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
398 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
401 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
403 struct rk3399_grf_regs *grf;
405 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
407 rk_clrsetreg(&grf->soc_con5,
408 RK3399_GMAC_PHY_INTF_SEL_MASK,
409 RK3399_GMAC_PHY_INTF_SEL_RGMII);
411 rk_clrsetreg(&grf->soc_con6,
412 RK3399_RXCLK_DLY_ENA_GMAC_MASK |
413 RK3399_TXCLK_DLY_ENA_GMAC_MASK |
414 RK3399_CLK_RX_DL_CFG_GMAC_MASK |
415 RK3399_CLK_TX_DL_CFG_GMAC_MASK,
416 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE |
417 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE |
418 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
419 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
422 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
424 struct rv1108_grf *grf;
427 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
428 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,
431 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
432 rk_clrsetreg(&grf->gmac_con0,
433 RV1108_GMAC_PHY_INTF_SEL_MASK,
434 RV1108_GMAC_PHY_INTF_SEL_RMII);
437 static int gmac_rockchip_probe(struct udevice *dev)
439 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
440 struct rk_gmac_ops *ops =
441 (struct rk_gmac_ops *)dev_get_driver_data(dev);
442 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
443 struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
448 ret = clk_get_by_index(dev, 0, &clk);
452 switch (eth_pdata->phy_interface) {
453 case PHY_INTERFACE_MODE_RGMII:
455 * If the gmac clock is from internal pll, need to set and
456 * check the return value for gmac clock at RGMII mode. If
457 * the gmac clock is from external source, the clock rate
458 * is not set, because of it is bypassed.
460 if (!pdata->clock_input) {
461 rate = clk_set_rate(&clk, 125000000);
462 if (rate != 125000000)
466 /* Set to RGMII mode */
467 if (ops->set_to_rgmii)
468 ops->set_to_rgmii(pdata);
473 case PHY_INTERFACE_MODE_RMII:
474 /* The commet is the same as RGMII mode */
475 if (!pdata->clock_input) {
476 rate = clk_set_rate(&clk, 50000000);
477 if (rate != 50000000)
481 /* Set to RMII mode */
482 if (ops->set_to_rmii)
483 ops->set_to_rmii(pdata);
489 debug("NO interface defined!\n");
493 return designware_eth_probe(dev);
496 static int gmac_rockchip_eth_start(struct udevice *dev)
498 struct eth_pdata *pdata = dev_get_platdata(dev);
499 struct dw_eth_dev *priv = dev_get_priv(dev);
500 struct rk_gmac_ops *ops =
501 (struct rk_gmac_ops *)dev_get_driver_data(dev);
504 ret = designware_eth_init(priv, pdata->enetaddr);
507 ret = ops->fix_mac_speed(priv);
510 ret = designware_eth_enable(priv);
517 const struct eth_ops gmac_rockchip_eth_ops = {
518 .start = gmac_rockchip_eth_start,
519 .send = designware_eth_send,
520 .recv = designware_eth_recv,
521 .free_pkt = designware_eth_free_pkt,
522 .stop = designware_eth_stop,
523 .write_hwaddr = designware_eth_write_hwaddr,
526 const struct rk_gmac_ops rk3228_gmac_ops = {
527 .fix_mac_speed = rk3228_gmac_fix_mac_speed,
528 .set_to_rgmii = rk3228_gmac_set_to_rgmii,
531 const struct rk_gmac_ops rk3288_gmac_ops = {
532 .fix_mac_speed = rk3288_gmac_fix_mac_speed,
533 .set_to_rgmii = rk3288_gmac_set_to_rgmii,
536 const struct rk_gmac_ops rk3328_gmac_ops = {
537 .fix_mac_speed = rk3328_gmac_fix_mac_speed,
538 .set_to_rgmii = rk3328_gmac_set_to_rgmii,
541 const struct rk_gmac_ops rk3368_gmac_ops = {
542 .fix_mac_speed = rk3368_gmac_fix_mac_speed,
543 .set_to_rgmii = rk3368_gmac_set_to_rgmii,
546 const struct rk_gmac_ops rk3399_gmac_ops = {
547 .fix_mac_speed = rk3399_gmac_fix_mac_speed,
548 .set_to_rgmii = rk3399_gmac_set_to_rgmii,
551 const struct rk_gmac_ops rv1108_gmac_ops = {
552 .fix_mac_speed = rv1108_set_rmii_speed,
553 .set_to_rmii = rv1108_gmac_set_to_rmii,
556 static const struct udevice_id rockchip_gmac_ids[] = {
557 { .compatible = "rockchip,rk3228-gmac",
558 .data = (ulong)&rk3228_gmac_ops },
559 { .compatible = "rockchip,rk3288-gmac",
560 .data = (ulong)&rk3288_gmac_ops },
561 { .compatible = "rockchip,rk3328-gmac",
562 .data = (ulong)&rk3328_gmac_ops },
563 { .compatible = "rockchip,rk3368-gmac",
564 .data = (ulong)&rk3368_gmac_ops },
565 { .compatible = "rockchip,rk3399-gmac",
566 .data = (ulong)&rk3399_gmac_ops },
567 { .compatible = "rockchip,rv1108-gmac",
568 .data = (ulong)&rv1108_gmac_ops },
572 U_BOOT_DRIVER(eth_gmac_rockchip) = {
573 .name = "gmac_rockchip",
575 .of_match = rockchip_gmac_ids,
576 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
577 .probe = gmac_rockchip_probe,
578 .ops = &gmac_rockchip_eth_ops,
579 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
580 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
581 .flags = DM_FLAG_ALLOC_PRIV_DMA,