1 // SPDX-License-Identifier: GPL-2.0+
3 * Faraday FTGMAC100 Ethernet
5 * (C) Copyright 2009 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
8 * (C) Copyright 2010 Andes Technology
9 * Macpaul Lin <macpaul@andestech.com>
17 #include <asm/dma-mapping.h>
18 #include <linux/mii.h>
20 #include "ftgmac100.h"
23 #define CFG_XBUF_SIZE 1536
25 /* RBSR - hw default init value is also 0x640 */
26 #define RBSR_DEFAULT_VALUE 0x640
28 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
29 #define PKTBUFSTX 4 /* must be power of 2 */
31 struct ftgmac100_data {
33 struct ftgmac100_txdes *txdes;
35 struct ftgmac100_rxdes *rxdes;
42 * struct mii_bus functions
44 static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr,
47 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
51 phycr = readl(&ftgmac100->phycr);
53 /* preserve MDC cycle threshold */
54 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
56 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
57 | FTGMAC100_PHYCR_REGAD(regnum)
58 | FTGMAC100_PHYCR_MIIRD;
60 writel(phycr, &ftgmac100->phycr);
62 for (i = 0; i < 10; i++) {
63 phycr = readl(&ftgmac100->phycr);
65 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
68 data = readl(&ftgmac100->phydata);
69 return FTGMAC100_PHYDATA_MIIRDATA(data);
75 debug("mdio read timed out\n");
79 static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr,
80 int regnum, u16 value)
82 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
87 phycr = readl(&ftgmac100->phycr);
89 /* preserve MDC cycle threshold */
90 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
92 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
93 | FTGMAC100_PHYCR_REGAD(regnum)
94 | FTGMAC100_PHYCR_MIIWR;
96 data = FTGMAC100_PHYDATA_MIIWDATA(value);
98 writel(data, &ftgmac100->phydata);
99 writel(phycr, &ftgmac100->phycr);
101 for (i = 0; i < 10; i++) {
102 phycr = readl(&ftgmac100->phycr);
104 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) {
105 debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \
106 "phy_addr: %x\n", phy_addr);
113 debug("mdio write timed out\n");
117 int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value)
119 *value = ftgmac100_mdiobus_read(dev , addr, reg);
127 int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value)
129 if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1)
135 static int ftgmac100_phy_reset(struct eth_device *dev)
137 struct ftgmac100_data *priv = dev->priv;
141 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
143 ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv);
145 printf("%s: Starting autonegotiation...\n", dev->name);
147 ftgmac100_phy_write(dev, priv->phy_addr,
148 MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
150 for (i = 0; i < 100000 / 100; i++) {
151 ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
153 if (status & BMSR_ANEGCOMPLETE)
158 if (status & BMSR_ANEGCOMPLETE) {
159 printf("%s: Autonegotiation complete\n", dev->name);
161 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
169 static int ftgmac100_phy_init(struct eth_device *dev)
171 struct ftgmac100_data *priv = dev->priv;
174 u16 phy_id, status, adv, lpa, stat_ge;
175 int media, speed, duplex;
178 /* Check if the PHY is up to snuff... */
179 for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) {
181 ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id);
184 * When it is unable to found PHY,
185 * the interface usually return 0xffff or 0x0000
187 if (phy_id != 0xffff && phy_id != 0x0) {
188 printf("%s: found PHY at 0x%02x\n",
189 dev->name, phy_addr);
190 priv->phy_addr = phy_addr;
195 if (phy_id == 0xffff || phy_id == 0x0) {
196 printf("%s: no PHY present\n", dev->name);
200 ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
202 if (!(status & BMSR_LSTATUS)) {
203 /* Try to re-negotiate if we don't have link already. */
204 ftgmac100_phy_reset(dev);
206 for (i = 0; i < 100000 / 100; i++) {
207 ftgmac100_phy_read(dev, priv->phy_addr,
209 if (status & BMSR_LSTATUS)
215 if (!(status & BMSR_LSTATUS)) {
216 printf("%s: link down\n", dev->name);
220 #ifdef CONFIG_FTGMAC100_EGIGA
221 /* 1000 Base-T Status Register */
222 ftgmac100_phy_read(dev, priv->phy_addr,
223 MII_STAT1000, &stat_ge);
225 speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF)
228 duplex = ((stat_ge & LPA_1000FULL)
231 if (speed) { /* Speed is 1000 */
232 printf("%s: link up, 1000bps %s-duplex\n",
233 dev->name, duplex ? "full" : "half");
238 ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv);
239 ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa);
241 media = mii_nway_result(lpa & adv);
242 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0);
243 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
245 printf("%s: link up, %sMbps %s-duplex\n",
246 dev->name, speed ? "100" : "10", duplex ? "full" : "half");
251 static int ftgmac100_update_link_speed(struct eth_device *dev)
253 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
254 struct ftgmac100_data *priv = dev->priv;
256 unsigned short stat_fe;
257 unsigned short stat_ge;
260 #ifdef CONFIG_FTGMAC100_EGIGA
261 /* 1000 Base-T Status Register */
262 ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge);
265 ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe);
267 if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */
270 /* read MAC control register and clear related bits */
271 maccr = readl(&ftgmac100->maccr) &
272 ~(FTGMAC100_MACCR_GIGA_MODE |
273 FTGMAC100_MACCR_FAST_MODE |
274 FTGMAC100_MACCR_FULLDUP);
276 #ifdef CONFIG_FTGMAC100_EGIGA
277 if (stat_ge & LPA_1000FULL) {
278 /* set gmac for 1000BaseTX and Full Duplex */
279 maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP;
282 if (stat_ge & LPA_1000HALF) {
283 /* set gmac for 1000BaseTX and Half Duplex */
284 maccr |= FTGMAC100_MACCR_GIGA_MODE;
288 if (stat_fe & BMSR_100FULL) {
289 /* set MII for 100BaseTX and Full Duplex */
290 maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP;
293 if (stat_fe & BMSR_10FULL) {
294 /* set MII for 10BaseT and Full Duplex */
295 maccr |= FTGMAC100_MACCR_FULLDUP;
298 if (stat_fe & BMSR_100HALF) {
299 /* set MII for 100BaseTX and Half Duplex */
300 maccr |= FTGMAC100_MACCR_FAST_MODE;
303 if (stat_fe & BMSR_10HALF) {
304 /* set MII for 10BaseT and Half Duplex */
305 /* we have already clear these bits, do nothing */
309 /* update MII config into maccr */
310 writel(maccr, &ftgmac100->maccr);
318 static void ftgmac100_reset(struct eth_device *dev)
320 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
322 debug("%s()\n", __func__);
324 writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr);
326 while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
333 static void ftgmac100_set_mac(struct eth_device *dev,
334 const unsigned char *mac)
336 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
337 unsigned int maddr = mac[0] << 8 | mac[1];
338 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
340 debug("%s(%x %x)\n", __func__, maddr, laddr);
342 writel(maddr, &ftgmac100->mac_madr);
343 writel(laddr, &ftgmac100->mac_ladr);
346 static void ftgmac100_set_mac_from_env(struct eth_device *dev)
348 eth_env_get_enetaddr("ethaddr", dev->enetaddr);
350 ftgmac100_set_mac(dev, dev->enetaddr);
354 * disable transmitter, receiver
356 static void ftgmac100_halt(struct eth_device *dev)
358 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
360 debug("%s()\n", __func__);
362 writel(0, &ftgmac100->maccr);
365 static int ftgmac100_init(struct eth_device *dev, bd_t *bd)
367 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
368 struct ftgmac100_data *priv = dev->priv;
369 struct ftgmac100_txdes *txdes;
370 struct ftgmac100_rxdes *rxdes;
375 debug("%s()\n", __func__);
378 txdes = dma_alloc_coherent(
379 sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma);
381 panic("ftgmac100: out of memory\n");
382 memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
388 rxdes = dma_alloc_coherent(
389 sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma);
391 panic("ftgmac100: out of memory\n");
392 memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
397 /* set the ethernet address */
398 ftgmac100_set_mac_from_env(dev);
400 /* disable all interrupts */
401 writel(0, &ftgmac100->ier);
403 /* initialize descriptors */
407 txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
408 rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
410 for (i = 0; i < PKTBUFSTX; i++) {
412 if (!txdes[i].txdes2) {
413 buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
415 panic("ftgmac100: out of memory\n");
416 txdes[i].txdes3 = virt_to_phys(buf);
417 txdes[i].txdes2 = (uint)buf;
422 for (i = 0; i < PKTBUFSRX; i++) {
424 if (!rxdes[i].rxdes2) {
425 buf = net_rx_packets[i];
426 rxdes[i].rxdes3 = virt_to_phys(buf);
427 rxdes[i].rxdes2 = (uint)buf;
429 rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
433 writel(priv->txdes_dma, &ftgmac100->txr_badr);
436 writel(priv->rxdes_dma, &ftgmac100->rxr_badr);
438 /* poll receive descriptor automatically */
439 writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
441 /* config receive buffer size register */
442 writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr);
444 /* enable transmitter, receiver */
445 maccr = FTGMAC100_MACCR_TXMAC_EN |
446 FTGMAC100_MACCR_RXMAC_EN |
447 FTGMAC100_MACCR_TXDMA_EN |
448 FTGMAC100_MACCR_RXDMA_EN |
449 FTGMAC100_MACCR_CRC_APD |
450 FTGMAC100_MACCR_FULLDUP |
451 FTGMAC100_MACCR_RX_RUNT |
452 FTGMAC100_MACCR_RX_BROADPKT;
454 writel(maccr, &ftgmac100->maccr);
456 if (!ftgmac100_phy_init(dev)) {
457 if (!ftgmac100_update_link_speed(dev))
465 * Get a data block via Ethernet
467 static int ftgmac100_recv(struct eth_device *dev)
469 struct ftgmac100_data *priv = dev->priv;
470 struct ftgmac100_rxdes *curr_des;
471 unsigned short rxlen;
473 curr_des = &priv->rxdes[priv->rx_index];
475 if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
478 if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
479 FTGMAC100_RXDES0_CRC_ERR |
480 FTGMAC100_RXDES0_FTL |
481 FTGMAC100_RXDES0_RUNT |
482 FTGMAC100_RXDES0_RX_ODD_NB)) {
486 rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
488 debug("%s(): RX buffer %d, %x received\n",
489 __func__, priv->rx_index, rxlen);
491 /* invalidate d-cache */
492 dma_map_single((void *)curr_des->rxdes2, rxlen, DMA_FROM_DEVICE);
494 /* pass the packet up to the protocol layers. */
495 net_process_received_packet((void *)curr_des->rxdes2, rxlen);
497 /* release buffer to DMA */
498 curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
500 priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
506 * Send a data block via Ethernet
508 static int ftgmac100_send(struct eth_device *dev, void *packet, int length)
510 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
511 struct ftgmac100_data *priv = dev->priv;
512 struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
514 if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
515 debug("%s(): no TX descriptor available\n", __func__);
519 debug("%s(%x, %x)\n", __func__, (int)packet, length);
521 length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
523 memcpy((void *)curr_des->txdes2, (void *)packet, length);
524 dma_map_single((void *)curr_des->txdes2, length, DMA_TO_DEVICE);
526 /* only one descriptor on TXBUF */
527 curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
528 curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
529 FTGMAC100_TXDES0_LTS |
530 FTGMAC100_TXDES0_TXBUF_SIZE(length) |
531 FTGMAC100_TXDES0_TXDMA_OWN ;
534 writel(1, &ftgmac100->txpd);
536 debug("%s(): packet sent\n", __func__);
538 priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
543 int ftgmac100_initialize(bd_t *bd)
545 struct eth_device *dev;
546 struct ftgmac100_data *priv;
548 dev = malloc(sizeof *dev);
550 printf("%s(): failed to allocate dev\n", __func__);
554 /* Transmit and receive descriptors should align to 16 bytes */
555 priv = memalign(16, sizeof(struct ftgmac100_data));
557 printf("%s(): failed to allocate priv\n", __func__);
561 memset(dev, 0, sizeof(*dev));
562 memset(priv, 0, sizeof(*priv));
564 strcpy(dev->name, "FTGMAC100");
565 dev->iobase = CONFIG_FTGMAC100_BASE;
566 dev->init = ftgmac100_init;
567 dev->halt = ftgmac100_halt;
568 dev->send = ftgmac100_send;
569 dev->recv = ftgmac100_recv;
574 ftgmac100_reset(dev);