1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * (C) Copyright 2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
21 #include <linux/delay.h>
22 #include <linux/mii.h>
23 #include <asm/immap.h>
24 #include <asm/fsl_mcdmafec.h>
31 /* Ethernet Transmit and Receive Buffers */
32 #define DBUF_LENGTH 1520
33 #define PKT_MAXBUF_SIZE 1518
34 #define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
36 /* RxBD bits definitions */
37 #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
38 BD_ENET_RX_OV | BD_ENET_RX_TR)
40 DECLARE_GLOBAL_DATA_PTR;
42 static void init_eth_info(struct fec_info_dma *info)
44 /* setup Receive and Transmit buffer descriptor */
45 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
49 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
51 info->rxbd = (cbd_t *)DBUF_LENGTH;
53 info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
54 tmp = (u32)info->rxbd;
56 (cbd_t *)((u32)info->txbd + tmp +
57 (PKTBUFSRX * sizeof(cbd_t)));
58 tmp = (u32)info->txbd;
60 (char *)((u32)info->txbuf + tmp +
61 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
62 tmp = (u32)info->txbuf;
65 (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
66 (PKTBUFSRX * sizeof(cbd_t)));
68 (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
69 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
71 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
75 printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
77 info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
80 static void fec_halt(struct udevice *dev)
82 struct fec_info_dma *info = dev->priv;
83 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
86 /* issue graceful stop command to the FEC transmitter if necessary */
87 fecp->tcr |= FEC_TCR_GTS;
89 /* wait for graceful stop to register */
90 while ((counter--) && (!(fecp->eir & FEC_EIR_GRA)))
93 /* Disable DMA tasks */
94 MCD_killDma(info->tx_task);
95 MCD_killDma(info->rx_task);
97 /* Disable the Ethernet Controller */
98 fecp->ecr &= ~FEC_ECR_ETHER_EN;
100 /* Clear FIFO status registers */
101 fecp->rfsr &= FIFO_ERRSTAT;
102 fecp->tfsr &= FIFO_ERRSTAT;
104 fecp->frst = 0x01000000;
106 /* Issue a reset command to the FEC chip */
107 fecp->ecr |= FEC_ECR_RESET;
109 /* wait at least 20 clock cycles */
113 printf("Ethernet task stopped\n");
118 static void dbg_fec_regs(struct eth_device *dev)
120 struct fec_info_dma *info = dev->priv;
121 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
124 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
125 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
126 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
127 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
128 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
129 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
130 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
131 printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
132 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
133 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
134 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
135 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
136 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
137 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
138 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
139 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
140 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
141 printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
142 printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
143 printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
144 printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
145 printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
146 printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
147 printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
148 printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
149 printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
150 printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
151 printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
152 printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
153 printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
154 printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
155 printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
156 printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
157 printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
158 printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
162 static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd)
166 if ((dup_spd >> 16) == FULL) {
167 /* Set maximum frame length */
168 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
169 FEC_RCR_PROM | 0x100;
170 fecp->tcr = FEC_TCR_FDEN;
172 /* Half duplex mode */
173 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
174 FEC_RCR_MII_MODE | FEC_RCR_DRT;
175 fecp->tcr &= ~FEC_TCR_FDEN;
178 if ((dup_spd & 0xFFFF) == _100BASET) {
182 bd->bi_ethspeed = 100;
187 bd->bi_ethspeed = 10;
191 static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac)
193 u8 curr_byte; /* byte for which to compute the CRC */
194 int byte; /* loop - counter */
195 int bit; /* loop - counter */
196 u32 crc = 0xffffffff; /* initial value */
198 for (byte = 0; byte < 6; byte++) {
199 curr_byte = mac[byte];
200 for (bit = 0; bit < 8; bit++) {
201 if ((curr_byte & 0x01) ^ (crc & 0x01)) {
203 crc = crc ^ 0xedb88320;
213 /* Set individual hash table register */
215 fecp->ialr = (1 << (crc - 32));
219 fecp->iaur = (1 << crc);
222 /* Set physical address */
223 fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
224 fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
226 /* Clear multicast address hash table */
231 static int fec_init(struct udevice *dev)
233 struct fec_info_dma *info = dev->priv;
234 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
239 printf("fec_init: iobase 0x%08x ...\n", info->iobase);
242 fecpin_setclear(info, 1);
245 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
246 defined (CONFIG_SYS_DISCOVER_PHY)
249 set_fec_duplex_speed(fecp, info->dup_spd);
251 #ifndef CONFIG_SYS_DISCOVER_PHY
252 set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED);
253 #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
254 #endif /* CONFIG_CMD_MII || CONFIG_MII */
256 /* We use strictly polling mode only */
259 /* Clear any pending interrupt */
260 fecp->eir = 0xffffffff;
262 /* Set station address */
263 if (info->index == 0)
264 rval = eth_env_get_enetaddr("ethaddr", enetaddr);
266 rval = eth_env_get_enetaddr("eth1addr", enetaddr);
269 puts("Please set a valid MAC address\n");
273 fec_set_hwaddr(fecp, enetaddr);
275 /* Set Opcode/Pause Duration Register */
276 fecp->opd = 0x00010020;
278 /* Setup Buffers and Buffer Descriptors */
282 /* Setup Receiver Buffer Descriptors (13.14.24.18)
283 * Settings: Empty, Wrap */
284 for (i = 0; i < PKTBUFSRX; i++) {
285 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
286 info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
287 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
289 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
291 /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
292 * Settings: Last, Tx CRC */
293 for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
294 info->txbd[i].cbd_sc = 0;
295 info->txbd[i].cbd_datlen = 0;
296 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
298 info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
300 info->used_tbd_idx = 0;
301 info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER;
303 /* Set Rx FIFO alarm and granularity value */
304 fecp->rfcr = 0x0c000000;
305 fecp->rfar = 0x0000030c;
307 /* Set Tx FIFO granularity value */
308 fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
309 fecp->tfar = 0x00000080;
312 fecp->ctcwr = 0x03000000;
314 /* Enable DMA receive task */
315 MCD_startDma(info->rx_task,
324 (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),
325 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
328 /* Enable DMA tx task with no ready buffer descriptors */
329 MCD_startDma(info->tx_task,
338 (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),
339 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
342 /* Now enable the transmit and receive processing */
343 fecp->ecr |= FEC_ECR_ETHER_EN;
348 static int mcdmafec_init(struct udevice *dev)
350 return fec_init(dev);
353 static int mcdmafec_send(struct udevice *dev, void *packet, int length)
355 struct fec_info_dma *info = dev->priv;
356 cbd_t *p_tbd, *p_used_tbd;
359 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
361 /* process all the consumed TBDs */
362 while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) {
363 p_used_tbd = &info->txbd[info->used_tbd_idx];
364 if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
366 printf("Cannot clean TBD %d, in use\n",
367 info->clean_tbd_num);
372 /* clean this buffer descriptor */
373 if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
374 p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
376 p_used_tbd->cbd_sc = 0;
378 /* update some indeces for a correct handling of TBD ring */
379 info->clean_tbd_num++;
380 info->used_tbd_idx = (info->used_tbd_idx + 1)
381 % CONFIG_SYS_TX_ETH_BUFFER;
384 /* Check for valid length of data. */
385 if (length > 1500 || length <= 0)
388 /* Check the number of vacant TxBDs. */
389 if (info->clean_tbd_num < 1) {
390 printf("No available TxBDs ...\n");
394 /* Get the first TxBD to send the mac header */
395 p_tbd = &info->txbd[info->tx_idx];
396 p_tbd->cbd_datlen = length;
397 p_tbd->cbd_bufaddr = (u32)packet;
398 p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
399 info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
401 /* Enable DMA transmit task */
402 MCD_continDma(info->tx_task);
404 info->clean_tbd_num -= 1;
406 /* wait until frame is sent . */
407 while (p_tbd->cbd_sc & BD_ENET_TX_READY)
410 return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
413 static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp)
415 struct fec_info_dma *info = dev->priv;
416 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
418 cbd_t *prbd = &info->rxbd[info->rx_idx];
420 int frame_length, len = 0;
422 /* Check if any critical events have happened */
427 if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
428 printf("fec_recv: error\n");
434 if (ievent & FEC_EIR_HBERR) {
435 /* Heartbeat error */
436 fecp->tcr |= FEC_TCR_GTS;
439 if (ievent & FEC_EIR_GRA) {
440 /* Graceful stop complete */
441 if (fecp->tcr & FEC_TCR_GTS) {
442 printf("fec_recv: tcr_gts\n");
444 fecp->tcr &= ~FEC_TCR_GTS;
450 if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
451 if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
452 !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
453 ((prbd->cbd_datlen - 4) > 14)) {
454 /* Get buffer address and size */
455 frame_length = prbd->cbd_datlen - 4;
457 /* Fill the buffer and pass it to upper layers */
458 net_process_received_packet((uchar *)prbd->cbd_bufaddr,
463 /* Reset buffer descriptor as empty */
464 if (info->rx_idx == (PKTBUFSRX - 1))
465 prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
467 prbd->cbd_sc = BD_ENET_RX_EMPTY;
469 prbd->cbd_datlen = PKTSIZE_ALIGN;
471 /* Now, we have an empty RxBD, restart the DMA receive task */
472 MCD_continDma(info->rx_task);
474 /* Increment BD count */
475 info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX;
481 static void mcdmafec_halt(struct udevice *dev)
486 static const struct eth_ops mcdmafec_ops = {
487 .start = mcdmafec_init,
488 .send = mcdmafec_send,
489 .recv = mcdmafec_recv,
490 .stop = mcdmafec_halt,
494 * Boot sequence, called just after mcffec_ofdata_to_platdata,
495 * as DM way, it replaces old mcffec_initialize.
497 static int mcdmafec_probe(struct udevice *dev)
499 struct fec_info_dma *info = dev->priv;
500 struct eth_pdata *pdata = dev_get_platdata(dev);
501 int node = dev_of_offset(dev);
505 info->index = dev->seq;
506 info->iobase = pdata->iobase;
507 info->miibase = pdata->iobase;
510 val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL);
512 info->rx_task = fdt32_to_cpu(*val);
514 val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL);
516 info->tx_task = fdt32_to_cpu(*val);
518 val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL);
520 info->rx_pri = fdt32_to_cpu(*val);
522 val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL);
524 info->tx_pri = fdt32_to_cpu(*val);
526 val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL);
528 info->rx_init = fdt32_to_cpu(*val);
530 val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL);
532 info->tx_init = fdt32_to_cpu(*val);
534 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
535 u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
539 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
540 info->bus = mdio_alloc();
543 strncpy(info->bus->name, dev->name, MDIO_NAME_LEN);
544 info->bus->read = mcffec_miiphy_read;
545 info->bus->write = mcffec_miiphy_write;
547 retval = mdio_register(info->bus);
555 static int mcdmafec_remove(struct udevice *dev)
557 struct fec_info_dma *priv = dev_get_priv(dev);
559 mdio_unregister(priv->bus);
560 mdio_free(priv->bus);
566 * Boot sequence, called 1st
568 static int mcdmafec_ofdata_to_platdata(struct udevice *dev)
570 struct eth_pdata *pdata = dev_get_platdata(dev);
573 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
574 /* Default to 10Mbit/s */
575 pdata->max_speed = 10;
577 val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
579 pdata->max_speed = fdt32_to_cpu(*val);
584 static const struct udevice_id mcdmafec_ids[] = {
585 { .compatible = "fsl,mcf-dma-fec" },
589 U_BOOT_DRIVER(mcffec) = {
592 .of_match = mcdmafec_ids,
593 .ofdata_to_platdata = mcdmafec_ofdata_to_platdata,
594 .probe = mcdmafec_probe,
595 .remove = mcdmafec_remove,
596 .ops = &mcdmafec_ops,
597 .priv_auto_alloc_size = sizeof(struct fec_info_dma),
598 .platdata_auto_alloc_size = sizeof(struct eth_pdata),