1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * ENETC ethernet controller driver
4 * Copyright 2017-2019 NXP
10 #define enetc_dbg(dev, fmt, args...) debug("%s:" fmt, dev->name, ##args)
12 /* PCI function IDs */
13 #define PCI_DEVICE_ID_ENETC_ETH 0xE100
14 #define PCI_DEVICE_ID_ENETC_MDIO 0xEE01
16 /* ENETC Ethernet controller registers */
17 /* Station interface register offsets */
18 #define ENETC_SIMR 0x000
19 #define ENETC_SIMR_EN BIT(31)
20 #define ENETC_SICAR0 0x040
21 /* write cache cfg: snoop, no allocate, data & BD coherent */
22 #define ENETC_SICAR_WR_CFG 0x6767
23 /* read cache cfg: coherent copy, look up, don't alloc in cache */
24 #define ENETC_SICAR_RD_CFG 0x27270000
25 #define ENETC_SIROCT 0x300
26 #define ENETC_SIRFRM 0x308
27 #define ENETC_SITOCT 0x320
28 #define ENETC_SITFRM 0x328
30 /* Rx/Tx Buffer Descriptor Ring registers */
31 enum enetc_bdr_type {TX, RX};
32 #define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 + (off))
33 #define ENETC_BDR_IDX_MASK 0xffff
35 /* Rx BDR reg offsets */
36 #define ENETC_RBMR 0x00
37 #define ENETC_RBMR_EN BIT(31)
38 #define ENETC_RBBSR 0x08
39 /* initial consumer index for Rx BDR */
40 #define ENETC_RBCIR 0x0c
41 #define ENETC_RBBAR0 0x10
42 #define ENETC_RBBAR1 0x14
43 #define ENETC_RBPIR 0x18
44 #define ENETC_RBLENR 0x20
46 /* Tx BDR reg offsets */
47 #define ENETC_TBMR 0x00
48 #define ENETC_TBMR_EN BIT(31)
49 #define ENETC_TBBAR0 0x10
50 #define ENETC_TBBAR1 0x14
51 #define ENETC_TBPIR 0x18
52 #define ENETC_TBCIR 0x1c
53 #define ENETC_TBLENR 0x20
55 /* Port registers offset */
56 #define ENETC_PORT_REGS_OFF 0x10000
59 #define ENETC_PMR 0x0000
60 #define ENETC_PMR_SI0_EN BIT(16)
61 #define ENETC_PSIPMMR 0x0018
62 #define ENETC_PSIPMAR0 0x0100
63 #define ENETC_PSIPMAR1 0x0104
64 #define ENETC_PCAPR0 0x0900
65 #define ENETC_PCAPRO_MDIO BIT(11)
66 #define ENETC_PSICFGR(n) (0x0940 + (n) * 0x10)
67 #define ENETC_PSICFGR_SET_TXBDR(val) ((val) & 0xff)
68 #define ENETC_PSICFGR_SET_RXBDR(val) (((val) & 0xff) << 16)
69 /* MAC configuration */
70 #define ENETC_PM_CC 0x8008
71 #define ENETC_PM_CC_DEFAULT 0x0810
72 #define ENETC_PM_CC_RX_TX_EN 0x8813
73 #define ENETC_PM_MAXFRM 0x8014
74 #define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN
75 #define ENETC_PM_IMDIO_BASE 0x8030
76 #define ENETC_PM_IF_MODE 0x8300
77 #define ENETC_PM_IF_MODE_RG BIT(2)
78 #define ENETC_PM_IF_MODE_AN_ENA BIT(15)
79 #define ENETC_PM_IF_IFMODE_MASK GENMASK(1, 0)
81 /* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
82 #define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER
83 #define ENETC_BD_ALIGN 128
85 /* single pair of Rx/Tx rings */
86 #define ENETC_RX_BDR_CNT 1
87 #define ENETC_TX_BDR_CNT 1
88 #define ENETC_RX_BDR_ID 0
89 #define ENETC_TX_BDR_ID 0
91 /* Tx buffer descriptor */
100 #define ENETC_TXBD_FLAGS_F BIT(15)
101 #define ENETC_POLL_TRIES 32000
103 /* Rx buffer descriptor */
105 /* SW provided BD format */
111 /* ENETC returned BD format */
114 __le16 parse_summary;
128 #define ENETC_RXBD_STATUS_R(status) (((status) >> 30) & 0x1)
129 #define ENETC_RXBD_STATUS_F(status) (((status) >> 31) & 0x1)
130 #define ENETC_RXBD_STATUS_ERRORS(status) (((status) >> 16) & 0xff)
131 #define ENETC_RXBD_STATUS(flags) ((flags) << 16)
133 /* Tx/Rx ring info */
137 /* next BD index to use */
143 /* ENETC private structure */
145 struct enetc_tx_bd *enetc_txbd;
146 union enetc_rx_bd *enetc_rxbd;
148 void *regs_base; /* base ENETC registers */
149 void *port_regs; /* base ENETC port registers */
151 /* Rx/Tx buffer descriptor rings info */
152 struct bd_ring tx_bdr;
153 struct bd_ring rx_bdr;
156 struct mii_dev imdio;
159 /* register accessors */
160 #define enetc_read_reg(x) readl((x))
161 #define enetc_write_reg(x, val) writel((val), (x))
162 #define enetc_read(priv, off) enetc_read_reg((priv)->regs_base + (off))
163 #define enetc_write(priv, off, v) \
164 enetc_write_reg((priv)->regs_base + (off), v)
166 /* port register accessors */
167 #define enetc_port_regs(priv, off) ((priv)->port_regs + (off))
168 #define enetc_read_port(priv, off) \
169 enetc_read_reg(enetc_port_regs((priv), (off)))
170 #define enetc_write_port(priv, off, v) \
171 enetc_write_reg(enetc_port_regs((priv), (off)), v)
173 /* BDR register accessors, see ENETC_BDR() */
174 #define enetc_bdr_read(priv, t, n, off) \
175 enetc_read(priv, ENETC_BDR(t, n, off))
176 #define enetc_bdr_write(priv, t, n, off, val) \
177 enetc_write(priv, ENETC_BDR(t, n, off), val)
179 /* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */
180 #define ENETC_PCS_PHY_ADDR 0
183 #define ENETC_PCS_CR 0x00
184 #define ENETC_PCS_CR_RESET_AN 0x1200
185 #define ENETC_PCS_CR_DEF_VAL 0x0140
186 #define ENETC_PCS_CR_RST BIT(15)
187 #define ENETC_PCS_DEV_ABILITY 0x04
188 #define ENETC_PCS_DEV_ABILITY_SGMII 0x4001
189 #define ENETC_PCS_DEV_ABILITY_SXGMII 0x5001
190 #define ENETC_PCS_LINK_TIMER1 0x12
191 #define ENETC_PCS_LINK_TIMER1_VAL 0x06a0
192 #define ENETC_PCS_LINK_TIMER2 0x13
193 #define ENETC_PCS_LINK_TIMER2_VAL 0x0003
194 #define ENETC_PCS_IF_MODE 0x14
195 #define ENETC_PCS_IF_MODE_SGMII BIT(0)
196 #define ENETC_PCS_IF_MODE_SGMII_AN BIT(1)
197 #define ENETC_PCS_IF_MODE_SPEED_1G BIT(3)
199 /* PCS replicator block for USXGMII */
200 #define ENETC_PCS_DEVAD_REPL 0x1f
202 /* ENETC external MDIO registers */
203 #define ENETC_MDIO_BASE 0x1c00
204 #define ENETC_MDIO_CFG 0x00
205 #define ENETC_EMDIO_CFG_C22 0x00809508
206 #define ENETC_EMDIO_CFG_C45 0x00809548
207 #define ENETC_EMDIO_CFG_RD_ER BIT(1)
208 #define ENETC_EMDIO_CFG_BSY BIT(0)
209 #define ENETC_MDIO_CTL 0x04
210 #define ENETC_MDIO_CTL_READ BIT(15)
211 #define ENETC_MDIO_DATA 0x08
212 #define ENETC_MDIO_STAT 0x0c
214 #define ENETC_MDIO_READ_ERR 0xffff
216 struct enetc_mdio_priv {
221 * these functions are implemented by ENETC_MDIO and are re-used by ENETC driver
222 * to drive serdes / internal SoC PHYs
224 int enetc_mdio_read_priv(struct enetc_mdio_priv *priv, int addr, int devad,
226 int enetc_mdio_write_priv(struct enetc_mdio_priv *priv, int addr, int devad,
229 #endif /* _ENETC_H */