1 // SPDX-License-Identifier: GPL-2.0+
3 * ENETC ethernet controller driver
4 * Copyright 2017-2019 NXP
15 #include "fsl_enetc.h"
19 * - set a more explicit name on the interface
21 static int enetc_bind(struct udevice *dev)
24 static int eth_num_devices;
27 * prefer using PCI function numbers to number interfaces, but these
28 * are only available if dts nodes are present. For PCI they are
29 * optional, handle that case too. Just in case some nodes are present
30 * and some are not, use different naming scheme - enetc-N based on
31 * PCI function # and enetc#N based on interface count
33 if (ofnode_valid(dev->node))
34 sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
36 sprintf(name, "enetc#%u", eth_num_devices++);
37 device_set_name(dev, name);
42 /* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */
43 static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
45 struct enetc_mdio_priv priv;
47 priv.regs_base = bus->priv;
48 return enetc_mdio_read_priv(&priv, addr, devad, reg);
51 static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
54 struct enetc_mdio_priv priv;
56 priv.regs_base = bus->priv;
57 return enetc_mdio_write_priv(&priv, addr, devad, reg, val);
60 /* only interfaces that can pin out through serdes have internal MDIO */
61 static bool enetc_has_imdio(struct udevice *dev)
63 struct enetc_priv *priv = dev_get_priv(dev);
65 return !!(priv->imdio.priv);
68 /* set up serdes for SGMII */
69 static int enetc_init_sgmii(struct udevice *dev)
71 struct enetc_priv *priv = dev_get_priv(dev);
75 if (!enetc_has_imdio(dev))
78 if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
82 * Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed.
83 * Although fixed speed is 1Gbps, we could be running at 2.5Gbps based
84 * on PLL configuration. Setting 1G for 2.5G here is counter intuitive
87 reg = ENETC_PCS_IF_MODE_SGMII;
88 reg |= is2500 ? ENETC_PCS_IF_MODE_SPEED_1G : ENETC_PCS_IF_MODE_SGMII_AN;
89 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
90 ENETC_PCS_IF_MODE, reg);
92 /* Dev ability - SGMII */
93 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
94 ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII);
96 /* Adjust link timer for SGMII */
97 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
98 ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL);
99 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
100 ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
102 reg = ENETC_PCS_CR_DEF_VAL;
103 reg |= is2500 ? ENETC_PCS_CR_RST : ENETC_PCS_CR_RESET_AN;
105 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
111 /* set up MAC for RGMII */
112 static int enetc_init_rgmii(struct udevice *dev)
114 struct enetc_priv *priv = dev_get_priv(dev);
117 /* enable RGMII AN */
118 if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
119 if_mode |= ENETC_PM_IF_MODE_AN_ENA;
120 enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
125 /* set up MAC and serdes for SXGMII */
126 static int enetc_init_sxgmii(struct udevice *dev)
128 struct enetc_priv *priv = dev_get_priv(dev);
131 /* set ifmode to (US)XGMII */
132 if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
133 if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
134 enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
136 if (!enetc_has_imdio(dev))
139 /* Dev ability - SXGMII */
140 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
141 ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
144 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
146 ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
151 /* Apply protocol specific configuration to MAC, serdes as needed */
152 static void enetc_start_pcs(struct udevice *dev)
154 struct enetc_priv *priv = dev_get_priv(dev);
157 priv->if_type = PHY_INTERFACE_MODE_NONE;
159 /* check internal mdio capability, not all ports need it */
160 if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) {
162 * set up internal MDIO, this is part of ETH PCI function and is
163 * used to access serdes / internal SoC PHYs.
164 * We don't currently register it as a MDIO bus as it goes away
165 * when the interface is removed, so it can't practically be
166 * used in the console.
168 priv->imdio.read = enetc_mdio_read;
169 priv->imdio.write = enetc_mdio_write;
170 priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
171 strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
174 if (!ofnode_valid(dev->node)) {
175 enetc_dbg(dev, "no enetc ofnode found, skipping PCS set-up\n");
179 if_str = ofnode_read_string(dev->node, "phy-mode");
181 priv->if_type = phy_get_interface_by_name(if_str);
184 "phy-mode property not found, defaulting to SGMII\n");
185 if (priv->if_type < 0)
186 priv->if_type = PHY_INTERFACE_MODE_NONE;
188 switch (priv->if_type) {
189 case PHY_INTERFACE_MODE_SGMII:
190 case PHY_INTERFACE_MODE_SGMII_2500:
191 enetc_init_sgmii(dev);
193 case PHY_INTERFACE_MODE_RGMII:
194 case PHY_INTERFACE_MODE_RGMII_ID:
195 case PHY_INTERFACE_MODE_RGMII_RXID:
196 case PHY_INTERFACE_MODE_RGMII_TXID:
197 enetc_init_rgmii(dev);
199 case PHY_INTERFACE_MODE_XGMII:
200 enetc_init_sxgmii(dev);
205 /* Configure the actual/external ethernet PHY, if one is found */
206 static void enetc_start_phy(struct udevice *dev)
208 struct enetc_priv *priv = dev_get_priv(dev);
209 struct udevice *miidev;
210 struct phy_device *phy;
215 if (!ofnode_valid(dev->node)) {
216 enetc_dbg(dev, "no enetc ofnode found, skipping PHY set-up\n");
220 if (ofnode_read_u32(dev->node, "phy-handle", &phandle)) {
221 enetc_dbg(dev, "phy-handle not found, skipping PHY set-up\n");
225 phy_node = ofnode_get_by_phandle(phandle);
226 if (!ofnode_valid(phy_node)) {
227 enetc_dbg(dev, "invalid phy node, skipping PHY set-up\n");
230 enetc_dbg(dev, "phy node: %s\n", ofnode_get_name(phy_node));
232 if (ofnode_read_u32(phy_node, "reg", &phy_id)) {
234 "missing reg in PHY node, skipping PHY set-up\n");
238 if (uclass_get_device_by_ofnode(UCLASS_MDIO,
239 ofnode_get_parent(phy_node),
241 enetc_dbg(dev, "can't find MDIO bus for node %s\n",
242 ofnode_get_name(ofnode_get_parent(phy_node)));
246 phy = dm_mdio_phy_connect(miidev, phy_id, dev, priv->if_type);
248 enetc_dbg(dev, "dm_mdio_phy_connect returned null\n");
252 supported = GENMASK(6, 0); /* speeds up to 1G & AN */
253 phy->advertising = phy->supported & supported;
254 phy->node = phy_node;
260 * Probe ENETC driver:
261 * - initialize port and station interface BARs
263 static int enetc_probe(struct udevice *dev)
265 struct enetc_priv *priv = dev_get_priv(dev);
267 if (ofnode_valid(dev->node) && !ofnode_is_available(dev->node)) {
268 enetc_dbg(dev, "interface disabled\n");
272 priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
273 sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
274 priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
275 sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
277 if (!priv->enetc_txbd || !priv->enetc_rxbd) {
278 /* free should be able to handle NULL, just free all pointers */
279 free(priv->enetc_txbd);
280 free(priv->enetc_rxbd);
285 /* initialize register */
286 priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
287 if (!priv->regs_base) {
288 enetc_dbg(dev, "failed to map BAR0\n");
291 priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
293 dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
299 * Remove the driver from an interface:
300 * - free up allocated memory
302 static int enetc_remove(struct udevice *dev)
304 struct enetc_priv *priv = dev_get_priv(dev);
306 free(priv->enetc_txbd);
307 free(priv->enetc_rxbd);
312 /* ENETC Port MAC address registers, accepts big-endian format */
313 static void enetc_set_primary_mac_addr(struct enetc_priv *priv, const u8 *addr)
315 u16 lower = *(const u16 *)(addr + 4);
316 u32 upper = *(const u32 *)addr;
318 enetc_write_port(priv, ENETC_PSIPMAR0, upper);
319 enetc_write_port(priv, ENETC_PSIPMAR1, lower);
322 /* Configure port parameters (# of rings, frame size, enable port) */
323 static void enetc_enable_si_port(struct enetc_priv *priv)
327 /* set Rx/Tx BDR count */
328 val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
329 val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
330 enetc_write_port(priv, ENETC_PSICFGR(0), val);
331 /* set Rx max frame size */
332 enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
333 /* enable MAC port */
334 enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
336 enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
337 /* set SI cache policy */
338 enetc_write(priv, ENETC_SICAR0,
339 ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG);
341 enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
344 /* returns DMA address for a given buffer index */
345 static inline u64 enetc_rxb_address(struct udevice *dev, int i)
347 return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
351 * Setup a single Tx BD Ring (ID = 0):
352 * - set Tx buffer descriptor address
354 * - initialize the producer and consumer index
356 static void enetc_setup_tx_bdr(struct udevice *dev)
358 struct enetc_priv *priv = dev_get_priv(dev);
359 struct bd_ring *tx_bdr = &priv->tx_bdr;
360 u64 tx_bd_add = (u64)priv->enetc_txbd;
362 /* used later to advance to the next Tx BD */
363 tx_bdr->bd_count = ENETC_BD_CNT;
364 tx_bdr->next_prod_idx = 0;
365 tx_bdr->next_cons_idx = 0;
366 tx_bdr->cons_idx = priv->regs_base +
367 ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
368 tx_bdr->prod_idx = priv->regs_base +
369 ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
371 /* set Tx BD address */
372 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
373 lower_32_bits(tx_bd_add));
374 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
375 upper_32_bits(tx_bd_add));
376 /* set Tx 8 BD count */
377 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
380 /* reset both producer/consumer indexes */
381 enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
382 enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
385 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
389 * Setup a single Rx BD Ring (ID = 0):
390 * - set Rx buffer descriptors address (one descriptor per buffer)
391 * - set buffer size as max frame size
393 * - reset consumer and producer indexes
394 * - set buffer for each descriptor
396 static void enetc_setup_rx_bdr(struct udevice *dev)
398 struct enetc_priv *priv = dev_get_priv(dev);
399 struct bd_ring *rx_bdr = &priv->rx_bdr;
400 u64 rx_bd_add = (u64)priv->enetc_rxbd;
403 /* used later to advance to the next BD produced by ENETC HW */
404 rx_bdr->bd_count = ENETC_BD_CNT;
405 rx_bdr->next_prod_idx = 0;
406 rx_bdr->next_cons_idx = 0;
407 rx_bdr->cons_idx = priv->regs_base +
408 ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
409 rx_bdr->prod_idx = priv->regs_base +
410 ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
412 /* set Rx BD address */
413 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
414 lower_32_bits(rx_bd_add));
415 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
416 upper_32_bits(rx_bd_add));
417 /* set Rx BD count (multiple of 8) */
418 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
420 /* set Rx buffer size */
421 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
424 memset(priv->enetc_rxbd, 0,
425 rx_bdr->bd_count * sizeof(union enetc_rx_bd));
426 for (i = 0; i < rx_bdr->bd_count; i++) {
427 priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
428 /* each RX buffer must be aligned to 64B */
429 WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
432 /* reset producer (ENETC owned) and consumer (SW owned) index */
433 enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
434 enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
437 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
441 * Start ENETC interface:
443 * - enable access to port and SI registers
445 * - setup TX/RX buffer descriptors
446 * - enable Tx/Rx rings
448 static int enetc_start(struct udevice *dev)
450 struct eth_pdata *plat = dev_get_platdata(dev);
451 struct enetc_priv *priv = dev_get_priv(dev);
453 /* reset and enable the PCI device */
455 dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
456 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
458 if (!is_valid_ethaddr(plat->enetaddr)) {
459 enetc_dbg(dev, "invalid MAC address, generate random ...\n");
460 net_random_ethaddr(plat->enetaddr);
462 enetc_set_primary_mac_addr(priv, plat->enetaddr);
464 enetc_enable_si_port(priv);
466 /* setup Tx/Rx buffer descriptors */
467 enetc_setup_tx_bdr(dev);
468 enetc_setup_rx_bdr(dev);
470 enetc_start_pcs(dev);
471 enetc_start_phy(dev);
477 * Stop the network interface:
478 * - just quiesce it, we can wipe all configuration as _start starts from
481 static void enetc_stop(struct udevice *dev)
483 /* FLR is sufficient to quiesce the device */
488 * ENETC transmit packet:
489 * - check if Tx BD ring is full
490 * - set buffer/packet address (dma address)
491 * - set final fragment flag
492 * - try while producer index equals consumer index or timeout
494 static int enetc_send(struct udevice *dev, void *packet, int length)
496 struct enetc_priv *priv = dev_get_priv(dev);
497 struct bd_ring *txr = &priv->tx_bdr;
498 void *nv_packet = (void *)packet;
499 int tries = ENETC_POLL_TRIES;
502 pi = txr->next_prod_idx;
503 ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
504 /* Tx ring is full when */
505 if (((pi + 1) % txr->bd_count) == ci) {
506 enetc_dbg(dev, "Tx BDR full\n");
509 enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
510 upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
513 memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
514 priv->enetc_txbd[pi].addr =
515 cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
516 priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
517 priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
518 priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
520 /* send frame: increment producer index */
521 pi = (pi + 1) % txr->bd_count;
522 txr->next_prod_idx = pi;
523 enetc_write_reg(txr->prod_idx, pi);
524 while ((--tries >= 0) &&
525 (pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
528 return tries > 0 ? 0 : -ETIMEDOUT;
533 * - wait for the next BD to get ready bit set
534 * - clean up the descriptor
535 * - move on and indicate to HW that the cleaned BD is available for Rx
537 static int enetc_recv(struct udevice *dev, int flags, uchar **packetp)
539 struct enetc_priv *priv = dev_get_priv(dev);
540 struct bd_ring *rxr = &priv->rx_bdr;
541 int tries = ENETC_POLL_TRIES;
542 int pi = rxr->next_prod_idx;
543 int ci = rxr->next_cons_idx;
550 status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
551 /* check if current BD is ready to be consumed */
552 rdy = ENETC_RXBD_STATUS_R(status);
553 } while (--tries >= 0 && !rdy);
559 len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
560 *packetp = (uchar *)enetc_rxb_address(dev, pi);
561 enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
562 ENETC_RXBD_STATUS_ERRORS(status),
563 upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp));
565 /* BD clean up and advance to next in ring */
566 memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
567 priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
568 rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
569 ci = (ci + 1) % rxr->bd_count;
570 rxr->next_cons_idx = ci;
572 /* free up the slot in the ring for HW */
573 enetc_write_reg(rxr->cons_idx, ci);
578 static const struct eth_ops enetc_ops = {
579 .start = enetc_start,
585 U_BOOT_DRIVER(eth_enetc) = {
589 .probe = enetc_probe,
590 .remove = enetc_remove,
592 .priv_auto_alloc_size = sizeof(struct enetc_priv),
593 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
596 static struct pci_device_id enetc_ids[] = {
597 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
601 U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);