1 // SPDX-License-Identifier: GPL-2.0+
3 * ENETC ethernet controller driver
4 * Copyright 2017-2019 NXP
14 #include "fsl_enetc.h"
18 * - set a more explicit name on the interface
20 static int enetc_bind(struct udevice *dev)
23 static int eth_num_devices;
26 * prefer using PCI function numbers to number interfaces, but these
27 * are only available if dts nodes are present. For PCI they are
28 * optional, handle that case too. Just in case some nodes are present
29 * and some are not, use different naming scheme - enetc-N based on
30 * PCI function # and enetc#N based on interface count
32 if (ofnode_valid(dev->node))
33 sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
35 sprintf(name, "enetc#%u", eth_num_devices++);
36 device_set_name(dev, name);
43 * - initialize port and station interface BARs
45 static int enetc_probe(struct udevice *dev)
47 struct enetc_priv *priv = dev_get_priv(dev);
49 if (ofnode_valid(dev->node) && !ofnode_is_available(dev->node)) {
50 enetc_dbg(dev, "interface disabled\n");
54 priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
55 sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
56 priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
57 sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
59 if (!priv->enetc_txbd || !priv->enetc_rxbd) {
60 /* free should be able to handle NULL, just free all pointers */
61 free(priv->enetc_txbd);
62 free(priv->enetc_rxbd);
67 /* initialize register */
68 priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
69 if (!priv->regs_base) {
70 enetc_dbg(dev, "failed to map BAR0\n");
73 priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
75 dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
81 * Remove the driver from an interface:
82 * - free up allocated memory
84 static int enetc_remove(struct udevice *dev)
86 struct enetc_priv *priv = dev_get_priv(dev);
88 free(priv->enetc_txbd);
89 free(priv->enetc_rxbd);
94 /* ENETC Port MAC address registers, accepts big-endian format */
95 static void enetc_set_primary_mac_addr(struct enetc_priv *priv, const u8 *addr)
97 u16 lower = *(const u16 *)(addr + 4);
98 u32 upper = *(const u32 *)addr;
100 enetc_write_port(priv, ENETC_PSIPMAR0, upper);
101 enetc_write_port(priv, ENETC_PSIPMAR1, lower);
104 /* Configure port parameters (# of rings, frame size, enable port) */
105 static void enetc_enable_si_port(struct enetc_priv *priv)
109 /* set Rx/Tx BDR count */
110 val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
111 val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
112 enetc_write_port(priv, ENETC_PSICFGR(0), val);
113 /* set Rx max frame size */
114 enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
115 /* enable MAC port */
116 enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
118 enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
119 /* set SI cache policy */
120 enetc_write(priv, ENETC_SICAR0,
121 ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG);
123 enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
126 /* returns DMA address for a given buffer index */
127 static inline u64 enetc_rxb_address(struct udevice *dev, int i)
129 return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
133 * Setup a single Tx BD Ring (ID = 0):
134 * - set Tx buffer descriptor address
136 * - initialize the producer and consumer index
138 static void enetc_setup_tx_bdr(struct udevice *dev)
140 struct enetc_priv *priv = dev_get_priv(dev);
141 struct bd_ring *tx_bdr = &priv->tx_bdr;
142 u64 tx_bd_add = (u64)priv->enetc_txbd;
144 /* used later to advance to the next Tx BD */
145 tx_bdr->bd_count = ENETC_BD_CNT;
146 tx_bdr->next_prod_idx = 0;
147 tx_bdr->next_cons_idx = 0;
148 tx_bdr->cons_idx = priv->regs_base +
149 ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
150 tx_bdr->prod_idx = priv->regs_base +
151 ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
153 /* set Tx BD address */
154 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
155 lower_32_bits(tx_bd_add));
156 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
157 upper_32_bits(tx_bd_add));
158 /* set Tx 8 BD count */
159 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
162 /* reset both producer/consumer indexes */
163 enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
164 enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
167 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
171 * Setup a single Rx BD Ring (ID = 0):
172 * - set Rx buffer descriptors address (one descriptor per buffer)
173 * - set buffer size as max frame size
175 * - reset consumer and producer indexes
176 * - set buffer for each descriptor
178 static void enetc_setup_rx_bdr(struct udevice *dev)
180 struct enetc_priv *priv = dev_get_priv(dev);
181 struct bd_ring *rx_bdr = &priv->rx_bdr;
182 u64 rx_bd_add = (u64)priv->enetc_rxbd;
185 /* used later to advance to the next BD produced by ENETC HW */
186 rx_bdr->bd_count = ENETC_BD_CNT;
187 rx_bdr->next_prod_idx = 0;
188 rx_bdr->next_cons_idx = 0;
189 rx_bdr->cons_idx = priv->regs_base +
190 ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
191 rx_bdr->prod_idx = priv->regs_base +
192 ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
194 /* set Rx BD address */
195 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
196 lower_32_bits(rx_bd_add));
197 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
198 upper_32_bits(rx_bd_add));
199 /* set Rx BD count (multiple of 8) */
200 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
202 /* set Rx buffer size */
203 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
206 memset(priv->enetc_rxbd, 0,
207 rx_bdr->bd_count * sizeof(union enetc_rx_bd));
208 for (i = 0; i < rx_bdr->bd_count; i++) {
209 priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
210 /* each RX buffer must be aligned to 64B */
211 WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
214 /* reset producer (ENETC owned) and consumer (SW owned) index */
215 enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
216 enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
219 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
223 * Start ENETC interface:
225 * - enable access to port and SI registers
227 * - setup TX/RX buffer descriptors
228 * - enable Tx/Rx rings
230 static int enetc_start(struct udevice *dev)
232 struct eth_pdata *plat = dev_get_platdata(dev);
233 struct enetc_priv *priv = dev_get_priv(dev);
235 /* reset and enable the PCI device */
237 dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
238 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
240 if (!is_valid_ethaddr(plat->enetaddr)) {
241 enetc_dbg(dev, "invalid MAC address, generate random ...\n");
242 net_random_ethaddr(plat->enetaddr);
244 enetc_set_primary_mac_addr(priv, plat->enetaddr);
246 enetc_enable_si_port(priv);
248 /* setup Tx/Rx buffer descriptors */
249 enetc_setup_tx_bdr(dev);
250 enetc_setup_rx_bdr(dev);
256 * Stop the network interface:
257 * - just quiesce it, we can wipe all configuration as _start starts from
260 static void enetc_stop(struct udevice *dev)
262 /* FLR is sufficient to quiesce the device */
267 * ENETC transmit packet:
268 * - check if Tx BD ring is full
269 * - set buffer/packet address (dma address)
270 * - set final fragment flag
271 * - try while producer index equals consumer index or timeout
273 static int enetc_send(struct udevice *dev, void *packet, int length)
275 struct enetc_priv *priv = dev_get_priv(dev);
276 struct bd_ring *txr = &priv->tx_bdr;
277 void *nv_packet = (void *)packet;
278 int tries = ENETC_POLL_TRIES;
281 pi = txr->next_prod_idx;
282 ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
283 /* Tx ring is full when */
284 if (((pi + 1) % txr->bd_count) == ci) {
285 enetc_dbg(dev, "Tx BDR full\n");
288 enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
289 upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
292 memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
293 priv->enetc_txbd[pi].addr =
294 cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
295 priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
296 priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
297 priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
299 /* send frame: increment producer index */
300 pi = (pi + 1) % txr->bd_count;
301 txr->next_prod_idx = pi;
302 enetc_write_reg(txr->prod_idx, pi);
303 while ((--tries >= 0) &&
304 (pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
307 return tries > 0 ? 0 : -ETIMEDOUT;
312 * - wait for the next BD to get ready bit set
313 * - clean up the descriptor
314 * - move on and indicate to HW that the cleaned BD is available for Rx
316 static int enetc_recv(struct udevice *dev, int flags, uchar **packetp)
318 struct enetc_priv *priv = dev_get_priv(dev);
319 struct bd_ring *rxr = &priv->rx_bdr;
320 int tries = ENETC_POLL_TRIES;
321 int pi = rxr->next_prod_idx;
322 int ci = rxr->next_cons_idx;
329 status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
330 /* check if current BD is ready to be consumed */
331 rdy = ENETC_RXBD_STATUS_R(status);
332 } while (--tries >= 0 && !rdy);
338 len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
339 *packetp = (uchar *)enetc_rxb_address(dev, pi);
340 enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
341 ENETC_RXBD_STATUS_ERRORS(status),
342 upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp));
344 /* BD clean up and advance to next in ring */
345 memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
346 priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
347 rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
348 ci = (ci + 1) % rxr->bd_count;
349 rxr->next_cons_idx = ci;
351 /* free up the slot in the ring for HW */
352 enetc_write_reg(rxr->cons_idx, ci);
357 static const struct eth_ops enetc_ops = {
358 .start = enetc_start,
364 U_BOOT_DRIVER(eth_enetc) = {
368 .probe = enetc_probe,
369 .remove = enetc_remove,
371 .priv_auto_alloc_size = sizeof(struct enetc_priv),
372 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
375 static struct pci_device_id enetc_ids[] = {
376 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
380 U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);