2 * Copyright (C) 2014 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <fsl-mc/fsl_mc.h>
9 #include <fsl-mc/fsl_mc_sys.h>
10 #include <fsl-mc/fsl_mc_private.h>
11 #include <fsl-mc/fsl_dpmng.h>
12 #include <fsl_debug_server.h>
13 #include <fsl-mc/fsl_dprc.h>
14 #include <fsl-mc/fsl_dpio.h>
15 #include <fsl-mc/fsl_qbman_portal.h>
17 #define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
18 #define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1))
19 #define MC_RAM_SIZE_ALIGNMENT (256UL * 1024 * 1024)
21 #define MC_MEM_SIZE_ENV_VAR "mcmemsize"
22 #define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
24 DECLARE_GLOBAL_DATA_PTR;
25 static int mc_boot_status;
26 struct fsl_mc_io *dflt_mc_io = NULL;
27 uint16_t dflt_dprc_handle = 0;
28 struct fsl_dpbp_obj *dflt_dpbp = NULL;
29 struct fsl_dpio_obj *dflt_dpio = NULL;
30 uint16_t dflt_dpio_handle = 0;
33 void dump_ram_words(const char *title, void *addr)
36 uint32_t *words = addr;
38 printf("Dumping beginning of %s (%p):\n", title, addr);
39 for (i = 0; i < 16; i++)
40 printf("%#x ", words[i]);
45 void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs)
47 printf("MC CCSR registers:\n"
57 mc_ccsr_regs->reg_gcr1,
58 mc_ccsr_regs->reg_gsr,
59 mc_ccsr_regs->reg_sicbalr,
60 mc_ccsr_regs->reg_sicbahr,
61 mc_ccsr_regs->reg_sicapr,
62 mc_ccsr_regs->reg_mcfbalr,
63 mc_ccsr_regs->reg_mcfbahr,
64 mc_ccsr_regs->reg_mcfapr,
65 mc_ccsr_regs->reg_psr);
69 #define dump_ram_words(title, addr)
70 #define dump_mc_ccsr_regs(mc_ccsr_regs)
74 #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
76 * Copying MC firmware or DPL image to DDR
78 static int mc_copy_image(const char *title,
79 u64 image_addr, u32 image_size, u64 mc_ram_addr)
81 debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
82 memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
83 flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size);
88 * MC firmware FIT image parser checks if the image is in FIT
89 * format, verifies integrity of the image and calculates
90 * raw image address and size values.
91 * Returns 0 on success and a negative errno on error.
94 int parse_mc_firmware_fit_image(const void **raw_image_addr,
95 size_t *raw_image_size)
102 const char *uname = "firmware";
104 /* Check if the image is in NOR flash */
105 #ifdef CONFIG_SYS_LS_MC_FW_IN_NOR
106 fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR;
108 #error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined"
111 /* Check if Image is in FIT format */
112 format = genimg_get_format(fit_hdr);
114 if (format != IMAGE_FORMAT_FIT) {
115 printf("fsl-mc: ERROR: Bad firmware image (not a FIT image)\n");
119 if (!fit_check_format(fit_hdr)) {
120 printf("fsl-mc: ERROR: Bad firmware image (bad FIT header)\n");
124 node_offset = fit_image_get_node(fit_hdr, uname);
126 if (node_offset < 0) {
127 printf("fsl-mc: ERROR: Bad firmware image (missing subimage)\n");
131 /* Verify MC firmware image */
132 if (!(fit_image_verify(fit_hdr, node_offset))) {
133 printf("fsl-mc: ERROR: Bad firmware image (bad CRC)\n");
137 /* Get address and size of raw image */
138 fit_image_get_data(fit_hdr, node_offset, &data, &size);
140 *raw_image_addr = data;
141 *raw_image_size = size;
148 * Calculates the values to be used to specify the address range
149 * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers.
150 * It returns the highest 512MB-aligned address within the given
151 * address range, in '*aligned_base_addr', and the number of 256 MiB
152 * blocks in it, in 'num_256mb_blocks'.
154 static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr,
156 u64 *aligned_base_addr,
157 u8 *num_256mb_blocks)
162 if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) {
163 printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
168 num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
169 if (num_blocks < 1 || num_blocks > 0xff) {
170 printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
175 addr = (mc_private_ram_start_addr + mc_ram_size - 1) &
176 MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
178 if (addr < mc_private_ram_start_addr) {
179 printf("fsl-mc: ERROR: bad start address %#llx\n",
180 mc_private_ram_start_addr);
184 *aligned_base_addr = addr;
185 *num_256mb_blocks = num_blocks;
189 static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size)
192 #ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
198 #ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
199 BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
200 CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
202 mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET;
204 #error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
208 * Load the MC DPC blob in the MC private DRAM block:
210 #ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
211 printf("MC DPC is preloaded to %#llx\n", mc_ram_addr + mc_dpc_offset);
214 * Get address and size of the DPC blob stored in flash:
216 #ifdef CONFIG_SYS_LS_MC_DPC_IN_NOR
217 dpc_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPC_ADDR;
219 #error "No CONFIG_SYS_LS_MC_DPC_IN_xxx defined"
222 error = fdt_check_header(dpc_fdt_hdr);
225 * Don't return with error here, since the MC firmware can
226 * still boot without a DPC
228 printf("fsl-mc: WARNING: No DPC image found\n");
232 dpc_size = fdt_totalsize(dpc_fdt_hdr);
233 if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) {
234 printf("fsl-mc: ERROR: Bad DPC image (too large: %d)\n",
239 mc_copy_image("MC DPC blob",
240 (u64)dpc_fdt_hdr, dpc_size, mc_ram_addr + mc_dpc_offset);
241 #endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */
243 dump_ram_words("DPC", (void *)(mc_ram_addr + mc_dpc_offset));
247 static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size)
250 #ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR
256 #ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
257 BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
258 CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
260 mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
262 #error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
266 * Load the MC DPL blob in the MC private DRAM block:
268 #ifdef CONFIG_SYS_LS_MC_DPL_IN_DDR
269 printf("MC DPL is preloaded to %#llx\n", mc_ram_addr + mc_dpl_offset);
272 * Get address and size of the DPL blob stored in flash:
274 #ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR
275 dpl_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR;
277 #error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined"
280 error = fdt_check_header(dpl_fdt_hdr);
282 printf("fsl-mc: ERROR: Bad DPL image (bad header)\n");
286 dpl_size = fdt_totalsize(dpl_fdt_hdr);
287 if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
288 printf("fsl-mc: ERROR: Bad DPL image (too large: %d)\n",
293 mc_copy_image("MC DPL blob",
294 (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
295 #endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */
297 dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset));
302 * Return the MC boot timeout value in milliseconds
304 static unsigned long get_mc_boot_timeout_ms(void)
306 unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
308 char *timeout_ms_env_var = getenv(MC_BOOT_TIMEOUT_ENV_VAR);
310 if (timeout_ms_env_var) {
311 timeout_ms = simple_strtoul(timeout_ms_env_var, NULL, 10);
312 if (timeout_ms == 0) {
313 printf("fsl-mc: WARNING: Invalid value for \'"
314 MC_BOOT_TIMEOUT_ENV_VAR
315 "\' environment variable: %lu\n",
318 timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
325 static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
328 u32 mc_fw_boot_status;
329 unsigned long timeout_ms = get_mc_boot_timeout_ms();
330 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
333 debug("Polling mc_ccsr_regs->reg_gsr ...\n");
334 assert(timeout_ms > 0);
336 udelay(1000); /* throttle polling */
337 reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
338 mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
339 if (mc_fw_boot_status & 0x1)
347 if (timeout_ms == 0) {
349 printf("fsl-mc: timeout booting management complex firmware\n");
351 printf("fsl-mc: timeout deploying data path layout\n");
353 /* TODO: Get an error status from an MC CCSR register */
357 if (mc_fw_boot_status != 0x1) {
359 * TODO: Identify critical errors from the GSR register's FS
360 * field and for those errors, set error to -ENODEV or other
361 * appropriate errno, so that the status property is set to
362 * failure in the fsl,dprc device tree node.
365 printf("fsl-mc: WARNING: Firmware booted with error (GSR: %#x)\n",
368 printf("fsl-mc: WARNING: Data path layout deployed with error (GSR: %#x)\n",
373 *final_reg_gsr = reg_gsr;
381 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
385 #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
386 const void *raw_image_addr;
387 size_t raw_image_size = 0;
389 struct mc_version mc_ver_info;
390 u64 mc_ram_aligned_base_addr;
391 u8 mc_ram_num_256mb_blocks;
392 size_t mc_ram_size = mc_get_dram_block_size();
395 * The MC private DRAM block was already carved at the end of DRAM
396 * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
398 if (gd->bd->bi_dram[1].start) {
400 gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
403 gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
406 #ifdef CONFIG_FSL_DEBUG_SERVER
408 * FIXME: I don't think this is right. See get_dram_size_to_hide()
410 mc_ram_addr -= debug_server_get_dram_block_size();
413 error = calculate_mc_private_ram_params(mc_ram_addr,
415 &mc_ram_aligned_base_addr,
416 &mc_ram_num_256mb_blocks);
421 * Management Complex cores should be held at reset out of POR.
422 * U-boot should be the first software to touch MC. To be safe,
423 * we reset all cores again by setting GCR1 to 0. It doesn't do
424 * anything if they are held at reset. After we setup the firmware
425 * we kick off MC by deasserting the reset bit for core 0, and
426 * deasserting the reset bits for Command Portal Managers.
427 * The stop bits are not touched here. They are used to stop the
428 * cores when they are active. Setting stop bits doesn't stop the
429 * cores from fetching instructions when they are released from
432 out_le32(&mc_ccsr_regs->reg_gcr1, 0);
435 #ifdef CONFIG_SYS_LS_MC_FW_IN_DDR
436 printf("MC firmware is preloaded to %#llx\n", mc_ram_addr);
438 error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size);
442 * Load the MC FW at the beginning of the MC private DRAM block:
444 mc_copy_image("MC Firmware",
445 (u64)raw_image_addr, raw_image_size, mc_ram_addr);
447 dump_ram_words("firmware", (void *)mc_ram_addr);
449 error = load_mc_dpc(mc_ram_addr, mc_ram_size);
453 error = load_mc_dpl(mc_ram_addr, mc_ram_size);
457 debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
458 dump_mc_ccsr_regs(mc_ccsr_regs);
461 * Tell MC what is the address range of the DRAM block assigned to it:
463 reg_mcfbalr = (u32)mc_ram_aligned_base_addr |
464 (mc_ram_num_256mb_blocks - 1);
465 out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
466 out_le32(&mc_ccsr_regs->reg_mcfbahr,
467 (u32)(mc_ram_aligned_base_addr >> 32));
468 out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK);
471 * Tell the MC that we want delayed DPL deployment.
473 out_le32(&mc_ccsr_regs->reg_gsr, 0xDD00);
475 printf("\nfsl-mc: Booting Management Complex ...\n");
478 * Deassert reset and release MC core 0 to run
480 out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
481 error = wait_for_mc(true, ®_gsr);
486 * TODO: need to obtain the portal_id for the root container from the
492 * Initialize the global default MC portal
493 * And check that the MC firmware is responding portal commands:
495 dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
497 printf(" No memory: malloc() failed\n");
501 dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
502 debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n",
503 portal_id, dflt_mc_io->mmio_regs);
505 error = mc_get_version(dflt_mc_io, &mc_ver_info);
507 printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n",
512 if (MC_VER_MAJOR != mc_ver_info.major)
513 printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n",
514 mc_ver_info.major, MC_VER_MAJOR);
516 if (MC_VER_MINOR != mc_ver_info.minor)
517 printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n",
518 mc_ver_info.minor, MC_VER_MINOR);
520 printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
521 mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
522 reg_gsr & GSR_FS_MASK);
525 * Tell the MC to deploy the DPL:
527 out_le32(&mc_ccsr_regs->reg_gsr, 0x0);
528 printf("\nfsl-mc: Deploying data path layout ...\n");
529 error = wait_for_mc(false, ®_gsr);
534 mc_boot_status = -error;
541 int get_mc_boot_status(void)
543 return mc_boot_status;
547 * Return the actual size of the MC private DRAM block.
549 unsigned long mc_get_dram_block_size(void)
551 unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
553 char *dram_block_size_env_var = getenv(MC_MEM_SIZE_ENV_VAR);
555 if (dram_block_size_env_var) {
556 dram_block_size = simple_strtoul(dram_block_size_env_var, NULL,
559 if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
560 printf("fsl-mc: WARNING: Invalid value for \'"
562 "\' environment variable: %lu\n",
565 dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
569 return dram_block_size;
572 int dpio_init(struct dprc_obj_desc obj_desc)
574 struct qbman_swp_desc p_des;
575 struct dpio_attr attr;
578 dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj));
580 printf(" No memory: malloc() failed\n");
584 dflt_dpio->dpio_id = obj_desc.id;
586 err = dpio_open(dflt_mc_io, obj_desc.id, &dflt_dpio_handle);
588 printf("dpio_open() failed\n");
592 err = dpio_get_attributes(dflt_mc_io, dflt_dpio_handle, &attr);
594 printf("dpio_get_attributes() failed %d\n", err);
598 err = dpio_enable(dflt_mc_io, dflt_dpio_handle);
600 printf("dpio_enable() failed %d\n", err);
603 debug("ce_paddr=0x%llx, ci_paddr=0x%llx, portalid=%d, prios=%d\n",
604 attr.qbman_portal_ce_paddr,
605 attr.qbman_portal_ci_paddr,
606 attr.qbman_portal_id,
607 attr.num_priorities);
609 p_des.cena_bar = (void *)attr.qbman_portal_ce_paddr;
610 p_des.cinh_bar = (void *)attr.qbman_portal_ci_paddr;
612 dflt_dpio->sw_portal = qbman_swp_init(&p_des);
613 if (dflt_dpio->sw_portal == NULL) {
614 printf("qbman_swp_init() failed\n");
615 goto err_get_swp_init;
621 dpio_disable(dflt_mc_io, dflt_dpio_handle);
623 dpio_close(dflt_mc_io, dflt_dpio_handle);
629 int dpbp_init(struct dprc_obj_desc obj_desc)
631 dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj));
633 printf(" No memory: malloc() failed\n");
636 dflt_dpbp->dpbp_attr.id = obj_desc.id;
641 int dprc_init_container_obj(struct dprc_obj_desc obj_desc, uint16_t dprc_handle)
643 int error = 0, state = 0;
644 struct dprc_endpoint dpni_endpoint, dpmac_endpoint;
645 if (!strcmp(obj_desc.type, "dpbp")) {
647 error = dpbp_init(obj_desc);
649 printf("dpbp_init failed\n");
651 } else if (!strcmp(obj_desc.type, "dpio")) {
653 error = dpio_init(obj_desc);
655 printf("dpio_init failed\n");
657 } else if (!strcmp(obj_desc.type, "dpni")) {
658 strcpy(dpni_endpoint.type, obj_desc.type);
659 dpni_endpoint.id = obj_desc.id;
660 error = dprc_get_connection(dflt_mc_io, dprc_handle,
661 &dpni_endpoint, &dpmac_endpoint, &state);
662 if (!strcmp(dpmac_endpoint.type, "dpmac"))
663 error = ldpaa_eth_init(obj_desc);
665 printf("ldpaa_eth_init failed\n");
671 int dprc_scan_container_obj(uint16_t dprc_handle, char *obj_type, int i)
674 struct dprc_obj_desc obj_desc;
676 memset((void *)&obj_desc, 0x00, sizeof(struct dprc_obj_desc));
678 error = dprc_get_obj(dflt_mc_io, dprc_handle,
681 printf("dprc_get_obj(i=%d) failed: %d\n",
686 if (!strcmp(obj_desc.type, obj_type)) {
687 debug("Discovered object: type %s, id %d, req %s\n",
688 obj_desc.type, obj_desc.id, obj_type);
690 error = dprc_init_container_obj(obj_desc, dprc_handle);
692 printf("dprc_init_container_obj(i=%d) failed: %d\n",
701 int fsl_mc_ldpaa_init(bd_t *bis)
704 int dprc_opened = 0, container_id;
705 int num_child_objects = 0;
711 error = dprc_get_container_id(dflt_mc_io, &container_id);
713 printf("dprc_get_container_id() failed: %d\n", error);
717 debug("fsl-mc: Container id=0x%x\n", container_id);
719 error = dprc_open(dflt_mc_io, container_id, &dflt_dprc_handle);
721 printf("dprc_open() failed: %d\n", error);
726 error = dprc_get_obj_count(dflt_mc_io,
730 printf("dprc_get_obj_count() failed: %d\n", error);
733 debug("Total child in container %d = %d\n", container_id,
736 if (num_child_objects != 0) {
738 * Discover objects currently in the DPRC container in the MC:
740 for (i = 0; i < num_child_objects; i++)
741 error = dprc_scan_container_obj(dflt_dprc_handle,
744 for (i = 0; i < num_child_objects; i++)
745 error = dprc_scan_container_obj(dflt_dprc_handle,
748 for (i = 0; i < num_child_objects; i++)
749 error = dprc_scan_container_obj(dflt_dprc_handle,
754 dprc_close(dflt_mc_io, dflt_dprc_handle);
759 void fsl_mc_ldpaa_exit(bd_t *bis)
763 if (get_mc_boot_status() == 0) {
764 err = dpio_disable(dflt_mc_io, dflt_dpio_handle);
766 printf("dpio_disable() failed: %d\n", err);
769 err = dpio_reset(dflt_mc_io, dflt_dpio_handle);
771 printf("dpio_reset() failed: %d\n", err);
774 err = dpio_close(dflt_mc_io, dflt_dpio_handle);
776 printf("dpio_close() failed: %d\n", err);