2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/immap_85xx.h>
11 #include <asm/fsl_serdes.h>
13 phy_interface_t fman_port_enet_if(enum fm_port port)
15 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
16 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
18 /* handle RGMII first */
19 if ((port == FM1_DTSEC2) &&
20 ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
21 FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) {
22 if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
23 FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
24 return PHY_INTERFACE_MODE_RGMII;
25 else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
26 FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
27 return PHY_INTERFACE_MODE_MII;
30 if ((port == FM1_DTSEC4) &&
31 ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
32 FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) {
33 if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
34 FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
35 return PHY_INTERFACE_MODE_RGMII;
36 else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
37 FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
38 return PHY_INTERFACE_MODE_MII;
41 if (port == FM1_DTSEC5) {
42 if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
43 FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)
44 return PHY_INTERFACE_MODE_RGMII;
45 else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
46 FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII)
47 return PHY_INTERFACE_MODE_MII;
53 if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) ||
54 is_serdes_configured(SGMII_SW1_MAC1 + port - FM1_DTSEC1))
55 return PHY_INTERFACE_MODE_QSGMII;
59 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
60 return PHY_INTERFACE_MODE_SGMII;
63 return PHY_INTERFACE_MODE_NONE;
66 return PHY_INTERFACE_MODE_NONE;