2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/immap_85xx.h>
11 #include <asm/fsl_serdes.h>
13 static u32 port_to_devdisr[] = {
14 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
15 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
16 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
17 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
18 [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
19 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
22 static int is_device_disabled(enum fm_port port)
24 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
25 u32 devdisr2 = in_be32(&gur->devdisr2);
27 return port_to_devdisr[port] & devdisr2;
30 void fman_disable_port(enum fm_port port)
32 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
34 /* don't allow disabling of DTSEC1 as its needed for MDIO */
35 if (port == FM1_DTSEC1)
38 setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
41 void fman_enable_port(enum fm_port port)
43 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
45 clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
48 phy_interface_t fman_port_enet_if(enum fm_port port)
50 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
51 u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
53 if (is_device_disabled(port))
54 return PHY_INTERFACE_MODE_NONE;
56 if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
57 return PHY_INTERFACE_MODE_XGMII;
59 /* handle RGMII first */
60 if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
61 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII))
62 return PHY_INTERFACE_MODE_RGMII;
64 if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
65 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII))
66 return PHY_INTERFACE_MODE_MII;
68 if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
69 FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII))
70 return PHY_INTERFACE_MODE_RGMII;
72 if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
73 FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII))
74 return PHY_INTERFACE_MODE_MII;
82 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
83 return PHY_INTERFACE_MODE_SGMII;
86 return PHY_INTERFACE_MODE_NONE;
89 return PHY_INTERFACE_MODE_NONE;