2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Andy Fleming <afleming@freescale.com>
4 * Roy Zang <tie-fei.zang@freescale.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * Some part is taken from tsec.c
26 #include <asm/fsl_memac.h>
30 * Write value to the PHY for this device to the register at regnum, waiting
31 * until the write is done before it returns. All PHY configuration has to be
32 * done through the TSEC1 MIIM regs
34 int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
35 int regnum, u16 value)
38 struct memac_mdio_controller *regs = bus->priv;
39 u32 c45 = 1; /* Default to 10G interface */
41 if (dev_addr == MDIO_DEVAD_NONE) {
42 c45 = 0; /* clause 22 */
43 dev_addr = regnum & 0x1f;
44 clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
46 setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
47 setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK);
50 /* Wait till the bus is free */
51 while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
54 /* Set the port and dev addr */
55 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
56 out_be32(®s->mdio_ctl, mdio_ctl);
58 /* Set the register address */
60 out_be32(®s->mdio_addr, regnum & 0xffff);
62 /* Wait till the bus is free */
63 while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
66 /* Write the value to the register */
67 out_be32(®s->mdio_data, MDIO_DATA(value));
69 /* Wait till the MDIO write is complete */
70 while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
77 * Reads from register regnum in the PHY for device dev, returning the value.
78 * Clears miimcom first. All PHY configuration has to be done through the
81 int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
85 struct memac_mdio_controller *regs = bus->priv;
88 if (dev_addr == MDIO_DEVAD_NONE) {
89 c45 = 0; /* clause 22 */
90 dev_addr = regnum & 0x1f;
91 clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
93 setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
94 setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK);
97 /* Wait till the bus is free */
98 while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
101 /* Set the Port and Device Addrs */
102 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
103 out_be32(®s->mdio_ctl, mdio_ctl);
105 /* Set the register address */
107 out_be32(®s->mdio_addr, regnum & 0xffff);
109 /* Wait till the bus is free */
110 while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
113 /* Initiate the read */
114 mdio_ctl |= MDIO_CTL_READ;
115 out_be32(®s->mdio_ctl, mdio_ctl);
117 /* Wait till the MDIO write is complete */
118 while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
121 /* Return all Fs if nothing was there */
122 if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER)
125 return in_be32(®s->mdio_data) & 0xffff;
128 int memac_mdio_reset(struct mii_dev *bus)
133 int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
135 struct mii_dev *bus = mdio_alloc();
138 printf("Failed to allocate FM TGEC MDIO bus\n");
142 bus->read = memac_mdio_read;
143 bus->write = memac_mdio_write;
144 bus->reset = memac_mdio_reset;
145 sprintf(bus->name, info->name);
147 bus->priv = info->regs;
149 return mdio_register(bus);