2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fsl_serdes.h>
12 #define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
13 #define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
14 #define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
15 #define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
16 #define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
17 #define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
18 #define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
19 #define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
20 #define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
22 u32 port_to_devdisr[] = {
23 [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
24 [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
25 [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
26 [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
27 [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
28 [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
29 [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
30 [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
31 [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
32 [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
33 [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
34 [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
37 static int is_device_disabled(enum fm_port port)
39 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
40 u32 devdisr2 = in_be32(&gur->devdisr2);
42 return port_to_devdisr[port] & devdisr2;
45 void fman_disable_port(enum fm_port port)
47 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
49 setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
52 phy_interface_t fman_port_enet_if(enum fm_port port)
54 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
55 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
57 if (is_device_disabled(port))
58 return PHY_INTERFACE_MODE_NONE;
60 if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
61 return PHY_INTERFACE_MODE_XGMII;
63 if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
64 return PHY_INTERFACE_MODE_NONE;
66 if (port == FM1_DTSEC3)
67 if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
68 FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
69 return PHY_INTERFACE_MODE_RGMII_TXID;
71 if (port == FM1_DTSEC4)
72 if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
73 FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
74 return PHY_INTERFACE_MODE_RGMII_TXID;
81 if ((port == FM1_DTSEC2) &&
82 is_serdes_configured(SGMII_2500_FM1_DTSEC2))
83 return PHY_INTERFACE_MODE_SGMII_2500;
87 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
88 return PHY_INTERFACE_MODE_SGMII;
89 else if ((port == FM1_DTSEC9) &&
90 is_serdes_configured(SGMII_2500_FM1_DTSEC9))
91 return PHY_INTERFACE_MODE_SGMII_2500;
103 /* only MAC 1,2,5,6 available for QSGMII */
104 if (is_serdes_configured(QSGMII_FM1_A))
105 return PHY_INTERFACE_MODE_QSGMII;
111 return PHY_INTERFACE_MODE_NONE;