2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm/arch/clock.h>
21 #include <asm/arch/imx-regs.h>
22 #include <asm/imx-common/sys_proto.h>
24 #include <linux/errno.h>
25 #include <linux/compiler.h>
27 DECLARE_GLOBAL_DATA_PTR;
30 * Timeout the transfer after 5 mS. This is usually a bit more, since
31 * the code in the tightloops this timeout is used in adds some overhead.
33 #define FEC_XFER_TIMEOUT 5000
36 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
37 * 64-byte alignment in the DMA RX FEC buffer.
38 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
39 * satisfies the alignment on other SoCs (32-bytes)
41 #define FEC_DMA_RX_MINALIGN 64
44 #error "CONFIG_MII has to be defined!"
47 #ifndef CONFIG_FEC_XCV_TYPE
48 #define CONFIG_FEC_XCV_TYPE MII100
52 * The i.MX28 operates with packets in big endian. We need to swap them before
53 * sending and after receiving.
56 #define CONFIG_FEC_MXC_SWAP_PACKET
59 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
61 /* Check various alignment issues at compile time */
62 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
63 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
66 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
67 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
68 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
73 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
74 static void swap_packet(uint32_t *packet, int length)
78 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
79 packet[i] = __swab32(packet[i]);
84 * MII-interface related functions
86 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
89 uint32_t reg; /* convenient holder for the PHY register */
90 uint32_t phy; /* convenient holder for the PHY */
95 * reading from any PHY's register is done by properly
96 * programming the FEC's MII data register.
98 writel(FEC_IEVENT_MII, ð->ievent);
99 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
100 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
102 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
103 phy | reg, ð->mii_data);
106 * wait for the related interrupt
108 start = get_timer(0);
109 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
110 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
111 printf("Read MDIO failed...\n");
117 * clear mii interrupt bit
119 writel(FEC_IEVENT_MII, ð->ievent);
122 * it's now safe to read the PHY's register
124 val = (unsigned short)readl(ð->mii_data);
125 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
130 static void fec_mii_setspeed(struct ethernet_regs *eth)
133 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
134 * and do not drop the Preamble.
136 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
137 * MII_SPEED) register that defines the MDIO output hold time. Earlier
138 * versions are RAZ there, so just ignore the difference and write the
140 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
141 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
143 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
144 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
145 * holdtime cannot result in a value greater than 3.
147 u32 pclk = imx_get_fecclk();
148 u32 speed = DIV_ROUND_UP(pclk, 5000000);
149 u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
150 #ifdef FEC_QUIRK_ENET_MAC
153 writel(speed << 1 | hold << 8, ð->mii_speed);
154 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
157 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
158 uint8_t regAddr, uint16_t data)
160 uint32_t reg; /* convenient holder for the PHY register */
161 uint32_t phy; /* convenient holder for the PHY */
164 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
165 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
167 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
168 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
171 * wait for the MII interrupt
173 start = get_timer(0);
174 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
175 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
176 printf("Write MDIO failed...\n");
182 * clear MII interrupt bit
184 writel(FEC_IEVENT_MII, ð->ievent);
185 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
191 static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr,
194 return fec_mdio_read(bus->priv, phyAddr, regAddr);
197 static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr,
198 int regAddr, u16 data)
200 return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
203 #ifndef CONFIG_PHYLIB
204 static int miiphy_restart_aneg(struct eth_device *dev)
207 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
208 struct fec_priv *fec = (struct fec_priv *)dev->priv;
209 struct ethernet_regs *eth = fec->bus->priv;
212 * Wake up from sleep if necessary
213 * Reset PHY, then delay 300ns
216 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
218 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
222 * Set the auto-negotiation advertisement register bits
224 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
225 LPA_100FULL | LPA_100HALF | LPA_10FULL |
226 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
227 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
228 BMCR_ANENABLE | BMCR_ANRESTART);
230 if (fec->mii_postcall)
231 ret = fec->mii_postcall(fec->phy_id);
237 #ifndef CONFIG_FEC_FIXED_SPEED
238 static int miiphy_wait_aneg(struct eth_device *dev)
242 struct fec_priv *fec = (struct fec_priv *)dev->priv;
243 struct ethernet_regs *eth = fec->bus->priv;
246 * Wait for AN completion
248 start = get_timer(0);
250 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
251 printf("%s: Autonegotiation timeout\n", dev->name);
255 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
257 printf("%s: Autonegotiation failed. status: %d\n",
261 } while (!(status & BMSR_LSTATUS));
265 #endif /* CONFIG_FEC_FIXED_SPEED */
268 static int fec_rx_task_enable(struct fec_priv *fec)
270 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
274 static int fec_rx_task_disable(struct fec_priv *fec)
279 static int fec_tx_task_enable(struct fec_priv *fec)
281 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
285 static int fec_tx_task_disable(struct fec_priv *fec)
291 * Initialize receive task's buffer descriptors
292 * @param[in] fec all we know about the device yet
293 * @param[in] count receive buffer count to be allocated
294 * @param[in] dsize desired size of each receive buffer
295 * @return 0 on success
297 * Init all RX descriptors to default values.
299 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
306 * Reload the RX descriptors with default values and wipe
309 size = roundup(dsize, ARCH_DMA_MINALIGN);
310 for (i = 0; i < count; i++) {
311 data = (uint8_t *)fec->rbd_base[i].data_pointer;
312 memset(data, 0, dsize);
313 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
315 fec->rbd_base[i].status = FEC_RBD_EMPTY;
316 fec->rbd_base[i].data_length = 0;
319 /* Mark the last RBD to close the ring. */
320 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
323 flush_dcache_range((unsigned)fec->rbd_base,
324 (unsigned)fec->rbd_base + size);
328 * Initialize transmit task's buffer descriptors
329 * @param[in] fec all we know about the device yet
331 * Transmit buffers are created externally. We only have to init the BDs here.\n
332 * Note: There is a race condition in the hardware. When only one BD is in
333 * use it must be marked with the WRAP bit to use it for every transmitt.
334 * This bit in combination with the READY bit results into double transmit
335 * of each data buffer. It seems the state machine checks READY earlier then
336 * resetting it after the first transfer.
337 * Using two BDs solves this issue.
339 static void fec_tbd_init(struct fec_priv *fec)
341 unsigned addr = (unsigned)fec->tbd_base;
342 unsigned size = roundup(2 * sizeof(struct fec_bd),
345 memset(fec->tbd_base, 0, size);
346 fec->tbd_base[0].status = 0;
347 fec->tbd_base[1].status = FEC_TBD_WRAP;
349 flush_dcache_range(addr, addr + size);
353 * Mark the given read buffer descriptor as free
354 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
355 * @param[in] pRbd buffer descriptor to mark free again
357 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
359 unsigned short flags = FEC_RBD_EMPTY;
361 flags |= FEC_RBD_WRAP;
362 writew(flags, &pRbd->status);
363 writew(0, &pRbd->data_length);
366 static int fec_get_hwaddr(int dev_id, unsigned char *mac)
368 imx_get_mac_from_fuse(dev_id, mac);
369 return !is_valid_ethaddr(mac);
373 static int fecmxc_set_hwaddr(struct udevice *dev)
375 static int fec_set_hwaddr(struct eth_device *dev)
379 struct fec_priv *fec = dev_get_priv(dev);
380 struct eth_pdata *pdata = dev_get_platdata(dev);
381 uchar *mac = pdata->enetaddr;
383 uchar *mac = dev->enetaddr;
384 struct fec_priv *fec = (struct fec_priv *)dev->priv;
387 writel(0, &fec->eth->iaddr1);
388 writel(0, &fec->eth->iaddr2);
389 writel(0, &fec->eth->gaddr1);
390 writel(0, &fec->eth->gaddr2);
393 * Set physical address
395 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
397 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
403 * Do initial configuration of the FEC registers
405 static void fec_reg_setup(struct fec_priv *fec)
410 * Set interrupt mask register
412 writel(0x00000000, &fec->eth->imask);
415 * Clear FEC-Lite interrupt event register(IEVENT)
417 writel(0xffffffff, &fec->eth->ievent);
421 * Set FEC-Lite receive control register(R_CNTRL):
424 /* Start with frame length = 1518, common for all modes. */
425 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
426 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
427 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
428 if (fec->xcv_type == RGMII)
429 rcntrl |= FEC_RCNTRL_RGMII;
430 else if (fec->xcv_type == RMII)
431 rcntrl |= FEC_RCNTRL_RMII;
433 writel(rcntrl, &fec->eth->r_cntrl);
437 * Start the FEC engine
438 * @param[in] dev Our device to handle
441 static int fec_open(struct udevice *dev)
443 static int fec_open(struct eth_device *edev)
447 struct fec_priv *fec = dev_get_priv(dev);
449 struct fec_priv *fec = (struct fec_priv *)edev->priv;
455 debug("fec_open: fec_open(dev)\n");
456 /* full-duplex, heartbeat disabled */
457 writel(1 << 2, &fec->eth->x_cntrl);
460 /* Invalidate all descriptors */
461 for (i = 0; i < FEC_RBD_NUM - 1; i++)
462 fec_rbd_clean(0, &fec->rbd_base[i]);
463 fec_rbd_clean(1, &fec->rbd_base[i]);
465 /* Flush the descriptors into RAM */
466 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
468 addr = (uint32_t)fec->rbd_base;
469 flush_dcache_range(addr, addr + size);
471 #ifdef FEC_QUIRK_ENET_MAC
472 /* Enable ENET HW endian SWAP */
473 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
475 /* Enable ENET store and forward mode */
476 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
480 * Enable FEC-Lite controller
482 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
484 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
487 * setup the MII gasket for RMII mode
490 /* disable the gasket */
491 writew(0, &fec->eth->miigsk_enr);
493 /* wait for the gasket to be disabled */
494 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
497 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
498 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
500 /* re-enable the gasket */
501 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
503 /* wait until MII gasket is ready */
505 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
506 if (--max_loops <= 0) {
507 printf("WAIT for MII Gasket ready timed out\n");
515 /* Start up the PHY */
516 int ret = phy_startup(fec->phydev);
519 printf("Could not initialize PHY %s\n",
520 fec->phydev->dev->name);
523 speed = fec->phydev->speed;
525 #elif CONFIG_FEC_FIXED_SPEED
526 speed = CONFIG_FEC_FIXED_SPEED;
528 miiphy_wait_aneg(edev);
529 speed = miiphy_speed(edev->name, fec->phy_id);
530 miiphy_duplex(edev->name, fec->phy_id);
533 #ifdef FEC_QUIRK_ENET_MAC
535 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
536 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
537 if (speed == _1000BASET)
538 ecr |= FEC_ECNTRL_SPEED;
539 else if (speed != _100BASET)
540 rcr |= FEC_RCNTRL_RMII_10T;
541 writel(ecr, &fec->eth->ecntrl);
542 writel(rcr, &fec->eth->r_cntrl);
545 debug("%s:Speed=%i\n", __func__, speed);
548 * Enable SmartDMA receive task
550 fec_rx_task_enable(fec);
557 static int fecmxc_init(struct udevice *dev)
559 static int fec_init(struct eth_device *dev, bd_t* bd)
563 struct fec_priv *fec = dev_get_priv(dev);
565 struct fec_priv *fec = (struct fec_priv *)dev->priv;
567 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
570 /* Initialize MAC address */
572 fecmxc_set_hwaddr(dev);
578 * Setup transmit descriptors, there are two in total.
582 /* Setup receive descriptors. */
583 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
587 if (fec->xcv_type != SEVENWIRE)
588 fec_mii_setspeed(fec->bus->priv);
591 * Set Opcode/Pause Duration Register
593 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
594 writel(0x2, &fec->eth->x_wmrk);
596 * Set multicast address filter
598 writel(0x00000000, &fec->eth->gaddr1);
599 writel(0x00000000, &fec->eth->gaddr2);
602 /* Do not access reserved register for i.MX6UL */
605 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
608 /* FIFO receive start register */
609 writel(0x520, &fec->eth->r_fstart);
612 /* size and address of each buffer */
613 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
614 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
615 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
617 #ifndef CONFIG_PHYLIB
618 if (fec->xcv_type != SEVENWIRE)
619 miiphy_restart_aneg(dev);
626 * Halt the FEC engine
627 * @param[in] dev Our device to handle
630 static void fecmxc_halt(struct udevice *dev)
632 static void fec_halt(struct eth_device *dev)
636 struct fec_priv *fec = dev_get_priv(dev);
638 struct fec_priv *fec = (struct fec_priv *)dev->priv;
640 int counter = 0xffff;
643 * issue graceful stop command to the FEC transmitter if necessary
645 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
648 debug("eth_halt: wait for stop regs\n");
650 * wait for graceful stop to register
652 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
656 * Disable SmartDMA tasks
658 fec_tx_task_disable(fec);
659 fec_rx_task_disable(fec);
662 * Disable the Ethernet Controller
663 * Note: this will also reset the BD index counter!
665 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
669 debug("eth_halt: done\n");
674 * @param[in] dev Our ethernet device to handle
675 * @param[in] packet Pointer to the data to be transmitted
676 * @param[in] length Data count in bytes
677 * @return 0 on success
680 static int fecmxc_send(struct udevice *dev, void *packet, int length)
682 static int fec_send(struct eth_device *dev, void *packet, int length)
688 int timeout = FEC_XFER_TIMEOUT;
692 * This routine transmits one frame. This routine only accepts
693 * 6-byte Ethernet addresses.
696 struct fec_priv *fec = dev_get_priv(dev);
698 struct fec_priv *fec = (struct fec_priv *)dev->priv;
702 * Check for valid length of data.
704 if ((length > 1500) || (length <= 0)) {
705 printf("Payload (%d) too large\n", length);
710 * Setup the transmit buffer. We are always using the first buffer for
711 * transmission, the second will be empty and only used to stop the DMA
712 * engine. We also flush the packet to RAM here to avoid cache trouble.
714 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
715 swap_packet((uint32_t *)packet, length);
718 addr = (uint32_t)packet;
719 end = roundup(addr + length, ARCH_DMA_MINALIGN);
720 addr &= ~(ARCH_DMA_MINALIGN - 1);
721 flush_dcache_range(addr, end);
723 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
724 writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
727 * update BD's status now
729 * - is always the last in a chain (means no chain)
730 * - should transmitt the CRC
731 * - might be the last BD in the list, so the address counter should
732 * wrap (-> keep the WRAP flag)
734 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
735 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
736 writew(status, &fec->tbd_base[fec->tbd_index].status);
739 * Flush data cache. This code flushes both TX descriptors to RAM.
740 * After this code, the descriptors will be safely in RAM and we
743 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
744 addr = (uint32_t)fec->tbd_base;
745 flush_dcache_range(addr, addr + size);
748 * Below we read the DMA descriptor's last four bytes back from the
749 * DRAM. This is important in order to make sure that all WRITE
750 * operations on the bus that were triggered by previous cache FLUSH
753 * Otherwise, on MX28, it is possible to observe a corruption of the
754 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
755 * for the bus structure of MX28. The scenario is as follows:
757 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
758 * to DRAM due to flush_dcache_range()
759 * 2) ARM core writes the FEC registers via AHB_ARB2
760 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
762 * Note that 2) does sometimes finish before 1) due to reordering of
763 * WRITE accesses on the AHB bus, therefore triggering 3) before the
764 * DMA descriptor is fully written into DRAM. This results in occasional
765 * corruption of the DMA descriptor.
767 readl(addr + size - 4);
770 * Enable SmartDMA transmit task
772 fec_tx_task_enable(fec);
775 * Wait until frame is sent. On each turn of the wait cycle, we must
776 * invalidate data cache to see what's really in RAM. Also, we need
780 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
790 * The TDAR bit is cleared when the descriptors are all out from TX
791 * but on mx6solox we noticed that the READY bit is still not cleared
793 * These are two distinct signals, and in IC simulation, we found that
794 * TDAR always gets cleared prior than the READY bit of last BD becomes
796 * In mx6solox, we use a later version of FEC IP. It looks like that
797 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
800 * Fix this by polling the READY bit of BD after the TDAR polling,
801 * which covers the mx6solox case and does not harm the other SoCs.
803 timeout = FEC_XFER_TIMEOUT;
805 invalidate_dcache_range(addr, addr + size);
806 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
815 debug("fec_send: status 0x%x index %d ret %i\n",
816 readw(&fec->tbd_base[fec->tbd_index].status),
817 fec->tbd_index, ret);
818 /* for next transmission use the other buffer */
828 * Pull one frame from the card
829 * @param[in] dev Our ethernet device to handle
830 * @return Length of packet read
833 static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
835 static int fec_recv(struct eth_device *dev)
839 struct fec_priv *fec = dev_get_priv(dev);
841 struct fec_priv *fec = (struct fec_priv *)dev->priv;
843 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
844 unsigned long ievent;
845 int frame_length, len = 0;
847 uint32_t addr, size, end;
849 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
852 * Check if any critical events have happened
854 ievent = readl(&fec->eth->ievent);
855 writel(ievent, &fec->eth->ievent);
856 debug("fec_recv: ievent 0x%lx\n", ievent);
857 if (ievent & FEC_IEVENT_BABR) {
863 fec_init(dev, fec->bd);
865 printf("some error: 0x%08lx\n", ievent);
868 if (ievent & FEC_IEVENT_HBERR) {
869 /* Heartbeat error */
870 writel(0x00000001 | readl(&fec->eth->x_cntrl),
873 if (ievent & FEC_IEVENT_GRA) {
874 /* Graceful stop complete */
875 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
881 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
886 fec_init(dev, fec->bd);
892 * Read the buffer status. Before the status can be read, the data cache
893 * must be invalidated, because the data in RAM might have been changed
894 * by DMA. The descriptors are properly aligned to cachelines so there's
895 * no need to worry they'd overlap.
897 * WARNING: By invalidating the descriptor here, we also invalidate
898 * the descriptors surrounding this one. Therefore we can NOT change the
899 * contents of this descriptor nor the surrounding ones. The problem is
900 * that in order to mark the descriptor as processed, we need to change
901 * the descriptor. The solution is to mark the whole cache line when all
902 * descriptors in the cache line are processed.
904 addr = (uint32_t)rbd;
905 addr &= ~(ARCH_DMA_MINALIGN - 1);
906 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
907 invalidate_dcache_range(addr, addr + size);
909 bd_status = readw(&rbd->status);
910 debug("fec_recv: status 0x%x\n", bd_status);
912 if (!(bd_status & FEC_RBD_EMPTY)) {
913 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
914 ((readw(&rbd->data_length) - 4) > 14)) {
916 * Get buffer address and size
918 addr = readl(&rbd->data_pointer);
919 frame_length = readw(&rbd->data_length) - 4;
921 * Invalidate data cache over the buffer
923 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
924 addr &= ~(ARCH_DMA_MINALIGN - 1);
925 invalidate_dcache_range(addr, end);
928 * Fill the buffer and pass it to upper layers
930 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
931 swap_packet((uint32_t *)addr, frame_length);
933 memcpy(buff, (char *)addr, frame_length);
934 net_process_received_packet(buff, frame_length);
937 if (bd_status & FEC_RBD_ERR)
938 printf("error frame: 0x%08x 0x%08x\n",
943 * Free the current buffer, restart the engine and move forward
944 * to the next buffer. Here we check if the whole cacheline of
945 * descriptors was already processed and if so, we mark it free
948 size = RXDESC_PER_CACHELINE - 1;
949 if ((fec->rbd_index & size) == size) {
950 i = fec->rbd_index - size;
951 addr = (uint32_t)&fec->rbd_base[i];
952 for (; i <= fec->rbd_index ; i++) {
953 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
956 flush_dcache_range(addr,
957 addr + ARCH_DMA_MINALIGN);
960 fec_rx_task_enable(fec);
961 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
963 debug("fec_recv: stop\n");
968 static void fec_set_dev_name(char *dest, int dev_id)
970 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
973 static int fec_alloc_descs(struct fec_priv *fec)
979 /* Allocate TX descriptors. */
980 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
981 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
985 /* Allocate RX descriptors. */
986 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
987 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
991 memset(fec->rbd_base, 0, size);
993 /* Allocate RX buffers. */
995 /* Maximum RX buffer size. */
996 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
997 for (i = 0; i < FEC_RBD_NUM; i++) {
998 data = memalign(FEC_DMA_RX_MINALIGN, size);
1000 printf("%s: error allocating rxbuf %d\n", __func__, i);
1004 memset(data, 0, size);
1006 fec->rbd_base[i].data_pointer = (uint32_t)data;
1007 fec->rbd_base[i].status = FEC_RBD_EMPTY;
1008 fec->rbd_base[i].data_length = 0;
1009 /* Flush the buffer to memory. */
1010 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
1013 /* Mark the last RBD to close the ring. */
1014 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
1023 free((void *)fec->rbd_base[i].data_pointer);
1024 free(fec->rbd_base);
1026 free(fec->tbd_base);
1031 static void fec_free_descs(struct fec_priv *fec)
1035 for (i = 0; i < FEC_RBD_NUM; i++)
1036 free((void *)fec->rbd_base[i].data_pointer);
1037 free(fec->rbd_base);
1038 free(fec->tbd_base);
1041 struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
1043 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1044 struct mii_dev *bus;
1049 printf("mdio_alloc failed\n");
1052 bus->read = fec_phy_read;
1053 bus->write = fec_phy_write;
1055 fec_set_dev_name(bus->name, dev_id);
1057 ret = mdio_register(bus);
1059 printf("mdio_register failed\n");
1063 fec_mii_setspeed(eth);
1067 #ifndef CONFIG_DM_ETH
1068 #ifdef CONFIG_PHYLIB
1069 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1070 struct mii_dev *bus, struct phy_device *phydev)
1072 static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1073 struct mii_dev *bus, int phy_id)
1076 struct eth_device *edev;
1077 struct fec_priv *fec;
1078 unsigned char ethaddr[6];
1082 /* create and fill edev struct */
1083 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1085 puts("fec_mxc: not enough malloc memory for eth_device\n");
1090 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1092 puts("fec_mxc: not enough malloc memory for fec_priv\n");
1097 memset(edev, 0, sizeof(*edev));
1098 memset(fec, 0, sizeof(*fec));
1100 ret = fec_alloc_descs(fec);
1105 edev->init = fec_init;
1106 edev->send = fec_send;
1107 edev->recv = fec_recv;
1108 edev->halt = fec_halt;
1109 edev->write_hwaddr = fec_set_hwaddr;
1111 fec->eth = (struct ethernet_regs *)base_addr;
1114 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1117 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1118 start = get_timer(0);
1119 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1120 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1121 printf("FEC MXC: Timeout resetting chip\n");
1128 fec_set_dev_name(edev->name, dev_id);
1129 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1131 fec_mii_setspeed(bus->priv);
1132 #ifdef CONFIG_PHYLIB
1133 fec->phydev = phydev;
1134 phy_connect_dev(phydev, edev);
1138 fec->phy_id = phy_id;
1142 if (fec_get_hwaddr(dev_id, ethaddr) == 0) {
1143 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
1144 memcpy(edev->enetaddr, ethaddr, 6);
1145 if (!getenv("ethaddr"))
1146 eth_setenv_enetaddr("ethaddr", ethaddr);
1150 fec_free_descs(fec);
1159 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1162 struct mii_dev *bus = NULL;
1163 #ifdef CONFIG_PHYLIB
1164 struct phy_device *phydev = NULL;
1170 * The i.MX28 has two ethernet interfaces, but they are not equal.
1171 * Only the first one can access the MDIO bus.
1173 base_mii = MXS_ENET0_BASE;
1177 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1178 bus = fec_get_miibus(base_mii, dev_id);
1181 #ifdef CONFIG_PHYLIB
1182 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1184 mdio_unregister(bus);
1188 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1190 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1193 #ifdef CONFIG_PHYLIB
1196 mdio_unregister(bus);
1202 #ifdef CONFIG_FEC_MXC_PHYADDR
1203 int fecmxc_initialize(bd_t *bd)
1205 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1210 #ifndef CONFIG_PHYLIB
1211 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1213 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1214 fec->mii_postcall = cb;
1221 static const struct eth_ops fecmxc_ops = {
1222 .start = fecmxc_init,
1223 .send = fecmxc_send,
1224 .recv = fecmxc_recv,
1225 .stop = fecmxc_halt,
1226 .write_hwaddr = fecmxc_set_hwaddr,
1229 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1231 struct phy_device *phydev;
1232 int mask = 0xffffffff;
1234 #ifdef CONFIG_PHYLIB
1235 mask = 1 << CONFIG_FEC_MXC_PHYADDR;
1238 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
1242 phy_connect_dev(phydev, dev);
1244 priv->phydev = phydev;
1250 static int fecmxc_probe(struct udevice *dev)
1252 struct eth_pdata *pdata = dev_get_platdata(dev);
1253 struct fec_priv *priv = dev_get_priv(dev);
1254 struct mii_dev *bus = NULL;
1256 unsigned char ethaddr[6];
1260 ret = fec_alloc_descs(priv);
1264 bus = fec_get_miibus((uint32_t)priv->eth, dev_id);
1269 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1270 priv->interface = pdata->phy_interface;
1271 ret = fec_phy_init(priv, dev);
1276 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, &priv->eth->ecntrl);
1277 start = get_timer(0);
1278 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1279 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1280 printf("FEC MXC: Timeout reseting chip\n");
1286 fec_reg_setup(priv);
1287 fec_set_dev_name((char *)dev->name, dev_id);
1288 priv->dev_id = (dev_id == -1) ? 0 : dev_id;
1290 ret = fec_get_hwaddr(dev_id, ethaddr);
1292 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
1293 memcpy(pdata->enetaddr, ethaddr, 6);
1294 if (!getenv("ethaddr"))
1295 eth_setenv_enetaddr("ethaddr", ethaddr);
1303 mdio_unregister(bus);
1306 fec_free_descs(priv);
1310 static int fecmxc_remove(struct udevice *dev)
1312 struct fec_priv *priv = dev_get_priv(dev);
1315 fec_free_descs(priv);
1316 mdio_unregister(priv->bus);
1317 mdio_free(priv->bus);
1322 static int fecmxc_ofdata_to_platdata(struct udevice *dev)
1324 struct eth_pdata *pdata = dev_get_platdata(dev);
1325 struct fec_priv *priv = dev_get_priv(dev);
1326 const char *phy_mode;
1328 pdata->iobase = (phys_addr_t)dev_get_addr(dev);
1329 priv->eth = (struct ethernet_regs *)pdata->iobase;
1331 pdata->phy_interface = -1;
1332 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
1334 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1335 if (pdata->phy_interface == -1) {
1336 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1341 * Need to get the reset-gpio and related properties from DT
1342 * and implemet the enet reset code on .probe call
1348 static const struct udevice_id fecmxc_ids[] = {
1349 { .compatible = "fsl,imx6q-fec" },
1353 U_BOOT_DRIVER(fecmxc_gem) = {
1356 .of_match = fecmxc_ids,
1357 .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
1358 .probe = fecmxc_probe,
1359 .remove = fecmxc_remove,
1361 .priv_auto_alloc_size = sizeof(struct fec_priv),
1362 .platdata_auto_alloc_size = sizeof(struct eth_pdata),