2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clock.h>
31 #include <asm/arch/imx-regs.h>
33 #include <asm/errno.h>
35 DECLARE_GLOBAL_DATA_PTR;
38 #error "CONFIG_MII has to be defined!"
41 #ifndef CONFIG_FEC_XCV_TYPE
42 #define CONFIG_FEC_XCV_TYPE MII100
48 uint8_t data[1500]; /**< actual data */
49 int length; /**< actual length */
50 int used; /**< buffer in use or not */
51 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
55 * MII-interface related functions
57 static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr,
60 struct eth_device *edev = eth_get_dev_by_name(dev);
61 struct fec_priv *fec = (struct fec_priv *)edev->priv;
62 struct ethernet_regs *eth = fec->eth;
64 uint32_t reg; /* convenient holder for the PHY register */
65 uint32_t phy; /* convenient holder for the PHY */
69 * reading from any PHY's register is done by properly
70 * programming the FEC's MII data register.
72 writel(FEC_IEVENT_MII, ð->ievent);
73 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
74 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
76 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
77 phy | reg, ð->mii_data);
80 * wait for the related interrupt
83 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
84 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
85 printf("Read MDIO failed...\n");
91 * clear mii interrupt bit
93 writel(FEC_IEVENT_MII, ð->ievent);
96 * it's now safe to read the PHY's register
98 *retVal = readl(ð->mii_data);
99 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
104 static void fec_mii_setspeed(struct fec_priv *fec)
107 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
108 * and do not drop the Preamble.
110 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
111 &fec->eth->mii_speed);
112 debug("fec_init: mii_speed %#lx\n",
113 readl(&fec->eth->mii_speed));
115 static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
118 struct eth_device *edev = eth_get_dev_by_name(dev);
119 struct fec_priv *fec = (struct fec_priv *)edev->priv;
120 struct ethernet_regs *eth = fec->eth;
122 uint32_t reg; /* convenient holder for the PHY register */
123 uint32_t phy; /* convenient holder for the PHY */
126 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
127 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
129 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
130 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
133 * wait for the MII interrupt
135 start = get_timer(0);
136 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
137 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
138 printf("Write MDIO failed...\n");
144 * clear MII interrupt bit
146 writel(FEC_IEVENT_MII, ð->ievent);
147 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
153 static int miiphy_restart_aneg(struct eth_device *dev)
155 struct fec_priv *fec = (struct fec_priv *)dev->priv;
159 * Wake up from sleep if necessary
160 * Reset PHY, then delay 300ns
163 miiphy_write(dev->name, fec->phy_id, MII_DCOUNTER, 0x00FF);
165 miiphy_write(dev->name, fec->phy_id, MII_BMCR,
170 * Set the auto-negotiation advertisement register bits
172 miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE,
173 LPA_100FULL | LPA_100HALF | LPA_10FULL |
174 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
175 miiphy_write(dev->name, fec->phy_id, MII_BMCR,
176 BMCR_ANENABLE | BMCR_ANRESTART);
178 if (fec->mii_postcall)
179 ret = fec->mii_postcall(fec->phy_id);
184 static int miiphy_wait_aneg(struct eth_device *dev)
188 struct fec_priv *fec = (struct fec_priv *)dev->priv;
191 * Wait for AN completion
193 start = get_timer(0);
195 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
196 printf("%s: Autonegotiation timeout\n", dev->name);
200 if (miiphy_read(dev->name, fec->phy_id,
201 MII_BMSR, &status)) {
202 printf("%s: Autonegotiation failed. status: 0x%04x\n",
206 } while (!(status & BMSR_LSTATUS));
210 static int fec_rx_task_enable(struct fec_priv *fec)
212 writel(1 << 24, &fec->eth->r_des_active);
216 static int fec_rx_task_disable(struct fec_priv *fec)
221 static int fec_tx_task_enable(struct fec_priv *fec)
223 writel(1 << 24, &fec->eth->x_des_active);
227 static int fec_tx_task_disable(struct fec_priv *fec)
233 * Initialize receive task's buffer descriptors
234 * @param[in] fec all we know about the device yet
235 * @param[in] count receive buffer count to be allocated
236 * @param[in] size size of each receive buffer
237 * @return 0 on success
239 * For this task we need additional memory for the data buffers. And each
240 * data buffer requires some alignment. Thy must be aligned to a specific
241 * boundary each (DB_DATA_ALIGNMENT).
243 static int fec_rbd_init(struct fec_priv *fec, int count, int size)
248 /* reserve data memory and consider alignment */
249 if (fec->rdb_ptr == NULL)
250 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
251 p = (uint32_t)fec->rdb_ptr;
253 puts("fec_mxc: not enough malloc memory\n");
256 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
257 p += DB_DATA_ALIGNMENT-1;
258 p &= ~(DB_DATA_ALIGNMENT-1);
260 for (ix = 0; ix < count; ix++) {
261 writel(p, &fec->rbd_base[ix].data_pointer);
263 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
264 writew(0, &fec->rbd_base[ix].data_length);
267 * mark the last RBD to close the ring
269 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
276 * Initialize transmit task's buffer descriptors
277 * @param[in] fec all we know about the device yet
279 * Transmit buffers are created externally. We only have to init the BDs here.\n
280 * Note: There is a race condition in the hardware. When only one BD is in
281 * use it must be marked with the WRAP bit to use it for every transmitt.
282 * This bit in combination with the READY bit results into double transmit
283 * of each data buffer. It seems the state machine checks READY earlier then
284 * resetting it after the first transfer.
285 * Using two BDs solves this issue.
287 static void fec_tbd_init(struct fec_priv *fec)
289 writew(0x0000, &fec->tbd_base[0].status);
290 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
295 * Mark the given read buffer descriptor as free
296 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
297 * @param[in] pRbd buffer descriptor to mark free again
299 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
302 * Reset buffer descriptor as empty
305 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
307 writew(FEC_RBD_EMPTY, &pRbd->status);
311 writew(0, &pRbd->data_length);
314 static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
316 imx_get_mac_from_fuse(mac);
317 return !is_valid_ether_addr(mac);
320 static int fec_set_hwaddr(struct eth_device *dev)
322 uchar *mac = dev->enetaddr;
323 struct fec_priv *fec = (struct fec_priv *)dev->priv;
325 writel(0, &fec->eth->iaddr1);
326 writel(0, &fec->eth->iaddr2);
327 writel(0, &fec->eth->gaddr1);
328 writel(0, &fec->eth->gaddr2);
331 * Set physical address
333 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
335 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
341 * Start the FEC engine
342 * @param[in] dev Our device to handle
344 static int fec_open(struct eth_device *edev)
346 struct fec_priv *fec = (struct fec_priv *)edev->priv;
348 debug("fec_open: fec_open(dev)\n");
349 /* full-duplex, heartbeat disabled */
350 writel(1 << 2, &fec->eth->x_cntrl);
354 * Enable FEC-Lite controller
356 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
358 #if defined(CONFIG_MX25) || defined(CONFIG_MX53)
361 * setup the MII gasket for RMII mode
364 /* disable the gasket */
365 writew(0, &fec->eth->miigsk_enr);
367 /* wait for the gasket to be disabled */
368 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
371 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
372 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
374 /* re-enable the gasket */
375 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
377 /* wait until MII gasket is ready */
379 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
380 if (--max_loops <= 0) {
381 printf("WAIT for MII Gasket ready timed out\n");
387 miiphy_wait_aneg(edev);
388 miiphy_speed(edev->name, fec->phy_id);
389 miiphy_duplex(edev->name, fec->phy_id);
392 * Enable SmartDMA receive task
394 fec_rx_task_enable(fec);
400 static int fec_init(struct eth_device *dev, bd_t* bd)
403 struct fec_priv *fec = (struct fec_priv *)dev->priv;
404 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
408 /* Initialize MAC address */
412 * reserve memory for both buffer descriptor chains at once
413 * Datasheet forces the startaddress of each chain is 16 byte
416 if (fec->base_ptr == NULL)
417 fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
418 sizeof(struct fec_bd) + DB_ALIGNMENT);
419 base = (uint32_t)fec->base_ptr;
421 puts("fec_mxc: not enough malloc memory\n");
424 memset((void *)base, 0, (2 + FEC_RBD_NUM) *
425 sizeof(struct fec_bd) + DB_ALIGNMENT);
426 base += (DB_ALIGNMENT-1);
427 base &= ~(DB_ALIGNMENT-1);
429 fec->rbd_base = (struct fec_bd *)base;
431 base += FEC_RBD_NUM * sizeof(struct fec_bd);
433 fec->tbd_base = (struct fec_bd *)base;
436 * Set interrupt mask register
438 writel(0x00000000, &fec->eth->imask);
441 * Clear FEC-Lite interrupt event register(IEVENT)
443 writel(0xffffffff, &fec->eth->ievent);
447 * Set FEC-Lite receive control register(R_CNTRL):
450 /* Start with frame length = 1518, common for all modes. */
451 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
452 if (fec->xcv_type == SEVENWIRE)
453 rcntrl |= FEC_RCNTRL_FCE;
454 else if (fec->xcv_type == RMII)
455 rcntrl |= FEC_RCNTRL_RMII;
457 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
459 writel(rcntrl, &fec->eth->r_cntrl);
461 if (fec->xcv_type == MII10 || fec->xcv_type == MII100)
462 fec_mii_setspeed(fec);
465 * Set Opcode/Pause Duration Register
467 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
468 writel(0x2, &fec->eth->x_wmrk);
470 * Set multicast address filter
472 writel(0x00000000, &fec->eth->gaddr1);
473 writel(0x00000000, &fec->eth->gaddr2);
477 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
480 /* FIFO receive start register */
481 writel(0x520, &fec->eth->r_fstart);
483 /* size and address of each buffer */
484 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
485 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
486 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
489 * Initialize RxBD/TxBD rings
491 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
493 fec->base_ptr = NULL;
499 if (fec->xcv_type != SEVENWIRE)
500 miiphy_restart_aneg(dev);
507 * Halt the FEC engine
508 * @param[in] dev Our device to handle
510 static void fec_halt(struct eth_device *dev)
512 struct fec_priv *fec = (struct fec_priv *)dev->priv;
513 int counter = 0xffff;
516 * issue graceful stop command to the FEC transmitter if necessary
518 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
521 debug("eth_halt: wait for stop regs\n");
523 * wait for graceful stop to register
525 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
529 * Disable SmartDMA tasks
531 fec_tx_task_disable(fec);
532 fec_rx_task_disable(fec);
535 * Disable the Ethernet Controller
536 * Note: this will also reset the BD index counter!
538 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
542 debug("eth_halt: done\n");
547 * @param[in] dev Our ethernet device to handle
548 * @param[in] packet Pointer to the data to be transmitted
549 * @param[in] length Data count in bytes
550 * @return 0 on success
552 static int fec_send(struct eth_device *dev, volatile void* packet, int length)
557 * This routine transmits one frame. This routine only accepts
558 * 6-byte Ethernet addresses.
560 struct fec_priv *fec = (struct fec_priv *)dev->priv;
563 * Check for valid length of data.
565 if ((length > 1500) || (length <= 0)) {
566 printf("Payload (%d) too large\n", length);
571 * Setup the transmit buffer
572 * Note: We are always using the first buffer for transmission,
573 * the second will be empty and only used to stop the DMA engine
575 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
576 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
578 * update BD's status now
580 * - is always the last in a chain (means no chain)
581 * - should transmitt the CRC
582 * - might be the last BD in the list, so the address counter should
583 * wrap (-> keep the WRAP flag)
585 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
586 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
587 writew(status, &fec->tbd_base[fec->tbd_index].status);
590 * Enable SmartDMA transmit task
592 fec_tx_task_enable(fec);
595 * wait until frame is sent .
597 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
600 debug("fec_send: status 0x%x index %d\n",
601 readw(&fec->tbd_base[fec->tbd_index].status),
603 /* for next transmission use the other buffer */
613 * Pull one frame from the card
614 * @param[in] dev Our ethernet device to handle
615 * @return Length of packet read
617 static int fec_recv(struct eth_device *dev)
619 struct fec_priv *fec = (struct fec_priv *)dev->priv;
620 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
621 unsigned long ievent;
622 int frame_length, len = 0;
625 uchar buff[FEC_MAX_PKT_SIZE];
628 * Check if any critical events have happened
630 ievent = readl(&fec->eth->ievent);
631 writel(ievent, &fec->eth->ievent);
632 debug("fec_recv: ievent 0x%x\n", ievent);
633 if (ievent & FEC_IEVENT_BABR) {
635 fec_init(dev, fec->bd);
636 printf("some error: 0x%08lx\n", ievent);
639 if (ievent & FEC_IEVENT_HBERR) {
640 /* Heartbeat error */
641 writel(0x00000001 | readl(&fec->eth->x_cntrl),
644 if (ievent & FEC_IEVENT_GRA) {
645 /* Graceful stop complete */
646 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
648 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
650 fec_init(dev, fec->bd);
655 * ensure reading the right buffer status
657 bd_status = readw(&rbd->status);
658 debug("fec_recv: status 0x%x\n", bd_status);
660 if (!(bd_status & FEC_RBD_EMPTY)) {
661 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
662 ((readw(&rbd->data_length) - 4) > 14)) {
664 * Get buffer address and size
666 frame = (struct nbuf *)readl(&rbd->data_pointer);
667 frame_length = readw(&rbd->data_length) - 4;
669 * Fill the buffer and pass it to upper layers
671 memcpy(buff, frame->data, frame_length);
672 NetReceive(buff, frame_length);
675 if (bd_status & FEC_RBD_ERR)
676 printf("error frame: 0x%08lx 0x%08x\n",
677 (ulong)rbd->data_pointer,
681 * free the current buffer, restart the engine
682 * and move forward to the next buffer
684 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
685 fec_rx_task_enable(fec);
686 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
688 debug("fec_recv: stop\n");
693 static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
695 struct eth_device *edev;
696 struct fec_priv *fec;
697 unsigned char ethaddr[6];
701 /* create and fill edev struct */
702 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
704 puts("fec_mxc: not enough malloc memory for eth_device\n");
709 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
711 puts("fec_mxc: not enough malloc memory for fec_priv\n");
716 memset(edev, 0, sizeof(*edev));
717 memset(fec, 0, sizeof(*fec));
720 edev->init = fec_init;
721 edev->send = fec_send;
722 edev->recv = fec_recv;
723 edev->halt = fec_halt;
724 edev->write_hwaddr = fec_set_hwaddr;
726 fec->eth = (struct ethernet_regs *)base_addr;
729 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
732 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
733 start = get_timer(0);
734 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
735 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
736 printf("FEC MXC: Timeout reseting chip\n");
743 * Set interrupt mask register
745 writel(0x00000000, &fec->eth->imask);
748 * Clear FEC-Lite interrupt event register(IEVENT)
750 writel(0xffffffff, &fec->eth->ievent);
753 * Set FEC-Lite receive control register(R_CNTRL):
756 * Frame length=1518; MII mode;
758 writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE |
759 FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl);
760 fec_mii_setspeed(fec);
763 sprintf(edev->name, "FEC");
766 sprintf(edev->name, "FEC%i", dev_id);
767 fec->dev_id = dev_id;
769 fec->phy_id = phy_id;
771 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
775 if (fec_get_hwaddr(edev, ethaddr) == 0) {
776 debug("got MAC address from fuse: %pM\n", ethaddr);
777 memcpy(edev->enetaddr, ethaddr, 6);
790 #ifndef CONFIG_FEC_MXC_MULTI
791 int fecmxc_initialize(bd_t *bd)
795 debug("eth_init: fec_probe(bd)\n");
796 lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
802 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
806 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
807 lout = fec_probe(bd, dev_id, phy_id, addr);
812 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
814 struct fec_priv *fec = (struct fec_priv *)dev->priv;
815 fec->mii_postcall = cb;