2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/clock.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/imx-common/sys_proto.h>
22 #include <asm/errno.h>
23 #include <linux/compiler.h>
25 DECLARE_GLOBAL_DATA_PTR;
28 * Timeout the transfer after 5 mS. This is usually a bit more, since
29 * the code in the tightloops this timeout is used in adds some overhead.
31 #define FEC_XFER_TIMEOUT 5000
34 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
35 * 64-byte alignment in the DMA RX FEC buffer.
36 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
37 * satisfies the alignment on other SoCs (32-bytes)
39 #define FEC_DMA_RX_MINALIGN 64
42 #error "CONFIG_MII has to be defined!"
45 #ifndef CONFIG_FEC_XCV_TYPE
46 #define CONFIG_FEC_XCV_TYPE MII100
50 * The i.MX28 operates with packets in big endian. We need to swap them before
51 * sending and after receiving.
54 #define CONFIG_FEC_MXC_SWAP_PACKET
57 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
59 /* Check various alignment issues at compile time */
60 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
61 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
64 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
65 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
66 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
71 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
72 static void swap_packet(uint32_t *packet, int length)
76 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
77 packet[i] = __swab32(packet[i]);
82 * MII-interface related functions
84 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
87 uint32_t reg; /* convenient holder for the PHY register */
88 uint32_t phy; /* convenient holder for the PHY */
93 * reading from any PHY's register is done by properly
94 * programming the FEC's MII data register.
96 writel(FEC_IEVENT_MII, ð->ievent);
97 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
98 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
100 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
101 phy | reg, ð->mii_data);
104 * wait for the related interrupt
106 start = get_timer(0);
107 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
108 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
109 printf("Read MDIO failed...\n");
115 * clear mii interrupt bit
117 writel(FEC_IEVENT_MII, ð->ievent);
120 * it's now safe to read the PHY's register
122 val = (unsigned short)readl(ð->mii_data);
123 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
128 static void fec_mii_setspeed(struct ethernet_regs *eth)
131 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
132 * and do not drop the Preamble.
134 register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000);
135 #ifdef FEC_QUIRK_ENET_MAC
139 writel(speed, ð->mii_speed);
140 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
143 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
144 uint8_t regAddr, uint16_t data)
146 uint32_t reg; /* convenient holder for the PHY register */
147 uint32_t phy; /* convenient holder for the PHY */
150 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
151 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
153 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
154 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
157 * wait for the MII interrupt
159 start = get_timer(0);
160 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
161 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
162 printf("Write MDIO failed...\n");
168 * clear MII interrupt bit
170 writel(FEC_IEVENT_MII, ð->ievent);
171 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
177 static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr,
180 return fec_mdio_read(bus->priv, phyAddr, regAddr);
183 static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr,
184 int regAddr, u16 data)
186 return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
189 #ifndef CONFIG_PHYLIB
190 static int miiphy_restart_aneg(struct eth_device *dev)
193 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
194 struct fec_priv *fec = (struct fec_priv *)dev->priv;
195 struct ethernet_regs *eth = fec->bus->priv;
198 * Wake up from sleep if necessary
199 * Reset PHY, then delay 300ns
202 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
204 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
208 * Set the auto-negotiation advertisement register bits
210 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
211 LPA_100FULL | LPA_100HALF | LPA_10FULL |
212 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
213 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
214 BMCR_ANENABLE | BMCR_ANRESTART);
216 if (fec->mii_postcall)
217 ret = fec->mii_postcall(fec->phy_id);
223 static int miiphy_wait_aneg(struct eth_device *dev)
227 struct fec_priv *fec = (struct fec_priv *)dev->priv;
228 struct ethernet_regs *eth = fec->bus->priv;
231 * Wait for AN completion
233 start = get_timer(0);
235 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
236 printf("%s: Autonegotiation timeout\n", dev->name);
240 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
242 printf("%s: Autonegotiation failed. status: %d\n",
246 } while (!(status & BMSR_LSTATUS));
252 static int fec_rx_task_enable(struct fec_priv *fec)
254 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
258 static int fec_rx_task_disable(struct fec_priv *fec)
263 static int fec_tx_task_enable(struct fec_priv *fec)
265 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
269 static int fec_tx_task_disable(struct fec_priv *fec)
275 * Initialize receive task's buffer descriptors
276 * @param[in] fec all we know about the device yet
277 * @param[in] count receive buffer count to be allocated
278 * @param[in] dsize desired size of each receive buffer
279 * @return 0 on success
281 * Init all RX descriptors to default values.
283 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
290 * Reload the RX descriptors with default values and wipe
293 size = roundup(dsize, ARCH_DMA_MINALIGN);
294 for (i = 0; i < count; i++) {
295 data = (uint8_t *)fec->rbd_base[i].data_pointer;
296 memset(data, 0, dsize);
297 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
299 fec->rbd_base[i].status = FEC_RBD_EMPTY;
300 fec->rbd_base[i].data_length = 0;
303 /* Mark the last RBD to close the ring. */
304 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
307 flush_dcache_range((unsigned)fec->rbd_base,
308 (unsigned)fec->rbd_base + size);
312 * Initialize transmit task's buffer descriptors
313 * @param[in] fec all we know about the device yet
315 * Transmit buffers are created externally. We only have to init the BDs here.\n
316 * Note: There is a race condition in the hardware. When only one BD is in
317 * use it must be marked with the WRAP bit to use it for every transmitt.
318 * This bit in combination with the READY bit results into double transmit
319 * of each data buffer. It seems the state machine checks READY earlier then
320 * resetting it after the first transfer.
321 * Using two BDs solves this issue.
323 static void fec_tbd_init(struct fec_priv *fec)
325 unsigned addr = (unsigned)fec->tbd_base;
326 unsigned size = roundup(2 * sizeof(struct fec_bd),
329 memset(fec->tbd_base, 0, size);
330 fec->tbd_base[0].status = 0;
331 fec->tbd_base[1].status = FEC_TBD_WRAP;
333 flush_dcache_range(addr, addr + size);
337 * Mark the given read buffer descriptor as free
338 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
339 * @param[in] pRbd buffer descriptor to mark free again
341 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
343 unsigned short flags = FEC_RBD_EMPTY;
345 flags |= FEC_RBD_WRAP;
346 writew(flags, &pRbd->status);
347 writew(0, &pRbd->data_length);
350 static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
353 imx_get_mac_from_fuse(dev_id, mac);
354 return !is_valid_ethaddr(mac);
357 static int fec_set_hwaddr(struct eth_device *dev)
359 uchar *mac = dev->enetaddr;
360 struct fec_priv *fec = (struct fec_priv *)dev->priv;
362 writel(0, &fec->eth->iaddr1);
363 writel(0, &fec->eth->iaddr2);
364 writel(0, &fec->eth->gaddr1);
365 writel(0, &fec->eth->gaddr2);
368 * Set physical address
370 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
372 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
378 * Do initial configuration of the FEC registers
380 static void fec_reg_setup(struct fec_priv *fec)
385 * Set interrupt mask register
387 writel(0x00000000, &fec->eth->imask);
390 * Clear FEC-Lite interrupt event register(IEVENT)
392 writel(0xffffffff, &fec->eth->ievent);
396 * Set FEC-Lite receive control register(R_CNTRL):
399 /* Start with frame length = 1518, common for all modes. */
400 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
401 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
402 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
403 if (fec->xcv_type == RGMII)
404 rcntrl |= FEC_RCNTRL_RGMII;
405 else if (fec->xcv_type == RMII)
406 rcntrl |= FEC_RCNTRL_RMII;
408 writel(rcntrl, &fec->eth->r_cntrl);
412 * Start the FEC engine
413 * @param[in] dev Our device to handle
415 static int fec_open(struct eth_device *edev)
417 struct fec_priv *fec = (struct fec_priv *)edev->priv;
422 debug("fec_open: fec_open(dev)\n");
423 /* full-duplex, heartbeat disabled */
424 writel(1 << 2, &fec->eth->x_cntrl);
427 /* Invalidate all descriptors */
428 for (i = 0; i < FEC_RBD_NUM - 1; i++)
429 fec_rbd_clean(0, &fec->rbd_base[i]);
430 fec_rbd_clean(1, &fec->rbd_base[i]);
432 /* Flush the descriptors into RAM */
433 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
435 addr = (uint32_t)fec->rbd_base;
436 flush_dcache_range(addr, addr + size);
438 #ifdef FEC_QUIRK_ENET_MAC
439 /* Enable ENET HW endian SWAP */
440 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
442 /* Enable ENET store and forward mode */
443 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
447 * Enable FEC-Lite controller
449 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
451 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
454 * setup the MII gasket for RMII mode
457 /* disable the gasket */
458 writew(0, &fec->eth->miigsk_enr);
460 /* wait for the gasket to be disabled */
461 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
464 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
465 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
467 /* re-enable the gasket */
468 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
470 /* wait until MII gasket is ready */
472 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
473 if (--max_loops <= 0) {
474 printf("WAIT for MII Gasket ready timed out\n");
482 /* Start up the PHY */
483 int ret = phy_startup(fec->phydev);
486 printf("Could not initialize PHY %s\n",
487 fec->phydev->dev->name);
490 speed = fec->phydev->speed;
493 miiphy_wait_aneg(edev);
494 speed = miiphy_speed(edev->name, fec->phy_id);
495 miiphy_duplex(edev->name, fec->phy_id);
498 #ifdef FEC_QUIRK_ENET_MAC
500 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
501 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
502 if (speed == _1000BASET)
503 ecr |= FEC_ECNTRL_SPEED;
504 else if (speed != _100BASET)
505 rcr |= FEC_RCNTRL_RMII_10T;
506 writel(ecr, &fec->eth->ecntrl);
507 writel(rcr, &fec->eth->r_cntrl);
510 debug("%s:Speed=%i\n", __func__, speed);
513 * Enable SmartDMA receive task
515 fec_rx_task_enable(fec);
521 static int fec_init(struct eth_device *dev, bd_t* bd)
523 struct fec_priv *fec = (struct fec_priv *)dev->priv;
524 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
527 /* Initialize MAC address */
531 * Setup transmit descriptors, there are two in total.
535 /* Setup receive descriptors. */
536 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
540 if (fec->xcv_type != SEVENWIRE)
541 fec_mii_setspeed(fec->bus->priv);
544 * Set Opcode/Pause Duration Register
546 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
547 writel(0x2, &fec->eth->x_wmrk);
549 * Set multicast address filter
551 writel(0x00000000, &fec->eth->gaddr1);
552 writel(0x00000000, &fec->eth->gaddr2);
555 /* Do not access reserved register for i.MX6UL */
556 if (!is_cpu_type(MXC_CPU_MX6UL)) {
558 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
561 /* FIFO receive start register */
562 writel(0x520, &fec->eth->r_fstart);
565 /* size and address of each buffer */
566 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
567 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
568 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
570 #ifndef CONFIG_PHYLIB
571 if (fec->xcv_type != SEVENWIRE)
572 miiphy_restart_aneg(dev);
579 * Halt the FEC engine
580 * @param[in] dev Our device to handle
582 static void fec_halt(struct eth_device *dev)
584 struct fec_priv *fec = (struct fec_priv *)dev->priv;
585 int counter = 0xffff;
588 * issue graceful stop command to the FEC transmitter if necessary
590 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
593 debug("eth_halt: wait for stop regs\n");
595 * wait for graceful stop to register
597 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
601 * Disable SmartDMA tasks
603 fec_tx_task_disable(fec);
604 fec_rx_task_disable(fec);
607 * Disable the Ethernet Controller
608 * Note: this will also reset the BD index counter!
610 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
614 debug("eth_halt: done\n");
619 * @param[in] dev Our ethernet device to handle
620 * @param[in] packet Pointer to the data to be transmitted
621 * @param[in] length Data count in bytes
622 * @return 0 on success
624 static int fec_send(struct eth_device *dev, void *packet, int length)
629 int timeout = FEC_XFER_TIMEOUT;
633 * This routine transmits one frame. This routine only accepts
634 * 6-byte Ethernet addresses.
636 struct fec_priv *fec = (struct fec_priv *)dev->priv;
639 * Check for valid length of data.
641 if ((length > 1500) || (length <= 0)) {
642 printf("Payload (%d) too large\n", length);
647 * Setup the transmit buffer. We are always using the first buffer for
648 * transmission, the second will be empty and only used to stop the DMA
649 * engine. We also flush the packet to RAM here to avoid cache trouble.
651 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
652 swap_packet((uint32_t *)packet, length);
655 addr = (uint32_t)packet;
656 end = roundup(addr + length, ARCH_DMA_MINALIGN);
657 addr &= ~(ARCH_DMA_MINALIGN - 1);
658 flush_dcache_range(addr, end);
660 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
661 writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
664 * update BD's status now
666 * - is always the last in a chain (means no chain)
667 * - should transmitt the CRC
668 * - might be the last BD in the list, so the address counter should
669 * wrap (-> keep the WRAP flag)
671 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
672 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
673 writew(status, &fec->tbd_base[fec->tbd_index].status);
676 * Flush data cache. This code flushes both TX descriptors to RAM.
677 * After this code, the descriptors will be safely in RAM and we
680 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
681 addr = (uint32_t)fec->tbd_base;
682 flush_dcache_range(addr, addr + size);
685 * Below we read the DMA descriptor's last four bytes back from the
686 * DRAM. This is important in order to make sure that all WRITE
687 * operations on the bus that were triggered by previous cache FLUSH
690 * Otherwise, on MX28, it is possible to observe a corruption of the
691 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
692 * for the bus structure of MX28. The scenario is as follows:
694 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
695 * to DRAM due to flush_dcache_range()
696 * 2) ARM core writes the FEC registers via AHB_ARB2
697 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
699 * Note that 2) does sometimes finish before 1) due to reordering of
700 * WRITE accesses on the AHB bus, therefore triggering 3) before the
701 * DMA descriptor is fully written into DRAM. This results in occasional
702 * corruption of the DMA descriptor.
704 readl(addr + size - 4);
707 * Enable SmartDMA transmit task
709 fec_tx_task_enable(fec);
712 * Wait until frame is sent. On each turn of the wait cycle, we must
713 * invalidate data cache to see what's really in RAM. Also, we need
717 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
727 * The TDAR bit is cleared when the descriptors are all out from TX
728 * but on mx6solox we noticed that the READY bit is still not cleared
730 * These are two distinct signals, and in IC simulation, we found that
731 * TDAR always gets cleared prior than the READY bit of last BD becomes
733 * In mx6solox, we use a later version of FEC IP. It looks like that
734 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
737 * Fix this by polling the READY bit of BD after the TDAR polling,
738 * which covers the mx6solox case and does not harm the other SoCs.
740 timeout = FEC_XFER_TIMEOUT;
742 invalidate_dcache_range(addr, addr + size);
743 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
752 debug("fec_send: status 0x%x index %d ret %i\n",
753 readw(&fec->tbd_base[fec->tbd_index].status),
754 fec->tbd_index, ret);
755 /* for next transmission use the other buffer */
765 * Pull one frame from the card
766 * @param[in] dev Our ethernet device to handle
767 * @return Length of packet read
769 static int fec_recv(struct eth_device *dev)
771 struct fec_priv *fec = (struct fec_priv *)dev->priv;
772 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
773 unsigned long ievent;
774 int frame_length, len = 0;
776 uint32_t addr, size, end;
778 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
781 * Check if any critical events have happened
783 ievent = readl(&fec->eth->ievent);
784 writel(ievent, &fec->eth->ievent);
785 debug("fec_recv: ievent 0x%lx\n", ievent);
786 if (ievent & FEC_IEVENT_BABR) {
788 fec_init(dev, fec->bd);
789 printf("some error: 0x%08lx\n", ievent);
792 if (ievent & FEC_IEVENT_HBERR) {
793 /* Heartbeat error */
794 writel(0x00000001 | readl(&fec->eth->x_cntrl),
797 if (ievent & FEC_IEVENT_GRA) {
798 /* Graceful stop complete */
799 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
801 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
803 fec_init(dev, fec->bd);
808 * Read the buffer status. Before the status can be read, the data cache
809 * must be invalidated, because the data in RAM might have been changed
810 * by DMA. The descriptors are properly aligned to cachelines so there's
811 * no need to worry they'd overlap.
813 * WARNING: By invalidating the descriptor here, we also invalidate
814 * the descriptors surrounding this one. Therefore we can NOT change the
815 * contents of this descriptor nor the surrounding ones. The problem is
816 * that in order to mark the descriptor as processed, we need to change
817 * the descriptor. The solution is to mark the whole cache line when all
818 * descriptors in the cache line are processed.
820 addr = (uint32_t)rbd;
821 addr &= ~(ARCH_DMA_MINALIGN - 1);
822 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
823 invalidate_dcache_range(addr, addr + size);
825 bd_status = readw(&rbd->status);
826 debug("fec_recv: status 0x%x\n", bd_status);
828 if (!(bd_status & FEC_RBD_EMPTY)) {
829 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
830 ((readw(&rbd->data_length) - 4) > 14)) {
832 * Get buffer address and size
834 addr = readl(&rbd->data_pointer);
835 frame_length = readw(&rbd->data_length) - 4;
837 * Invalidate data cache over the buffer
839 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
840 addr &= ~(ARCH_DMA_MINALIGN - 1);
841 invalidate_dcache_range(addr, end);
844 * Fill the buffer and pass it to upper layers
846 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
847 swap_packet((uint32_t *)addr, frame_length);
849 memcpy(buff, (char *)addr, frame_length);
850 net_process_received_packet(buff, frame_length);
853 if (bd_status & FEC_RBD_ERR)
854 printf("error frame: 0x%08x 0x%08x\n",
859 * Free the current buffer, restart the engine and move forward
860 * to the next buffer. Here we check if the whole cacheline of
861 * descriptors was already processed and if so, we mark it free
864 size = RXDESC_PER_CACHELINE - 1;
865 if ((fec->rbd_index & size) == size) {
866 i = fec->rbd_index - size;
867 addr = (uint32_t)&fec->rbd_base[i];
868 for (; i <= fec->rbd_index ; i++) {
869 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
872 flush_dcache_range(addr,
873 addr + ARCH_DMA_MINALIGN);
876 fec_rx_task_enable(fec);
877 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
879 debug("fec_recv: stop\n");
884 static void fec_set_dev_name(char *dest, int dev_id)
886 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
889 static int fec_alloc_descs(struct fec_priv *fec)
895 /* Allocate TX descriptors. */
896 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
897 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
901 /* Allocate RX descriptors. */
902 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
903 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
907 memset(fec->rbd_base, 0, size);
909 /* Allocate RX buffers. */
911 /* Maximum RX buffer size. */
912 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
913 for (i = 0; i < FEC_RBD_NUM; i++) {
914 data = memalign(FEC_DMA_RX_MINALIGN, size);
916 printf("%s: error allocating rxbuf %d\n", __func__, i);
920 memset(data, 0, size);
922 fec->rbd_base[i].data_pointer = (uint32_t)data;
923 fec->rbd_base[i].status = FEC_RBD_EMPTY;
924 fec->rbd_base[i].data_length = 0;
925 /* Flush the buffer to memory. */
926 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
929 /* Mark the last RBD to close the ring. */
930 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
939 free((void *)fec->rbd_base[i].data_pointer);
947 static void fec_free_descs(struct fec_priv *fec)
951 for (i = 0; i < FEC_RBD_NUM; i++)
952 free((void *)fec->rbd_base[i].data_pointer);
958 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
959 struct mii_dev *bus, struct phy_device *phydev)
961 static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
962 struct mii_dev *bus, int phy_id)
965 struct eth_device *edev;
966 struct fec_priv *fec;
967 unsigned char ethaddr[6];
971 /* create and fill edev struct */
972 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
974 puts("fec_mxc: not enough malloc memory for eth_device\n");
979 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
981 puts("fec_mxc: not enough malloc memory for fec_priv\n");
986 memset(edev, 0, sizeof(*edev));
987 memset(fec, 0, sizeof(*fec));
989 ret = fec_alloc_descs(fec);
994 edev->init = fec_init;
995 edev->send = fec_send;
996 edev->recv = fec_recv;
997 edev->halt = fec_halt;
998 edev->write_hwaddr = fec_set_hwaddr;
1000 fec->eth = (struct ethernet_regs *)base_addr;
1003 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1006 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1007 start = get_timer(0);
1008 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1009 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1010 printf("FEC MXC: Timeout reseting chip\n");
1017 fec_set_dev_name(edev->name, dev_id);
1018 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1020 fec_mii_setspeed(bus->priv);
1021 #ifdef CONFIG_PHYLIB
1022 fec->phydev = phydev;
1023 phy_connect_dev(phydev, edev);
1027 fec->phy_id = phy_id;
1031 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
1032 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
1033 memcpy(edev->enetaddr, ethaddr, 6);
1034 if (!getenv("ethaddr"))
1035 eth_setenv_enetaddr("ethaddr", ethaddr);
1039 fec_free_descs(fec);
1048 struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
1050 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1051 struct mii_dev *bus;
1056 printf("mdio_alloc failed\n");
1059 bus->read = fec_phy_read;
1060 bus->write = fec_phy_write;
1062 fec_set_dev_name(bus->name, dev_id);
1064 ret = mdio_register(bus);
1066 printf("mdio_register failed\n");
1070 fec_mii_setspeed(eth);
1074 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1077 struct mii_dev *bus = NULL;
1078 #ifdef CONFIG_PHYLIB
1079 struct phy_device *phydev = NULL;
1085 * The i.MX28 has two ethernet interfaces, but they are not equal.
1086 * Only the first one can access the MDIO bus.
1088 base_mii = MXS_ENET0_BASE;
1092 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1093 bus = fec_get_miibus(base_mii, dev_id);
1096 #ifdef CONFIG_PHYLIB
1097 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1102 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1104 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1107 #ifdef CONFIG_PHYLIB
1115 #ifdef CONFIG_FEC_MXC_PHYADDR
1116 int fecmxc_initialize(bd_t *bd)
1118 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1123 #ifndef CONFIG_PHYLIB
1124 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1126 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1127 fec->mii_postcall = cb;