1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
4 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
5 * (C) Copyright 2008 Armadeus Systems nc
6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
19 #include <asm/cache.h>
20 #include <power/regulator.h>
23 #include <linux/errno.h>
24 #include <linux/compiler.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/imx-regs.h>
28 #include <asm/mach-imx/sys_proto.h>
29 #include <asm-generic/gpio.h>
34 DECLARE_GLOBAL_DATA_PTR;
37 * Timeout the transfer after 5 mS. This is usually a bit more, since
38 * the code in the tightloops this timeout is used in adds some overhead.
40 #define FEC_XFER_TIMEOUT 5000
43 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
44 * 64-byte alignment in the DMA RX FEC buffer.
45 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
46 * satisfies the alignment on other SoCs (32-bytes)
48 #define FEC_DMA_RX_MINALIGN 64
51 #error "CONFIG_MII has to be defined!"
54 #ifndef CONFIG_FEC_XCV_TYPE
55 #define CONFIG_FEC_XCV_TYPE MII100
59 * The i.MX28 operates with packets in big endian. We need to swap them before
60 * sending and after receiving.
63 #define CONFIG_FEC_MXC_SWAP_PACKET
66 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
68 /* Check various alignment issues at compile time */
69 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
70 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
73 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
74 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
75 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
80 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
81 static void swap_packet(uint32_t *packet, int length)
85 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
86 packet[i] = __swab32(packet[i]);
90 /* MII-interface related functions */
91 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
94 uint32_t reg; /* convenient holder for the PHY register */
95 uint32_t phy; /* convenient holder for the PHY */
100 * reading from any PHY's register is done by properly
101 * programming the FEC's MII data register.
103 writel(FEC_IEVENT_MII, ð->ievent);
104 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
105 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
107 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
108 phy | reg, ð->mii_data);
110 /* wait for the related interrupt */
111 start = get_timer(0);
112 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
113 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
114 printf("Read MDIO failed...\n");
119 /* clear mii interrupt bit */
120 writel(FEC_IEVENT_MII, ð->ievent);
122 /* it's now safe to read the PHY's register */
123 val = (unsigned short)readl(ð->mii_data);
124 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
129 #ifndef imx_get_fecclk
130 u32 __weak imx_get_fecclk(void)
136 static int fec_get_clk_rate(void *udev, int idx)
138 struct fec_priv *fec;
142 if (IS_ENABLED(CONFIG_IMX8) ||
143 CONFIG_IS_ENABLED(CLK_CCF)) {
146 ret = uclass_get_device(UCLASS_ETH, idx, &dev);
148 debug("Can't get FEC udev: %d\n", ret);
153 fec = dev_get_priv(dev);
155 return fec->clk_rate;
159 return imx_get_fecclk();
163 static void fec_mii_setspeed(struct ethernet_regs *eth)
166 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
167 * and do not drop the Preamble.
169 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
170 * MII_SPEED) register that defines the MDIO output hold time. Earlier
171 * versions are RAZ there, so just ignore the difference and write the
173 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
174 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
176 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
177 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
178 * holdtime cannot result in a value greater than 3.
185 ret = fec_get_clk_rate(NULL, 0);
187 printf("Can't find FEC0 clk rate: %d\n", ret);
191 speed = DIV_ROUND_UP(pclk, 5000000);
192 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
194 #ifdef FEC_QUIRK_ENET_MAC
197 writel(speed << 1 | hold << 8, ð->mii_speed);
198 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
201 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
202 uint8_t regaddr, uint16_t data)
204 uint32_t reg; /* convenient holder for the PHY register */
205 uint32_t phy; /* convenient holder for the PHY */
208 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
209 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
211 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
212 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
214 /* wait for the MII interrupt */
215 start = get_timer(0);
216 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
217 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
218 printf("Write MDIO failed...\n");
223 /* clear MII interrupt bit */
224 writel(FEC_IEVENT_MII, ð->ievent);
225 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
231 static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
234 return fec_mdio_read(bus->priv, phyaddr, regaddr);
237 static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
238 int regaddr, u16 data)
240 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
243 #ifndef CONFIG_PHYLIB
244 static int miiphy_restart_aneg(struct eth_device *dev)
247 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
248 struct fec_priv *fec = (struct fec_priv *)dev->priv;
249 struct ethernet_regs *eth = fec->bus->priv;
252 * Wake up from sleep if necessary
253 * Reset PHY, then delay 300ns
256 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
258 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
261 /* Set the auto-negotiation advertisement register bits */
262 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
263 LPA_100FULL | LPA_100HALF | LPA_10FULL |
264 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
265 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
266 BMCR_ANENABLE | BMCR_ANRESTART);
268 if (fec->mii_postcall)
269 ret = fec->mii_postcall(fec->phy_id);
275 #ifndef CONFIG_FEC_FIXED_SPEED
276 static int miiphy_wait_aneg(struct eth_device *dev)
280 struct fec_priv *fec = (struct fec_priv *)dev->priv;
281 struct ethernet_regs *eth = fec->bus->priv;
283 /* Wait for AN completion */
284 start = get_timer(0);
286 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
287 printf("%s: Autonegotiation timeout\n", dev->name);
291 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
293 printf("%s: Autonegotiation failed. status: %d\n",
297 } while (!(status & BMSR_LSTATUS));
301 #endif /* CONFIG_FEC_FIXED_SPEED */
304 static int fec_rx_task_enable(struct fec_priv *fec)
306 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
310 static int fec_rx_task_disable(struct fec_priv *fec)
315 static int fec_tx_task_enable(struct fec_priv *fec)
317 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
321 static int fec_tx_task_disable(struct fec_priv *fec)
327 * Initialize receive task's buffer descriptors
328 * @param[in] fec all we know about the device yet
329 * @param[in] count receive buffer count to be allocated
330 * @param[in] dsize desired size of each receive buffer
331 * @return 0 on success
333 * Init all RX descriptors to default values.
335 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
342 * Reload the RX descriptors with default values and wipe
345 size = roundup(dsize, ARCH_DMA_MINALIGN);
346 for (i = 0; i < count; i++) {
347 data = fec->rbd_base[i].data_pointer;
348 memset((void *)data, 0, dsize);
349 flush_dcache_range(data, data + size);
351 fec->rbd_base[i].status = FEC_RBD_EMPTY;
352 fec->rbd_base[i].data_length = 0;
355 /* Mark the last RBD to close the ring. */
356 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
359 flush_dcache_range((ulong)fec->rbd_base,
360 (ulong)fec->rbd_base + size);
364 * Initialize transmit task's buffer descriptors
365 * @param[in] fec all we know about the device yet
367 * Transmit buffers are created externally. We only have to init the BDs here.\n
368 * Note: There is a race condition in the hardware. When only one BD is in
369 * use it must be marked with the WRAP bit to use it for every transmitt.
370 * This bit in combination with the READY bit results into double transmit
371 * of each data buffer. It seems the state machine checks READY earlier then
372 * resetting it after the first transfer.
373 * Using two BDs solves this issue.
375 static void fec_tbd_init(struct fec_priv *fec)
377 ulong addr = (ulong)fec->tbd_base;
378 unsigned size = roundup(2 * sizeof(struct fec_bd),
381 memset(fec->tbd_base, 0, size);
382 fec->tbd_base[0].status = 0;
383 fec->tbd_base[1].status = FEC_TBD_WRAP;
385 flush_dcache_range(addr, addr + size);
389 * Mark the given read buffer descriptor as free
390 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
391 * @param[in] prbd buffer descriptor to mark free again
393 static void fec_rbd_clean(int last, struct fec_bd *prbd)
395 unsigned short flags = FEC_RBD_EMPTY;
397 flags |= FEC_RBD_WRAP;
398 writew(flags, &prbd->status);
399 writew(0, &prbd->data_length);
402 static int fec_get_hwaddr(int dev_id, unsigned char *mac)
404 imx_get_mac_from_fuse(dev_id, mac);
405 return !is_valid_ethaddr(mac);
409 static int fecmxc_set_hwaddr(struct udevice *dev)
411 static int fec_set_hwaddr(struct eth_device *dev)
415 struct fec_priv *fec = dev_get_priv(dev);
416 struct eth_pdata *pdata = dev_get_platdata(dev);
417 uchar *mac = pdata->enetaddr;
419 uchar *mac = dev->enetaddr;
420 struct fec_priv *fec = (struct fec_priv *)dev->priv;
423 writel(0, &fec->eth->iaddr1);
424 writel(0, &fec->eth->iaddr2);
425 writel(0, &fec->eth->gaddr1);
426 writel(0, &fec->eth->gaddr2);
428 /* Set physical address */
429 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
431 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
436 /* Do initial configuration of the FEC registers */
437 static void fec_reg_setup(struct fec_priv *fec)
441 /* Set interrupt mask register */
442 writel(0x00000000, &fec->eth->imask);
444 /* Clear FEC-Lite interrupt event register(IEVENT) */
445 writel(0xffffffff, &fec->eth->ievent);
447 /* Set FEC-Lite receive control register(R_CNTRL): */
449 /* Start with frame length = 1518, common for all modes. */
450 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
451 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
452 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
453 if (fec->xcv_type == RGMII)
454 rcntrl |= FEC_RCNTRL_RGMII;
455 else if (fec->xcv_type == RMII)
456 rcntrl |= FEC_RCNTRL_RMII;
458 writel(rcntrl, &fec->eth->r_cntrl);
462 * Start the FEC engine
463 * @param[in] dev Our device to handle
466 static int fec_open(struct udevice *dev)
468 static int fec_open(struct eth_device *edev)
472 struct fec_priv *fec = dev_get_priv(dev);
474 struct fec_priv *fec = (struct fec_priv *)edev->priv;
480 debug("fec_open: fec_open(dev)\n");
481 /* full-duplex, heartbeat disabled */
482 writel(1 << 2, &fec->eth->x_cntrl);
485 /* Invalidate all descriptors */
486 for (i = 0; i < FEC_RBD_NUM - 1; i++)
487 fec_rbd_clean(0, &fec->rbd_base[i]);
488 fec_rbd_clean(1, &fec->rbd_base[i]);
490 /* Flush the descriptors into RAM */
491 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
493 addr = (ulong)fec->rbd_base;
494 flush_dcache_range(addr, addr + size);
496 #ifdef FEC_QUIRK_ENET_MAC
497 /* Enable ENET HW endian SWAP */
498 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
500 /* Enable ENET store and forward mode */
501 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
504 /* Enable FEC-Lite controller */
505 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
508 #ifdef FEC_ENET_ENABLE_TXC_DELAY
509 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_TXC_DLY,
513 #ifdef FEC_ENET_ENABLE_RXC_DELAY
514 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RXC_DLY,
518 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
521 /* setup the MII gasket for RMII mode */
522 /* disable the gasket */
523 writew(0, &fec->eth->miigsk_enr);
525 /* wait for the gasket to be disabled */
526 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
529 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
530 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
532 /* re-enable the gasket */
533 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
535 /* wait until MII gasket is ready */
537 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
538 if (--max_loops <= 0) {
539 printf("WAIT for MII Gasket ready timed out\n");
547 /* Start up the PHY */
548 int ret = phy_startup(fec->phydev);
551 printf("Could not initialize PHY %s\n",
552 fec->phydev->dev->name);
555 speed = fec->phydev->speed;
557 #elif CONFIG_FEC_FIXED_SPEED
558 speed = CONFIG_FEC_FIXED_SPEED;
560 miiphy_wait_aneg(edev);
561 speed = miiphy_speed(edev->name, fec->phy_id);
562 miiphy_duplex(edev->name, fec->phy_id);
565 #ifdef FEC_QUIRK_ENET_MAC
567 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
568 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
569 if (speed == _1000BASET)
570 ecr |= FEC_ECNTRL_SPEED;
571 else if (speed != _100BASET)
572 rcr |= FEC_RCNTRL_RMII_10T;
573 writel(ecr, &fec->eth->ecntrl);
574 writel(rcr, &fec->eth->r_cntrl);
577 debug("%s:Speed=%i\n", __func__, speed);
579 /* Enable SmartDMA receive task */
580 fec_rx_task_enable(fec);
587 static int fecmxc_init(struct udevice *dev)
589 static int fec_init(struct eth_device *dev, bd_t *bd)
593 struct fec_priv *fec = dev_get_priv(dev);
595 struct fec_priv *fec = (struct fec_priv *)dev->priv;
597 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
601 /* Initialize MAC address */
603 fecmxc_set_hwaddr(dev);
608 /* Setup transmit descriptors, there are two in total. */
611 /* Setup receive descriptors. */
612 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
616 if (fec->xcv_type != SEVENWIRE)
617 fec_mii_setspeed(fec->bus->priv);
619 /* Set Opcode/Pause Duration Register */
620 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
621 writel(0x2, &fec->eth->x_wmrk);
623 /* Set multicast address filter */
624 writel(0x00000000, &fec->eth->gaddr1);
625 writel(0x00000000, &fec->eth->gaddr2);
627 /* Do not access reserved register */
628 if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) {
630 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
633 /* FIFO receive start register */
634 writel(0x520, &fec->eth->r_fstart);
637 /* size and address of each buffer */
638 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
640 addr = (ulong)fec->tbd_base;
641 writel((uint32_t)addr, &fec->eth->etdsr);
643 addr = (ulong)fec->rbd_base;
644 writel((uint32_t)addr, &fec->eth->erdsr);
646 #ifndef CONFIG_PHYLIB
647 if (fec->xcv_type != SEVENWIRE)
648 miiphy_restart_aneg(dev);
655 * Halt the FEC engine
656 * @param[in] dev Our device to handle
659 static void fecmxc_halt(struct udevice *dev)
661 static void fec_halt(struct eth_device *dev)
665 struct fec_priv *fec = dev_get_priv(dev);
667 struct fec_priv *fec = (struct fec_priv *)dev->priv;
669 int counter = 0xffff;
671 /* issue graceful stop command to the FEC transmitter if necessary */
672 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
675 debug("eth_halt: wait for stop regs\n");
676 /* wait for graceful stop to register */
677 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
680 /* Disable SmartDMA tasks */
681 fec_tx_task_disable(fec);
682 fec_rx_task_disable(fec);
685 * Disable the Ethernet Controller
686 * Note: this will also reset the BD index counter!
688 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
692 debug("eth_halt: done\n");
697 * @param[in] dev Our ethernet device to handle
698 * @param[in] packet Pointer to the data to be transmitted
699 * @param[in] length Data count in bytes
700 * @return 0 on success
703 static int fecmxc_send(struct udevice *dev, void *packet, int length)
705 static int fec_send(struct eth_device *dev, void *packet, int length)
711 int timeout = FEC_XFER_TIMEOUT;
715 * This routine transmits one frame. This routine only accepts
716 * 6-byte Ethernet addresses.
719 struct fec_priv *fec = dev_get_priv(dev);
721 struct fec_priv *fec = (struct fec_priv *)dev->priv;
725 * Check for valid length of data.
727 if ((length > 1500) || (length <= 0)) {
728 printf("Payload (%d) too large\n", length);
733 * Setup the transmit buffer. We are always using the first buffer for
734 * transmission, the second will be empty and only used to stop the DMA
735 * engine. We also flush the packet to RAM here to avoid cache trouble.
737 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
738 swap_packet((uint32_t *)packet, length);
741 addr = (ulong)packet;
742 end = roundup(addr + length, ARCH_DMA_MINALIGN);
743 addr &= ~(ARCH_DMA_MINALIGN - 1);
744 flush_dcache_range(addr, end);
746 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
747 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
750 * update BD's status now
752 * - is always the last in a chain (means no chain)
753 * - should transmitt the CRC
754 * - might be the last BD in the list, so the address counter should
755 * wrap (-> keep the WRAP flag)
757 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
758 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
759 writew(status, &fec->tbd_base[fec->tbd_index].status);
762 * Flush data cache. This code flushes both TX descriptors to RAM.
763 * After this code, the descriptors will be safely in RAM and we
766 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
767 addr = (ulong)fec->tbd_base;
768 flush_dcache_range(addr, addr + size);
771 * Below we read the DMA descriptor's last four bytes back from the
772 * DRAM. This is important in order to make sure that all WRITE
773 * operations on the bus that were triggered by previous cache FLUSH
776 * Otherwise, on MX28, it is possible to observe a corruption of the
777 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
778 * for the bus structure of MX28. The scenario is as follows:
780 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
781 * to DRAM due to flush_dcache_range()
782 * 2) ARM core writes the FEC registers via AHB_ARB2
783 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
785 * Note that 2) does sometimes finish before 1) due to reordering of
786 * WRITE accesses on the AHB bus, therefore triggering 3) before the
787 * DMA descriptor is fully written into DRAM. This results in occasional
788 * corruption of the DMA descriptor.
790 readl(addr + size - 4);
792 /* Enable SmartDMA transmit task */
793 fec_tx_task_enable(fec);
796 * Wait until frame is sent. On each turn of the wait cycle, we must
797 * invalidate data cache to see what's really in RAM. Also, we need
801 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
811 * The TDAR bit is cleared when the descriptors are all out from TX
812 * but on mx6solox we noticed that the READY bit is still not cleared
814 * These are two distinct signals, and in IC simulation, we found that
815 * TDAR always gets cleared prior than the READY bit of last BD becomes
817 * In mx6solox, we use a later version of FEC IP. It looks like that
818 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
821 * Fix this by polling the READY bit of BD after the TDAR polling,
822 * which covers the mx6solox case and does not harm the other SoCs.
824 timeout = FEC_XFER_TIMEOUT;
826 invalidate_dcache_range(addr, addr + size);
827 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
836 debug("fec_send: status 0x%x index %d ret %i\n",
837 readw(&fec->tbd_base[fec->tbd_index].status),
838 fec->tbd_index, ret);
839 /* for next transmission use the other buffer */
849 * Pull one frame from the card
850 * @param[in] dev Our ethernet device to handle
851 * @return Length of packet read
854 static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
856 static int fec_recv(struct eth_device *dev)
860 struct fec_priv *fec = dev_get_priv(dev);
862 struct fec_priv *fec = (struct fec_priv *)dev->priv;
864 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
865 unsigned long ievent;
866 int frame_length, len = 0;
868 ulong addr, size, end;
872 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
874 printf("%s: error allocating packetp\n", __func__);
878 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
881 /* Check if any critical events have happened */
882 ievent = readl(&fec->eth->ievent);
883 writel(ievent, &fec->eth->ievent);
884 debug("fec_recv: ievent 0x%lx\n", ievent);
885 if (ievent & FEC_IEVENT_BABR) {
891 fec_init(dev, fec->bd);
893 printf("some error: 0x%08lx\n", ievent);
896 if (ievent & FEC_IEVENT_HBERR) {
897 /* Heartbeat error */
898 writel(0x00000001 | readl(&fec->eth->x_cntrl),
901 if (ievent & FEC_IEVENT_GRA) {
902 /* Graceful stop complete */
903 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
909 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
914 fec_init(dev, fec->bd);
920 * Read the buffer status. Before the status can be read, the data cache
921 * must be invalidated, because the data in RAM might have been changed
922 * by DMA. The descriptors are properly aligned to cachelines so there's
923 * no need to worry they'd overlap.
925 * WARNING: By invalidating the descriptor here, we also invalidate
926 * the descriptors surrounding this one. Therefore we can NOT change the
927 * contents of this descriptor nor the surrounding ones. The problem is
928 * that in order to mark the descriptor as processed, we need to change
929 * the descriptor. The solution is to mark the whole cache line when all
930 * descriptors in the cache line are processed.
933 addr &= ~(ARCH_DMA_MINALIGN - 1);
934 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
935 invalidate_dcache_range(addr, addr + size);
937 bd_status = readw(&rbd->status);
938 debug("fec_recv: status 0x%x\n", bd_status);
940 if (!(bd_status & FEC_RBD_EMPTY)) {
941 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
942 ((readw(&rbd->data_length) - 4) > 14)) {
943 /* Get buffer address and size */
944 addr = readl(&rbd->data_pointer);
945 frame_length = readw(&rbd->data_length) - 4;
946 /* Invalidate data cache over the buffer */
947 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
948 addr &= ~(ARCH_DMA_MINALIGN - 1);
949 invalidate_dcache_range(addr, end);
951 /* Fill the buffer and pass it to upper layers */
952 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
953 swap_packet((uint32_t *)addr, frame_length);
957 memcpy(*packetp, (char *)addr, frame_length);
959 memcpy(buff, (char *)addr, frame_length);
960 net_process_received_packet(buff, frame_length);
964 if (bd_status & FEC_RBD_ERR)
965 debug("error frame: 0x%08lx 0x%08x\n",
970 * Free the current buffer, restart the engine and move forward
971 * to the next buffer. Here we check if the whole cacheline of
972 * descriptors was already processed and if so, we mark it free
975 size = RXDESC_PER_CACHELINE - 1;
976 if ((fec->rbd_index & size) == size) {
977 i = fec->rbd_index - size;
978 addr = (ulong)&fec->rbd_base[i];
979 for (; i <= fec->rbd_index ; i++) {
980 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
983 flush_dcache_range(addr,
984 addr + ARCH_DMA_MINALIGN);
987 fec_rx_task_enable(fec);
988 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
990 debug("fec_recv: stop\n");
995 static void fec_set_dev_name(char *dest, int dev_id)
997 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
1000 static int fec_alloc_descs(struct fec_priv *fec)
1007 /* Allocate TX descriptors. */
1008 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
1009 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
1013 /* Allocate RX descriptors. */
1014 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
1015 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
1019 memset(fec->rbd_base, 0, size);
1021 /* Allocate RX buffers. */
1023 /* Maximum RX buffer size. */
1024 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
1025 for (i = 0; i < FEC_RBD_NUM; i++) {
1026 data = memalign(FEC_DMA_RX_MINALIGN, size);
1028 printf("%s: error allocating rxbuf %d\n", __func__, i);
1032 memset(data, 0, size);
1035 fec->rbd_base[i].data_pointer = (uint32_t)addr;
1036 fec->rbd_base[i].status = FEC_RBD_EMPTY;
1037 fec->rbd_base[i].data_length = 0;
1038 /* Flush the buffer to memory. */
1039 flush_dcache_range(addr, addr + size);
1042 /* Mark the last RBD to close the ring. */
1043 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
1051 for (; i >= 0; i--) {
1052 addr = fec->rbd_base[i].data_pointer;
1055 free(fec->rbd_base);
1057 free(fec->tbd_base);
1062 static void fec_free_descs(struct fec_priv *fec)
1067 for (i = 0; i < FEC_RBD_NUM; i++) {
1068 addr = fec->rbd_base[i].data_pointer;
1071 free(fec->rbd_base);
1072 free(fec->tbd_base);
1075 struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
1077 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1078 struct mii_dev *bus;
1083 printf("mdio_alloc failed\n");
1086 bus->read = fec_phy_read;
1087 bus->write = fec_phy_write;
1089 fec_set_dev_name(bus->name, dev_id);
1091 ret = mdio_register(bus);
1093 printf("mdio_register failed\n");
1097 fec_mii_setspeed(eth);
1101 #ifndef CONFIG_DM_ETH
1102 #ifdef CONFIG_PHYLIB
1103 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1104 struct mii_dev *bus, struct phy_device *phydev)
1106 static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1107 struct mii_dev *bus, int phy_id)
1110 struct eth_device *edev;
1111 struct fec_priv *fec;
1112 unsigned char ethaddr[6];
1117 /* create and fill edev struct */
1118 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1120 puts("fec_mxc: not enough malloc memory for eth_device\n");
1125 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1127 puts("fec_mxc: not enough malloc memory for fec_priv\n");
1132 memset(edev, 0, sizeof(*edev));
1133 memset(fec, 0, sizeof(*fec));
1135 ret = fec_alloc_descs(fec);
1140 edev->init = fec_init;
1141 edev->send = fec_send;
1142 edev->recv = fec_recv;
1143 edev->halt = fec_halt;
1144 edev->write_hwaddr = fec_set_hwaddr;
1146 fec->eth = (struct ethernet_regs *)(ulong)base_addr;
1149 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1152 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1153 start = get_timer(0);
1154 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1155 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1156 printf("FEC MXC: Timeout resetting chip\n");
1163 fec_set_dev_name(edev->name, dev_id);
1164 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1166 fec_mii_setspeed(bus->priv);
1167 #ifdef CONFIG_PHYLIB
1168 fec->phydev = phydev;
1169 phy_connect_dev(phydev, edev);
1173 fec->phy_id = phy_id;
1176 /* only support one eth device, the index number pointed by dev_id */
1177 edev->index = fec->dev_id;
1179 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1180 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
1181 memcpy(edev->enetaddr, ethaddr, 6);
1183 sprintf(mac, "eth%daddr", fec->dev_id);
1185 strcpy(mac, "ethaddr");
1187 eth_env_set_enetaddr(mac, ethaddr);
1191 fec_free_descs(fec);
1200 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1203 struct mii_dev *bus = NULL;
1204 #ifdef CONFIG_PHYLIB
1205 struct phy_device *phydev = NULL;
1209 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
1210 if (enet_fused((ulong)addr)) {
1211 printf("SoC fuse indicates Ethernet@0x%x is unavailable.\n", addr);
1216 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1218 * The i.MX28 has two ethernet interfaces, but they are not equal.
1219 * Only the first one can access the MDIO bus.
1221 base_mii = CONFIG_FEC_MXC_MDIO_BASE;
1225 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1226 bus = fec_get_miibus(base_mii, dev_id);
1229 #ifdef CONFIG_PHYLIB
1230 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1232 mdio_unregister(bus);
1236 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1238 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1241 #ifdef CONFIG_PHYLIB
1244 mdio_unregister(bus);
1250 #ifdef CONFIG_FEC_MXC_PHYADDR
1251 int fecmxc_initialize(bd_t *bd)
1253 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1258 #ifndef CONFIG_PHYLIB
1259 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1261 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1262 fec->mii_postcall = cb;
1269 static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1271 struct fec_priv *priv = dev_get_priv(dev);
1272 struct eth_pdata *pdata = dev_get_platdata(dev);
1274 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1277 static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
1285 static const struct eth_ops fecmxc_ops = {
1286 .start = fecmxc_init,
1287 .send = fecmxc_send,
1288 .recv = fecmxc_recv,
1289 .free_pkt = fecmxc_free_pkt,
1290 .stop = fecmxc_halt,
1291 .write_hwaddr = fecmxc_set_hwaddr,
1292 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
1295 static int device_get_phy_addr(struct udevice *dev)
1297 struct ofnode_phandle_args phandle_args;
1300 if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1302 debug("Failed to find phy-handle");
1306 reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
1311 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1313 struct phy_device *phydev;
1316 addr = device_get_phy_addr(dev);
1317 #ifdef CONFIG_FEC_MXC_PHYADDR
1318 addr = CONFIG_FEC_MXC_PHYADDR;
1321 phydev = phy_connect(priv->bus, addr, dev, priv->interface);
1325 priv->phydev = phydev;
1331 #if CONFIG_IS_ENABLED(DM_GPIO)
1332 /* FEC GPIO reset */
1333 static void fec_gpio_reset(struct fec_priv *priv)
1335 debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
1336 if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
1337 dm_gpio_set_value(&priv->phy_reset_gpio, 1);
1338 mdelay(priv->reset_delay);
1339 dm_gpio_set_value(&priv->phy_reset_gpio, 0);
1340 if (priv->reset_post_delay)
1341 mdelay(priv->reset_post_delay);
1346 static int fecmxc_probe(struct udevice *dev)
1348 struct eth_pdata *pdata = dev_get_platdata(dev);
1349 struct fec_priv *priv = dev_get_priv(dev);
1350 struct mii_dev *bus = NULL;
1354 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
1355 if (enet_fused((ulong)priv->eth)) {
1356 printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);
1361 if (IS_ENABLED(CONFIG_IMX8)) {
1362 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1364 debug("Can't get FEC ipg clk: %d\n", ret);
1367 ret = clk_enable(&priv->ipg_clk);
1369 debug("Can't enable FEC ipg clk: %d\n", ret);
1373 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1374 } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
1375 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1377 debug("Can't get FEC ipg clk: %d\n", ret);
1380 ret = clk_enable(&priv->ipg_clk);
1384 ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
1386 debug("Can't get FEC ahb clk: %d\n", ret);
1389 ret = clk_enable(&priv->ahb_clk);
1393 ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
1395 ret = clk_enable(&priv->clk_enet_out);
1400 ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
1402 ret = clk_enable(&priv->clk_ref);
1407 ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
1409 ret = clk_enable(&priv->clk_ptp);
1414 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1417 ret = fec_alloc_descs(priv);
1421 #ifdef CONFIG_DM_REGULATOR
1422 if (priv->phy_supply) {
1423 ret = regulator_set_enable(priv->phy_supply, true);
1425 printf("%s: Error enabling phy supply\n", dev->name);
1431 #if CONFIG_IS_ENABLED(DM_GPIO)
1432 fec_gpio_reset(priv);
1435 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1436 &priv->eth->ecntrl);
1437 start = get_timer(0);
1438 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1439 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1440 printf("FEC MXC: Timeout reseting chip\n");
1446 fec_reg_setup(priv);
1448 priv->dev_id = dev->seq;
1450 #ifdef CONFIG_DM_ETH_PHY
1451 bus = eth_phy_get_mdio_bus(dev);
1455 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1456 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
1458 bus = fec_get_miibus((ulong)priv->eth, dev->seq);
1466 #ifdef CONFIG_DM_ETH_PHY
1467 eth_phy_set_mdio_bus(dev, bus);
1471 priv->interface = pdata->phy_interface;
1472 switch (priv->interface) {
1473 case PHY_INTERFACE_MODE_MII:
1474 priv->xcv_type = MII100;
1476 case PHY_INTERFACE_MODE_RMII:
1477 priv->xcv_type = RMII;
1479 case PHY_INTERFACE_MODE_RGMII:
1480 case PHY_INTERFACE_MODE_RGMII_ID:
1481 case PHY_INTERFACE_MODE_RGMII_RXID:
1482 case PHY_INTERFACE_MODE_RGMII_TXID:
1483 priv->xcv_type = RGMII;
1486 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1487 printf("Unsupported interface type %d defaulting to %d\n",
1488 priv->interface, priv->xcv_type);
1492 ret = fec_phy_init(priv, dev);
1499 mdio_unregister(bus);
1503 fec_free_descs(priv);
1507 static int fecmxc_remove(struct udevice *dev)
1509 struct fec_priv *priv = dev_get_priv(dev);
1512 fec_free_descs(priv);
1513 mdio_unregister(priv->bus);
1514 mdio_free(priv->bus);
1516 #ifdef CONFIG_DM_REGULATOR
1517 if (priv->phy_supply)
1518 regulator_set_enable(priv->phy_supply, false);
1524 static int fecmxc_ofdata_to_platdata(struct udevice *dev)
1527 struct eth_pdata *pdata = dev_get_platdata(dev);
1528 struct fec_priv *priv = dev_get_priv(dev);
1529 const char *phy_mode;
1531 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
1532 priv->eth = (struct ethernet_regs *)pdata->iobase;
1534 pdata->phy_interface = -1;
1535 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1538 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1539 if (pdata->phy_interface == -1) {
1540 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1544 #ifdef CONFIG_DM_REGULATOR
1545 device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
1548 #if CONFIG_IS_ENABLED(DM_GPIO)
1549 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1550 &priv->phy_reset_gpio, GPIOD_IS_OUT);
1552 return 0; /* property is optional, don't return error! */
1554 priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
1555 if (priv->reset_delay > 1000) {
1556 printf("FEC MXC: phy reset duration should be <= 1000ms\n");
1557 /* property value wrong, use default value */
1558 priv->reset_delay = 1;
1561 priv->reset_post_delay = dev_read_u32_default(dev,
1562 "phy-reset-post-delay",
1564 if (priv->reset_post_delay > 1000) {
1565 printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
1566 /* property value wrong, use default value */
1567 priv->reset_post_delay = 0;
1574 static const struct udevice_id fecmxc_ids[] = {
1575 { .compatible = "fsl,imx28-fec" },
1576 { .compatible = "fsl,imx6q-fec" },
1577 { .compatible = "fsl,imx6sl-fec" },
1578 { .compatible = "fsl,imx6sx-fec" },
1579 { .compatible = "fsl,imx6ul-fec" },
1580 { .compatible = "fsl,imx53-fec" },
1581 { .compatible = "fsl,imx7d-fec" },
1582 { .compatible = "fsl,mvf600-fec" },
1586 U_BOOT_DRIVER(fecmxc_gem) = {
1589 .of_match = fecmxc_ids,
1590 .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
1591 .probe = fecmxc_probe,
1592 .remove = fecmxc_remove,
1594 .priv_auto_alloc_size = sizeof(struct fec_priv),
1595 .platdata_auto_alloc_size = sizeof(struct eth_pdata),