2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx-regs.h>
20 #include <asm/errno.h>
21 #include <linux/compiler.h>
23 DECLARE_GLOBAL_DATA_PTR;
26 * Timeout the transfer after 5 mS. This is usually a bit more, since
27 * the code in the tightloops this timeout is used in adds some overhead.
29 #define FEC_XFER_TIMEOUT 5000
32 #error "CONFIG_MII has to be defined!"
35 #ifndef CONFIG_FEC_XCV_TYPE
36 #define CONFIG_FEC_XCV_TYPE MII100
40 * The i.MX28 operates with packets in big endian. We need to swap them before
41 * sending and after receiving.
44 #define CONFIG_FEC_MXC_SWAP_PACKET
47 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
49 /* Check various alignment issues at compile time */
50 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
51 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
54 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
55 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
56 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
62 uint8_t data[1500]; /**< actual data */
63 int length; /**< actual length */
64 int used; /**< buffer in use or not */
65 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
68 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
69 static void swap_packet(uint32_t *packet, int length)
73 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
74 packet[i] = __swab32(packet[i]);
79 * MII-interface related functions
81 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
84 uint32_t reg; /* convenient holder for the PHY register */
85 uint32_t phy; /* convenient holder for the PHY */
90 * reading from any PHY's register is done by properly
91 * programming the FEC's MII data register.
93 writel(FEC_IEVENT_MII, ð->ievent);
94 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
95 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
97 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
98 phy | reg, ð->mii_data);
101 * wait for the related interrupt
103 start = get_timer(0);
104 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
105 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
106 printf("Read MDIO failed...\n");
112 * clear mii interrupt bit
114 writel(FEC_IEVENT_MII, ð->ievent);
117 * it's now safe to read the PHY's register
119 val = (unsigned short)readl(ð->mii_data);
120 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
125 static void fec_mii_setspeed(struct ethernet_regs *eth)
128 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
129 * and do not drop the Preamble.
131 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
133 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
136 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
137 uint8_t regAddr, uint16_t data)
139 uint32_t reg; /* convenient holder for the PHY register */
140 uint32_t phy; /* convenient holder for the PHY */
143 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
144 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
146 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
147 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
150 * wait for the MII interrupt
152 start = get_timer(0);
153 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
154 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
155 printf("Write MDIO failed...\n");
161 * clear MII interrupt bit
163 writel(FEC_IEVENT_MII, ð->ievent);
164 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
170 int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
172 return fec_mdio_read(bus->priv, phyAddr, regAddr);
175 int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
178 return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
181 #ifndef CONFIG_PHYLIB
182 static int miiphy_restart_aneg(struct eth_device *dev)
185 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
186 struct fec_priv *fec = (struct fec_priv *)dev->priv;
187 struct ethernet_regs *eth = fec->bus->priv;
190 * Wake up from sleep if necessary
191 * Reset PHY, then delay 300ns
194 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
196 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
200 * Set the auto-negotiation advertisement register bits
202 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
203 LPA_100FULL | LPA_100HALF | LPA_10FULL |
204 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
205 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
206 BMCR_ANENABLE | BMCR_ANRESTART);
208 if (fec->mii_postcall)
209 ret = fec->mii_postcall(fec->phy_id);
215 static int miiphy_wait_aneg(struct eth_device *dev)
219 struct fec_priv *fec = (struct fec_priv *)dev->priv;
220 struct ethernet_regs *eth = fec->bus->priv;
223 * Wait for AN completion
225 start = get_timer(0);
227 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
228 printf("%s: Autonegotiation timeout\n", dev->name);
232 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
234 printf("%s: Autonegotiation failed. status: %d\n",
238 } while (!(status & BMSR_LSTATUS));
244 static int fec_rx_task_enable(struct fec_priv *fec)
246 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
250 static int fec_rx_task_disable(struct fec_priv *fec)
255 static int fec_tx_task_enable(struct fec_priv *fec)
257 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
261 static int fec_tx_task_disable(struct fec_priv *fec)
267 * Initialize receive task's buffer descriptors
268 * @param[in] fec all we know about the device yet
269 * @param[in] count receive buffer count to be allocated
270 * @param[in] dsize desired size of each receive buffer
271 * @return 0 on success
273 * Init all RX descriptors to default values.
275 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
282 * Reload the RX descriptors with default values and wipe
285 size = roundup(dsize, ARCH_DMA_MINALIGN);
286 for (i = 0; i < count; i++) {
287 data = (uint8_t *)fec->rbd_base[i].data_pointer;
288 memset(data, 0, dsize);
289 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
291 fec->rbd_base[i].status = FEC_RBD_EMPTY;
292 fec->rbd_base[i].data_length = 0;
295 /* Mark the last RBD to close the ring. */
296 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
299 flush_dcache_range((unsigned)fec->rbd_base,
300 (unsigned)fec->rbd_base + size);
304 * Initialize transmit task's buffer descriptors
305 * @param[in] fec all we know about the device yet
307 * Transmit buffers are created externally. We only have to init the BDs here.\n
308 * Note: There is a race condition in the hardware. When only one BD is in
309 * use it must be marked with the WRAP bit to use it for every transmitt.
310 * This bit in combination with the READY bit results into double transmit
311 * of each data buffer. It seems the state machine checks READY earlier then
312 * resetting it after the first transfer.
313 * Using two BDs solves this issue.
315 static void fec_tbd_init(struct fec_priv *fec)
317 unsigned addr = (unsigned)fec->tbd_base;
318 unsigned size = roundup(2 * sizeof(struct fec_bd),
321 memset(fec->tbd_base, 0, size);
322 fec->tbd_base[0].status = 0;
323 fec->tbd_base[1].status = FEC_TBD_WRAP;
325 flush_dcache_range(addr, addr + size);
329 * Mark the given read buffer descriptor as free
330 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
331 * @param[in] pRbd buffer descriptor to mark free again
333 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
335 unsigned short flags = FEC_RBD_EMPTY;
337 flags |= FEC_RBD_WRAP;
338 writew(flags, &pRbd->status);
339 writew(0, &pRbd->data_length);
342 static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
345 imx_get_mac_from_fuse(dev_id, mac);
346 return !is_valid_ether_addr(mac);
349 static int fec_set_hwaddr(struct eth_device *dev)
351 uchar *mac = dev->enetaddr;
352 struct fec_priv *fec = (struct fec_priv *)dev->priv;
354 writel(0, &fec->eth->iaddr1);
355 writel(0, &fec->eth->iaddr2);
356 writel(0, &fec->eth->gaddr1);
357 writel(0, &fec->eth->gaddr2);
360 * Set physical address
362 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
364 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
370 * Do initial configuration of the FEC registers
372 static void fec_reg_setup(struct fec_priv *fec)
377 * Set interrupt mask register
379 writel(0x00000000, &fec->eth->imask);
382 * Clear FEC-Lite interrupt event register(IEVENT)
384 writel(0xffffffff, &fec->eth->ievent);
388 * Set FEC-Lite receive control register(R_CNTRL):
391 /* Start with frame length = 1518, common for all modes. */
392 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
393 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
394 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
395 if (fec->xcv_type == RGMII)
396 rcntrl |= FEC_RCNTRL_RGMII;
397 else if (fec->xcv_type == RMII)
398 rcntrl |= FEC_RCNTRL_RMII;
400 writel(rcntrl, &fec->eth->r_cntrl);
404 * Start the FEC engine
405 * @param[in] dev Our device to handle
407 static int fec_open(struct eth_device *edev)
409 struct fec_priv *fec = (struct fec_priv *)edev->priv;
414 debug("fec_open: fec_open(dev)\n");
415 /* full-duplex, heartbeat disabled */
416 writel(1 << 2, &fec->eth->x_cntrl);
419 /* Invalidate all descriptors */
420 for (i = 0; i < FEC_RBD_NUM - 1; i++)
421 fec_rbd_clean(0, &fec->rbd_base[i]);
422 fec_rbd_clean(1, &fec->rbd_base[i]);
424 /* Flush the descriptors into RAM */
425 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
427 addr = (uint32_t)fec->rbd_base;
428 flush_dcache_range(addr, addr + size);
430 #ifdef FEC_QUIRK_ENET_MAC
431 /* Enable ENET HW endian SWAP */
432 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
434 /* Enable ENET store and forward mode */
435 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
439 * Enable FEC-Lite controller
441 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
443 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
446 * setup the MII gasket for RMII mode
449 /* disable the gasket */
450 writew(0, &fec->eth->miigsk_enr);
452 /* wait for the gasket to be disabled */
453 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
456 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
457 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
459 /* re-enable the gasket */
460 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
462 /* wait until MII gasket is ready */
464 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
465 if (--max_loops <= 0) {
466 printf("WAIT for MII Gasket ready timed out\n");
474 /* Start up the PHY */
475 int ret = phy_startup(fec->phydev);
478 printf("Could not initialize PHY %s\n",
479 fec->phydev->dev->name);
482 speed = fec->phydev->speed;
485 miiphy_wait_aneg(edev);
486 speed = miiphy_speed(edev->name, fec->phy_id);
487 miiphy_duplex(edev->name, fec->phy_id);
490 #ifdef FEC_QUIRK_ENET_MAC
492 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
493 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
494 if (speed == _1000BASET)
495 ecr |= FEC_ECNTRL_SPEED;
496 else if (speed != _100BASET)
497 rcr |= FEC_RCNTRL_RMII_10T;
498 writel(ecr, &fec->eth->ecntrl);
499 writel(rcr, &fec->eth->r_cntrl);
502 debug("%s:Speed=%i\n", __func__, speed);
505 * Enable SmartDMA receive task
507 fec_rx_task_enable(fec);
513 static int fec_init(struct eth_device *dev, bd_t* bd)
515 struct fec_priv *fec = (struct fec_priv *)dev->priv;
516 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
519 /* Initialize MAC address */
523 * Setup transmit descriptors, there are two in total.
527 /* Setup receive descriptors. */
528 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
532 if (fec->xcv_type != SEVENWIRE)
533 fec_mii_setspeed(fec->bus->priv);
536 * Set Opcode/Pause Duration Register
538 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
539 writel(0x2, &fec->eth->x_wmrk);
541 * Set multicast address filter
543 writel(0x00000000, &fec->eth->gaddr1);
544 writel(0x00000000, &fec->eth->gaddr2);
548 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
551 /* FIFO receive start register */
552 writel(0x520, &fec->eth->r_fstart);
554 /* size and address of each buffer */
555 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
556 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
557 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
559 #ifndef CONFIG_PHYLIB
560 if (fec->xcv_type != SEVENWIRE)
561 miiphy_restart_aneg(dev);
568 * Halt the FEC engine
569 * @param[in] dev Our device to handle
571 static void fec_halt(struct eth_device *dev)
573 struct fec_priv *fec = (struct fec_priv *)dev->priv;
574 int counter = 0xffff;
577 * issue graceful stop command to the FEC transmitter if necessary
579 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
582 debug("eth_halt: wait for stop regs\n");
584 * wait for graceful stop to register
586 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
590 * Disable SmartDMA tasks
592 fec_tx_task_disable(fec);
593 fec_rx_task_disable(fec);
596 * Disable the Ethernet Controller
597 * Note: this will also reset the BD index counter!
599 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
603 debug("eth_halt: done\n");
608 * @param[in] dev Our ethernet device to handle
609 * @param[in] packet Pointer to the data to be transmitted
610 * @param[in] length Data count in bytes
611 * @return 0 on success
613 static int fec_send(struct eth_device *dev, void *packet, int length)
618 int timeout = FEC_XFER_TIMEOUT;
622 * This routine transmits one frame. This routine only accepts
623 * 6-byte Ethernet addresses.
625 struct fec_priv *fec = (struct fec_priv *)dev->priv;
628 * Check for valid length of data.
630 if ((length > 1500) || (length <= 0)) {
631 printf("Payload (%d) too large\n", length);
636 * Setup the transmit buffer. We are always using the first buffer for
637 * transmission, the second will be empty and only used to stop the DMA
638 * engine. We also flush the packet to RAM here to avoid cache trouble.
640 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
641 swap_packet((uint32_t *)packet, length);
644 addr = (uint32_t)packet;
645 end = roundup(addr + length, ARCH_DMA_MINALIGN);
646 addr &= ~(ARCH_DMA_MINALIGN - 1);
647 flush_dcache_range(addr, end);
649 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
650 writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
653 * update BD's status now
655 * - is always the last in a chain (means no chain)
656 * - should transmitt the CRC
657 * - might be the last BD in the list, so the address counter should
658 * wrap (-> keep the WRAP flag)
660 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
661 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
662 writew(status, &fec->tbd_base[fec->tbd_index].status);
665 * Flush data cache. This code flushes both TX descriptors to RAM.
666 * After this code, the descriptors will be safely in RAM and we
669 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
670 addr = (uint32_t)fec->tbd_base;
671 flush_dcache_range(addr, addr + size);
674 * Below we read the DMA descriptor's last four bytes back from the
675 * DRAM. This is important in order to make sure that all WRITE
676 * operations on the bus that were triggered by previous cache FLUSH
679 * Otherwise, on MX28, it is possible to observe a corruption of the
680 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
681 * for the bus structure of MX28. The scenario is as follows:
683 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
684 * to DRAM due to flush_dcache_range()
685 * 2) ARM core writes the FEC registers via AHB_ARB2
686 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
688 * Note that 2) does sometimes finish before 1) due to reordering of
689 * WRITE accesses on the AHB bus, therefore triggering 3) before the
690 * DMA descriptor is fully written into DRAM. This results in occasional
691 * corruption of the DMA descriptor.
693 readl(addr + size - 4);
696 * Enable SmartDMA transmit task
698 fec_tx_task_enable(fec);
701 * Wait until frame is sent. On each turn of the wait cycle, we must
702 * invalidate data cache to see what's really in RAM. Also, we need
706 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
713 invalidate_dcache_range(addr, addr + size);
714 if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
717 debug("fec_send: status 0x%x index %d ret %i\n",
718 readw(&fec->tbd_base[fec->tbd_index].status),
719 fec->tbd_index, ret);
720 /* for next transmission use the other buffer */
730 * Pull one frame from the card
731 * @param[in] dev Our ethernet device to handle
732 * @return Length of packet read
734 static int fec_recv(struct eth_device *dev)
736 struct fec_priv *fec = (struct fec_priv *)dev->priv;
737 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
738 unsigned long ievent;
739 int frame_length, len = 0;
742 uint32_t addr, size, end;
744 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
747 * Check if any critical events have happened
749 ievent = readl(&fec->eth->ievent);
750 writel(ievent, &fec->eth->ievent);
751 debug("fec_recv: ievent 0x%lx\n", ievent);
752 if (ievent & FEC_IEVENT_BABR) {
754 fec_init(dev, fec->bd);
755 printf("some error: 0x%08lx\n", ievent);
758 if (ievent & FEC_IEVENT_HBERR) {
759 /* Heartbeat error */
760 writel(0x00000001 | readl(&fec->eth->x_cntrl),
763 if (ievent & FEC_IEVENT_GRA) {
764 /* Graceful stop complete */
765 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
767 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
769 fec_init(dev, fec->bd);
774 * Read the buffer status. Before the status can be read, the data cache
775 * must be invalidated, because the data in RAM might have been changed
776 * by DMA. The descriptors are properly aligned to cachelines so there's
777 * no need to worry they'd overlap.
779 * WARNING: By invalidating the descriptor here, we also invalidate
780 * the descriptors surrounding this one. Therefore we can NOT change the
781 * contents of this descriptor nor the surrounding ones. The problem is
782 * that in order to mark the descriptor as processed, we need to change
783 * the descriptor. The solution is to mark the whole cache line when all
784 * descriptors in the cache line are processed.
786 addr = (uint32_t)rbd;
787 addr &= ~(ARCH_DMA_MINALIGN - 1);
788 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
789 invalidate_dcache_range(addr, addr + size);
791 bd_status = readw(&rbd->status);
792 debug("fec_recv: status 0x%x\n", bd_status);
794 if (!(bd_status & FEC_RBD_EMPTY)) {
795 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
796 ((readw(&rbd->data_length) - 4) > 14)) {
798 * Get buffer address and size
800 frame = (struct nbuf *)readl(&rbd->data_pointer);
801 frame_length = readw(&rbd->data_length) - 4;
803 * Invalidate data cache over the buffer
805 addr = (uint32_t)frame;
806 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
807 addr &= ~(ARCH_DMA_MINALIGN - 1);
808 invalidate_dcache_range(addr, end);
811 * Fill the buffer and pass it to upper layers
813 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
814 swap_packet((uint32_t *)frame->data, frame_length);
816 memcpy(buff, frame->data, frame_length);
817 NetReceive(buff, frame_length);
820 if (bd_status & FEC_RBD_ERR)
821 printf("error frame: 0x%08lx 0x%08x\n",
822 (ulong)rbd->data_pointer,
827 * Free the current buffer, restart the engine and move forward
828 * to the next buffer. Here we check if the whole cacheline of
829 * descriptors was already processed and if so, we mark it free
832 size = RXDESC_PER_CACHELINE - 1;
833 if ((fec->rbd_index & size) == size) {
834 i = fec->rbd_index - size;
835 addr = (uint32_t)&fec->rbd_base[i];
836 for (; i <= fec->rbd_index ; i++) {
837 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
840 flush_dcache_range(addr,
841 addr + ARCH_DMA_MINALIGN);
844 fec_rx_task_enable(fec);
845 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
847 debug("fec_recv: stop\n");
852 static void fec_set_dev_name(char *dest, int dev_id)
854 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
857 static int fec_alloc_descs(struct fec_priv *fec)
863 /* Allocate TX descriptors. */
864 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
865 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
869 /* Allocate RX descriptors. */
870 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
871 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
875 memset(fec->rbd_base, 0, size);
877 /* Allocate RX buffers. */
879 /* Maximum RX buffer size. */
880 size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN);
881 for (i = 0; i < FEC_RBD_NUM; i++) {
882 data = memalign(ARCH_DMA_MINALIGN, size);
884 printf("%s: error allocating rxbuf %d\n", __func__, i);
888 memset(data, 0, size);
890 fec->rbd_base[i].data_pointer = (uint32_t)data;
891 fec->rbd_base[i].status = FEC_RBD_EMPTY;
892 fec->rbd_base[i].data_length = 0;
893 /* Flush the buffer to memory. */
894 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
897 /* Mark the last RBD to close the ring. */
898 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
907 free((void *)fec->rbd_base[i].data_pointer);
915 static void fec_free_descs(struct fec_priv *fec)
919 for (i = 0; i < FEC_RBD_NUM; i++)
920 free((void *)fec->rbd_base[i].data_pointer);
926 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
927 struct mii_dev *bus, struct phy_device *phydev)
929 static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
930 struct mii_dev *bus, int phy_id)
933 struct eth_device *edev;
934 struct fec_priv *fec;
935 unsigned char ethaddr[6];
939 /* create and fill edev struct */
940 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
942 puts("fec_mxc: not enough malloc memory for eth_device\n");
947 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
949 puts("fec_mxc: not enough malloc memory for fec_priv\n");
954 memset(edev, 0, sizeof(*edev));
955 memset(fec, 0, sizeof(*fec));
957 ret = fec_alloc_descs(fec);
962 edev->init = fec_init;
963 edev->send = fec_send;
964 edev->recv = fec_recv;
965 edev->halt = fec_halt;
966 edev->write_hwaddr = fec_set_hwaddr;
968 fec->eth = (struct ethernet_regs *)base_addr;
971 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
974 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
975 start = get_timer(0);
976 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
977 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
978 printf("FEC MXC: Timeout reseting chip\n");
985 fec_set_dev_name(edev->name, dev_id);
986 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
988 fec_mii_setspeed(bus->priv);
990 fec->phydev = phydev;
991 phy_connect_dev(phydev, edev);
995 fec->phy_id = phy_id;
999 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
1000 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
1001 memcpy(edev->enetaddr, ethaddr, 6);
1002 if (!getenv("ethaddr"))
1003 eth_setenv_enetaddr("ethaddr", ethaddr);
1007 fec_free_descs(fec);
1016 struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
1018 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1019 struct mii_dev *bus;
1024 printf("mdio_alloc failed\n");
1027 bus->read = fec_phy_read;
1028 bus->write = fec_phy_write;
1030 fec_set_dev_name(bus->name, dev_id);
1032 ret = mdio_register(bus);
1034 printf("mdio_register failed\n");
1038 fec_mii_setspeed(eth);
1042 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1045 struct mii_dev *bus = NULL;
1046 #ifdef CONFIG_PHYLIB
1047 struct phy_device *phydev = NULL;
1053 * The i.MX28 has two ethernet interfaces, but they are not equal.
1054 * Only the first one can access the MDIO bus.
1056 base_mii = MXS_ENET0_BASE;
1060 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1061 bus = fec_get_miibus(base_mii, dev_id);
1064 #ifdef CONFIG_PHYLIB
1065 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1070 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1072 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1075 #ifdef CONFIG_PHYLIB
1083 #ifdef CONFIG_FEC_MXC_PHYADDR
1084 int fecmxc_initialize(bd_t *bd)
1086 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1091 #ifndef CONFIG_PHYLIB
1092 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1094 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1095 fec->mii_postcall = cb;