2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <environment.h>
22 #include <linux/errno.h>
23 #include <linux/compiler.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/mach-imx/sys_proto.h>
29 DECLARE_GLOBAL_DATA_PTR;
32 * Timeout the transfer after 5 mS. This is usually a bit more, since
33 * the code in the tightloops this timeout is used in adds some overhead.
35 #define FEC_XFER_TIMEOUT 5000
38 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
39 * 64-byte alignment in the DMA RX FEC buffer.
40 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
41 * satisfies the alignment on other SoCs (32-bytes)
43 #define FEC_DMA_RX_MINALIGN 64
46 #error "CONFIG_MII has to be defined!"
49 #ifndef CONFIG_FEC_XCV_TYPE
50 #define CONFIG_FEC_XCV_TYPE MII100
54 * The i.MX28 operates with packets in big endian. We need to swap them before
55 * sending and after receiving.
58 #define CONFIG_FEC_MXC_SWAP_PACKET
61 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
63 /* Check various alignment issues at compile time */
64 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
65 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
68 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
69 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
70 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
75 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
76 static void swap_packet(uint32_t *packet, int length)
80 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
81 packet[i] = __swab32(packet[i]);
85 /* MII-interface related functions */
86 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
89 uint32_t reg; /* convenient holder for the PHY register */
90 uint32_t phy; /* convenient holder for the PHY */
95 * reading from any PHY's register is done by properly
96 * programming the FEC's MII data register.
98 writel(FEC_IEVENT_MII, ð->ievent);
99 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
100 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
102 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
103 phy | reg, ð->mii_data);
105 /* wait for the related interrupt */
106 start = get_timer(0);
107 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
108 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
109 printf("Read MDIO failed...\n");
114 /* clear mii interrupt bit */
115 writel(FEC_IEVENT_MII, ð->ievent);
117 /* it's now safe to read the PHY's register */
118 val = (unsigned short)readl(ð->mii_data);
119 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
124 static void fec_mii_setspeed(struct ethernet_regs *eth)
127 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
128 * and do not drop the Preamble.
130 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
131 * MII_SPEED) register that defines the MDIO output hold time. Earlier
132 * versions are RAZ there, so just ignore the difference and write the
134 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
135 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
137 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
138 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
139 * holdtime cannot result in a value greater than 3.
141 u32 pclk = imx_get_fecclk();
142 u32 speed = DIV_ROUND_UP(pclk, 5000000);
143 u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
144 #ifdef FEC_QUIRK_ENET_MAC
147 writel(speed << 1 | hold << 8, ð->mii_speed);
148 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
151 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
152 uint8_t regaddr, uint16_t data)
154 uint32_t reg; /* convenient holder for the PHY register */
155 uint32_t phy; /* convenient holder for the PHY */
158 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
159 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
161 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
162 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
164 /* wait for the MII interrupt */
165 start = get_timer(0);
166 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
167 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
168 printf("Write MDIO failed...\n");
173 /* clear MII interrupt bit */
174 writel(FEC_IEVENT_MII, ð->ievent);
175 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
181 static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
184 return fec_mdio_read(bus->priv, phyaddr, regaddr);
187 static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
188 int regaddr, u16 data)
190 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
193 #ifndef CONFIG_PHYLIB
194 static int miiphy_restart_aneg(struct eth_device *dev)
197 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
198 struct fec_priv *fec = (struct fec_priv *)dev->priv;
199 struct ethernet_regs *eth = fec->bus->priv;
202 * Wake up from sleep if necessary
203 * Reset PHY, then delay 300ns
206 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
208 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
211 /* Set the auto-negotiation advertisement register bits */
212 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
213 LPA_100FULL | LPA_100HALF | LPA_10FULL |
214 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
215 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
216 BMCR_ANENABLE | BMCR_ANRESTART);
218 if (fec->mii_postcall)
219 ret = fec->mii_postcall(fec->phy_id);
225 #ifndef CONFIG_FEC_FIXED_SPEED
226 static int miiphy_wait_aneg(struct eth_device *dev)
230 struct fec_priv *fec = (struct fec_priv *)dev->priv;
231 struct ethernet_regs *eth = fec->bus->priv;
233 /* Wait for AN completion */
234 start = get_timer(0);
236 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
237 printf("%s: Autonegotiation timeout\n", dev->name);
241 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
243 printf("%s: Autonegotiation failed. status: %d\n",
247 } while (!(status & BMSR_LSTATUS));
251 #endif /* CONFIG_FEC_FIXED_SPEED */
254 static int fec_rx_task_enable(struct fec_priv *fec)
256 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
260 static int fec_rx_task_disable(struct fec_priv *fec)
265 static int fec_tx_task_enable(struct fec_priv *fec)
267 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
271 static int fec_tx_task_disable(struct fec_priv *fec)
277 * Initialize receive task's buffer descriptors
278 * @param[in] fec all we know about the device yet
279 * @param[in] count receive buffer count to be allocated
280 * @param[in] dsize desired size of each receive buffer
281 * @return 0 on success
283 * Init all RX descriptors to default values.
285 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
292 * Reload the RX descriptors with default values and wipe
295 size = roundup(dsize, ARCH_DMA_MINALIGN);
296 for (i = 0; i < count; i++) {
297 data = fec->rbd_base[i].data_pointer;
298 memset((void *)data, 0, dsize);
299 flush_dcache_range(data, data + size);
301 fec->rbd_base[i].status = FEC_RBD_EMPTY;
302 fec->rbd_base[i].data_length = 0;
305 /* Mark the last RBD to close the ring. */
306 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
309 flush_dcache_range((ulong)fec->rbd_base,
310 (ulong)fec->rbd_base + size);
314 * Initialize transmit task's buffer descriptors
315 * @param[in] fec all we know about the device yet
317 * Transmit buffers are created externally. We only have to init the BDs here.\n
318 * Note: There is a race condition in the hardware. When only one BD is in
319 * use it must be marked with the WRAP bit to use it for every transmitt.
320 * This bit in combination with the READY bit results into double transmit
321 * of each data buffer. It seems the state machine checks READY earlier then
322 * resetting it after the first transfer.
323 * Using two BDs solves this issue.
325 static void fec_tbd_init(struct fec_priv *fec)
327 ulong addr = (ulong)fec->tbd_base;
328 unsigned size = roundup(2 * sizeof(struct fec_bd),
331 memset(fec->tbd_base, 0, size);
332 fec->tbd_base[0].status = 0;
333 fec->tbd_base[1].status = FEC_TBD_WRAP;
335 flush_dcache_range(addr, addr + size);
339 * Mark the given read buffer descriptor as free
340 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
341 * @param[in] prbd buffer descriptor to mark free again
343 static void fec_rbd_clean(int last, struct fec_bd *prbd)
345 unsigned short flags = FEC_RBD_EMPTY;
347 flags |= FEC_RBD_WRAP;
348 writew(flags, &prbd->status);
349 writew(0, &prbd->data_length);
352 static int fec_get_hwaddr(int dev_id, unsigned char *mac)
354 imx_get_mac_from_fuse(dev_id, mac);
355 return !is_valid_ethaddr(mac);
359 static int fecmxc_set_hwaddr(struct udevice *dev)
361 static int fec_set_hwaddr(struct eth_device *dev)
365 struct fec_priv *fec = dev_get_priv(dev);
366 struct eth_pdata *pdata = dev_get_platdata(dev);
367 uchar *mac = pdata->enetaddr;
369 uchar *mac = dev->enetaddr;
370 struct fec_priv *fec = (struct fec_priv *)dev->priv;
373 writel(0, &fec->eth->iaddr1);
374 writel(0, &fec->eth->iaddr2);
375 writel(0, &fec->eth->gaddr1);
376 writel(0, &fec->eth->gaddr2);
378 /* Set physical address */
379 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
381 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
386 /* Do initial configuration of the FEC registers */
387 static void fec_reg_setup(struct fec_priv *fec)
391 /* Set interrupt mask register */
392 writel(0x00000000, &fec->eth->imask);
394 /* Clear FEC-Lite interrupt event register(IEVENT) */
395 writel(0xffffffff, &fec->eth->ievent);
397 /* Set FEC-Lite receive control register(R_CNTRL): */
399 /* Start with frame length = 1518, common for all modes. */
400 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
401 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
402 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
403 if (fec->xcv_type == RGMII)
404 rcntrl |= FEC_RCNTRL_RGMII;
405 else if (fec->xcv_type == RMII)
406 rcntrl |= FEC_RCNTRL_RMII;
408 writel(rcntrl, &fec->eth->r_cntrl);
412 * Start the FEC engine
413 * @param[in] dev Our device to handle
416 static int fec_open(struct udevice *dev)
418 static int fec_open(struct eth_device *edev)
422 struct fec_priv *fec = dev_get_priv(dev);
424 struct fec_priv *fec = (struct fec_priv *)edev->priv;
430 debug("fec_open: fec_open(dev)\n");
431 /* full-duplex, heartbeat disabled */
432 writel(1 << 2, &fec->eth->x_cntrl);
435 /* Invalidate all descriptors */
436 for (i = 0; i < FEC_RBD_NUM - 1; i++)
437 fec_rbd_clean(0, &fec->rbd_base[i]);
438 fec_rbd_clean(1, &fec->rbd_base[i]);
440 /* Flush the descriptors into RAM */
441 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
443 addr = (ulong)fec->rbd_base;
444 flush_dcache_range(addr, addr + size);
446 #ifdef FEC_QUIRK_ENET_MAC
447 /* Enable ENET HW endian SWAP */
448 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
450 /* Enable ENET store and forward mode */
451 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
454 /* Enable FEC-Lite controller */
455 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
458 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
461 /* setup the MII gasket for RMII mode */
462 /* disable the gasket */
463 writew(0, &fec->eth->miigsk_enr);
465 /* wait for the gasket to be disabled */
466 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
469 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
470 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
472 /* re-enable the gasket */
473 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
475 /* wait until MII gasket is ready */
477 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
478 if (--max_loops <= 0) {
479 printf("WAIT for MII Gasket ready timed out\n");
487 /* Start up the PHY */
488 int ret = phy_startup(fec->phydev);
491 printf("Could not initialize PHY %s\n",
492 fec->phydev->dev->name);
495 speed = fec->phydev->speed;
497 #elif CONFIG_FEC_FIXED_SPEED
498 speed = CONFIG_FEC_FIXED_SPEED;
500 miiphy_wait_aneg(edev);
501 speed = miiphy_speed(edev->name, fec->phy_id);
502 miiphy_duplex(edev->name, fec->phy_id);
505 #ifdef FEC_QUIRK_ENET_MAC
507 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
508 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
509 if (speed == _1000BASET)
510 ecr |= FEC_ECNTRL_SPEED;
511 else if (speed != _100BASET)
512 rcr |= FEC_RCNTRL_RMII_10T;
513 writel(ecr, &fec->eth->ecntrl);
514 writel(rcr, &fec->eth->r_cntrl);
517 debug("%s:Speed=%i\n", __func__, speed);
519 /* Enable SmartDMA receive task */
520 fec_rx_task_enable(fec);
527 static int fecmxc_init(struct udevice *dev)
529 static int fec_init(struct eth_device *dev, bd_t *bd)
533 struct fec_priv *fec = dev_get_priv(dev);
535 struct fec_priv *fec = (struct fec_priv *)dev->priv;
537 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
541 /* Initialize MAC address */
543 fecmxc_set_hwaddr(dev);
548 /* Setup transmit descriptors, there are two in total. */
551 /* Setup receive descriptors. */
552 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
556 if (fec->xcv_type != SEVENWIRE)
557 fec_mii_setspeed(fec->bus->priv);
559 /* Set Opcode/Pause Duration Register */
560 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
561 writel(0x2, &fec->eth->x_wmrk);
563 /* Set multicast address filter */
564 writel(0x00000000, &fec->eth->gaddr1);
565 writel(0x00000000, &fec->eth->gaddr2);
567 /* Do not access reserved register */
568 if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
570 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
573 /* FIFO receive start register */
574 writel(0x520, &fec->eth->r_fstart);
577 /* size and address of each buffer */
578 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
580 addr = (ulong)fec->tbd_base;
581 writel((uint32_t)addr, &fec->eth->etdsr);
583 addr = (ulong)fec->rbd_base;
584 writel((uint32_t)addr, &fec->eth->erdsr);
586 #ifndef CONFIG_PHYLIB
587 if (fec->xcv_type != SEVENWIRE)
588 miiphy_restart_aneg(dev);
595 * Halt the FEC engine
596 * @param[in] dev Our device to handle
599 static void fecmxc_halt(struct udevice *dev)
601 static void fec_halt(struct eth_device *dev)
605 struct fec_priv *fec = dev_get_priv(dev);
607 struct fec_priv *fec = (struct fec_priv *)dev->priv;
609 int counter = 0xffff;
611 /* issue graceful stop command to the FEC transmitter if necessary */
612 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
615 debug("eth_halt: wait for stop regs\n");
616 /* wait for graceful stop to register */
617 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
620 /* Disable SmartDMA tasks */
621 fec_tx_task_disable(fec);
622 fec_rx_task_disable(fec);
625 * Disable the Ethernet Controller
626 * Note: this will also reset the BD index counter!
628 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
632 debug("eth_halt: done\n");
637 * @param[in] dev Our ethernet device to handle
638 * @param[in] packet Pointer to the data to be transmitted
639 * @param[in] length Data count in bytes
640 * @return 0 on success
643 static int fecmxc_send(struct udevice *dev, void *packet, int length)
645 static int fec_send(struct eth_device *dev, void *packet, int length)
651 int timeout = FEC_XFER_TIMEOUT;
655 * This routine transmits one frame. This routine only accepts
656 * 6-byte Ethernet addresses.
659 struct fec_priv *fec = dev_get_priv(dev);
661 struct fec_priv *fec = (struct fec_priv *)dev->priv;
665 * Check for valid length of data.
667 if ((length > 1500) || (length <= 0)) {
668 printf("Payload (%d) too large\n", length);
673 * Setup the transmit buffer. We are always using the first buffer for
674 * transmission, the second will be empty and only used to stop the DMA
675 * engine. We also flush the packet to RAM here to avoid cache trouble.
677 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
678 swap_packet((uint32_t *)packet, length);
681 addr = (ulong)packet;
682 end = roundup(addr + length, ARCH_DMA_MINALIGN);
683 addr &= ~(ARCH_DMA_MINALIGN - 1);
684 flush_dcache_range(addr, end);
686 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
687 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
690 * update BD's status now
692 * - is always the last in a chain (means no chain)
693 * - should transmitt the CRC
694 * - might be the last BD in the list, so the address counter should
695 * wrap (-> keep the WRAP flag)
697 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
698 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
699 writew(status, &fec->tbd_base[fec->tbd_index].status);
702 * Flush data cache. This code flushes both TX descriptors to RAM.
703 * After this code, the descriptors will be safely in RAM and we
706 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
707 addr = (ulong)fec->tbd_base;
708 flush_dcache_range(addr, addr + size);
711 * Below we read the DMA descriptor's last four bytes back from the
712 * DRAM. This is important in order to make sure that all WRITE
713 * operations on the bus that were triggered by previous cache FLUSH
716 * Otherwise, on MX28, it is possible to observe a corruption of the
717 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
718 * for the bus structure of MX28. The scenario is as follows:
720 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
721 * to DRAM due to flush_dcache_range()
722 * 2) ARM core writes the FEC registers via AHB_ARB2
723 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
725 * Note that 2) does sometimes finish before 1) due to reordering of
726 * WRITE accesses on the AHB bus, therefore triggering 3) before the
727 * DMA descriptor is fully written into DRAM. This results in occasional
728 * corruption of the DMA descriptor.
730 readl(addr + size - 4);
732 /* Enable SmartDMA transmit task */
733 fec_tx_task_enable(fec);
736 * Wait until frame is sent. On each turn of the wait cycle, we must
737 * invalidate data cache to see what's really in RAM. Also, we need
741 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
751 * The TDAR bit is cleared when the descriptors are all out from TX
752 * but on mx6solox we noticed that the READY bit is still not cleared
754 * These are two distinct signals, and in IC simulation, we found that
755 * TDAR always gets cleared prior than the READY bit of last BD becomes
757 * In mx6solox, we use a later version of FEC IP. It looks like that
758 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
761 * Fix this by polling the READY bit of BD after the TDAR polling,
762 * which covers the mx6solox case and does not harm the other SoCs.
764 timeout = FEC_XFER_TIMEOUT;
766 invalidate_dcache_range(addr, addr + size);
767 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
776 debug("fec_send: status 0x%x index %d ret %i\n",
777 readw(&fec->tbd_base[fec->tbd_index].status),
778 fec->tbd_index, ret);
779 /* for next transmission use the other buffer */
789 * Pull one frame from the card
790 * @param[in] dev Our ethernet device to handle
791 * @return Length of packet read
794 static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
796 static int fec_recv(struct eth_device *dev)
800 struct fec_priv *fec = dev_get_priv(dev);
802 struct fec_priv *fec = (struct fec_priv *)dev->priv;
804 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
805 unsigned long ievent;
806 int frame_length, len = 0;
808 ulong addr, size, end;
810 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
812 /* Check if any critical events have happened */
813 ievent = readl(&fec->eth->ievent);
814 writel(ievent, &fec->eth->ievent);
815 debug("fec_recv: ievent 0x%lx\n", ievent);
816 if (ievent & FEC_IEVENT_BABR) {
822 fec_init(dev, fec->bd);
824 printf("some error: 0x%08lx\n", ievent);
827 if (ievent & FEC_IEVENT_HBERR) {
828 /* Heartbeat error */
829 writel(0x00000001 | readl(&fec->eth->x_cntrl),
832 if (ievent & FEC_IEVENT_GRA) {
833 /* Graceful stop complete */
834 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
840 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
845 fec_init(dev, fec->bd);
851 * Read the buffer status. Before the status can be read, the data cache
852 * must be invalidated, because the data in RAM might have been changed
853 * by DMA. The descriptors are properly aligned to cachelines so there's
854 * no need to worry they'd overlap.
856 * WARNING: By invalidating the descriptor here, we also invalidate
857 * the descriptors surrounding this one. Therefore we can NOT change the
858 * contents of this descriptor nor the surrounding ones. The problem is
859 * that in order to mark the descriptor as processed, we need to change
860 * the descriptor. The solution is to mark the whole cache line when all
861 * descriptors in the cache line are processed.
864 addr &= ~(ARCH_DMA_MINALIGN - 1);
865 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
866 invalidate_dcache_range(addr, addr + size);
868 bd_status = readw(&rbd->status);
869 debug("fec_recv: status 0x%x\n", bd_status);
871 if (!(bd_status & FEC_RBD_EMPTY)) {
872 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
873 ((readw(&rbd->data_length) - 4) > 14)) {
874 /* Get buffer address and size */
875 addr = readl(&rbd->data_pointer);
876 frame_length = readw(&rbd->data_length) - 4;
877 /* Invalidate data cache over the buffer */
878 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
879 addr &= ~(ARCH_DMA_MINALIGN - 1);
880 invalidate_dcache_range(addr, end);
882 /* Fill the buffer and pass it to upper layers */
883 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
884 swap_packet((uint32_t *)addr, frame_length);
886 memcpy(buff, (char *)addr, frame_length);
887 net_process_received_packet(buff, frame_length);
890 if (bd_status & FEC_RBD_ERR)
891 debug("error frame: 0x%08lx 0x%08x\n",
896 * Free the current buffer, restart the engine and move forward
897 * to the next buffer. Here we check if the whole cacheline of
898 * descriptors was already processed and if so, we mark it free
901 size = RXDESC_PER_CACHELINE - 1;
902 if ((fec->rbd_index & size) == size) {
903 i = fec->rbd_index - size;
904 addr = (ulong)&fec->rbd_base[i];
905 for (; i <= fec->rbd_index ; i++) {
906 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
909 flush_dcache_range(addr,
910 addr + ARCH_DMA_MINALIGN);
913 fec_rx_task_enable(fec);
914 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
916 debug("fec_recv: stop\n");
921 static void fec_set_dev_name(char *dest, int dev_id)
923 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
926 static int fec_alloc_descs(struct fec_priv *fec)
933 /* Allocate TX descriptors. */
934 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
935 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
939 /* Allocate RX descriptors. */
940 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
941 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
945 memset(fec->rbd_base, 0, size);
947 /* Allocate RX buffers. */
949 /* Maximum RX buffer size. */
950 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
951 for (i = 0; i < FEC_RBD_NUM; i++) {
952 data = memalign(FEC_DMA_RX_MINALIGN, size);
954 printf("%s: error allocating rxbuf %d\n", __func__, i);
958 memset(data, 0, size);
961 fec->rbd_base[i].data_pointer = (uint32_t)addr;
962 fec->rbd_base[i].status = FEC_RBD_EMPTY;
963 fec->rbd_base[i].data_length = 0;
964 /* Flush the buffer to memory. */
965 flush_dcache_range(addr, addr + size);
968 /* Mark the last RBD to close the ring. */
969 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
977 for (; i >= 0; i--) {
978 addr = fec->rbd_base[i].data_pointer;
988 static void fec_free_descs(struct fec_priv *fec)
993 for (i = 0; i < FEC_RBD_NUM; i++) {
994 addr = fec->rbd_base[i].data_pointer;
1001 #ifdef CONFIG_DM_ETH
1002 struct mii_dev *fec_get_miibus(struct udevice *dev, int dev_id)
1004 struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
1007 #ifdef CONFIG_DM_ETH
1008 struct fec_priv *priv = dev_get_priv(dev);
1009 struct ethernet_regs *eth = priv->eth;
1011 struct ethernet_regs *eth = (struct ethernet_regs *)(ulong)base_addr;
1013 struct mii_dev *bus;
1018 printf("mdio_alloc failed\n");
1021 bus->read = fec_phy_read;
1022 bus->write = fec_phy_write;
1024 fec_set_dev_name(bus->name, dev_id);
1026 ret = mdio_register(bus);
1028 printf("mdio_register failed\n");
1032 fec_mii_setspeed(eth);
1036 #ifndef CONFIG_DM_ETH
1037 #ifdef CONFIG_PHYLIB
1038 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1039 struct mii_dev *bus, struct phy_device *phydev)
1041 static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1042 struct mii_dev *bus, int phy_id)
1045 struct eth_device *edev;
1046 struct fec_priv *fec;
1047 unsigned char ethaddr[6];
1052 /* create and fill edev struct */
1053 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1055 puts("fec_mxc: not enough malloc memory for eth_device\n");
1060 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1062 puts("fec_mxc: not enough malloc memory for fec_priv\n");
1067 memset(edev, 0, sizeof(*edev));
1068 memset(fec, 0, sizeof(*fec));
1070 ret = fec_alloc_descs(fec);
1075 edev->init = fec_init;
1076 edev->send = fec_send;
1077 edev->recv = fec_recv;
1078 edev->halt = fec_halt;
1079 edev->write_hwaddr = fec_set_hwaddr;
1081 fec->eth = (struct ethernet_regs *)(ulong)base_addr;
1084 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1087 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1088 start = get_timer(0);
1089 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1090 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1091 printf("FEC MXC: Timeout resetting chip\n");
1098 fec_set_dev_name(edev->name, dev_id);
1099 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1101 fec_mii_setspeed(bus->priv);
1102 #ifdef CONFIG_PHYLIB
1103 fec->phydev = phydev;
1104 phy_connect_dev(phydev, edev);
1108 fec->phy_id = phy_id;
1111 /* only support one eth device, the index number pointed by dev_id */
1112 edev->index = fec->dev_id;
1114 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1115 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
1116 memcpy(edev->enetaddr, ethaddr, 6);
1118 sprintf(mac, "eth%daddr", fec->dev_id);
1120 strcpy(mac, "ethaddr");
1122 eth_env_set_enetaddr(mac, ethaddr);
1126 fec_free_descs(fec);
1135 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1138 struct mii_dev *bus = NULL;
1139 #ifdef CONFIG_PHYLIB
1140 struct phy_device *phydev = NULL;
1146 * The i.MX28 has two ethernet interfaces, but they are not equal.
1147 * Only the first one can access the MDIO bus.
1149 base_mii = MXS_ENET0_BASE;
1153 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1154 bus = fec_get_miibus(base_mii, dev_id);
1157 #ifdef CONFIG_PHYLIB
1158 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1160 mdio_unregister(bus);
1164 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1166 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1169 #ifdef CONFIG_PHYLIB
1172 mdio_unregister(bus);
1178 #ifdef CONFIG_FEC_MXC_PHYADDR
1179 int fecmxc_initialize(bd_t *bd)
1181 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1186 #ifndef CONFIG_PHYLIB
1187 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1189 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1190 fec->mii_postcall = cb;
1197 static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1199 struct fec_priv *priv = dev_get_priv(dev);
1200 struct eth_pdata *pdata = dev_get_platdata(dev);
1202 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1205 static const struct eth_ops fecmxc_ops = {
1206 .start = fecmxc_init,
1207 .send = fecmxc_send,
1208 .recv = fecmxc_recv,
1209 .stop = fecmxc_halt,
1210 .write_hwaddr = fecmxc_set_hwaddr,
1211 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
1214 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1216 struct phy_device *phydev;
1217 int mask = 0xffffffff;
1219 #ifdef CONFIG_PHYLIB
1220 mask = 1 << CONFIG_FEC_MXC_PHYADDR;
1223 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
1227 phy_connect_dev(phydev, dev);
1229 priv->phydev = phydev;
1235 static int fecmxc_probe(struct udevice *dev)
1237 struct eth_pdata *pdata = dev_get_platdata(dev);
1238 struct fec_priv *priv = dev_get_priv(dev);
1239 struct mii_dev *bus = NULL;
1244 ret = fec_alloc_descs(priv);
1249 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1250 &priv->eth->ecntrl);
1251 start = get_timer(0);
1252 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1253 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1254 printf("FEC MXC: Timeout reseting chip\n");
1260 fec_reg_setup(priv);
1261 priv->dev_id = (dev_id == -1) ? 0 : dev_id;
1263 bus = fec_get_miibus(dev, dev_id);
1270 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1271 priv->interface = pdata->phy_interface;
1272 ret = fec_phy_init(priv, dev);
1281 mdio_unregister(bus);
1284 fec_free_descs(priv);
1288 static int fecmxc_remove(struct udevice *dev)
1290 struct fec_priv *priv = dev_get_priv(dev);
1293 fec_free_descs(priv);
1294 mdio_unregister(priv->bus);
1295 mdio_free(priv->bus);
1300 static int fecmxc_ofdata_to_platdata(struct udevice *dev)
1302 struct eth_pdata *pdata = dev_get_platdata(dev);
1303 struct fec_priv *priv = dev_get_priv(dev);
1304 const char *phy_mode;
1306 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
1307 priv->eth = (struct ethernet_regs *)pdata->iobase;
1309 pdata->phy_interface = -1;
1310 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1313 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1314 if (pdata->phy_interface == -1) {
1315 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1320 * Need to get the reset-gpio and related properties from DT
1321 * and implemet the enet reset code on .probe call
1327 static const struct udevice_id fecmxc_ids[] = {
1328 { .compatible = "fsl,imx6q-fec" },
1332 U_BOOT_DRIVER(fecmxc_gem) = {
1335 .of_match = fecmxc_ids,
1336 .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
1337 .probe = fecmxc_probe,
1338 .remove = fecmxc_remove,
1340 .priv_auto_alloc_size = sizeof(struct fec_priv),
1341 .platdata_auto_alloc_size = sizeof(struct eth_pdata),