1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
7 This only implements the mac core functions for this chip.
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
12 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
13 *******************************************************************************/
15 #include <linux/crc32.h>
16 #include <linux/slab.h>
17 #include <linux/ethtool.h>
21 #include "stmmac_pcs.h"
22 #include "dwmac1000.h"
24 static void dwmac1000_core_init(struct mac_device_info *hw,
25 struct net_device *dev)
27 struct stmmac_priv *priv = netdev_priv(dev);
28 void __iomem *ioaddr = hw->pcsr;
29 u32 value = readl(ioaddr + GMAC_CONTROL);
32 /* Configure GMAC core */
33 value |= GMAC_CORE_INIT;
35 /* Clear ACS bit because Ethernet switch tagging formats such as
36 * Broadcom tags can look like invalid LLC/SNAP packets and cause the
37 * hardware to truncate packets on reception.
39 if (netdev_uses_dsa(dev) || !priv->plat->enh_desc)
40 value &= ~GMAC_CONTROL_ACS;
43 value |= GMAC_CONTROL_2K;
45 value |= GMAC_CONTROL_JE;
48 value |= GMAC_CONTROL_TE;
50 value &= ~hw->link.speed_mask;
53 value |= hw->link.speed1000;
56 value |= hw->link.speed100;
59 value |= hw->link.speed10;
64 writel(value, ioaddr + GMAC_CONTROL);
66 /* Mask GMAC interrupts */
67 value = GMAC_INT_DEFAULT_MASK;
70 value &= ~GMAC_INT_DISABLE_PCS;
72 writel(value, ioaddr + GMAC_INT_MASK);
74 #ifdef STMMAC_VLAN_TAG_USED
75 /* Tag detection without filtering */
76 writel(0x0, ioaddr + GMAC_VLAN_TAG);
80 static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
82 void __iomem *ioaddr = hw->pcsr;
83 u32 value = readl(ioaddr + GMAC_CONTROL);
86 value |= GMAC_CONTROL_IPC;
88 value &= ~GMAC_CONTROL_IPC;
90 writel(value, ioaddr + GMAC_CONTROL);
92 value = readl(ioaddr + GMAC_CONTROL);
94 return !!(value & GMAC_CONTROL_IPC);
97 static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
99 void __iomem *ioaddr = hw->pcsr;
102 for (i = 0; i < 55; i++)
103 reg_space[i] = readl(ioaddr + i * 4);
106 static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
110 void __iomem *ioaddr = hw->pcsr;
111 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
112 GMAC_ADDR_LOW(reg_n));
115 static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
119 void __iomem *ioaddr = hw->pcsr;
120 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
121 GMAC_ADDR_LOW(reg_n));
124 static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
127 int numhashregs, regs;
129 switch (mcbitslog2) {
131 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
132 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
142 pr_debug("STMMAC: err in setting multicast filter\n");
146 for (regs = 0; regs < numhashregs; regs++)
147 writel(mcfilterbits[regs],
148 ioaddr + GMAC_EXTHASH_BASE + regs * 4);
151 static void dwmac1000_set_filter(struct mac_device_info *hw,
152 struct net_device *dev)
154 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
155 unsigned int value = 0;
156 unsigned int perfect_addr_number = hw->unicast_filter_entries;
158 int mcbitslog2 = hw->mcast_bits_log2;
160 pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
161 netdev_mc_count(dev), netdev_uc_count(dev));
163 memset(mc_filter, 0, sizeof(mc_filter));
165 if (dev->flags & IFF_PROMISC) {
166 value = GMAC_FRAME_FILTER_PR | GMAC_FRAME_FILTER_PCF;
167 } else if (dev->flags & IFF_ALLMULTI) {
168 value = GMAC_FRAME_FILTER_PM; /* pass all multi */
169 } else if (!netdev_mc_empty(dev)) {
170 struct netdev_hw_addr *ha;
172 /* Hash filter for multicast */
173 value = GMAC_FRAME_FILTER_HMC;
175 netdev_for_each_mc_addr(ha, dev) {
176 /* The upper n bits of the calculated CRC are used to
177 * index the contents of the hash table. The number of
178 * bits used depends on the hardware configuration
179 * selected at core configuration time.
181 int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
184 /* The most significant bit determines the register to
185 * use (H/L) while the other 5 bits determine the bit
186 * within the register.
188 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
192 value |= GMAC_FRAME_FILTER_HPF;
193 dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
195 /* Handle multiple unicast addresses (perfect filtering) */
196 if (netdev_uc_count(dev) > perfect_addr_number)
197 /* Switch to promiscuous mode if more than unicast
198 * addresses are requested than supported by hardware.
200 value |= GMAC_FRAME_FILTER_PR;
203 struct netdev_hw_addr *ha;
205 netdev_for_each_uc_addr(ha, dev) {
206 stmmac_set_mac_addr(ioaddr, ha->addr,
212 while (reg < perfect_addr_number) {
213 writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
214 writel(0, ioaddr + GMAC_ADDR_LOW(reg));
219 #ifdef FRAME_FILTER_DEBUG
220 /* Enable Receive all mode (to debug filtering_fail errors) */
221 value |= GMAC_FRAME_FILTER_RA;
223 writel(value, ioaddr + GMAC_FRAME_FILTER);
227 static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
228 unsigned int fc, unsigned int pause_time,
231 void __iomem *ioaddr = hw->pcsr;
232 /* Set flow such that DZPQ in Mac Register 6 is 0,
233 * and unicast pause detect is enabled.
235 unsigned int flow = GMAC_FLOW_CTRL_UP;
237 pr_debug("GMAC Flow-Control:\n");
239 pr_debug("\tReceive Flow-Control ON\n");
240 flow |= GMAC_FLOW_CTRL_RFE;
243 pr_debug("\tTransmit Flow-Control ON\n");
244 flow |= GMAC_FLOW_CTRL_TFE;
248 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
249 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
252 writel(flow, ioaddr + GMAC_FLOW_CTRL);
255 static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
257 void __iomem *ioaddr = hw->pcsr;
258 unsigned int pmt = 0;
260 if (mode & WAKE_MAGIC) {
261 pr_debug("GMAC: WOL Magic frame\n");
262 pmt |= power_down | magic_pkt_en;
264 if (mode & WAKE_UCAST) {
265 pr_debug("GMAC: WOL on global unicast\n");
266 pmt |= power_down | global_unicast | wake_up_frame_en;
269 writel(pmt, ioaddr + GMAC_PMT);
272 /* RGMII or SMII interface */
273 static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
277 status = readl(ioaddr + GMAC_RGSMIIIS);
280 /* Check the link status */
281 if (status & GMAC_RGSMIIIS_LNKSTS) {
286 speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
287 GMAC_RGSMIIIS_SPEED_SHIFT);
288 if (speed_value == GMAC_RGSMIIIS_SPEED_125)
289 x->pcs_speed = SPEED_1000;
290 else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
291 x->pcs_speed = SPEED_100;
293 x->pcs_speed = SPEED_10;
295 x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
297 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
298 x->pcs_duplex ? "Full" : "Half");
301 pr_info("Link is Down\n");
305 static int dwmac1000_irq_status(struct mac_device_info *hw,
306 struct stmmac_extra_stats *x)
308 void __iomem *ioaddr = hw->pcsr;
309 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
310 u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
313 /* Discard masked bits */
314 intr_status &= ~intr_mask;
316 /* Not used events (e.g. MMC interrupts) are not handled. */
317 if ((intr_status & GMAC_INT_STATUS_MMCTIS))
319 if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
321 if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
322 x->mmc_rx_csum_offload_irq_n++;
323 if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
324 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
325 readl(ioaddr + GMAC_PMT);
326 x->irq_receive_pmt_irq_n++;
329 /* MAC tx/rx EEE LPI entry/exit interrupts */
330 if (intr_status & GMAC_INT_STATUS_LPIIS) {
331 /* Clean LPI interrupt by reading the Reg 12 */
332 ret = readl(ioaddr + LPI_CTRL_STATUS);
334 if (ret & LPI_CTRL_STATUS_TLPIEN)
335 x->irq_tx_path_in_lpi_mode_n++;
336 if (ret & LPI_CTRL_STATUS_TLPIEX)
337 x->irq_tx_path_exit_lpi_mode_n++;
338 if (ret & LPI_CTRL_STATUS_RLPIEN)
339 x->irq_rx_path_in_lpi_mode_n++;
340 if (ret & LPI_CTRL_STATUS_RLPIEX)
341 x->irq_rx_path_exit_lpi_mode_n++;
344 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
346 if (intr_status & PCS_RGSMIIIS_IRQ)
347 dwmac1000_rgsmii(ioaddr, x);
352 static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
353 bool en_tx_lpi_clockgating)
355 void __iomem *ioaddr = hw->pcsr;
358 /*TODO - en_tx_lpi_clockgating treatment */
360 /* Enable the link status receive on RGMII, SGMII ore SMII
361 * receive path and instruct the transmit to enter in LPI
364 value = readl(ioaddr + LPI_CTRL_STATUS);
365 value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
366 writel(value, ioaddr + LPI_CTRL_STATUS);
369 static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
371 void __iomem *ioaddr = hw->pcsr;
374 value = readl(ioaddr + LPI_CTRL_STATUS);
375 value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
376 writel(value, ioaddr + LPI_CTRL_STATUS);
379 static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
381 void __iomem *ioaddr = hw->pcsr;
384 value = readl(ioaddr + LPI_CTRL_STATUS);
387 value |= LPI_CTRL_STATUS_PLS;
389 value &= ~LPI_CTRL_STATUS_PLS;
391 writel(value, ioaddr + LPI_CTRL_STATUS);
394 static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
396 void __iomem *ioaddr = hw->pcsr;
397 int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
399 /* Program the timers in the LPI timer control register:
400 * LS: minimum time (ms) for which the link
401 * status from PHY should be ok before transmitting
403 * TW: minimum time (us) for which the core waits
404 * after it has stopped transmitting the LPI pattern.
406 writel(value, ioaddr + LPI_TIMER_CTRL);
409 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
412 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
415 static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
417 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
420 static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
422 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
425 static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
426 u32 rx_queues, u32 tx_queues)
428 u32 value = readl(ioaddr + GMAC_DEBUG);
430 if (value & GMAC_DEBUG_TXSTSFSTS)
431 x->mtl_tx_status_fifo_full++;
432 if (value & GMAC_DEBUG_TXFSTS)
433 x->mtl_tx_fifo_not_empty++;
434 if (value & GMAC_DEBUG_TWCSTS)
436 if (value & GMAC_DEBUG_TRCSTS_MASK) {
437 u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
438 >> GMAC_DEBUG_TRCSTS_SHIFT;
439 if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
440 x->mtl_tx_fifo_read_ctrl_write++;
441 else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
442 x->mtl_tx_fifo_read_ctrl_wait++;
443 else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
444 x->mtl_tx_fifo_read_ctrl_read++;
446 x->mtl_tx_fifo_read_ctrl_idle++;
448 if (value & GMAC_DEBUG_TXPAUSED)
449 x->mac_tx_in_pause++;
450 if (value & GMAC_DEBUG_TFCSTS_MASK) {
451 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
452 >> GMAC_DEBUG_TFCSTS_SHIFT;
454 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
455 x->mac_tx_frame_ctrl_xfer++;
456 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
457 x->mac_tx_frame_ctrl_pause++;
458 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
459 x->mac_tx_frame_ctrl_wait++;
461 x->mac_tx_frame_ctrl_idle++;
463 if (value & GMAC_DEBUG_TPESTS)
464 x->mac_gmii_tx_proto_engine++;
465 if (value & GMAC_DEBUG_RXFSTS_MASK) {
466 u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
467 >> GMAC_DEBUG_RRCSTS_SHIFT;
469 if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
470 x->mtl_rx_fifo_fill_level_full++;
471 else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
472 x->mtl_rx_fifo_fill_above_thresh++;
473 else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
474 x->mtl_rx_fifo_fill_below_thresh++;
476 x->mtl_rx_fifo_fill_level_empty++;
478 if (value & GMAC_DEBUG_RRCSTS_MASK) {
479 u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
480 GMAC_DEBUG_RRCSTS_SHIFT;
482 if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
483 x->mtl_rx_fifo_read_ctrl_flush++;
484 else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
485 x->mtl_rx_fifo_read_ctrl_read_data++;
486 else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
487 x->mtl_rx_fifo_read_ctrl_status++;
489 x->mtl_rx_fifo_read_ctrl_idle++;
491 if (value & GMAC_DEBUG_RWCSTS)
492 x->mtl_rx_fifo_ctrl_active++;
493 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
494 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
495 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
496 if (value & GMAC_DEBUG_RPESTS)
497 x->mac_gmii_rx_proto_engine++;
500 static void dwmac1000_set_mac_loopback(void __iomem *ioaddr, bool enable)
502 u32 value = readl(ioaddr + GMAC_CONTROL);
505 value |= GMAC_CONTROL_LM;
507 value &= ~GMAC_CONTROL_LM;
509 writel(value, ioaddr + GMAC_CONTROL);
512 const struct stmmac_ops dwmac1000_ops = {
513 .core_init = dwmac1000_core_init,
514 .set_mac = stmmac_set_mac,
515 .rx_ipc = dwmac1000_rx_ipc_enable,
516 .dump_regs = dwmac1000_dump_regs,
517 .host_irq_status = dwmac1000_irq_status,
518 .set_filter = dwmac1000_set_filter,
519 .flow_ctrl = dwmac1000_flow_ctrl,
520 .pmt = dwmac1000_pmt,
521 .set_umac_addr = dwmac1000_set_umac_addr,
522 .get_umac_addr = dwmac1000_get_umac_addr,
523 .set_eee_mode = dwmac1000_set_eee_mode,
524 .reset_eee_mode = dwmac1000_reset_eee_mode,
525 .set_eee_timer = dwmac1000_set_eee_timer,
526 .set_eee_pls = dwmac1000_set_eee_pls,
527 .debug = dwmac1000_debug,
528 .pcs_ctrl_ane = dwmac1000_ctrl_ane,
529 .pcs_rane = dwmac1000_rane,
530 .pcs_get_adv_lp = dwmac1000_get_adv_lp,
531 .set_mac_loopback = dwmac1000_set_mac_loopback,
534 int dwmac1000_setup(struct stmmac_priv *priv)
536 struct mac_device_info *mac = priv->hw;
538 dev_info(priv->device, "\tDWMAC1000\n");
540 priv->dev->priv_flags |= IFF_UNICAST_FLT;
541 mac->pcsr = priv->ioaddr;
542 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
543 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
544 mac->mcast_bits_log2 = 0;
546 if (mac->multicast_filter_bins)
547 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
549 mac->link.duplex = GMAC_CONTROL_DM;
550 mac->link.speed10 = GMAC_CONTROL_PS;
551 mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
552 mac->link.speed1000 = 0;
553 mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
554 mac->mii.addr = GMAC_MII_ADDR;
555 mac->mii.data = GMAC_MII_DATA;
556 mac->mii.addr_shift = 11;
557 mac->mii.addr_mask = 0x0000F800;
558 mac->mii.reg_shift = 6;
559 mac->mii.reg_mask = 0x000007C0;
560 mac->mii.clk_csr_shift = 2;
561 mac->mii.clk_csr_mask = GENMASK(5, 2);