1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * meth.c -- O2 Builtin 10/100 Ethernet driver
5 * Copyright (C) 2001-2003 Ilya Volynets
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/slab.h>
13 #include <linux/errno.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
18 #include <linux/in6.h>
19 #include <linux/device.h> /* struct device, et al */
20 #include <linux/netdevice.h> /* struct device, and other headers */
21 #include <linux/etherdevice.h> /* eth_type_trans */
22 #include <linux/ip.h> /* struct iphdr */
23 #include <linux/tcp.h> /* struct tcphdr */
24 #include <linux/skbuff.h>
25 #include <linux/mii.h> /* MII definitions */
26 #include <linux/crc32.h>
28 #include <asm/ip32/mace.h>
29 #include <asm/ip32/ip32_ints.h>
40 #define DPRINTK(str,args...) printk(KERN_DEBUG "meth: %s: " str, __func__ , ## args)
41 #define MFE_RX_DEBUG 2
43 #define DPRINTK(str,args...)
44 #define MFE_RX_DEBUG 0
48 static const char *meth_str="SGI O2 Fast Ethernet";
50 /* The maximum time waited (in jiffies) before assuming a Tx failed. (400ms) */
51 #define TX_TIMEOUT (400*HZ/1000)
53 static int timeout = TX_TIMEOUT;
54 module_param(timeout, int, 0);
57 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 * MACE Ethernet uses a 64 element hash table based on the Ethernet CRC.
60 #define METH_MCF_LIMIT 32
63 * This structure is private to each device. It is used to pass
64 * packets in and out, so there is place for a packet
67 struct platform_device *pdev;
69 /* in-memory copy of MAC Control register */
72 /* in-memory copy of DMA Control register */
73 unsigned long dma_ctrl;
74 /* address of PHY, used by mdio_* functions, initialized in mdio_probe */
75 unsigned long phy_addr;
77 dma_addr_t tx_ring_dma;
78 struct sk_buff *tx_skbs[TX_RING_ENTRIES];
79 dma_addr_t tx_skb_dmas[TX_RING_ENTRIES];
80 unsigned long tx_read, tx_write, tx_count;
82 rx_packet *rx_ring[RX_RING_ENTRIES];
83 dma_addr_t rx_ring_dmas[RX_RING_ENTRIES];
84 struct sk_buff *rx_skbs[RX_RING_ENTRIES];
85 unsigned long rx_write;
87 /* Multicast filter. */
93 static void meth_tx_timeout(struct net_device *dev);
94 static irqreturn_t meth_interrupt(int irq, void *dev_id);
96 /* global, initialized in ip32-setup.c */
97 char o2meth_eaddr[8]={0,0,0,0,0,0,0,0};
99 static inline void load_eaddr(struct net_device *dev)
104 DPRINTK("Loading MAC Address: %pM\n", dev->dev_addr);
106 for (i = 0; i < 6; i++)
107 macaddr |= (u64)dev->dev_addr[i] << ((5 - i) * 8);
109 mace->eth.mac_addr = macaddr;
113 * Waits for BUSY status of mdio bus to clear
115 #define WAIT_FOR_PHY(___rval) \
116 while ((___rval = mace->eth.phy_data) & MDIO_BUSY) { \
119 /*read phy register, return value read */
120 static unsigned long mdio_read(struct meth_private *priv, unsigned long phyreg)
124 mace->eth.phy_regs = (priv->phy_addr << 5) | (phyreg & 0x1f);
126 mace->eth.phy_trans_go = 1;
129 return rval & MDIO_DATA_MASK;
132 static int mdio_probe(struct meth_private *priv)
135 unsigned long p2, p3, flags;
136 /* check if phy is detected already */
137 if(priv->phy_addr>=0&&priv->phy_addr<32)
139 spin_lock_irqsave(&priv->meth_lock, flags);
142 p2=mdio_read(priv,2);
143 p3=mdio_read(priv,3);
145 switch ((p2<<12)|(p3>>4)){
147 DPRINTK("PHY is QS6612X\n");
150 DPRINTK("PHY is ICS1889\n");
153 DPRINTK("PHY is ICS1890\n");
156 DPRINTK("PHY is DP83840\n");
160 if(p2!=0xffff&&p2!=0x0000){
161 DPRINTK("PHY code: %x\n",(p2<<12)|(p3>>4));
165 spin_unlock_irqrestore(&priv->meth_lock, flags);
166 if(priv->phy_addr<32) {
169 DPRINTK("Oopsie! PHY is not known!\n");
174 static void meth_check_link(struct net_device *dev)
176 struct meth_private *priv = netdev_priv(dev);
177 unsigned long mii_advertising = mdio_read(priv, 4);
178 unsigned long mii_partner = mdio_read(priv, 5);
179 unsigned long negotiated = mii_advertising & mii_partner;
180 unsigned long duplex, speed;
182 if (mii_partner == 0xffff)
185 speed = (negotiated & 0x0380) ? METH_100MBIT : 0;
186 duplex = ((negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040) ?
189 if ((priv->mac_ctrl & METH_PHY_FDX) ^ duplex) {
190 DPRINTK("Setting %s-duplex\n", duplex ? "full" : "half");
192 priv->mac_ctrl |= METH_PHY_FDX;
194 priv->mac_ctrl &= ~METH_PHY_FDX;
195 mace->eth.mac_ctrl = priv->mac_ctrl;
198 if ((priv->mac_ctrl & METH_100MBIT) ^ speed) {
199 DPRINTK("Setting %dMbs mode\n", speed ? 100 : 10);
201 priv->mac_ctrl |= METH_100MBIT;
203 priv->mac_ctrl &= ~METH_100MBIT;
204 mace->eth.mac_ctrl = priv->mac_ctrl;
209 static int meth_init_tx_ring(struct meth_private *priv)
212 priv->tx_ring = dma_alloc_coherent(&priv->pdev->dev,
213 TX_RING_BUFFER_SIZE, &priv->tx_ring_dma, GFP_ATOMIC);
217 priv->tx_count = priv->tx_read = priv->tx_write = 0;
218 mace->eth.tx_ring_base = priv->tx_ring_dma;
219 /* Now init skb save area */
220 memset(priv->tx_skbs, 0, sizeof(priv->tx_skbs));
221 memset(priv->tx_skb_dmas, 0, sizeof(priv->tx_skb_dmas));
225 static int meth_init_rx_ring(struct meth_private *priv)
229 for (i = 0; i < RX_RING_ENTRIES; i++) {
230 priv->rx_skbs[i] = alloc_skb(METH_RX_BUFF_SIZE, 0);
231 /* 8byte status vector + 3quad padding + 2byte padding,
232 * to put data on 64bit aligned boundary */
233 skb_reserve(priv->rx_skbs[i],METH_RX_HEAD);
234 priv->rx_ring[i]=(rx_packet*)(priv->rx_skbs[i]->head);
235 /* I'll need to re-sync it after each RX */
236 priv->rx_ring_dmas[i] =
237 dma_map_single(&priv->pdev->dev, priv->rx_ring[i],
238 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
239 mace->eth.rx_fifo = priv->rx_ring_dmas[i];
244 static void meth_free_tx_ring(struct meth_private *priv)
248 /* Remove any pending skb */
249 for (i = 0; i < TX_RING_ENTRIES; i++) {
250 if (priv->tx_skbs[i])
251 dev_kfree_skb(priv->tx_skbs[i]);
252 priv->tx_skbs[i] = NULL;
254 dma_free_coherent(&priv->pdev->dev, TX_RING_BUFFER_SIZE, priv->tx_ring,
258 /* Presumes RX DMA engine is stopped, and RX fifo ring is reset */
259 static void meth_free_rx_ring(struct meth_private *priv)
263 for (i = 0; i < RX_RING_ENTRIES; i++) {
264 dma_unmap_single(&priv->pdev->dev, priv->rx_ring_dmas[i],
265 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
266 priv->rx_ring[i] = 0;
267 priv->rx_ring_dmas[i] = 0;
268 kfree_skb(priv->rx_skbs[i]);
272 int meth_reset(struct net_device *dev)
274 struct meth_private *priv = netdev_priv(dev);
277 mace->eth.mac_ctrl = SGI_MAC_RESET;
279 mace->eth.mac_ctrl = 0;
282 /* Load ethernet address */
284 /* Should load some "errata", but later */
286 /* Check for device */
287 if (mdio_probe(priv) < 0) {
288 DPRINTK("Unable to find PHY\n");
292 /* Initial mode: 10 | Half-duplex | Accept normal packets */
293 priv->mac_ctrl = METH_ACCEPT_MCAST | METH_DEFAULT_IPG;
294 if (dev->flags & IFF_PROMISC)
295 priv->mac_ctrl |= METH_PROMISC;
296 mace->eth.mac_ctrl = priv->mac_ctrl;
298 /* Autonegotiate speed and duplex mode */
299 meth_check_link(dev);
301 /* Now set dma control, but don't enable DMA, yet */
302 priv->dma_ctrl = (4 << METH_RX_OFFSET_SHIFT) |
303 (RX_RING_ENTRIES << METH_RX_DEPTH_SHIFT);
304 mace->eth.dma_ctrl = priv->dma_ctrl;
309 /*============End Helper Routines=====================*/
314 static int meth_open(struct net_device *dev)
316 struct meth_private *priv = netdev_priv(dev);
319 priv->phy_addr = -1; /* No PHY is known yet... */
321 /* Initialize the hardware */
322 ret = meth_reset(dev);
326 /* Allocate the ring buffers */
327 ret = meth_init_tx_ring(priv);
330 ret = meth_init_rx_ring(priv);
332 goto out_free_tx_ring;
334 ret = request_irq(dev->irq, meth_interrupt, 0, meth_str, dev);
336 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
337 goto out_free_rx_ring;
341 priv->dma_ctrl |= METH_DMA_TX_EN | /*METH_DMA_TX_INT_EN |*/
342 METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
343 mace->eth.dma_ctrl = priv->dma_ctrl;
345 DPRINTK("About to start queue\n");
346 netif_start_queue(dev);
351 meth_free_rx_ring(priv);
353 meth_free_tx_ring(priv);
358 static int meth_release(struct net_device *dev)
360 struct meth_private *priv = netdev_priv(dev);
362 DPRINTK("Stopping queue\n");
363 netif_stop_queue(dev); /* can't transmit any more */
365 priv->dma_ctrl &= ~(METH_DMA_TX_EN | METH_DMA_TX_INT_EN |
366 METH_DMA_RX_EN | METH_DMA_RX_INT_EN);
367 mace->eth.dma_ctrl = priv->dma_ctrl;
368 free_irq(dev->irq, dev);
369 meth_free_tx_ring(priv);
370 meth_free_rx_ring(priv);
376 * Receive a packet: retrieve, encapsulate and pass over to upper levels
378 static void meth_rx(struct net_device* dev, unsigned long int_status)
381 unsigned long status, flags;
382 struct meth_private *priv = netdev_priv(dev);
383 unsigned long fifo_rptr = (int_status & METH_INT_RX_RPTR_MASK) >> 8;
385 spin_lock_irqsave(&priv->meth_lock, flags);
386 priv->dma_ctrl &= ~METH_DMA_RX_INT_EN;
387 mace->eth.dma_ctrl = priv->dma_ctrl;
388 spin_unlock_irqrestore(&priv->meth_lock, flags);
390 if (int_status & METH_INT_RX_UNDERFLOW) {
391 fifo_rptr = (fifo_rptr - 1) & 0x0f;
393 while (priv->rx_write != fifo_rptr) {
394 dma_unmap_single(&priv->pdev->dev,
395 priv->rx_ring_dmas[priv->rx_write],
396 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
397 status = priv->rx_ring[priv->rx_write]->status.raw;
399 if (!(status & METH_RX_ST_VALID)) {
400 DPRINTK("Not received? status=%016lx\n",status);
403 if ((!(status & METH_RX_STATUS_ERRORS)) && (status & METH_RX_ST_VALID)) {
404 int len = (status & 0xffff) - 4; /* omit CRC */
405 /* length sanity check */
406 if (len < 60 || len > 1518) {
407 printk(KERN_DEBUG "%s: bogus packet size: %ld, status=%#2Lx.\n",
408 dev->name, priv->rx_write,
409 priv->rx_ring[priv->rx_write]->status.raw);
410 dev->stats.rx_errors++;
411 dev->stats.rx_length_errors++;
412 skb = priv->rx_skbs[priv->rx_write];
414 skb = alloc_skb(METH_RX_BUFF_SIZE, GFP_ATOMIC);
416 /* Ouch! No memory! Drop packet on the floor */
417 DPRINTK("No mem: dropping packet\n");
418 dev->stats.rx_dropped++;
419 skb = priv->rx_skbs[priv->rx_write];
421 struct sk_buff *skb_c = priv->rx_skbs[priv->rx_write];
422 /* 8byte status vector + 3quad padding + 2byte padding,
423 * to put data on 64bit aligned boundary */
424 skb_reserve(skb, METH_RX_HEAD);
425 /* Write metadata, and then pass to the receive level */
427 priv->rx_skbs[priv->rx_write] = skb;
428 skb_c->protocol = eth_type_trans(skb_c, dev);
429 dev->stats.rx_packets++;
430 dev->stats.rx_bytes += len;
435 dev->stats.rx_errors++;
436 skb=priv->rx_skbs[priv->rx_write];
438 printk(KERN_WARNING "meth: RX error: status=0x%016lx\n",status);
439 if(status&METH_RX_ST_RCV_CODE_VIOLATION)
440 printk(KERN_WARNING "Receive Code Violation\n");
441 if(status&METH_RX_ST_CRC_ERR)
442 printk(KERN_WARNING "CRC error\n");
443 if(status&METH_RX_ST_INV_PREAMBLE_CTX)
444 printk(KERN_WARNING "Invalid Preamble Context\n");
445 if(status&METH_RX_ST_LONG_EVT_SEEN)
446 printk(KERN_WARNING "Long Event Seen...\n");
447 if(status&METH_RX_ST_BAD_PACKET)
448 printk(KERN_WARNING "Bad Packet\n");
449 if(status&METH_RX_ST_CARRIER_EVT_SEEN)
450 printk(KERN_WARNING "Carrier Event Seen\n");
453 priv->rx_ring[priv->rx_write] = (rx_packet*)skb->head;
454 priv->rx_ring[priv->rx_write]->status.raw = 0;
455 priv->rx_ring_dmas[priv->rx_write] =
456 dma_map_single(&priv->pdev->dev,
457 priv->rx_ring[priv->rx_write],
458 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
459 mace->eth.rx_fifo = priv->rx_ring_dmas[priv->rx_write];
460 ADVANCE_RX_PTR(priv->rx_write);
462 spin_lock_irqsave(&priv->meth_lock, flags);
463 /* In case there was underflow, and Rx DMA was disabled */
464 priv->dma_ctrl |= METH_DMA_RX_INT_EN | METH_DMA_RX_EN;
465 mace->eth.dma_ctrl = priv->dma_ctrl;
466 mace->eth.int_stat = METH_INT_RX_THRESHOLD;
467 spin_unlock_irqrestore(&priv->meth_lock, flags);
470 static int meth_tx_full(struct net_device *dev)
472 struct meth_private *priv = netdev_priv(dev);
474 return priv->tx_count >= TX_RING_ENTRIES - 1;
477 static void meth_tx_cleanup(struct net_device* dev, unsigned long int_status)
479 struct meth_private *priv = netdev_priv(dev);
480 unsigned long status, flags;
482 unsigned long rptr = (int_status&TX_INFO_RPTR) >> 16;
484 spin_lock_irqsave(&priv->meth_lock, flags);
486 /* Stop DMA notification */
487 priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
488 mace->eth.dma_ctrl = priv->dma_ctrl;
490 while (priv->tx_read != rptr) {
491 skb = priv->tx_skbs[priv->tx_read];
492 status = priv->tx_ring[priv->tx_read].header.raw;
494 if (priv->tx_read == priv->tx_write)
495 DPRINTK("Auchi! tx_read=%d,tx_write=%d,rptr=%d?\n", priv->tx_read, priv->tx_write,rptr);
497 if (status & METH_TX_ST_DONE) {
498 if (status & METH_TX_ST_SUCCESS){
499 dev->stats.tx_packets++;
500 dev->stats.tx_bytes += skb->len;
502 dev->stats.tx_errors++;
504 DPRINTK("TX error: status=%016lx <",status);
505 if(status & METH_TX_ST_SUCCESS)
507 if(status & METH_TX_ST_TOOLONG)
509 if(status & METH_TX_ST_UNDERRUN)
511 if(status & METH_TX_ST_EXCCOLL)
513 if(status & METH_TX_ST_DEFER)
515 if(status & METH_TX_ST_LATECOLL)
521 DPRINTK("RPTR points us here, but packet not done?\n");
524 dev_consume_skb_irq(skb);
525 priv->tx_skbs[priv->tx_read] = NULL;
526 priv->tx_ring[priv->tx_read].header.raw = 0;
527 priv->tx_read = (priv->tx_read+1)&(TX_RING_ENTRIES-1);
531 /* wake up queue if it was stopped */
532 if (netif_queue_stopped(dev) && !meth_tx_full(dev)) {
533 netif_wake_queue(dev);
536 mace->eth.int_stat = METH_INT_TX_EMPTY | METH_INT_TX_PKT;
537 spin_unlock_irqrestore(&priv->meth_lock, flags);
540 static void meth_error(struct net_device* dev, unsigned status)
542 struct meth_private *priv = netdev_priv(dev);
545 printk(KERN_WARNING "meth: error status: 0x%08x\n",status);
546 /* check for errors too... */
547 if (status & (METH_INT_TX_LINK_FAIL))
548 printk(KERN_WARNING "meth: link failure\n");
549 /* Should I do full reset in this case? */
550 if (status & (METH_INT_MEM_ERROR))
551 printk(KERN_WARNING "meth: memory error\n");
552 if (status & (METH_INT_TX_ABORT))
553 printk(KERN_WARNING "meth: aborted\n");
554 if (status & (METH_INT_RX_OVERFLOW))
555 printk(KERN_WARNING "meth: Rx overflow\n");
556 if (status & (METH_INT_RX_UNDERFLOW)) {
557 printk(KERN_WARNING "meth: Rx underflow\n");
558 spin_lock_irqsave(&priv->meth_lock, flags);
559 mace->eth.int_stat = METH_INT_RX_UNDERFLOW;
560 /* more underflow interrupts will be delivered,
561 * effectively throwing us into an infinite loop.
562 * Thus I stop processing Rx in this case. */
563 priv->dma_ctrl &= ~METH_DMA_RX_EN;
564 mace->eth.dma_ctrl = priv->dma_ctrl;
565 DPRINTK("Disabled meth Rx DMA temporarily\n");
566 spin_unlock_irqrestore(&priv->meth_lock, flags);
568 mace->eth.int_stat = METH_INT_ERROR;
572 * The typical interrupt entry point
574 static irqreturn_t meth_interrupt(int irq, void *dev_id)
576 struct net_device *dev = (struct net_device *)dev_id;
577 struct meth_private *priv = netdev_priv(dev);
578 unsigned long status;
580 status = mace->eth.int_stat;
581 while (status & 0xff) {
582 /* First handle errors - if we get Rx underflow,
583 * Rx DMA will be disabled, and Rx handler will reenable
584 * it. I don't think it's possible to get Rx underflow,
585 * without getting Rx interrupt */
586 if (status & METH_INT_ERROR) {
587 meth_error(dev, status);
589 if (status & (METH_INT_TX_EMPTY | METH_INT_TX_PKT)) {
590 /* a transmission is over: free the skb */
591 meth_tx_cleanup(dev, status);
593 if (status & METH_INT_RX_THRESHOLD) {
594 if (!(priv->dma_ctrl & METH_DMA_RX_INT_EN))
596 /* send it to meth_rx for handling */
597 meth_rx(dev, status);
599 status = mace->eth.int_stat;
606 * Transmits packets that fit into TX descriptor (are <=120B)
608 static void meth_tx_short_prepare(struct meth_private *priv,
611 tx_packet *desc = &priv->tx_ring[priv->tx_write];
612 int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
614 desc->header.raw = METH_TX_CMD_INT_EN | (len-1) | ((128-len) << 16);
615 /* maybe I should set whole thing to 0 first... */
616 skb_copy_from_linear_data(skb, desc->data.dt + (120 - len), skb->len);
618 memset(desc->data.dt + 120 - len + skb->len, 0, len-skb->len);
620 #define TX_CATBUF1 BIT(25)
621 static void meth_tx_1page_prepare(struct meth_private *priv,
624 tx_packet *desc = &priv->tx_ring[priv->tx_write];
625 void *buffer_data = (void *)(((unsigned long)skb->data + 7) & ~7);
626 int unaligned_len = (int)((unsigned long)buffer_data - (unsigned long)skb->data);
627 int buffer_len = skb->len - unaligned_len;
630 desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | (skb->len - 1);
634 skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
636 desc->header.raw |= (128 - unaligned_len) << 16;
640 catbuf = dma_map_single(&priv->pdev->dev, buffer_data, buffer_len,
642 desc->data.cat_buf[0].form.start_addr = catbuf >> 3;
643 desc->data.cat_buf[0].form.len = buffer_len - 1;
645 #define TX_CATBUF2 BIT(26)
646 static void meth_tx_2page_prepare(struct meth_private *priv,
649 tx_packet *desc = &priv->tx_ring[priv->tx_write];
650 void *buffer1_data = (void *)(((unsigned long)skb->data + 7) & ~7);
651 void *buffer2_data = (void *)PAGE_ALIGN((unsigned long)skb->data);
652 int unaligned_len = (int)((unsigned long)buffer1_data - (unsigned long)skb->data);
653 int buffer1_len = (int)((unsigned long)buffer2_data - (unsigned long)buffer1_data);
654 int buffer2_len = skb->len - buffer1_len - unaligned_len;
655 dma_addr_t catbuf1, catbuf2;
657 desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | TX_CATBUF2| (skb->len - 1);
660 skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
662 desc->header.raw |= (128 - unaligned_len) << 16;
666 catbuf1 = dma_map_single(&priv->pdev->dev, buffer1_data, buffer1_len,
668 desc->data.cat_buf[0].form.start_addr = catbuf1 >> 3;
669 desc->data.cat_buf[0].form.len = buffer1_len - 1;
671 catbuf2 = dma_map_single(&priv->pdev->dev, buffer2_data, buffer2_len,
673 desc->data.cat_buf[1].form.start_addr = catbuf2 >> 3;
674 desc->data.cat_buf[1].form.len = buffer2_len - 1;
677 static void meth_add_to_tx_ring(struct meth_private *priv, struct sk_buff *skb)
679 /* Remember the skb, so we can free it at interrupt time */
680 priv->tx_skbs[priv->tx_write] = skb;
681 if (skb->len <= 120) {
682 /* Whole packet fits into descriptor */
683 meth_tx_short_prepare(priv, skb);
684 } else if (PAGE_ALIGN((unsigned long)skb->data) !=
685 PAGE_ALIGN((unsigned long)skb->data + skb->len - 1)) {
686 /* Packet crosses page boundary */
687 meth_tx_2page_prepare(priv, skb);
689 /* Packet is in one page */
690 meth_tx_1page_prepare(priv, skb);
692 priv->tx_write = (priv->tx_write + 1) & (TX_RING_ENTRIES - 1);
693 mace->eth.tx_info = priv->tx_write;
698 * Transmit a packet (called by the kernel)
700 static netdev_tx_t meth_tx(struct sk_buff *skb, struct net_device *dev)
702 struct meth_private *priv = netdev_priv(dev);
705 spin_lock_irqsave(&priv->meth_lock, flags);
706 /* Stop DMA notification */
707 priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
708 mace->eth.dma_ctrl = priv->dma_ctrl;
710 meth_add_to_tx_ring(priv, skb);
711 netif_trans_update(dev); /* save the timestamp */
713 /* If TX ring is full, tell the upper layer to stop sending packets */
714 if (meth_tx_full(dev)) {
715 printk(KERN_DEBUG "TX full: stopping\n");
716 netif_stop_queue(dev);
719 /* Restart DMA notification */
720 priv->dma_ctrl |= METH_DMA_TX_INT_EN;
721 mace->eth.dma_ctrl = priv->dma_ctrl;
723 spin_unlock_irqrestore(&priv->meth_lock, flags);
729 * Deal with a transmit timeout.
731 static void meth_tx_timeout(struct net_device *dev)
733 struct meth_private *priv = netdev_priv(dev);
736 printk(KERN_WARNING "%s: transmit timed out\n", dev->name);
738 /* Protect against concurrent rx interrupts */
739 spin_lock_irqsave(&priv->meth_lock,flags);
741 /* Try to reset the interface. */
744 dev->stats.tx_errors++;
746 /* Clear all rings */
747 meth_free_tx_ring(priv);
748 meth_free_rx_ring(priv);
749 meth_init_tx_ring(priv);
750 meth_init_rx_ring(priv);
753 priv->dma_ctrl |= METH_DMA_TX_EN | METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
754 mace->eth.dma_ctrl = priv->dma_ctrl;
756 /* Enable interrupt */
757 spin_unlock_irqrestore(&priv->meth_lock, flags);
759 netif_trans_update(dev); /* prevent tx timeout */
760 netif_wake_queue(dev);
766 static int meth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
768 /* XXX Not yet implemented */
778 static void meth_set_rx_mode(struct net_device *dev)
780 struct meth_private *priv = netdev_priv(dev);
783 netif_stop_queue(dev);
784 spin_lock_irqsave(&priv->meth_lock, flags);
785 priv->mac_ctrl &= ~METH_PROMISC;
787 if (dev->flags & IFF_PROMISC) {
788 priv->mac_ctrl |= METH_PROMISC;
789 priv->mcast_filter = 0xffffffffffffffffUL;
790 } else if ((netdev_mc_count(dev) > METH_MCF_LIMIT) ||
791 (dev->flags & IFF_ALLMULTI)) {
792 priv->mac_ctrl |= METH_ACCEPT_AMCAST;
793 priv->mcast_filter = 0xffffffffffffffffUL;
795 struct netdev_hw_addr *ha;
796 priv->mac_ctrl |= METH_ACCEPT_MCAST;
798 netdev_for_each_mc_addr(ha, dev)
799 set_bit((ether_crc(ETH_ALEN, ha->addr) >> 26),
800 (volatile unsigned long *)&priv->mcast_filter);
803 /* Write the changes to the chip registers. */
804 mace->eth.mac_ctrl = priv->mac_ctrl;
805 mace->eth.mcast_filter = priv->mcast_filter;
808 spin_unlock_irqrestore(&priv->meth_lock, flags);
809 netif_wake_queue(dev);
812 static const struct net_device_ops meth_netdev_ops = {
813 .ndo_open = meth_open,
814 .ndo_stop = meth_release,
815 .ndo_start_xmit = meth_tx,
816 .ndo_do_ioctl = meth_ioctl,
817 .ndo_tx_timeout = meth_tx_timeout,
818 .ndo_validate_addr = eth_validate_addr,
819 .ndo_set_mac_address = eth_mac_addr,
820 .ndo_set_rx_mode = meth_set_rx_mode,
826 static int meth_probe(struct platform_device *pdev)
828 struct net_device *dev;
829 struct meth_private *priv;
832 dev = alloc_etherdev(sizeof(struct meth_private));
836 dev->netdev_ops = &meth_netdev_ops;
837 dev->watchdog_timeo = timeout;
838 dev->irq = MACE_ETHERNET_IRQ;
839 dev->base_addr = (unsigned long)&mace->eth;
840 memcpy(dev->dev_addr, o2meth_eaddr, ETH_ALEN);
842 priv = netdev_priv(dev);
844 spin_lock_init(&priv->meth_lock);
845 SET_NETDEV_DEV(dev, &pdev->dev);
847 err = register_netdev(dev);
853 printk(KERN_INFO "%s: SGI MACE Ethernet rev. %d\n",
854 dev->name, (unsigned int)(mace->eth.mac_ctrl >> 29));
858 static int meth_remove(struct platform_device *pdev)
860 struct net_device *dev = platform_get_drvdata(pdev);
862 unregister_netdev(dev);
868 static struct platform_driver meth_driver = {
870 .remove = meth_remove,
876 module_platform_driver(meth_driver);
878 MODULE_AUTHOR("Ilya Volynets <ilya@theIlya.com>");
879 MODULE_DESCRIPTION("SGI O2 Builtin Fast Ethernet driver");
880 MODULE_LICENSE("GPL");
881 MODULE_ALIAS("platform:meth");