1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include "net_driver.h"
11 #include "ef10_regs.h"
14 #include "mcdi_pcol.h"
16 #include "workarounds.h"
18 #include "ef10_sriov.h"
20 #include <linux/jhash.h>
21 #include <linux/wait.h>
22 #include <linux/workqueue.h>
24 /* Hardware control for EF10 architecture including 'Huntington'. */
26 #define EFX_EF10_DRVGEN_EV 7
32 /* The reserved RSS context value */
33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
34 /* The maximum size of a shared RSS context */
35 /* TODO: this should really be from the mcdi protocol export */
36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
38 /* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
50 #define HUNT_FILTER_TBL_ROWS 8192
52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
54 #define EFX_EF10_FILTER_DEV_UC_MAX 32
55 #define EFX_EF10_FILTER_DEV_MC_MAX 256
58 struct efx_ef10_vlan {
59 struct list_head list;
63 enum efx_ef10_default_filters {
67 EFX_EF10_VXLAN4_UCDEF,
68 EFX_EF10_VXLAN4_MCDEF,
69 EFX_EF10_VXLAN6_UCDEF,
70 EFX_EF10_VXLAN6_MCDEF,
71 EFX_EF10_NVGRE4_UCDEF,
72 EFX_EF10_NVGRE4_MCDEF,
73 EFX_EF10_NVGRE6_UCDEF,
74 EFX_EF10_NVGRE6_MCDEF,
75 EFX_EF10_GENEVE4_UCDEF,
76 EFX_EF10_GENEVE4_MCDEF,
77 EFX_EF10_GENEVE6_UCDEF,
78 EFX_EF10_GENEVE6_MCDEF,
80 EFX_EF10_NUM_DEFAULT_FILTERS
83 /* Per-VLAN filters information */
84 struct efx_ef10_filter_vlan {
85 struct list_head list;
87 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
88 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
89 u16 default_filters[EFX_EF10_NUM_DEFAULT_FILTERS];
92 struct efx_ef10_dev_addr {
96 struct efx_ef10_filter_table {
97 /* The MCDI match masks supported by this fw & hw, in order of priority */
98 u32 rx_match_mcdi_flags[
99 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM * 2];
100 unsigned int rx_match_count;
103 unsigned long spec; /* pointer to spec plus flag bits */
104 /* BUSY flag indicates that an update is in progress. AUTO_OLD is
105 * used to mark and sweep MAC filters for the device address lists.
107 #define EFX_EF10_FILTER_FLAG_BUSY 1UL
108 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
109 #define EFX_EF10_FILTER_FLAGS 3UL
110 u64 handle; /* firmware handle */
112 wait_queue_head_t waitq;
113 /* Shadow of net_device address lists, guarded by mac_lock */
114 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
115 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
120 /* Whether in multicast promiscuous mode when last changed */
121 bool mc_promisc_last;
122 bool mc_overflow; /* Too many MC addrs; should always imply mc_promisc */
124 struct list_head vlan_list;
127 /* An arbitrary search limit for the software hash table */
128 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
130 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
131 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
132 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
133 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
134 struct efx_ef10_filter_vlan *vlan);
135 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
136 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading);
138 static u32 efx_ef10_filter_get_unsafe_id(u32 filter_id)
140 WARN_ON_ONCE(filter_id == EFX_EF10_FILTER_ID_INVALID);
141 return filter_id & (HUNT_FILTER_TBL_ROWS - 1);
144 static unsigned int efx_ef10_filter_get_unsafe_pri(u32 filter_id)
146 return filter_id / (HUNT_FILTER_TBL_ROWS * 2);
149 static u32 efx_ef10_make_filter_id(unsigned int pri, u16 idx)
151 return pri * HUNT_FILTER_TBL_ROWS * 2 + idx;
154 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
158 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS);
159 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
160 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
163 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
167 bar = efx->type->mem_bar;
168 return resource_size(&efx->pci_dev->resource[bar]);
171 static bool efx_ef10_is_vf(struct efx_nic *efx)
173 return efx->type->is_vf;
176 static int efx_ef10_get_pf_index(struct efx_nic *efx)
178 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
179 struct efx_ef10_nic_data *nic_data = efx->nic_data;
183 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
184 sizeof(outbuf), &outlen);
187 if (outlen < sizeof(outbuf))
190 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
194 #ifdef CONFIG_SFC_SRIOV
195 static int efx_ef10_get_vf_index(struct efx_nic *efx)
197 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
198 struct efx_ef10_nic_data *nic_data = efx->nic_data;
202 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
203 sizeof(outbuf), &outlen);
206 if (outlen < sizeof(outbuf))
209 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
214 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
216 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN);
217 struct efx_ef10_nic_data *nic_data = efx->nic_data;
221 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
223 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
224 outbuf, sizeof(outbuf), &outlen);
227 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
228 netif_err(efx, drv, efx->net_dev,
229 "unable to read datapath firmware capabilities\n");
233 nic_data->datapath_caps =
234 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
236 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
237 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
238 GET_CAPABILITIES_V2_OUT_FLAGS2);
239 nic_data->piobuf_size = MCDI_WORD(outbuf,
240 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
242 nic_data->datapath_caps2 = 0;
243 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
246 /* record the DPCPU firmware IDs to determine VEB vswitching support.
248 nic_data->rx_dpcpu_fw_id =
249 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
250 nic_data->tx_dpcpu_fw_id =
251 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
253 if (!(nic_data->datapath_caps &
254 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
255 netif_err(efx, probe, efx->net_dev,
256 "current firmware does not support an RX prefix\n");
263 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
265 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
268 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
269 outbuf, sizeof(outbuf), NULL);
272 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
273 return rc > 0 ? rc : -ERANGE;
276 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
278 struct efx_ef10_nic_data *nic_data = efx->nic_data;
279 unsigned int implemented;
280 unsigned int enabled;
283 nic_data->workaround_35388 = false;
284 nic_data->workaround_61265 = false;
286 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
289 /* Firmware without GET_WORKAROUNDS - not a problem. */
291 } else if (rc == 0) {
292 /* Bug61265 workaround is always enabled if implemented. */
293 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
294 nic_data->workaround_61265 = true;
296 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
297 nic_data->workaround_35388 = true;
298 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
299 /* Workaround is implemented but not enabled.
302 rc = efx_mcdi_set_workaround(efx,
303 MC_CMD_WORKAROUND_BUG35388,
306 nic_data->workaround_35388 = true;
307 /* If we failed to set the workaround just carry on. */
312 netif_dbg(efx, probe, efx->net_dev,
313 "workaround for bug 35388 is %sabled\n",
314 nic_data->workaround_35388 ? "en" : "dis");
315 netif_dbg(efx, probe, efx->net_dev,
316 "workaround for bug 61265 is %sabled\n",
317 nic_data->workaround_61265 ? "en" : "dis");
322 static void efx_ef10_process_timer_config(struct efx_nic *efx,
323 const efx_dword_t *data)
325 unsigned int max_count;
327 if (EFX_EF10_WORKAROUND_61265(efx)) {
328 efx->timer_quantum_ns = MCDI_DWORD(data,
329 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
330 efx->timer_max_ns = MCDI_DWORD(data,
331 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
332 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
333 efx->timer_quantum_ns = MCDI_DWORD(data,
334 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
335 max_count = MCDI_DWORD(data,
336 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
337 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
339 efx->timer_quantum_ns = MCDI_DWORD(data,
340 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
341 max_count = MCDI_DWORD(data,
342 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
343 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
346 netif_dbg(efx, probe, efx->net_dev,
347 "got timer properties from MC: quantum %u ns; max %u ns\n",
348 efx->timer_quantum_ns, efx->timer_max_ns);
351 static int efx_ef10_get_timer_config(struct efx_nic *efx)
353 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
356 rc = efx_ef10_get_timer_workarounds(efx);
360 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
361 outbuf, sizeof(outbuf), NULL);
364 efx_ef10_process_timer_config(efx, outbuf);
365 } else if (rc == -ENOSYS || rc == -EPERM) {
366 /* Not available - fall back to Huntington defaults. */
367 unsigned int quantum;
369 rc = efx_ef10_get_sysclk_freq(efx);
373 quantum = 1536000 / rc; /* 1536 cycles */
374 efx->timer_quantum_ns = quantum;
375 efx->timer_max_ns = efx->type->timer_period_max * quantum;
378 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
379 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
386 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
388 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
392 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
394 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
395 outbuf, sizeof(outbuf), &outlen);
398 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
401 ether_addr_copy(mac_address,
402 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
406 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
408 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
409 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
413 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
414 EVB_PORT_ID_ASSIGNED);
415 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
416 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
420 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
423 num_addrs = MCDI_DWORD(outbuf,
424 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
426 WARN_ON(num_addrs != 1);
428 ether_addr_copy(mac_address,
429 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
434 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
435 struct device_attribute *attr,
438 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
440 return sprintf(buf, "%d\n",
441 ((efx->mcdi->fn_flags) &
442 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
446 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
447 struct device_attribute *attr,
450 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
452 return sprintf(buf, "%d\n",
453 ((efx->mcdi->fn_flags) &
454 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
458 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
460 struct efx_ef10_nic_data *nic_data = efx->nic_data;
461 struct efx_ef10_vlan *vlan;
463 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
465 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
466 if (vlan->vid == vid)
473 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
475 struct efx_ef10_nic_data *nic_data = efx->nic_data;
476 struct efx_ef10_vlan *vlan;
479 mutex_lock(&nic_data->vlan_lock);
481 vlan = efx_ef10_find_vlan(efx, vid);
483 /* We add VID 0 on init. 8021q adds it on module init
484 * for all interfaces with VLAN filtring feature.
488 netif_warn(efx, drv, efx->net_dev,
489 "VLAN %u already added\n", vid);
495 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
501 list_add_tail(&vlan->list, &nic_data->vlan_list);
503 if (efx->filter_state) {
504 mutex_lock(&efx->mac_lock);
505 down_write(&efx->filter_sem);
506 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
507 up_write(&efx->filter_sem);
508 mutex_unlock(&efx->mac_lock);
510 goto fail_filter_add_vlan;
514 mutex_unlock(&nic_data->vlan_lock);
517 fail_filter_add_vlan:
518 list_del(&vlan->list);
522 mutex_unlock(&nic_data->vlan_lock);
526 static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
527 struct efx_ef10_vlan *vlan)
529 struct efx_ef10_nic_data *nic_data = efx->nic_data;
531 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
533 if (efx->filter_state) {
534 down_write(&efx->filter_sem);
535 efx_ef10_filter_del_vlan(efx, vlan->vid);
536 up_write(&efx->filter_sem);
539 list_del(&vlan->list);
543 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
545 struct efx_ef10_nic_data *nic_data = efx->nic_data;
546 struct efx_ef10_vlan *vlan;
549 /* 8021q removes VID 0 on module unload for all interfaces
550 * with VLAN filtering feature. We need to keep it to receive
556 mutex_lock(&nic_data->vlan_lock);
558 vlan = efx_ef10_find_vlan(efx, vid);
560 netif_err(efx, drv, efx->net_dev,
561 "VLAN %u to be deleted not found\n", vid);
564 efx_ef10_del_vlan_internal(efx, vlan);
567 mutex_unlock(&nic_data->vlan_lock);
572 static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
574 struct efx_ef10_nic_data *nic_data = efx->nic_data;
575 struct efx_ef10_vlan *vlan, *next_vlan;
577 mutex_lock(&nic_data->vlan_lock);
578 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
579 efx_ef10_del_vlan_internal(efx, vlan);
580 mutex_unlock(&nic_data->vlan_lock);
583 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
585 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
587 static int efx_ef10_probe(struct efx_nic *efx)
589 struct efx_ef10_nic_data *nic_data;
592 /* We can have one VI for each 8K region. However, until we
593 * use TX option descriptors we need two TX queues per channel.
595 efx->max_channels = min_t(unsigned int,
597 efx_ef10_mem_map_size(efx) /
598 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
599 efx->max_tx_channels = efx->max_channels;
600 if (WARN_ON(efx->max_channels == 0))
603 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
606 efx->nic_data = nic_data;
608 /* we assume later that we can copy from this buffer in dwords */
609 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
611 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
612 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
616 /* Get the MC's warm boot count. In case it's rebooting right
617 * now, be prepared to retry.
621 rc = efx_ef10_get_warm_boot_count(efx);
628 nic_data->warm_boot_count = rc;
630 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
632 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
634 /* In case we're recovering from a crash (kexec), we want to
635 * cancel any outstanding request by the previous user of this
636 * function. We send a special message using the least
637 * significant bits of the 'high' (doorbell) register.
639 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
641 rc = efx_mcdi_init(efx);
645 mutex_init(&nic_data->udp_tunnels_lock);
647 /* Reset (most) configuration for this function */
648 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
652 /* Enable event logging */
653 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
657 rc = device_create_file(&efx->pci_dev->dev,
658 &dev_attr_link_control_flag);
662 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
666 rc = efx_ef10_get_pf_index(efx);
670 rc = efx_ef10_init_datapath_caps(efx);
674 efx->rx_packet_len_offset =
675 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
677 if (nic_data->datapath_caps &
678 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN))
679 efx->net_dev->hw_features |= NETIF_F_RXFCS;
681 rc = efx_mcdi_port_get_number(efx);
686 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
690 rc = efx_ef10_get_timer_config(efx);
694 rc = efx_mcdi_mon_probe(efx);
695 if (rc && rc != -EPERM)
698 efx_ptp_probe(efx, NULL);
700 #ifdef CONFIG_SFC_SRIOV
701 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
702 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
703 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
705 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
708 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
710 INIT_LIST_HEAD(&nic_data->vlan_list);
711 mutex_init(&nic_data->vlan_lock);
713 /* Add unspecified VID to support VLAN filtering being disabled */
714 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
716 goto fail_add_vid_unspec;
718 /* If VLAN filtering is enabled, we need VID 0 to get untagged
719 * traffic. It is added automatically if 8021q module is loaded,
720 * but we can't rely on it since module may be not loaded.
722 rc = efx_ef10_add_vlan(efx, 0);
729 efx_ef10_cleanup_vlans(efx);
731 mutex_destroy(&nic_data->vlan_lock);
733 efx_mcdi_mon_remove(efx);
735 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
737 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
739 efx_mcdi_detach(efx);
741 mutex_lock(&nic_data->udp_tunnels_lock);
742 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
743 (void)efx_ef10_set_udp_tnl_ports(efx, true);
744 mutex_unlock(&nic_data->udp_tunnels_lock);
745 mutex_destroy(&nic_data->udp_tunnels_lock);
749 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
752 efx->nic_data = NULL;
756 static int efx_ef10_free_vis(struct efx_nic *efx)
758 MCDI_DECLARE_BUF_ERR(outbuf);
760 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
761 outbuf, sizeof(outbuf), &outlen);
763 /* -EALREADY means nothing to free, so ignore */
767 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
774 static void efx_ef10_free_piobufs(struct efx_nic *efx)
776 struct efx_ef10_nic_data *nic_data = efx->nic_data;
777 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
781 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
783 for (i = 0; i < nic_data->n_piobufs; i++) {
784 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
785 nic_data->piobuf_handle[i]);
786 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
791 nic_data->n_piobufs = 0;
794 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
796 struct efx_ef10_nic_data *nic_data = efx->nic_data;
797 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
802 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
804 for (i = 0; i < n; i++) {
805 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
806 outbuf, sizeof(outbuf), &outlen);
808 /* Don't display the MC error if we didn't have space
811 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
812 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
813 0, outbuf, outlen, rc);
816 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
820 nic_data->piobuf_handle[i] =
821 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
822 netif_dbg(efx, probe, efx->net_dev,
823 "allocated PIO buffer %u handle %x\n", i,
824 nic_data->piobuf_handle[i]);
827 nic_data->n_piobufs = i;
829 efx_ef10_free_piobufs(efx);
833 static int efx_ef10_link_piobufs(struct efx_nic *efx)
835 struct efx_ef10_nic_data *nic_data = efx->nic_data;
836 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN);
837 struct efx_channel *channel;
838 struct efx_tx_queue *tx_queue;
839 unsigned int offset, index;
842 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
843 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
845 /* Link a buffer to each VI in the write-combining mapping */
846 for (index = 0; index < nic_data->n_piobufs; ++index) {
847 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
848 nic_data->piobuf_handle[index]);
849 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
850 nic_data->pio_write_vi_base + index);
851 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
852 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
855 netif_err(efx, drv, efx->net_dev,
856 "failed to link VI %u to PIO buffer %u (%d)\n",
857 nic_data->pio_write_vi_base + index, index,
861 netif_dbg(efx, probe, efx->net_dev,
862 "linked VI %u to PIO buffer %u\n",
863 nic_data->pio_write_vi_base + index, index);
866 /* Link a buffer to each TX queue */
867 efx_for_each_channel(channel, efx) {
868 efx_for_each_channel_tx_queue(tx_queue, channel) {
869 /* We assign the PIO buffers to queues in
870 * reverse order to allow for the following
873 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
874 tx_queue->channel->channel - 1) *
876 index = offset / nic_data->piobuf_size;
877 offset = offset % nic_data->piobuf_size;
879 /* When the host page size is 4K, the first
880 * host page in the WC mapping may be within
881 * the same VI page as the last TX queue. We
882 * can only link one buffer to each VI.
884 if (tx_queue->queue == nic_data->pio_write_vi_base) {
888 MCDI_SET_DWORD(inbuf,
889 LINK_PIOBUF_IN_PIOBUF_HANDLE,
890 nic_data->piobuf_handle[index]);
891 MCDI_SET_DWORD(inbuf,
892 LINK_PIOBUF_IN_TXQ_INSTANCE,
894 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
895 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
900 /* This is non-fatal; the TX path just
901 * won't use PIO for this queue
903 netif_err(efx, drv, efx->net_dev,
904 "failed to link VI %u to PIO buffer %u (%d)\n",
905 tx_queue->queue, index, rc);
906 tx_queue->piobuf = NULL;
909 nic_data->pio_write_base +
910 index * EFX_VI_PAGE_SIZE + offset;
911 tx_queue->piobuf_offset = offset;
912 netif_dbg(efx, probe, efx->net_dev,
913 "linked VI %u to PIO buffer %u offset %x addr %p\n",
914 tx_queue->queue, index,
915 tx_queue->piobuf_offset,
924 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same
925 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter.
927 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN);
929 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
930 nic_data->pio_write_vi_base + index);
931 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
932 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
938 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
940 struct efx_channel *channel;
941 struct efx_tx_queue *tx_queue;
943 /* All our existing PIO buffers went away */
944 efx_for_each_channel(channel, efx)
945 efx_for_each_channel_tx_queue(tx_queue, channel)
946 tx_queue->piobuf = NULL;
949 #else /* !EFX_USE_PIO */
951 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
953 return n == 0 ? 0 : -ENOBUFS;
956 static int efx_ef10_link_piobufs(struct efx_nic *efx)
961 static void efx_ef10_free_piobufs(struct efx_nic *efx)
965 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
969 #endif /* EFX_USE_PIO */
971 static void efx_ef10_remove(struct efx_nic *efx)
973 struct efx_ef10_nic_data *nic_data = efx->nic_data;
976 #ifdef CONFIG_SFC_SRIOV
977 struct efx_ef10_nic_data *nic_data_pf;
978 struct pci_dev *pci_dev_pf;
979 struct efx_nic *efx_pf;
982 if (efx->pci_dev->is_virtfn) {
983 pci_dev_pf = efx->pci_dev->physfn;
985 efx_pf = pci_get_drvdata(pci_dev_pf);
986 nic_data_pf = efx_pf->nic_data;
987 vf = nic_data_pf->vf + nic_data->vf_index;
990 netif_info(efx, drv, efx->net_dev,
991 "Could not get the PF id from VF\n");
995 efx_ef10_cleanup_vlans(efx);
996 mutex_destroy(&nic_data->vlan_lock);
1000 efx_mcdi_mon_remove(efx);
1002 efx_ef10_rx_free_indir_table(efx);
1004 if (nic_data->wc_membase)
1005 iounmap(nic_data->wc_membase);
1007 rc = efx_ef10_free_vis(efx);
1010 if (!nic_data->must_restore_piobufs)
1011 efx_ef10_free_piobufs(efx);
1013 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
1014 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
1016 efx_mcdi_detach(efx);
1018 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
1019 mutex_lock(&nic_data->udp_tunnels_lock);
1020 (void)efx_ef10_set_udp_tnl_ports(efx, true);
1021 mutex_unlock(&nic_data->udp_tunnels_lock);
1023 mutex_destroy(&nic_data->udp_tunnels_lock);
1026 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1030 static int efx_ef10_probe_pf(struct efx_nic *efx)
1032 return efx_ef10_probe(efx);
1035 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
1036 u32 *port_flags, u32 *vadaptor_flags,
1037 unsigned int *vlan_tags)
1039 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1040 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
1041 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
1045 if (nic_data->datapath_caps &
1046 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
1047 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
1050 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
1051 outbuf, sizeof(outbuf), &outlen);
1055 if (outlen < sizeof(outbuf)) {
1062 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1065 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1069 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1074 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1076 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1078 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1079 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1083 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1085 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1087 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1088 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1092 int efx_ef10_vport_add_mac(struct efx_nic *efx,
1093 unsigned int port_id, u8 *mac)
1095 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1097 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1098 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1100 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1101 sizeof(inbuf), NULL, 0, NULL);
1104 int efx_ef10_vport_del_mac(struct efx_nic *efx,
1105 unsigned int port_id, u8 *mac)
1107 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1109 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1110 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1112 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1113 sizeof(inbuf), NULL, 0, NULL);
1116 #ifdef CONFIG_SFC_SRIOV
1117 static int efx_ef10_probe_vf(struct efx_nic *efx)
1120 struct pci_dev *pci_dev_pf;
1122 /* If the parent PF has no VF data structure, it doesn't know about this
1123 * VF so fail probe. The VF needs to be re-created. This can happen
1124 * if the PF driver is unloaded while the VF is assigned to a guest.
1126 pci_dev_pf = efx->pci_dev->physfn;
1128 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1129 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1131 if (!nic_data_pf->vf) {
1132 netif_info(efx, drv, efx->net_dev,
1133 "The VF cannot link to its parent PF; "
1134 "please destroy and re-create the VF\n");
1139 rc = efx_ef10_probe(efx);
1143 rc = efx_ef10_get_vf_index(efx);
1147 if (efx->pci_dev->is_virtfn) {
1148 if (efx->pci_dev->physfn) {
1149 struct efx_nic *efx_pf =
1150 pci_get_drvdata(efx->pci_dev->physfn);
1151 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1152 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1154 nic_data_p->vf[nic_data->vf_index].efx = efx;
1155 nic_data_p->vf[nic_data->vf_index].pci_dev =
1158 netif_info(efx, drv, efx->net_dev,
1159 "Could not get the PF id from VF\n");
1165 efx_ef10_remove(efx);
1169 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1175 static int efx_ef10_alloc_vis(struct efx_nic *efx,
1176 unsigned int min_vis, unsigned int max_vis)
1178 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1179 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1180 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1184 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1185 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1186 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1187 outbuf, sizeof(outbuf), &outlen);
1191 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1194 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1195 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1197 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1198 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1202 /* Note that the failure path of this function does not free
1203 * resources, as this will be done by efx_ef10_remove().
1205 static int efx_ef10_dimension_resources(struct efx_nic *efx)
1207 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1208 unsigned int uc_mem_map_size, wc_mem_map_size;
1209 unsigned int min_vis = max(EFX_TXQ_TYPES,
1210 efx_separate_tx_channels ? 2 : 1);
1211 unsigned int channel_vis, pio_write_vi_base, max_vis;
1212 void __iomem *membase;
1215 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1218 /* Try to allocate PIO buffers if wanted and if the full
1219 * number of PIO buffers would be sufficient to allocate one
1220 * copy-buffer per TX channel. Failure is non-fatal, as there
1221 * are only a small number of PIO buffers shared between all
1222 * functions of the controller.
1224 if (efx_piobuf_size != 0 &&
1225 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1226 efx->n_tx_channels) {
1227 unsigned int n_piobufs =
1228 DIV_ROUND_UP(efx->n_tx_channels,
1229 nic_data->piobuf_size / efx_piobuf_size);
1231 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1233 netif_dbg(efx, probe, efx->net_dev,
1234 "out of PIO buffers; cannot allocate more\n");
1235 else if (rc == -EPERM)
1236 netif_dbg(efx, probe, efx->net_dev,
1237 "not permitted to allocate PIO buffers\n");
1239 netif_err(efx, probe, efx->net_dev,
1240 "failed to allocate PIO buffers (%d)\n", rc);
1242 netif_dbg(efx, probe, efx->net_dev,
1243 "allocated %u PIO buffers\n", n_piobufs);
1246 nic_data->n_piobufs = 0;
1249 /* PIO buffers should be mapped with write-combining enabled,
1250 * and we want to make single UC and WC mappings rather than
1251 * several of each (in fact that's the only option if host
1252 * page size is >4K). So we may allocate some extra VIs just
1253 * for writing PIO buffers through.
1255 * The UC mapping contains (channel_vis - 1) complete VIs and the
1256 * first half of the next VI. Then the WC mapping begins with
1257 * the second half of this last VI.
1259 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
1261 if (nic_data->n_piobufs) {
1262 /* pio_write_vi_base rounds down to give the number of complete
1263 * VIs inside the UC mapping.
1265 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1266 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1267 nic_data->n_piobufs) *
1270 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1272 pio_write_vi_base = 0;
1273 wc_mem_map_size = 0;
1274 max_vis = channel_vis;
1277 /* In case the last attached driver failed to free VIs, do it now */
1278 rc = efx_ef10_free_vis(efx);
1282 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1286 if (nic_data->n_allocated_vis < channel_vis) {
1287 netif_info(efx, drv, efx->net_dev,
1288 "Could not allocate enough VIs to satisfy RSS"
1289 " requirements. Performance may not be optimal.\n");
1290 /* We didn't get the VIs to populate our channels.
1291 * We could keep what we got but then we'd have more
1292 * interrupts than we need.
1293 * Instead calculate new max_channels and restart
1295 efx->max_channels = nic_data->n_allocated_vis;
1296 efx->max_tx_channels =
1297 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1299 efx_ef10_free_vis(efx);
1303 /* If we didn't get enough VIs to map all the PIO buffers, free the
1306 if (nic_data->n_piobufs &&
1307 nic_data->n_allocated_vis <
1308 pio_write_vi_base + nic_data->n_piobufs) {
1309 netif_dbg(efx, probe, efx->net_dev,
1310 "%u VIs are not sufficient to map %u PIO buffers\n",
1311 nic_data->n_allocated_vis, nic_data->n_piobufs);
1312 efx_ef10_free_piobufs(efx);
1315 /* Shrink the original UC mapping of the memory BAR */
1316 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1318 netif_err(efx, probe, efx->net_dev,
1319 "could not shrink memory BAR to %x\n",
1323 iounmap(efx->membase);
1324 efx->membase = membase;
1326 /* Set up the WC mapping if needed */
1327 if (wc_mem_map_size) {
1328 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1331 if (!nic_data->wc_membase) {
1332 netif_err(efx, probe, efx->net_dev,
1333 "could not allocate WC mapping of size %x\n",
1337 nic_data->pio_write_vi_base = pio_write_vi_base;
1338 nic_data->pio_write_base =
1339 nic_data->wc_membase +
1340 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1343 rc = efx_ef10_link_piobufs(efx);
1345 efx_ef10_free_piobufs(efx);
1348 netif_dbg(efx, probe, efx->net_dev,
1349 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1350 &efx->membase_phys, efx->membase, uc_mem_map_size,
1351 nic_data->wc_membase, wc_mem_map_size);
1356 static int efx_ef10_init_nic(struct efx_nic *efx)
1358 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1361 if (nic_data->must_check_datapath_caps) {
1362 rc = efx_ef10_init_datapath_caps(efx);
1365 nic_data->must_check_datapath_caps = false;
1368 if (nic_data->must_realloc_vis) {
1369 /* We cannot let the number of VIs change now */
1370 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1371 nic_data->n_allocated_vis);
1374 nic_data->must_realloc_vis = false;
1377 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1378 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1380 rc = efx_ef10_link_piobufs(efx);
1382 efx_ef10_free_piobufs(efx);
1385 /* Log an error on failure, but this is non-fatal.
1386 * Permission errors are less important - we've presumably
1387 * had the PIO buffer licence removed.
1390 netif_dbg(efx, drv, efx->net_dev,
1391 "not permitted to restore PIO buffers\n");
1393 netif_err(efx, drv, efx->net_dev,
1394 "failed to restore PIO buffers (%d)\n", rc);
1395 nic_data->must_restore_piobufs = false;
1398 /* don't fail init if RSS setup doesn't work */
1399 rc = efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table, NULL);
1400 efx->rss_active = (rc == 0);
1405 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1407 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1408 #ifdef CONFIG_SFC_SRIOV
1412 /* All our allocations have been reset */
1413 nic_data->must_realloc_vis = true;
1414 nic_data->must_restore_filters = true;
1415 nic_data->must_restore_piobufs = true;
1416 efx_ef10_forget_old_piobufs(efx);
1417 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1419 /* Driver-created vswitches and vports must be re-created */
1420 nic_data->must_probe_vswitching = true;
1421 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1422 #ifdef CONFIG_SFC_SRIOV
1424 for (i = 0; i < efx->vf_count; i++)
1425 nic_data->vf[i].vport_id = 0;
1429 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1431 if (reason == RESET_TYPE_MC_FAILURE)
1432 return RESET_TYPE_DATAPATH;
1434 return efx_mcdi_map_reset_reason(reason);
1437 static int efx_ef10_map_reset_flags(u32 *flags)
1440 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1441 ETH_RESET_SHARED_SHIFT),
1442 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1443 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1444 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1445 ETH_RESET_SHARED_SHIFT)
1448 /* We assume for now that our PCI function is permitted to
1452 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1453 *flags &= ~EF10_RESET_MC;
1454 return RESET_TYPE_WORLD;
1457 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1458 *flags &= ~EF10_RESET_PORT;
1459 return RESET_TYPE_ALL;
1462 /* no invisible reset implemented */
1467 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1469 int rc = efx_mcdi_reset(efx, reset_type);
1471 /* Unprivileged functions return -EPERM, but need to return success
1472 * here so that the datapath is brought back up.
1474 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1477 /* If it was a port reset, trigger reallocation of MC resources.
1478 * Note that on an MC reset nothing needs to be done now because we'll
1479 * detect the MC reset later and handle it then.
1480 * For an FLR, we never get an MC reset event, but the MC has reset all
1481 * resources assigned to us, so we have to trigger reallocation now.
1483 if ((reset_type == RESET_TYPE_ALL ||
1484 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1485 efx_ef10_reset_mc_allocations(efx);
1489 #define EF10_DMA_STAT(ext_name, mcdi_name) \
1490 [EF10_STAT_ ## ext_name] = \
1491 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1492 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1493 [EF10_STAT_ ## int_name] = \
1494 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1495 #define EF10_OTHER_STAT(ext_name) \
1496 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1497 #define GENERIC_SW_STAT(ext_name) \
1498 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1500 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1501 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1502 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1503 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1504 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1505 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1506 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1507 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1508 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1509 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1510 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1511 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1512 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1513 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1514 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1515 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1516 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1517 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1518 EF10_OTHER_STAT(port_rx_good_bytes),
1519 EF10_OTHER_STAT(port_rx_bad_bytes),
1520 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1521 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1522 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1523 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1524 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1525 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1526 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1527 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1528 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1529 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1530 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1531 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1532 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1533 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1534 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1535 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1536 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1537 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1538 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1539 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1540 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1541 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1542 GENERIC_SW_STAT(rx_nodesc_trunc),
1543 GENERIC_SW_STAT(rx_noskb_drops),
1544 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1545 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1546 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1547 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1548 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1549 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1550 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1551 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1552 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1553 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1554 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1555 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1556 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1557 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1558 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1559 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1560 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1561 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1562 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1563 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1564 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1565 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1566 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1567 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1568 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1569 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1570 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1571 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1572 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1573 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1576 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1577 (1ULL << EF10_STAT_port_tx_packets) | \
1578 (1ULL << EF10_STAT_port_tx_pause) | \
1579 (1ULL << EF10_STAT_port_tx_unicast) | \
1580 (1ULL << EF10_STAT_port_tx_multicast) | \
1581 (1ULL << EF10_STAT_port_tx_broadcast) | \
1582 (1ULL << EF10_STAT_port_rx_bytes) | \
1584 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1585 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1586 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1587 (1ULL << EF10_STAT_port_rx_packets) | \
1588 (1ULL << EF10_STAT_port_rx_good) | \
1589 (1ULL << EF10_STAT_port_rx_bad) | \
1590 (1ULL << EF10_STAT_port_rx_pause) | \
1591 (1ULL << EF10_STAT_port_rx_control) | \
1592 (1ULL << EF10_STAT_port_rx_unicast) | \
1593 (1ULL << EF10_STAT_port_rx_multicast) | \
1594 (1ULL << EF10_STAT_port_rx_broadcast) | \
1595 (1ULL << EF10_STAT_port_rx_lt64) | \
1596 (1ULL << EF10_STAT_port_rx_64) | \
1597 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1598 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1599 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1600 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1601 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1602 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1603 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1604 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1605 (1ULL << EF10_STAT_port_rx_overflow) | \
1606 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1607 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1608 (1ULL << GENERIC_STAT_rx_noskb_drops))
1610 /* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1611 * For a 10G/40G switchable port we do not expose these because they might
1612 * not include all the packets they should.
1613 * On 8000 series NICs these statistics are always provided.
1615 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1616 (1ULL << EF10_STAT_port_tx_lt64) | \
1617 (1ULL << EF10_STAT_port_tx_64) | \
1618 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1619 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1620 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1621 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1622 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1623 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1625 /* These statistics are only provided by the 40G MAC. For a 10G/40G
1626 * switchable port we do expose these because the errors will otherwise
1629 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1630 (1ULL << EF10_STAT_port_rx_length_error))
1632 /* These statistics are only provided if the firmware supports the
1633 * capability PM_AND_RXDP_COUNTERS.
1635 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
1636 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1637 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1638 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1639 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1640 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1641 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1642 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1643 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1644 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1645 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1646 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1647 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1649 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1651 u64 raw_mask = HUNT_COMMON_STAT_MASK;
1652 u32 port_caps = efx_mcdi_phy_get_caps(efx);
1653 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1655 if (!(efx->mcdi->fn_flags &
1656 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1659 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
1660 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1661 /* 8000 series have everything even at 40G */
1662 if (nic_data->datapath_caps2 &
1663 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1664 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1666 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1669 if (nic_data->datapath_caps &
1670 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1671 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1676 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1678 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1681 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1683 /* Only show vadaptor stats when EVB capability is present */
1684 if (nic_data->datapath_caps &
1685 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1686 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1687 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1692 #if BITS_PER_LONG == 64
1693 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
1694 mask[0] = raw_mask[0];
1695 mask[1] = raw_mask[1];
1697 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
1698 mask[0] = raw_mask[0] & 0xffffffff;
1699 mask[1] = raw_mask[0] >> 32;
1700 mask[2] = raw_mask[1] & 0xffffffff;
1704 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1706 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1708 efx_ef10_get_stat_mask(efx, mask);
1709 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1713 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1714 struct rtnl_link_stats64 *core_stats)
1716 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1717 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1718 u64 *stats = nic_data->stats;
1719 size_t stats_count = 0, index;
1721 efx_ef10_get_stat_mask(efx, mask);
1724 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1725 if (efx_ef10_stat_desc[index].name) {
1726 *full_stats++ = stats[index];
1735 if (nic_data->datapath_caps &
1736 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1737 /* Use vadaptor stats. */
1738 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1739 stats[EF10_STAT_rx_multicast] +
1740 stats[EF10_STAT_rx_broadcast];
1741 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1742 stats[EF10_STAT_tx_multicast] +
1743 stats[EF10_STAT_tx_broadcast];
1744 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1745 stats[EF10_STAT_rx_multicast_bytes] +
1746 stats[EF10_STAT_rx_broadcast_bytes];
1747 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1748 stats[EF10_STAT_tx_multicast_bytes] +
1749 stats[EF10_STAT_tx_broadcast_bytes];
1750 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1751 stats[GENERIC_STAT_rx_noskb_drops];
1752 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1753 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1754 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1755 core_stats->rx_errors = core_stats->rx_crc_errors;
1756 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1758 /* Use port stats. */
1759 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1760 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1761 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1762 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1763 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1764 stats[GENERIC_STAT_rx_nodesc_trunc] +
1765 stats[GENERIC_STAT_rx_noskb_drops];
1766 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1767 core_stats->rx_length_errors =
1768 stats[EF10_STAT_port_rx_gtjumbo] +
1769 stats[EF10_STAT_port_rx_length_error];
1770 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1771 core_stats->rx_frame_errors =
1772 stats[EF10_STAT_port_rx_align_error];
1773 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1774 core_stats->rx_errors = (core_stats->rx_length_errors +
1775 core_stats->rx_crc_errors +
1776 core_stats->rx_frame_errors);
1782 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1784 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1785 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1786 __le64 generation_start, generation_end;
1787 u64 *stats = nic_data->stats;
1790 efx_ef10_get_stat_mask(efx, mask);
1792 dma_stats = efx->stats_buffer.addr;
1794 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1795 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1798 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1799 stats, efx->stats_buffer.addr, false);
1801 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1802 if (generation_end != generation_start)
1805 /* Update derived statistics */
1806 efx_nic_fix_nodesc_drop_stat(efx,
1807 &stats[EF10_STAT_port_rx_nodesc_drops]);
1808 stats[EF10_STAT_port_rx_good_bytes] =
1809 stats[EF10_STAT_port_rx_bytes] -
1810 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1811 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1812 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1813 efx_update_sw_stats(efx, stats);
1818 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1819 struct rtnl_link_stats64 *core_stats)
1823 /* If we're unlucky enough to read statistics during the DMA, wait
1824 * up to 10ms for it to finish (typically takes <500us)
1826 for (retry = 0; retry < 100; ++retry) {
1827 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1832 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1835 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1837 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1838 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1839 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1840 __le64 generation_start, generation_end;
1841 u64 *stats = nic_data->stats;
1842 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1843 struct efx_buffer stats_buf;
1847 spin_unlock_bh(&efx->stats_lock);
1849 if (in_interrupt()) {
1850 /* If in atomic context, cannot update stats. Just update the
1851 * software stats and return so the caller can continue.
1853 spin_lock_bh(&efx->stats_lock);
1854 efx_update_sw_stats(efx, stats);
1858 efx_ef10_get_stat_mask(efx, mask);
1860 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1862 spin_lock_bh(&efx->stats_lock);
1866 dma_stats = stats_buf.addr;
1867 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1869 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1870 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1871 MAC_STATS_IN_DMA, 1);
1872 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1873 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1875 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1877 spin_lock_bh(&efx->stats_lock);
1879 /* Expect ENOENT if DMA queues have not been set up */
1880 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1881 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1882 sizeof(inbuf), NULL, 0, rc);
1886 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1887 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1892 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1893 stats, stats_buf.addr, false);
1895 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1896 if (generation_end != generation_start) {
1901 efx_update_sw_stats(efx, stats);
1903 efx_nic_free_buffer(efx, &stats_buf);
1907 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1908 struct rtnl_link_stats64 *core_stats)
1910 if (efx_ef10_try_update_nic_stats_vf(efx))
1913 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1916 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1918 struct efx_nic *efx = channel->efx;
1919 unsigned int mode, usecs;
1920 efx_dword_t timer_cmd;
1922 if (channel->irq_moderation_us) {
1924 usecs = channel->irq_moderation_us;
1930 if (EFX_EF10_WORKAROUND_61265(efx)) {
1931 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1932 unsigned int ns = usecs * 1000;
1934 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1936 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1937 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1938 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1940 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1941 inbuf, sizeof(inbuf), 0, NULL, 0);
1942 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1943 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1945 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1946 EFE_DD_EVQ_IND_TIMER_FLAGS,
1947 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1948 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
1949 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1952 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1954 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1955 ERF_DZ_TC_TIMER_VAL, ticks);
1956 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1961 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1962 struct ethtool_wolinfo *wol) {}
1964 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1969 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1973 memset(&wol->sopass, 0, sizeof(wol->sopass));
1976 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1983 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1984 const efx_dword_t *hdr, size_t hdr_len,
1985 const efx_dword_t *sdu, size_t sdu_len)
1987 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1988 u8 *pdu = nic_data->mcdi_buf.addr;
1990 memcpy(pdu, hdr, hdr_len);
1991 memcpy(pdu + hdr_len, sdu, sdu_len);
1994 /* The hardware provides 'low' and 'high' (doorbell) registers
1995 * for passing the 64-bit address of an MCDI request to
1996 * firmware. However the dwords are swapped by firmware. The
1997 * least significant bits of the doorbell are then 0 for all
1998 * MCDI requests due to alignment.
2000 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
2002 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
2006 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
2008 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2009 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
2012 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
2016 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
2017 size_t offset, size_t outlen)
2019 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2020 const u8 *pdu = nic_data->mcdi_buf.addr;
2022 memcpy(outbuf, pdu + offset, outlen);
2025 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
2027 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2029 /* All our allocations have been reset */
2030 efx_ef10_reset_mc_allocations(efx);
2032 /* The datapath firmware might have been changed */
2033 nic_data->must_check_datapath_caps = true;
2035 /* MAC statistics have been cleared on the NIC; clear the local
2036 * statistic that we update with efx_update_diff_stat().
2038 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
2041 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2043 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2046 rc = efx_ef10_get_warm_boot_count(efx);
2048 /* The firmware is presumably in the process of
2049 * rebooting. However, we are supposed to report each
2050 * reboot just once, so we must only do that once we
2051 * can read and store the updated warm boot count.
2056 if (rc == nic_data->warm_boot_count)
2059 nic_data->warm_boot_count = rc;
2060 efx_ef10_mcdi_reboot_detected(efx);
2065 /* Handle an MSI interrupt
2067 * Handle an MSI hardware interrupt. This routine schedules event
2068 * queue processing. No interrupt acknowledgement cycle is necessary.
2069 * Also, we never need to check that the interrupt is for us, since
2070 * MSI interrupts cannot be shared.
2072 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2074 struct efx_msi_context *context = dev_id;
2075 struct efx_nic *efx = context->efx;
2077 netif_vdbg(efx, intr, efx->net_dev,
2078 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2080 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
2081 /* Note test interrupts */
2082 if (context->index == efx->irq_level)
2083 efx->last_irq_cpu = raw_smp_processor_id();
2085 /* Schedule processing of the channel */
2086 efx_schedule_channel_irq(efx->channel[context->index]);
2092 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2094 struct efx_nic *efx = dev_id;
2095 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled);
2096 struct efx_channel *channel;
2100 /* Read the ISR which also ACKs the interrupts */
2101 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR);
2102 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2107 if (likely(soft_enabled)) {
2108 /* Note test interrupts */
2109 if (queues & (1U << efx->irq_level))
2110 efx->last_irq_cpu = raw_smp_processor_id();
2112 efx_for_each_channel(channel, efx) {
2114 efx_schedule_channel_irq(channel);
2119 netif_vdbg(efx, intr, efx->net_dev,
2120 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2121 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2126 static int efx_ef10_irq_test_generate(struct efx_nic *efx)
2128 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2130 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2134 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2136 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
2137 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
2138 inbuf, sizeof(inbuf), NULL, 0, NULL);
2141 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2143 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2144 (tx_queue->ptr_mask + 1) *
2145 sizeof(efx_qword_t),
2149 /* This writes to the TX_DESC_WPTR and also pushes data */
2150 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2151 const efx_qword_t *txd)
2153 unsigned int write_ptr;
2156 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2157 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2158 reg.qword[0] = *txd;
2159 efx_writeo_page(tx_queue->efx, ®,
2160 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2163 /* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2165 static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2166 struct sk_buff *skb,
2169 struct efx_tx_buffer *buffer;
2177 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
2179 mss = skb_shinfo(skb)->gso_size;
2181 if (unlikely(mss < 4)) {
2182 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2187 if (ip->version == 4) {
2188 /* Modify IPv4 header if needed. */
2191 ipv4_id = ntohs(ip->id);
2193 /* Modify IPv6 header if needed. */
2194 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2196 ipv6->payload_len = 0;
2201 seqnum = ntohl(tcp->seq);
2203 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2205 buffer->flags = EFX_TX_BUF_OPTION;
2207 buffer->unmap_len = 0;
2208 EFX_POPULATE_QWORD_5(buffer->option,
2209 ESF_DZ_TX_DESC_IS_OPT, 1,
2210 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2211 ESF_DZ_TX_TSO_OPTION_TYPE,
2212 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2213 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2214 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2216 ++tx_queue->insert_count;
2218 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2220 buffer->flags = EFX_TX_BUF_OPTION;
2222 buffer->unmap_len = 0;
2223 EFX_POPULATE_QWORD_4(buffer->option,
2224 ESF_DZ_TX_DESC_IS_OPT, 1,
2225 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2226 ESF_DZ_TX_TSO_OPTION_TYPE,
2227 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2228 ESF_DZ_TX_TSO_TCP_MSS, mss
2230 ++tx_queue->insert_count;
2235 static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2237 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2238 u32 tso_versions = 0;
2240 if (nic_data->datapath_caps &
2241 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2242 tso_versions |= BIT(1);
2243 if (nic_data->datapath_caps2 &
2244 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2245 tso_versions |= BIT(2);
2246 return tso_versions;
2249 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2251 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2253 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2254 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2255 struct efx_channel *channel = tx_queue->channel;
2256 struct efx_nic *efx = tx_queue->efx;
2257 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2258 bool tso_v2 = false;
2260 dma_addr_t dma_addr;
2264 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
2266 /* TSOv2 is a limited resource that can only be configured on a limited
2267 * number of queues. TSO without checksum offload is not really a thing,
2268 * so we only enable it for those queues.
2270 if (csum_offload && (nic_data->datapath_caps2 &
2271 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))) {
2273 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2277 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2278 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2279 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2280 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
2281 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
2282 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
2284 dma_addr = tx_queue->txd.buf.dma_addr;
2286 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2287 tx_queue->queue, entries, (u64)dma_addr);
2289 for (i = 0; i < entries; ++i) {
2290 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2291 dma_addr += EFX_BUF_SIZE;
2294 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2297 MCDI_POPULATE_DWORD_3(inbuf, INIT_TXQ_IN_FLAGS,
2298 /* This flag was removed from mcdi_pcol.h for
2299 * the non-_EXT version of INIT_TXQ. However,
2300 * firmware still honours it.
2302 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2303 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2304 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2306 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2308 if (rc == -ENOSPC && tso_v2) {
2309 /* Retry without TSOv2 if we're short on contexts. */
2311 netif_warn(efx, probe, efx->net_dev,
2312 "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2314 efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2315 MC_CMD_INIT_TXQ_EXT_IN_LEN,
2321 /* A previous user of this TX queue might have set us up the
2322 * bomb by writing a descriptor to the TX push collector but
2323 * not the doorbell. (Each collector belongs to a port, not a
2324 * queue or function, so cannot easily be reset.) We must
2325 * attempt to push a no-op descriptor in its place.
2327 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2328 tx_queue->insert_count = 1;
2329 txd = efx_tx_desc(tx_queue, 0);
2330 EFX_POPULATE_QWORD_4(*txd,
2331 ESF_DZ_TX_DESC_IS_OPT, true,
2332 ESF_DZ_TX_OPTION_TYPE,
2333 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2334 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2335 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2336 tx_queue->write_count = 1;
2339 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2340 tx_queue->tso_version = 2;
2341 } else if (nic_data->datapath_caps &
2342 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2343 tx_queue->tso_version = 1;
2347 efx_ef10_push_tx_desc(tx_queue, txd);
2352 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2356 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2358 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
2359 MCDI_DECLARE_BUF_ERR(outbuf);
2360 struct efx_nic *efx = tx_queue->efx;
2364 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2367 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
2368 outbuf, sizeof(outbuf), &outlen);
2370 if (rc && rc != -EALREADY)
2376 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2377 outbuf, outlen, rc);
2380 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2382 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2385 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2386 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2388 unsigned int write_ptr;
2391 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2392 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2393 efx_writed_page(tx_queue->efx, ®,
2394 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2397 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2399 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2400 dma_addr_t dma_addr, unsigned int len)
2402 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2403 /* If we need to break across multiple descriptors we should
2404 * stop at a page boundary. This assumes the length limit is
2405 * greater than the page size.
2407 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2409 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2410 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2416 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2418 unsigned int old_write_count = tx_queue->write_count;
2419 struct efx_tx_buffer *buffer;
2420 unsigned int write_ptr;
2423 tx_queue->xmit_more_available = false;
2424 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2428 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2429 buffer = &tx_queue->buffer[write_ptr];
2430 txd = efx_tx_desc(tx_queue, write_ptr);
2431 ++tx_queue->write_count;
2433 /* Create TX descriptor ring entry */
2434 if (buffer->flags & EFX_TX_BUF_OPTION) {
2435 *txd = buffer->option;
2436 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2437 /* PIO descriptor */
2438 tx_queue->packet_write_count = tx_queue->write_count;
2440 tx_queue->packet_write_count = tx_queue->write_count;
2441 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2442 EFX_POPULATE_QWORD_3(
2445 buffer->flags & EFX_TX_BUF_CONT,
2446 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2447 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2449 } while (tx_queue->write_count != tx_queue->insert_count);
2451 wmb(); /* Ensure descriptors are written before they are fetched */
2453 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2454 txd = efx_tx_desc(tx_queue,
2455 old_write_count & tx_queue->ptr_mask);
2456 efx_ef10_push_tx_desc(tx_queue, txd);
2459 efx_ef10_notify_tx_desc(tx_queue);
2463 #define RSS_MODE_HASH_ADDRS (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2464 1 << RSS_MODE_HASH_DST_ADDR_LBN)
2465 #define RSS_MODE_HASH_PORTS (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2466 1 << RSS_MODE_HASH_DST_PORT_LBN)
2467 #define RSS_CONTEXT_FLAGS_DEFAULT (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2468 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2469 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2470 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2471 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2472 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2473 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2474 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2475 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2476 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2478 static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2480 /* Firmware had a bug (sfc bug 61952) where it would not actually
2481 * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2482 * This meant that it would always contain whatever was previously
2483 * in the MCDI buffer. Fortunately, all firmware versions with
2484 * this bug have the same default flags value for a newly-allocated
2485 * RSS context, and the only time we want to get the flags is just
2486 * after allocating. Moreover, the response has a 32-bit hole
2487 * where the context ID would be in the request, so we can use an
2488 * overlength buffer in the request and pre-fill the flags field
2489 * with what we believe the default to be. Thus if the firmware
2490 * has the bug, it will leave our pre-filled value in the flags
2491 * field of the response, and we will get the right answer.
2493 * However, this does mean that this function should NOT be used if
2494 * the RSS context flags might not be their defaults - it is ONLY
2495 * reliably correct for a newly-allocated RSS context.
2497 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2498 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2502 /* Check we have a hole for the context ID */
2503 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2504 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2505 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2506 RSS_CONTEXT_FLAGS_DEFAULT);
2507 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2508 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2510 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2513 *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2518 /* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2519 * If we fail, we just leave the RSS context at its default hash settings,
2520 * which is safe but may slightly reduce performance.
2521 * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2522 * just need to set the UDP ports flags (for both IP versions).
2524 static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context)
2526 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2529 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2531 if (efx_ef10_get_rss_flags(efx, context, &flags) != 0)
2533 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context);
2534 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2535 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2536 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
2537 if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2539 /* Succeeded, so UDP 4-tuple is now enabled */
2540 efx->rx_hash_udp_4tuple = true;
2543 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2544 bool exclusive, unsigned *context_size)
2546 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2547 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
2548 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2551 u32 alloc_type = exclusive ?
2552 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2553 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2554 unsigned rss_spread = exclusive ?
2556 min(rounddown_pow_of_two(efx->rss_spread),
2557 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2559 if (!exclusive && rss_spread == 1) {
2560 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2566 if (nic_data->datapath_caps &
2567 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2570 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
2571 nic_data->vport_id);
2572 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2573 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
2575 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2576 outbuf, sizeof(outbuf), &outlen);
2580 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2583 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2586 *context_size = rss_spread;
2588 if (nic_data->datapath_caps &
2589 1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2590 efx_ef10_set_rss_flags(efx, *context);
2595 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2597 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2600 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2603 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2608 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2609 const u32 *rx_indir_table, const u8 *key)
2611 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2612 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2615 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2617 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2618 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2620 /* This iterates over the length of efx->rx_indir_table, but copies
2621 * bytes from rx_indir_table. That's because the latter is a pointer
2622 * rather than an array, but should have the same length.
2623 * The efx->rx_hash_key loop below is similar.
2625 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2627 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
2628 (u8) rx_indir_table[i];
2630 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2631 sizeof(tablebuf), NULL, 0, NULL);
2635 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2637 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2638 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2639 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2640 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = key[i];
2642 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2643 sizeof(keybuf), NULL, 0, NULL);
2646 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2648 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2650 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2651 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2652 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2655 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2656 unsigned *context_size)
2658 u32 new_rx_rss_context;
2659 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2660 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2661 false, context_size);
2666 nic_data->rx_rss_context = new_rx_rss_context;
2667 nic_data->rx_rss_context_exclusive = false;
2668 efx_set_default_rx_indir_table(efx);
2672 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2673 const u32 *rx_indir_table,
2676 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2678 u32 new_rx_rss_context;
2680 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2681 !nic_data->rx_rss_context_exclusive) {
2682 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2684 if (rc == -EOPNOTSUPP)
2689 new_rx_rss_context = nic_data->rx_rss_context;
2692 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2693 rx_indir_table, key);
2697 if (nic_data->rx_rss_context != new_rx_rss_context)
2698 efx_ef10_rx_free_indir_table(efx);
2699 nic_data->rx_rss_context = new_rx_rss_context;
2700 nic_data->rx_rss_context_exclusive = true;
2701 if (rx_indir_table != efx->rx_indir_table)
2702 memcpy(efx->rx_indir_table, rx_indir_table,
2703 sizeof(efx->rx_indir_table));
2704 if (key != efx->rx_hash_key)
2705 memcpy(efx->rx_hash_key, key, efx->type->rx_hash_key_size);
2710 if (new_rx_rss_context != nic_data->rx_rss_context)
2711 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2713 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2717 static int efx_ef10_rx_pull_rss_config(struct efx_nic *efx)
2719 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2720 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN);
2721 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN);
2722 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN);
2726 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN !=
2727 MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN);
2729 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
2732 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID,
2733 nic_data->rx_rss_context);
2734 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2735 MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN);
2736 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_TABLE, inbuf, sizeof(inbuf),
2737 tablebuf, sizeof(tablebuf), &outlen);
2741 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN))
2744 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
2745 efx->rx_indir_table[i] = MCDI_PTR(tablebuf,
2746 RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE)[i];
2748 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID,
2749 nic_data->rx_rss_context);
2750 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2751 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2752 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_KEY, inbuf, sizeof(inbuf),
2753 keybuf, sizeof(keybuf), &outlen);
2757 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN))
2760 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2761 efx->rx_hash_key[i] = MCDI_PTR(
2762 keybuf, RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY)[i];
2767 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2768 const u32 *rx_indir_table,
2773 if (efx->rss_spread == 1)
2777 key = efx->rx_hash_key;
2779 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table, key);
2781 if (rc == -ENOBUFS && !user) {
2782 unsigned context_size;
2783 bool mismatch = false;
2786 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2788 mismatch = rx_indir_table[i] !=
2789 ethtool_rxfh_indir_default(i, efx->rss_spread);
2791 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2793 if (context_size != efx->rss_spread)
2794 netif_warn(efx, probe, efx->net_dev,
2795 "Could not allocate an exclusive RSS"
2796 " context; allocated a shared one of"
2798 " Wanted %u, got %u.\n",
2799 efx->rss_spread, context_size);
2801 netif_warn(efx, probe, efx->net_dev,
2802 "Could not allocate an exclusive RSS"
2803 " context; allocated a shared one but"
2804 " could not apply custom"
2807 netif_info(efx, probe, efx->net_dev,
2808 "Could not allocate an exclusive RSS"
2809 " context; allocated a shared one.\n");
2815 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2816 const u32 *rx_indir_table
2817 __attribute__ ((unused)),
2819 __attribute__ ((unused)))
2821 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2825 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2827 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2830 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2832 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2833 (rx_queue->ptr_mask + 1) *
2834 sizeof(efx_qword_t),
2838 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2840 MCDI_DECLARE_BUF(inbuf,
2841 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2843 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2844 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2845 struct efx_nic *efx = rx_queue->efx;
2846 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2848 dma_addr_t dma_addr;
2851 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2853 rx_queue->scatter_n = 0;
2854 rx_queue->scatter_len = 0;
2856 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2857 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2858 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2859 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2860 efx_rx_queue_index(rx_queue));
2861 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2862 INIT_RXQ_IN_FLAG_PREFIX, 1,
2863 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2864 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2865 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2867 dma_addr = rx_queue->rxd.buf.dma_addr;
2869 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2870 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2872 for (i = 0; i < entries; ++i) {
2873 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2874 dma_addr += EFX_BUF_SIZE;
2877 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2879 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2882 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2883 efx_rx_queue_index(rx_queue));
2886 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2888 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2889 MCDI_DECLARE_BUF_ERR(outbuf);
2890 struct efx_nic *efx = rx_queue->efx;
2894 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2895 efx_rx_queue_index(rx_queue));
2897 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2898 outbuf, sizeof(outbuf), &outlen);
2900 if (rc && rc != -EALREADY)
2906 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2907 outbuf, outlen, rc);
2910 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2912 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2915 /* This creates an entry in the RX descriptor queue */
2917 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2919 struct efx_rx_buffer *rx_buf;
2922 rxd = efx_rx_desc(rx_queue, index);
2923 rx_buf = efx_rx_buffer(rx_queue, index);
2924 EFX_POPULATE_QWORD_2(*rxd,
2925 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2926 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2929 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2931 struct efx_nic *efx = rx_queue->efx;
2932 unsigned int write_count;
2935 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2936 write_count = rx_queue->added_count & ~7;
2937 if (rx_queue->notified_count == write_count)
2941 efx_ef10_build_rx_desc(
2943 rx_queue->notified_count & rx_queue->ptr_mask);
2944 while (++rx_queue->notified_count != write_count);
2947 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2948 write_count & rx_queue->ptr_mask);
2949 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD,
2950 efx_rx_queue_index(rx_queue));
2953 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2955 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2957 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2958 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2961 EFX_POPULATE_QWORD_2(event,
2962 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2963 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2965 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2967 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2968 * already swapped the data to little-endian order.
2970 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2971 sizeof(efx_qword_t));
2973 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2974 inbuf, sizeof(inbuf), 0,
2975 efx_ef10_rx_defer_refill_complete, 0);
2979 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2980 int rc, efx_dword_t *outbuf,
2981 size_t outlen_actual)
2986 static int efx_ef10_ev_probe(struct efx_channel *channel)
2988 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2989 (channel->eventq_mask + 1) *
2990 sizeof(efx_qword_t),
2994 static void efx_ef10_ev_fini(struct efx_channel *channel)
2996 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2997 MCDI_DECLARE_BUF_ERR(outbuf);
2998 struct efx_nic *efx = channel->efx;
3002 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
3004 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
3005 outbuf, sizeof(outbuf), &outlen);
3007 if (rc && rc != -EALREADY)
3013 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
3014 outbuf, outlen, rc);
3017 static int efx_ef10_ev_init(struct efx_channel *channel)
3019 MCDI_DECLARE_BUF(inbuf,
3020 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
3022 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
3023 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
3024 struct efx_nic *efx = channel->efx;
3025 struct efx_ef10_nic_data *nic_data;
3026 size_t inlen, outlen;
3027 unsigned int enabled, implemented;
3028 dma_addr_t dma_addr;
3032 nic_data = efx->nic_data;
3034 /* Fill event queue with all ones (i.e. empty events) */
3035 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
3037 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
3038 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
3039 /* INIT_EVQ expects index in vector table, not absolute */
3040 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
3041 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
3042 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
3043 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
3044 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
3045 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
3046 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
3047 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
3049 if (nic_data->datapath_caps2 &
3050 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
3051 /* Use the new generic approach to specifying event queue
3052 * configuration, requesting lower latency or higher throughput.
3053 * The options that actually get used appear in the output.
3055 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
3056 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
3057 INIT_EVQ_V2_IN_FLAG_TYPE,
3058 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
3060 bool cut_thru = !(nic_data->datapath_caps &
3061 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
3063 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
3064 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
3065 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
3066 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
3067 INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
3070 dma_addr = channel->eventq.buf.dma_addr;
3071 for (i = 0; i < entries; ++i) {
3072 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
3073 dma_addr += EFX_BUF_SIZE;
3076 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
3078 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
3079 outbuf, sizeof(outbuf), &outlen);
3081 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
3082 netif_dbg(efx, drv, efx->net_dev,
3083 "Channel %d using event queue flags %08x\n",
3085 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
3087 /* IRQ return is ignored */
3088 if (channel->channel || rc)
3091 /* Successfully created event queue on channel 0 */
3092 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
3093 if (rc == -ENOSYS) {
3094 /* GET_WORKAROUNDS was implemented before this workaround,
3095 * thus it must be unavailable in this firmware.
3097 nic_data->workaround_26807 = false;
3102 nic_data->workaround_26807 =
3103 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
3105 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
3106 !nic_data->workaround_26807) {
3109 rc = efx_mcdi_set_workaround(efx,
3110 MC_CMD_WORKAROUND_BUG26807,
3115 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
3116 netif_info(efx, drv, efx->net_dev,
3117 "other functions on NIC have been reset\n");
3119 /* With MCFW v4.6.x and earlier, the
3120 * boot count will have incremented,
3121 * so re-read the warm_boot_count
3122 * value now to ensure this function
3123 * doesn't think it has changed next
3126 rc = efx_ef10_get_warm_boot_count(efx);
3128 nic_data->warm_boot_count = rc;
3132 nic_data->workaround_26807 = true;
3133 } else if (rc == -EPERM) {
3143 efx_ef10_ev_fini(channel);
3147 static void efx_ef10_ev_remove(struct efx_channel *channel)
3149 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3152 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3153 unsigned int rx_queue_label)
3155 struct efx_nic *efx = rx_queue->efx;
3157 netif_info(efx, hw, efx->net_dev,
3158 "rx event arrived on queue %d labeled as queue %u\n",
3159 efx_rx_queue_index(rx_queue), rx_queue_label);
3161 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3165 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3166 unsigned int actual, unsigned int expected)
3168 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3169 struct efx_nic *efx = rx_queue->efx;
3171 netif_info(efx, hw, efx->net_dev,
3172 "dropped %d events (index=%d expected=%d)\n",
3173 dropped, actual, expected);
3175 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3178 /* partially received RX was aborted. clean up. */
3179 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3181 unsigned int rx_desc_ptr;
3183 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3184 "scattered RX aborted (dropping %u buffers)\n",
3185 rx_queue->scatter_n);
3187 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3189 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3190 0, EFX_RX_PKT_DISCARD);
3192 rx_queue->removed_count += rx_queue->scatter_n;
3193 rx_queue->scatter_n = 0;
3194 rx_queue->scatter_len = 0;
3195 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3198 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
3199 unsigned int n_packets,
3200 unsigned int rx_encap_hdr,
3201 unsigned int rx_l3_class,
3202 unsigned int rx_l4_class,
3203 const efx_qword_t *event)
3205 struct efx_nic *efx = channel->efx;
3206 bool handled = false;
3208 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
3209 if (!(efx->net_dev->features & NETIF_F_RXALL)) {
3210 if (!efx->loopback_selftest)
3211 channel->n_rx_eth_crc_err += n_packets;
3212 return EFX_RX_PKT_DISCARD;
3216 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
3217 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3218 rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3219 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3220 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3221 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3222 netdev_WARN(efx->net_dev,
3223 "invalid class for RX_IPCKSUM_ERR: event="
3225 EFX_QWORD_VAL(*event));
3226 if (!efx->loopback_selftest)
3228 &channel->n_rx_outer_ip_hdr_chksum_err :
3229 &channel->n_rx_ip_hdr_chksum_err) += n_packets;
3232 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
3233 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3234 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3235 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3236 (rx_l4_class != ESE_DZ_L4_CLASS_TCP &&
3237 rx_l4_class != ESE_DZ_L4_CLASS_UDP))))
3238 netdev_WARN(efx->net_dev,
3239 "invalid class for RX_TCPUDP_CKSUM_ERR: event="
3241 EFX_QWORD_VAL(*event));
3242 if (!efx->loopback_selftest)
3244 &channel->n_rx_outer_tcp_udp_chksum_err :
3245 &channel->n_rx_tcp_udp_chksum_err) += n_packets;
3248 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
3249 if (unlikely(!rx_encap_hdr))
3250 netdev_WARN(efx->net_dev,
3251 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
3253 EFX_QWORD_VAL(*event));
3254 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3255 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3256 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3257 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3258 netdev_WARN(efx->net_dev,
3259 "invalid class for RX_IP_INNER_CHKSUM_ERR: event="
3261 EFX_QWORD_VAL(*event));
3262 if (!efx->loopback_selftest)
3263 channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
3266 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
3267 if (unlikely(!rx_encap_hdr))
3268 netdev_WARN(efx->net_dev,
3269 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3271 EFX_QWORD_VAL(*event));
3272 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3273 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3274 (rx_l4_class != ESE_DZ_L4_CLASS_TCP &&
3275 rx_l4_class != ESE_DZ_L4_CLASS_UDP)))
3276 netdev_WARN(efx->net_dev,
3277 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3279 EFX_QWORD_VAL(*event));
3280 if (!efx->loopback_selftest)
3281 channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
3285 WARN_ON(!handled); /* No error bits were recognised */
3289 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3290 const efx_qword_t *event)
3292 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
3293 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
3294 unsigned int n_descs, n_packets, i;
3295 struct efx_nic *efx = channel->efx;
3296 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3297 struct efx_rx_queue *rx_queue;
3302 if (unlikely(READ_ONCE(efx->reset_pending)))
3305 /* Basic packet information */
3306 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3307 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3308 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
3309 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
3310 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
3311 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
3313 nic_data->datapath_caps &
3314 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
3315 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
3316 ESE_EZ_ENCAP_HDR_NONE;
3318 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3319 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3321 EFX_QWORD_VAL(*event));
3323 rx_queue = efx_channel_get_rx_queue(channel);
3325 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3326 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3328 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3329 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3331 if (n_descs != rx_queue->scatter_n + 1) {
3332 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3334 /* detect rx abort */
3335 if (unlikely(n_descs == rx_queue->scatter_n)) {
3336 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3337 netdev_WARN(efx->net_dev,
3338 "invalid RX abort: scatter_n=%u event="
3340 rx_queue->scatter_n,
3341 EFX_QWORD_VAL(*event));
3342 efx_ef10_handle_rx_abort(rx_queue);
3346 /* Check that RX completion merging is valid, i.e.
3347 * the current firmware supports it and this is a
3348 * non-scattered packet.
3350 if (!(nic_data->datapath_caps &
3351 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3352 rx_queue->scatter_n != 0 || rx_cont) {
3353 efx_ef10_handle_rx_bad_lbits(
3354 rx_queue, next_ptr_lbits,
3355 (rx_queue->removed_count +
3356 rx_queue->scatter_n + 1) &
3357 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3361 /* Merged completion for multiple non-scattered packets */
3362 rx_queue->scatter_n = 1;
3363 rx_queue->scatter_len = 0;
3364 n_packets = n_descs;
3365 ++channel->n_rx_merge_events;
3366 channel->n_rx_merge_packets += n_packets;
3367 flags |= EFX_RX_PKT_PREFIX_LEN;
3369 ++rx_queue->scatter_n;
3370 rx_queue->scatter_len += rx_bytes;
3376 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
3377 ESF_DZ_RX_IPCKSUM_ERR, 1,
3378 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
3379 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
3380 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
3381 EFX_AND_QWORD(errors, *event, errors);
3382 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
3383 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
3385 rx_l3_class, rx_l4_class,
3388 bool tcpudp = rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
3389 rx_l4_class == ESE_DZ_L4_CLASS_UDP;
3391 switch (rx_encap_hdr) {
3392 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
3393 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */
3395 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */
3397 case ESE_EZ_ENCAP_HDR_GRE:
3398 case ESE_EZ_ENCAP_HDR_NONE:
3400 flags |= EFX_RX_PKT_CSUMMED;
3403 netdev_WARN(efx->net_dev,
3404 "unknown encapsulation type: event="
3406 EFX_QWORD_VAL(*event));
3410 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
3411 flags |= EFX_RX_PKT_TCP;
3413 channel->irq_mod_score += 2 * n_packets;
3415 /* Handle received packet(s) */
3416 for (i = 0; i < n_packets; i++) {
3417 efx_rx_packet(rx_queue,
3418 rx_queue->removed_count & rx_queue->ptr_mask,
3419 rx_queue->scatter_n, rx_queue->scatter_len,
3421 rx_queue->removed_count += rx_queue->scatter_n;
3424 rx_queue->scatter_n = 0;
3425 rx_queue->scatter_len = 0;
3431 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3433 struct efx_nic *efx = channel->efx;
3434 struct efx_tx_queue *tx_queue;
3435 unsigned int tx_ev_desc_ptr;
3436 unsigned int tx_ev_q_label;
3439 if (unlikely(READ_ONCE(efx->reset_pending)))
3442 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3445 /* Transmit completion */
3446 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3447 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3448 tx_queue = efx_channel_get_tx_queue(channel,
3449 tx_ev_q_label % EFX_TXQ_TYPES);
3450 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
3451 tx_queue->ptr_mask);
3452 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3458 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3460 struct efx_nic *efx = channel->efx;
3463 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3466 case ESE_DZ_DRV_TIMER_EV:
3467 case ESE_DZ_DRV_WAKE_UP_EV:
3469 case ESE_DZ_DRV_START_UP_EV:
3470 /* event queue init complete. ok. */
3473 netif_err(efx, hw, efx->net_dev,
3474 "channel %d unknown driver event type %d"
3475 " (data " EFX_QWORD_FMT ")\n",
3476 channel->channel, subcode,
3477 EFX_QWORD_VAL(*event));
3482 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3485 struct efx_nic *efx = channel->efx;
3488 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3492 channel->event_test_cpu = raw_smp_processor_id();
3494 case EFX_EF10_REFILL:
3495 /* The queue must be empty, so we won't receive any rx
3496 * events, so efx_process_channel() won't refill the
3497 * queue. Refill it here
3499 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
3502 netif_err(efx, hw, efx->net_dev,
3503 "channel %d unknown driver event type %u"
3504 " (data " EFX_QWORD_FMT ")\n",
3505 channel->channel, (unsigned) subcode,
3506 EFX_QWORD_VAL(*event));
3510 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3512 struct efx_nic *efx = channel->efx;
3513 efx_qword_t event, *p_event;
3514 unsigned int read_ptr;
3522 read_ptr = channel->eventq_read_ptr;
3525 p_event = efx_event(channel, read_ptr);
3528 if (!efx_event_present(&event))
3531 EFX_SET_QWORD(*p_event);
3535 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3537 netif_vdbg(efx, drv, efx->net_dev,
3538 "processing event on %d " EFX_QWORD_FMT "\n",
3539 channel->channel, EFX_QWORD_VAL(event));
3542 case ESE_DZ_EV_CODE_MCDI_EV:
3543 efx_mcdi_process_event(channel, &event);
3545 case ESE_DZ_EV_CODE_RX_EV:
3546 spent += efx_ef10_handle_rx_event(channel, &event);
3547 if (spent >= quota) {
3548 /* XXX can we split a merged event to
3549 * avoid going over-quota?
3555 case ESE_DZ_EV_CODE_TX_EV:
3556 tx_descs += efx_ef10_handle_tx_event(channel, &event);
3557 if (tx_descs > efx->txq_entries) {
3560 } else if (++spent == quota) {
3564 case ESE_DZ_EV_CODE_DRIVER_EV:
3565 efx_ef10_handle_driver_event(channel, &event);
3566 if (++spent == quota)
3569 case EFX_EF10_DRVGEN_EV:
3570 efx_ef10_handle_driver_generated_event(channel, &event);
3573 netif_err(efx, hw, efx->net_dev,
3574 "channel %d unknown event type %d"
3575 " (data " EFX_QWORD_FMT ")\n",
3576 channel->channel, ev_code,
3577 EFX_QWORD_VAL(event));
3582 channel->eventq_read_ptr = read_ptr;
3586 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3588 struct efx_nic *efx = channel->efx;
3591 if (EFX_EF10_WORKAROUND_35388(efx)) {
3592 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3593 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3594 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3595 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3597 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3598 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3599 ERF_DD_EVQ_IND_RPTR,
3600 (channel->eventq_read_ptr &
3601 channel->eventq_mask) >>
3602 ERF_DD_EVQ_IND_RPTR_WIDTH);
3603 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3605 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3606 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3607 ERF_DD_EVQ_IND_RPTR,
3608 channel->eventq_read_ptr &
3609 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3610 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3613 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3614 channel->eventq_read_ptr &
3615 channel->eventq_mask);
3616 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3620 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3622 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3623 struct efx_nic *efx = channel->efx;
3627 EFX_POPULATE_QWORD_2(event,
3628 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3629 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3631 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3633 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3634 * already swapped the data to little-endian order.
3636 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3637 sizeof(efx_qword_t));
3639 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3648 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3651 void efx_ef10_handle_drain_event(struct efx_nic *efx)
3653 if (atomic_dec_and_test(&efx->active_queues))
3654 wake_up(&efx->flush_wq);
3656 WARN_ON(atomic_read(&efx->active_queues) < 0);
3659 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3661 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3662 struct efx_channel *channel;
3663 struct efx_tx_queue *tx_queue;
3664 struct efx_rx_queue *rx_queue;
3667 /* If the MC has just rebooted, the TX/RX queues will have already been
3668 * torn down, but efx->active_queues needs to be set to zero.
3670 if (nic_data->must_realloc_vis) {
3671 atomic_set(&efx->active_queues, 0);
3675 /* Do not attempt to write to the NIC during EEH recovery */
3676 if (efx->state != STATE_RECOVERY) {
3677 efx_for_each_channel(channel, efx) {
3678 efx_for_each_channel_rx_queue(rx_queue, channel)
3679 efx_ef10_rx_fini(rx_queue);
3680 efx_for_each_channel_tx_queue(tx_queue, channel)
3681 efx_ef10_tx_fini(tx_queue);
3684 wait_event_timeout(efx->flush_wq,
3685 atomic_read(&efx->active_queues) == 0,
3686 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3687 pending = atomic_read(&efx->active_queues);
3689 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3698 static void efx_ef10_prepare_flr(struct efx_nic *efx)
3700 atomic_set(&efx->active_queues, 0);
3703 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3704 const struct efx_filter_spec *right)
3706 if ((left->match_flags ^ right->match_flags) |
3707 ((left->flags ^ right->flags) &
3708 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3711 return memcmp(&left->outer_vid, &right->outer_vid,
3712 sizeof(struct efx_filter_spec) -
3713 offsetof(struct efx_filter_spec, outer_vid)) == 0;
3716 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3718 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3719 return jhash2((const u32 *)&spec->outer_vid,
3720 (sizeof(struct efx_filter_spec) -
3721 offsetof(struct efx_filter_spec, outer_vid)) / 4,
3723 /* XXX should we randomise the initval? */
3726 /* Decide whether a filter should be exclusive or else should allow
3727 * delivery to additional recipients. Currently we decide that
3728 * filters for specific local unicast MAC and IP addresses are
3731 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3733 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3734 !is_multicast_ether_addr(spec->loc_mac))
3737 if ((spec->match_flags &
3738 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3739 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3740 if (spec->ether_type == htons(ETH_P_IP) &&
3741 !ipv4_is_multicast(spec->loc_host[0]))
3743 if (spec->ether_type == htons(ETH_P_IPV6) &&
3744 ((const u8 *)spec->loc_host)[0] != 0xff)
3751 static struct efx_filter_spec *
3752 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3753 unsigned int filter_idx)
3755 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3756 ~EFX_EF10_FILTER_FLAGS);
3760 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3761 unsigned int filter_idx)
3763 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3767 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3768 unsigned int filter_idx,
3769 const struct efx_filter_spec *spec,
3772 table->entry[filter_idx].spec = (unsigned long)spec | flags;
3776 efx_ef10_filter_push_prep_set_match_fields(struct efx_nic *efx,
3777 const struct efx_filter_spec *spec,
3780 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
3781 u32 match_fields = 0, uc_match, mc_match;
3783 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3784 efx_ef10_filter_is_exclusive(spec) ?
3785 MC_CMD_FILTER_OP_IN_OP_INSERT :
3786 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3788 /* Convert match flags and values. Unlike almost
3789 * everything else in MCDI, these fields are in
3790 * network byte order.
3792 #define COPY_VALUE(value, mcdi_field) \
3795 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3796 mcdi_field ## _LBN; \
3798 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3800 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3801 &value, sizeof(value)); \
3803 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3804 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3805 COPY_VALUE(spec->gen_field, mcdi_field); \
3807 /* Handle encap filters first. They will always be mismatch
3808 * (unknown UC or MC) filters
3811 /* ether_type and outer_ip_proto need to be variables
3812 * because COPY_VALUE wants to memcpy them
3815 htons(encap_type & EFX_ENCAP_FLAG_IPV6 ?
3816 ETH_P_IPV6 : ETH_P_IP);
3817 u8 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE;
3820 switch (encap_type & EFX_ENCAP_TYPES_MASK) {
3821 case EFX_ENCAP_TYPE_VXLAN:
3822 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN;
3824 case EFX_ENCAP_TYPE_GENEVE:
3825 COPY_VALUE(ether_type, ETHER_TYPE);
3826 outer_ip_proto = IPPROTO_UDP;
3827 COPY_VALUE(outer_ip_proto, IP_PROTO);
3828 /* We always need to set the type field, even
3829 * though we're not matching on the TNI.
3831 MCDI_POPULATE_DWORD_1(inbuf,
3832 FILTER_OP_EXT_IN_VNI_OR_VSID,
3833 FILTER_OP_EXT_IN_VNI_TYPE,
3836 case EFX_ENCAP_TYPE_NVGRE:
3837 COPY_VALUE(ether_type, ETHER_TYPE);
3838 outer_ip_proto = IPPROTO_GRE;
3839 COPY_VALUE(outer_ip_proto, IP_PROTO);
3845 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
3846 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
3848 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3849 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
3852 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3854 is_multicast_ether_addr(spec->loc_mac) ?
3857 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3858 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3859 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3860 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3861 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3862 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3863 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3864 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3865 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3866 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3869 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3873 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3874 const struct efx_filter_spec *spec,
3875 efx_dword_t *inbuf, u64 handle,
3878 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3879 u32 flags = spec->flags;
3881 memset(inbuf, 0, MC_CMD_FILTER_OP_EXT_IN_LEN);
3883 /* Remove RSS flag if we don't have an RSS context. */
3884 if (flags & EFX_FILTER_FLAG_RX_RSS &&
3885 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3886 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3887 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3890 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3891 MC_CMD_FILTER_OP_IN_OP_REPLACE);
3892 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3894 efx_ef10_filter_push_prep_set_match_fields(efx, spec, inbuf);
3897 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
3898 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3899 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3900 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3901 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
3902 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
3903 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3904 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
3905 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3906 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3908 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
3909 (flags & EFX_FILTER_FLAG_RX_RSS) ?
3910 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3911 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
3912 if (flags & EFX_FILTER_FLAG_RX_RSS)
3913 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3914 spec->rss_context !=
3915 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3916 spec->rss_context : nic_data->rx_rss_context);
3919 static int efx_ef10_filter_push(struct efx_nic *efx,
3920 const struct efx_filter_spec *spec,
3921 u64 *handle, bool replacing)
3923 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
3924 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_EXT_OUT_LEN);
3927 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3928 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3929 outbuf, sizeof(outbuf), NULL);
3931 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3933 rc = -EBUSY; /* to match efx_farch_filter_insert() */
3937 static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
3939 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
3940 unsigned int match_flags = spec->match_flags;
3941 unsigned int uc_match, mc_match;
3944 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field, encap) { \
3945 unsigned int old_match_flags = match_flags; \
3946 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
3947 if (match_flags != old_match_flags) \
3950 MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ ## \
3951 mcdi_field ## _LBN : \
3952 MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##\
3953 mcdi_field ## _LBN)); \
3955 /* inner or outer based on encap type */
3956 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP, encap_type);
3957 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP, encap_type);
3958 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC, encap_type);
3959 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT, encap_type);
3960 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC, encap_type);
3961 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT, encap_type);
3962 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE, encap_type);
3963 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO, encap_type);
3965 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN, false);
3966 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN, false);
3967 #undef MAP_FILTER_TO_MCDI_FLAG
3969 /* special handling for encap type, and mismatch */
3971 match_flags &= ~EFX_FILTER_MATCH_ENCAP_TYPE;
3973 (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
3974 mcdi_flags |= (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
3976 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
3977 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
3979 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3980 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
3983 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
3984 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
3986 is_multicast_ether_addr(spec->loc_mac) ?
3991 /* Did we map them all? */
3992 WARN_ON_ONCE(match_flags);
3997 static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
3998 const struct efx_filter_spec *spec)
4000 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
4001 unsigned int match_pri;
4004 match_pri < table->rx_match_count;
4006 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
4009 return -EPROTONOSUPPORT;
4012 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
4013 struct efx_filter_spec *spec,
4016 struct efx_ef10_filter_table *table = efx->filter_state;
4017 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4018 struct efx_filter_spec *saved_spec;
4019 unsigned int match_pri, hash;
4020 unsigned int priv_flags;
4021 bool replacing = false;
4027 /* For now, only support RX filters */
4028 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
4032 rc = efx_ef10_filter_pri(table, spec);
4037 hash = efx_ef10_filter_hash(spec);
4038 is_mc_recip = efx_filter_is_mc_recipient(spec);
4040 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4042 /* Find any existing filters with the same match tuple or
4043 * else a free slot to insert at. If any of them are busy,
4044 * we have to wait and retry.
4047 unsigned int depth = 1;
4050 spin_lock_bh(&efx->filter_lock);
4053 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4054 saved_spec = efx_ef10_filter_entry_spec(table, i);
4059 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4060 if (table->entry[i].spec &
4061 EFX_EF10_FILTER_FLAG_BUSY)
4063 if (spec->priority < saved_spec->priority &&
4064 spec->priority != EFX_FILTER_PRI_AUTO) {
4069 /* This is the only one */
4070 if (spec->priority ==
4071 saved_spec->priority &&
4078 } else if (spec->priority >
4079 saved_spec->priority ||
4081 saved_spec->priority &&
4086 __set_bit(depth, mc_rem_map);
4090 /* Once we reach the maximum search depth, use
4091 * the first suitable slot or return -EBUSY if
4094 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4095 if (ins_index < 0) {
4105 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4106 spin_unlock_bh(&efx->filter_lock);
4111 /* Create a software table entry if necessary, and mark it
4112 * busy. We might yet fail to insert, but any attempt to
4113 * insert a conflicting filter while we're waiting for the
4114 * firmware must find the busy entry.
4116 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4118 if (spec->priority == EFX_FILTER_PRI_AUTO &&
4119 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
4120 /* Just make sure it won't be removed */
4121 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
4122 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
4123 table->entry[ins_index].spec &=
4124 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4129 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
4131 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4136 *saved_spec = *spec;
4139 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4140 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
4142 /* Mark lower-priority multicast recipients busy prior to removal */
4144 unsigned int depth, i;
4146 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4147 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4148 if (test_bit(depth, mc_rem_map))
4149 table->entry[i].spec |=
4150 EFX_EF10_FILTER_FLAG_BUSY;
4154 spin_unlock_bh(&efx->filter_lock);
4156 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
4159 /* Finalise the software table entry */
4160 spin_lock_bh(&efx->filter_lock);
4163 /* Update the fields that may differ */
4164 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
4165 saved_spec->flags |=
4166 EFX_FILTER_FLAG_RX_OVER_AUTO;
4167 saved_spec->priority = spec->priority;
4168 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
4169 saved_spec->flags |= spec->flags;
4170 saved_spec->rss_context = spec->rss_context;
4171 saved_spec->dmaq_id = spec->dmaq_id;
4173 } else if (!replacing) {
4177 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4179 /* Remove and finalise entries for lower-priority multicast
4183 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4184 unsigned int depth, i;
4186 memset(inbuf, 0, sizeof(inbuf));
4188 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4189 if (!test_bit(depth, mc_rem_map))
4192 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4193 saved_spec = efx_ef10_filter_entry_spec(table, i);
4194 priv_flags = efx_ef10_filter_entry_flags(table, i);
4197 spin_unlock_bh(&efx->filter_lock);
4198 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4199 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4200 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4201 table->entry[i].handle);
4202 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
4203 inbuf, sizeof(inbuf),
4205 spin_lock_bh(&efx->filter_lock);
4213 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
4215 efx_ef10_filter_set_entry(table, i, saved_spec,
4220 /* If successful, return the inserted filter ID */
4222 rc = efx_ef10_make_filter_id(match_pri, ins_index);
4224 wake_up_all(&table->waitq);
4226 spin_unlock_bh(&efx->filter_lock);
4227 finish_wait(&table->waitq, &wait);
4231 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
4233 /* no need to do anything here on EF10 */
4237 * If !by_index, remove by ID
4238 * If by_index, remove by index
4239 * Filter ID may come from userland and must be range-checked.
4241 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
4242 unsigned int priority_mask,
4243 u32 filter_id, bool by_index)
4245 unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4246 struct efx_ef10_filter_table *table = efx->filter_state;
4247 MCDI_DECLARE_BUF(inbuf,
4248 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4249 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4250 struct efx_filter_spec *spec;
4254 /* Find the software table entry and mark it busy. Don't
4255 * remove it yet; any attempt to update while we're waiting
4256 * for the firmware must find the busy entry.
4259 spin_lock_bh(&efx->filter_lock);
4260 if (!(table->entry[filter_idx].spec &
4261 EFX_EF10_FILTER_FLAG_BUSY))
4263 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4264 spin_unlock_bh(&efx->filter_lock);
4268 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4271 efx_ef10_filter_pri(table, spec) !=
4272 efx_ef10_filter_get_unsafe_pri(filter_id))) {
4277 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
4278 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
4279 /* Just remove flags */
4280 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
4281 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4286 if (!(priority_mask & (1U << spec->priority))) {
4291 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4292 spin_unlock_bh(&efx->filter_lock);
4294 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
4295 /* Reset to an automatic filter */
4297 struct efx_filter_spec new_spec = *spec;
4299 new_spec.priority = EFX_FILTER_PRI_AUTO;
4300 new_spec.flags = (EFX_FILTER_FLAG_RX |
4301 (efx_rss_enabled(efx) ?
4302 EFX_FILTER_FLAG_RX_RSS : 0));
4303 new_spec.dmaq_id = 0;
4304 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
4305 rc = efx_ef10_filter_push(efx, &new_spec,
4306 &table->entry[filter_idx].handle,
4309 spin_lock_bh(&efx->filter_lock);
4313 /* Really remove the filter */
4315 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4316 efx_ef10_filter_is_exclusive(spec) ?
4317 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4318 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4319 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4320 table->entry[filter_idx].handle);
4321 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP,
4322 inbuf, sizeof(inbuf), NULL, 0, NULL);
4324 spin_lock_bh(&efx->filter_lock);
4325 if ((rc == 0) || (rc == -ENOENT)) {
4326 /* Filter removed OK or didn't actually exist */
4328 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4330 efx_mcdi_display_error(efx, MC_CMD_FILTER_OP,
4331 MC_CMD_FILTER_OP_EXT_IN_LEN,
4336 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4337 wake_up_all(&table->waitq);
4339 spin_unlock_bh(&efx->filter_lock);
4340 finish_wait(&table->waitq, &wait);
4344 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
4345 enum efx_filter_priority priority,
4348 return efx_ef10_filter_remove_internal(efx, 1U << priority,
4352 static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4353 enum efx_filter_priority priority,
4356 if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4358 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
4361 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4362 enum efx_filter_priority priority,
4363 u32 filter_id, struct efx_filter_spec *spec)
4365 unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4366 struct efx_ef10_filter_table *table = efx->filter_state;
4367 const struct efx_filter_spec *saved_spec;
4370 spin_lock_bh(&efx->filter_lock);
4371 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4372 if (saved_spec && saved_spec->priority == priority &&
4373 efx_ef10_filter_pri(table, saved_spec) ==
4374 efx_ef10_filter_get_unsafe_pri(filter_id)) {
4375 *spec = *saved_spec;
4380 spin_unlock_bh(&efx->filter_lock);
4384 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
4385 enum efx_filter_priority priority)
4387 unsigned int priority_mask;
4391 priority_mask = (((1U << (priority + 1)) - 1) &
4392 ~(1U << EFX_FILTER_PRI_AUTO));
4394 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4395 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4397 if (rc && rc != -ENOENT)
4404 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4405 enum efx_filter_priority priority)
4407 struct efx_ef10_filter_table *table = efx->filter_state;
4408 unsigned int filter_idx;
4411 spin_lock_bh(&efx->filter_lock);
4412 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4413 if (table->entry[filter_idx].spec &&
4414 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4418 spin_unlock_bh(&efx->filter_lock);
4422 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4424 struct efx_ef10_filter_table *table = efx->filter_state;
4426 return table->rx_match_count * HUNT_FILTER_TBL_ROWS * 2;
4429 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4430 enum efx_filter_priority priority,
4433 struct efx_ef10_filter_table *table = efx->filter_state;
4434 struct efx_filter_spec *spec;
4435 unsigned int filter_idx;
4438 spin_lock_bh(&efx->filter_lock);
4439 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4440 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4441 if (spec && spec->priority == priority) {
4442 if (count == size) {
4447 efx_ef10_make_filter_id(
4448 efx_ef10_filter_pri(table, spec),
4452 spin_unlock_bh(&efx->filter_lock);
4456 #ifdef CONFIG_RFS_ACCEL
4458 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
4460 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
4461 struct efx_filter_spec *spec)
4463 struct efx_ef10_filter_table *table = efx->filter_state;
4464 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4465 struct efx_filter_spec *saved_spec;
4466 unsigned int hash, i, depth = 1;
4467 bool replacing = false;
4472 /* Must be an RX filter without RSS and not for a multicast
4473 * destination address (RFS only works for connected sockets).
4474 * These restrictions allow us to pass only a tiny amount of
4475 * data through to the completion function.
4477 EFX_WARN_ON_PARANOID(spec->flags !=
4478 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
4479 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
4480 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
4482 hash = efx_ef10_filter_hash(spec);
4484 spin_lock_bh(&efx->filter_lock);
4486 /* Find any existing filter with the same match tuple or else
4487 * a free slot to insert at. If an existing filter is busy,
4488 * we have to give up.
4491 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4492 saved_spec = efx_ef10_filter_entry_spec(table, i);
4497 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4498 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
4502 if (spec->priority < saved_spec->priority) {
4510 /* Once we reach the maximum search depth, use the
4511 * first suitable slot or return -EBUSY if there was
4514 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4515 if (ins_index < 0) {
4525 /* Create a software table entry if necessary, and mark it
4526 * busy. We might yet fail to insert, but any attempt to
4527 * insert a conflicting filter while we're waiting for the
4528 * firmware must find the busy entry.
4530 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4534 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4539 *saved_spec = *spec;
4541 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4542 EFX_EF10_FILTER_FLAG_BUSY);
4544 spin_unlock_bh(&efx->filter_lock);
4546 /* Pack up the variables needed on completion */
4547 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
4549 efx_ef10_filter_push_prep(efx, spec, inbuf,
4550 table->entry[ins_index].handle, replacing);
4551 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4552 MC_CMD_FILTER_OP_OUT_LEN,
4553 efx_ef10_filter_rfs_insert_complete, cookie);
4558 spin_unlock_bh(&efx->filter_lock);
4563 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4564 int rc, efx_dword_t *outbuf,
4565 size_t outlen_actual)
4567 struct efx_ef10_filter_table *table = efx->filter_state;
4568 unsigned int ins_index, dmaq_id;
4569 struct efx_filter_spec *spec;
4572 /* Unpack the cookie */
4573 replacing = cookie >> 31;
4574 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4575 dmaq_id = cookie & 0xffff;
4577 spin_lock_bh(&efx->filter_lock);
4578 spec = efx_ef10_filter_entry_spec(table, ins_index);
4580 table->entry[ins_index].handle =
4581 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4583 spec->dmaq_id = dmaq_id;
4584 } else if (!replacing) {
4588 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4589 spin_unlock_bh(&efx->filter_lock);
4591 wake_up_all(&table->waitq);
4595 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4596 unsigned long filter_idx,
4597 int rc, efx_dword_t *outbuf,
4598 size_t outlen_actual);
4600 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4601 unsigned int filter_idx)
4603 struct efx_ef10_filter_table *table = efx->filter_state;
4604 struct efx_filter_spec *spec =
4605 efx_ef10_filter_entry_spec(table, filter_idx);
4606 MCDI_DECLARE_BUF(inbuf,
4607 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4608 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4611 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4612 spec->priority != EFX_FILTER_PRI_HINT ||
4613 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4614 flow_id, filter_idx))
4617 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4618 MC_CMD_FILTER_OP_IN_OP_REMOVE);
4619 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4620 table->entry[filter_idx].handle);
4621 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4622 efx_ef10_filter_rfs_expire_complete, filter_idx))
4625 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4630 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4631 unsigned long filter_idx,
4632 int rc, efx_dword_t *outbuf,
4633 size_t outlen_actual)
4635 struct efx_ef10_filter_table *table = efx->filter_state;
4636 struct efx_filter_spec *spec =
4637 efx_ef10_filter_entry_spec(table, filter_idx);
4639 spin_lock_bh(&efx->filter_lock);
4642 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4644 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4645 wake_up_all(&table->waitq);
4646 spin_unlock_bh(&efx->filter_lock);
4649 #endif /* CONFIG_RFS_ACCEL */
4651 static int efx_ef10_filter_match_flags_from_mcdi(bool encap, u32 mcdi_flags)
4653 int match_flags = 0;
4655 #define MAP_FLAG(gen_flag, mcdi_field) do { \
4656 u32 old_mcdi_flags = mcdi_flags; \
4657 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ ## \
4658 mcdi_field ## _LBN); \
4659 if (mcdi_flags != old_mcdi_flags) \
4660 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
4664 /* encap filters must specify encap type */
4665 match_flags |= EFX_FILTER_MATCH_ENCAP_TYPE;
4666 /* and imply ethertype and ip proto */
4668 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4670 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4671 /* VLAN tags refer to the outer packet */
4672 MAP_FLAG(INNER_VID, INNER_VLAN);
4673 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4674 /* everything else refers to the inner packet */
4675 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_UCAST_DST);
4676 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_MCAST_DST);
4677 MAP_FLAG(REM_HOST, IFRM_SRC_IP);
4678 MAP_FLAG(LOC_HOST, IFRM_DST_IP);
4679 MAP_FLAG(REM_MAC, IFRM_SRC_MAC);
4680 MAP_FLAG(REM_PORT, IFRM_SRC_PORT);
4681 MAP_FLAG(LOC_MAC, IFRM_DST_MAC);
4682 MAP_FLAG(LOC_PORT, IFRM_DST_PORT);
4683 MAP_FLAG(ETHER_TYPE, IFRM_ETHER_TYPE);
4684 MAP_FLAG(IP_PROTO, IFRM_IP_PROTO);
4686 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4687 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4688 MAP_FLAG(REM_HOST, SRC_IP);
4689 MAP_FLAG(LOC_HOST, DST_IP);
4690 MAP_FLAG(REM_MAC, SRC_MAC);
4691 MAP_FLAG(REM_PORT, SRC_PORT);
4692 MAP_FLAG(LOC_MAC, DST_MAC);
4693 MAP_FLAG(LOC_PORT, DST_PORT);
4694 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4695 MAP_FLAG(INNER_VID, INNER_VLAN);
4696 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4697 MAP_FLAG(IP_PROTO, IP_PROTO);
4701 /* Did we map them all? */
4708 static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4710 struct efx_ef10_filter_table *table = efx->filter_state;
4711 struct efx_ef10_filter_vlan *vlan, *next_vlan;
4713 /* See comment in efx_ef10_filter_table_remove() */
4714 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4720 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4721 efx_ef10_filter_del_vlan_internal(efx, vlan);
4724 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4726 enum efx_filter_match_flags match_flags)
4728 unsigned int match_pri;
4732 match_pri < table->rx_match_count;
4734 mf = efx_ef10_filter_match_flags_from_mcdi(encap,
4735 table->rx_match_mcdi_flags[match_pri]);
4736 if (mf == match_flags)
4744 efx_ef10_filter_table_probe_matches(struct efx_nic *efx,
4745 struct efx_ef10_filter_table *table,
4748 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4749 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4750 unsigned int pd_match_pri, pd_match_count;
4754 /* Find out which RX filter types are supported, and their priorities */
4755 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4757 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES :
4758 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4759 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4760 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4765 pd_match_count = MCDI_VAR_ARRAY_LEN(
4766 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4768 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4772 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4774 rc = efx_ef10_filter_match_flags_from_mcdi(encap, mcdi_flags);
4776 netif_dbg(efx, probe, efx->net_dev,
4777 "%s: fw flags %#x pri %u not supported in driver\n",
4778 __func__, mcdi_flags, pd_match_pri);
4780 netif_dbg(efx, probe, efx->net_dev,
4781 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4782 __func__, mcdi_flags, pd_match_pri,
4783 rc, table->rx_match_count);
4784 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4785 table->rx_match_count++;
4792 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4794 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4795 struct net_device *net_dev = efx->net_dev;
4796 struct efx_ef10_filter_table *table;
4797 struct efx_ef10_vlan *vlan;
4800 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4803 if (efx->filter_state) /* already probed */
4806 table = kzalloc(sizeof(*table), GFP_KERNEL);
4810 table->rx_match_count = 0;
4811 rc = efx_ef10_filter_table_probe_matches(efx, table, false);
4814 if (nic_data->datapath_caps &
4815 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
4816 rc = efx_ef10_filter_table_probe_matches(efx, table, true);
4819 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4820 !(efx_ef10_filter_match_supported(table, false,
4821 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4822 efx_ef10_filter_match_supported(table, false,
4823 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4824 netif_info(efx, probe, net_dev,
4825 "VLAN filters are not supported in this firmware variant\n");
4826 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4827 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4828 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4831 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4832 if (!table->entry) {
4837 table->mc_promisc_last = false;
4838 table->vlan_filter =
4839 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4840 INIT_LIST_HEAD(&table->vlan_list);
4842 efx->filter_state = table;
4843 init_waitqueue_head(&table->waitq);
4845 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4846 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4854 efx_ef10_filter_cleanup_vlans(efx);
4855 efx->filter_state = NULL;
4861 /* Caller must hold efx->filter_sem for read if race against
4862 * efx_ef10_filter_table_remove() is possible
4864 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4866 struct efx_ef10_filter_table *table = efx->filter_state;
4867 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4868 unsigned int invalid_filters = 0, failed = 0;
4869 struct efx_ef10_filter_vlan *vlan;
4870 struct efx_filter_spec *spec;
4871 unsigned int filter_idx;
4876 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4878 if (!nic_data->must_restore_filters)
4884 spin_lock_bh(&efx->filter_lock);
4886 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4887 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4891 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
4893 while (match_pri < table->rx_match_count &&
4894 table->rx_match_mcdi_flags[match_pri] != mcdi_flags)
4896 if (match_pri >= table->rx_match_count) {
4900 if (spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT &&
4901 spec->rss_context != nic_data->rx_rss_context)
4902 netif_warn(efx, drv, efx->net_dev,
4903 "Warning: unable to restore a filter with specific RSS context.\n");
4905 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4906 spin_unlock_bh(&efx->filter_lock);
4908 rc = efx_ef10_filter_push(efx, spec,
4909 &table->entry[filter_idx].handle,
4913 spin_lock_bh(&efx->filter_lock);
4917 list_for_each_entry(vlan, &table->vlan_list, list)
4918 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; ++i)
4919 if (vlan->default_filters[i] == filter_idx)
4920 vlan->default_filters[i] =
4921 EFX_EF10_FILTER_ID_INVALID;
4924 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4926 table->entry[filter_idx].spec &=
4927 ~EFX_EF10_FILTER_FLAG_BUSY;
4931 spin_unlock_bh(&efx->filter_lock);
4933 /* This can happen validly if the MC's capabilities have changed, so
4936 if (invalid_filters)
4937 netif_dbg(efx, drv, efx->net_dev,
4938 "Did not restore %u filters that are now unsupported.\n",
4942 netif_err(efx, hw, efx->net_dev,
4943 "unable to restore %u filters\n", failed);
4945 nic_data->must_restore_filters = false;
4948 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4950 struct efx_ef10_filter_table *table = efx->filter_state;
4951 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4952 struct efx_filter_spec *spec;
4953 unsigned int filter_idx;
4956 efx_ef10_filter_cleanup_vlans(efx);
4957 efx->filter_state = NULL;
4958 /* If we were called without locking, then it's not safe to free
4959 * the table as others might be using it. So we just WARN, leak
4960 * the memory, and potentially get an inconsistent filter table
4962 * This should never actually happen.
4964 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4970 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4971 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4975 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4976 efx_ef10_filter_is_exclusive(spec) ?
4977 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4978 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4979 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4980 table->entry[filter_idx].handle);
4981 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
4982 sizeof(inbuf), NULL, 0, NULL);
4984 netif_info(efx, drv, efx->net_dev,
4985 "%s: filter %04x remove failed\n",
4986 __func__, filter_idx);
4990 vfree(table->entry);
4994 static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
4996 struct efx_ef10_filter_table *table = efx->filter_state;
4997 unsigned int filter_idx;
4999 if (*id != EFX_EF10_FILTER_ID_INVALID) {
5000 filter_idx = efx_ef10_filter_get_unsafe_id(*id);
5001 if (!table->entry[filter_idx].spec)
5002 netif_dbg(efx, drv, efx->net_dev,
5003 "marked null spec old %04x:%04x\n", *id,
5005 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
5006 *id = EFX_EF10_FILTER_ID_INVALID;
5010 /* Mark old per-VLAN filters that may need to be removed */
5011 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
5012 struct efx_ef10_filter_vlan *vlan)
5014 struct efx_ef10_filter_table *table = efx->filter_state;
5017 for (i = 0; i < table->dev_uc_count; i++)
5018 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
5019 for (i = 0; i < table->dev_mc_count; i++)
5020 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
5021 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5022 efx_ef10_filter_mark_one_old(efx, &vlan->default_filters[i]);
5025 /* Mark old filters that may need to be removed.
5026 * Caller must hold efx->filter_sem for read if race against
5027 * efx_ef10_filter_table_remove() is possible
5029 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
5031 struct efx_ef10_filter_table *table = efx->filter_state;
5032 struct efx_ef10_filter_vlan *vlan;
5034 spin_lock_bh(&efx->filter_lock);
5035 list_for_each_entry(vlan, &table->vlan_list, list)
5036 _efx_ef10_filter_vlan_mark_old(efx, vlan);
5037 spin_unlock_bh(&efx->filter_lock);
5040 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
5042 struct efx_ef10_filter_table *table = efx->filter_state;
5043 struct net_device *net_dev = efx->net_dev;
5044 struct netdev_hw_addr *uc;
5047 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
5048 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
5050 netdev_for_each_uc_addr(uc, net_dev) {
5051 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
5052 table->uc_promisc = true;
5055 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
5059 table->dev_uc_count = i;
5062 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
5064 struct efx_ef10_filter_table *table = efx->filter_state;
5065 struct net_device *net_dev = efx->net_dev;
5066 struct netdev_hw_addr *mc;
5069 table->mc_overflow = false;
5070 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
5073 netdev_for_each_mc_addr(mc, net_dev) {
5074 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
5075 table->mc_promisc = true;
5076 table->mc_overflow = true;
5079 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
5083 table->dev_mc_count = i;
5086 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
5087 struct efx_ef10_filter_vlan *vlan,
5088 bool multicast, bool rollback)
5090 struct efx_ef10_filter_table *table = efx->filter_state;
5091 struct efx_ef10_dev_addr *addr_list;
5092 enum efx_filter_flags filter_flags;
5093 struct efx_filter_spec spec;
5101 addr_list = table->dev_mc_list;
5102 addr_count = table->dev_mc_count;
5105 addr_list = table->dev_uc_list;
5106 addr_count = table->dev_uc_count;
5110 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5112 /* Insert/renew filters */
5113 for (i = 0; i < addr_count; i++) {
5114 EFX_WARN_ON_PARANOID(ids[i] != EFX_EF10_FILTER_ID_INVALID);
5115 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5116 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
5117 rc = efx_ef10_filter_insert(efx, &spec, true);
5120 netif_info(efx, drv, efx->net_dev,
5121 "efx_ef10_filter_insert failed rc=%d\n",
5123 /* Fall back to promiscuous */
5124 for (j = 0; j < i; j++) {
5125 efx_ef10_filter_remove_unsafe(
5126 efx, EFX_FILTER_PRI_AUTO,
5128 ids[j] = EFX_EF10_FILTER_ID_INVALID;
5132 /* keep invalid ID, and carry on */
5135 ids[i] = efx_ef10_filter_get_unsafe_id(rc);
5139 if (multicast && rollback) {
5140 /* Also need an Ethernet broadcast filter */
5141 EFX_WARN_ON_PARANOID(vlan->default_filters[EFX_EF10_BCAST] !=
5142 EFX_EF10_FILTER_ID_INVALID);
5143 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5144 eth_broadcast_addr(baddr);
5145 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5146 rc = efx_ef10_filter_insert(efx, &spec, true);
5148 netif_warn(efx, drv, efx->net_dev,
5149 "Broadcast filter insert failed rc=%d\n", rc);
5150 /* Fall back to promiscuous */
5151 for (j = 0; j < i; j++) {
5152 efx_ef10_filter_remove_unsafe(
5153 efx, EFX_FILTER_PRI_AUTO,
5155 ids[j] = EFX_EF10_FILTER_ID_INVALID;
5159 vlan->default_filters[EFX_EF10_BCAST] =
5160 efx_ef10_filter_get_unsafe_id(rc);
5167 static int efx_ef10_filter_insert_def(struct efx_nic *efx,
5168 struct efx_ef10_filter_vlan *vlan,
5169 enum efx_encap_type encap_type,
5170 bool multicast, bool rollback)
5172 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5173 enum efx_filter_flags filter_flags;
5174 struct efx_filter_spec spec;
5179 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5181 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5184 efx_filter_set_mc_def(&spec);
5186 efx_filter_set_uc_def(&spec);
5189 if (nic_data->datapath_caps &
5190 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
5191 efx_filter_set_encap_type(&spec, encap_type);
5193 /* don't insert encap filters on non-supporting
5194 * platforms. ID will be left as INVALID.
5199 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
5200 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
5202 rc = efx_ef10_filter_insert(efx, &spec, true);
5204 const char *um = multicast ? "Multicast" : "Unicast";
5205 const char *encap_name = "";
5206 const char *encap_ipv = "";
5208 if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5209 EFX_ENCAP_TYPE_VXLAN)
5210 encap_name = "VXLAN ";
5211 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5212 EFX_ENCAP_TYPE_NVGRE)
5213 encap_name = "NVGRE ";
5214 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5215 EFX_ENCAP_TYPE_GENEVE)
5216 encap_name = "GENEVE ";
5217 if (encap_type & EFX_ENCAP_FLAG_IPV6)
5218 encap_ipv = "IPv6 ";
5219 else if (encap_type)
5220 encap_ipv = "IPv4 ";
5222 /* unprivileged functions can't insert mismatch filters
5223 * for encapsulated or unicast traffic, so downgrade
5224 * those warnings to debug.
5226 netif_cond_dbg(efx, drv, efx->net_dev,
5227 rc == -EPERM && (encap_type || !multicast), warn,
5228 "%s%s%s mismatch filter insert failed rc=%d\n",
5229 encap_name, encap_ipv, um, rc);
5230 } else if (multicast) {
5231 /* mapping from encap types to default filter IDs (multicast) */
5232 static enum efx_ef10_default_filters map[] = {
5233 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_MCDEF,
5234 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_MCDEF,
5235 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_MCDEF,
5236 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_MCDEF,
5237 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5238 EFX_EF10_VXLAN6_MCDEF,
5239 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5240 EFX_EF10_NVGRE6_MCDEF,
5241 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5242 EFX_EF10_GENEVE6_MCDEF,
5245 /* quick bounds check (BCAST result impossible) */
5246 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5247 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5251 /* then follow map */
5252 id = &vlan->default_filters[map[encap_type]];
5254 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5255 *id = efx_ef10_filter_get_unsafe_id(rc);
5256 if (!nic_data->workaround_26807 && !encap_type) {
5257 /* Also need an Ethernet broadcast filter */
5258 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
5260 eth_broadcast_addr(baddr);
5261 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5262 rc = efx_ef10_filter_insert(efx, &spec, true);
5264 netif_warn(efx, drv, efx->net_dev,
5265 "Broadcast filter insert failed rc=%d\n",
5268 /* Roll back the mc_def filter */
5269 efx_ef10_filter_remove_unsafe(
5270 efx, EFX_FILTER_PRI_AUTO,
5272 *id = EFX_EF10_FILTER_ID_INVALID;
5276 EFX_WARN_ON_PARANOID(
5277 vlan->default_filters[EFX_EF10_BCAST] !=
5278 EFX_EF10_FILTER_ID_INVALID);
5279 vlan->default_filters[EFX_EF10_BCAST] =
5280 efx_ef10_filter_get_unsafe_id(rc);
5285 /* mapping from encap types to default filter IDs (unicast) */
5286 static enum efx_ef10_default_filters map[] = {
5287 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_UCDEF,
5288 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_UCDEF,
5289 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_UCDEF,
5290 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_UCDEF,
5291 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5292 EFX_EF10_VXLAN6_UCDEF,
5293 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5294 EFX_EF10_NVGRE6_UCDEF,
5295 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5296 EFX_EF10_GENEVE6_UCDEF,
5299 /* quick bounds check (BCAST result impossible) */
5300 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5301 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5305 /* then follow map */
5306 id = &vlan->default_filters[map[encap_type]];
5307 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5314 /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
5315 * flag or removes these filters, we don't need to hold the filter_lock while
5316 * scanning for these filters.
5318 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
5320 struct efx_ef10_filter_table *table = efx->filter_state;
5321 int remove_failed = 0;
5322 int remove_noent = 0;
5326 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
5327 if (READ_ONCE(table->entry[i].spec) &
5328 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
5329 rc = efx_ef10_filter_remove_internal(efx,
5330 1U << EFX_FILTER_PRI_AUTO, i, true);
5339 netif_info(efx, drv, efx->net_dev,
5340 "%s: failed to remove %d filters\n",
5341 __func__, remove_failed);
5343 netif_info(efx, drv, efx->net_dev,
5344 "%s: failed to remove %d non-existent filters\n",
5345 __func__, remove_noent);
5348 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
5350 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5351 u8 mac_old[ETH_ALEN];
5354 /* Only reconfigure a PF-created vport */
5355 if (is_zero_ether_addr(nic_data->vport_mac))
5358 efx_device_detach_sync(efx);
5359 efx_net_stop(efx->net_dev);
5360 down_write(&efx->filter_sem);
5361 efx_ef10_filter_table_remove(efx);
5362 up_write(&efx->filter_sem);
5364 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
5366 goto restore_filters;
5368 ether_addr_copy(mac_old, nic_data->vport_mac);
5369 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
5370 nic_data->vport_mac);
5372 goto restore_vadaptor;
5374 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
5375 efx->net_dev->dev_addr);
5377 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
5379 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
5381 /* Failed to add original MAC, so clear vport_mac */
5382 eth_zero_addr(nic_data->vport_mac);
5388 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
5392 down_write(&efx->filter_sem);
5393 rc2 = efx_ef10_filter_table_probe(efx);
5394 up_write(&efx->filter_sem);
5398 rc2 = efx_net_open(efx->net_dev);
5402 efx_device_attach_if_not_resetting(efx);
5407 netif_err(efx, drv, efx->net_dev,
5408 "Failed to restore when changing MAC address - scheduling reset\n");
5409 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
5411 return rc ? rc : rc2;
5414 /* Caller must hold efx->filter_sem for read if race against
5415 * efx_ef10_filter_table_remove() is possible
5417 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
5418 struct efx_ef10_filter_vlan *vlan)
5420 struct efx_ef10_filter_table *table = efx->filter_state;
5421 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5423 /* Do not install unspecified VID if VLAN filtering is enabled.
5424 * Do not install all specified VIDs if VLAN filtering is disabled.
5426 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
5429 /* Insert/renew unicast filters */
5430 if (table->uc_promisc) {
5431 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NONE,
5433 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
5435 /* If any of the filters failed to insert, fall back to
5436 * promiscuous mode - add in the uc_def filter. But keep
5437 * our individual unicast filters.
5439 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
5440 efx_ef10_filter_insert_def(efx, vlan,
5441 EFX_ENCAP_TYPE_NONE,
5444 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5446 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5447 EFX_ENCAP_FLAG_IPV6,
5449 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5451 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5452 EFX_ENCAP_FLAG_IPV6,
5454 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5456 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5457 EFX_ENCAP_FLAG_IPV6,
5460 /* Insert/renew multicast filters */
5461 /* If changing promiscuous state with cascaded multicast filters, remove
5462 * old filters first, so that packets are dropped rather than duplicated
5464 if (nic_data->workaround_26807 &&
5465 table->mc_promisc_last != table->mc_promisc)
5466 efx_ef10_filter_remove_old(efx);
5467 if (table->mc_promisc) {
5468 if (nic_data->workaround_26807) {
5469 /* If we failed to insert promiscuous filters, rollback
5470 * and fall back to individual multicast filters
5472 if (efx_ef10_filter_insert_def(efx, vlan,
5473 EFX_ENCAP_TYPE_NONE,
5475 /* Changing promisc state, so remove old filters */
5476 efx_ef10_filter_remove_old(efx);
5477 efx_ef10_filter_insert_addr_list(efx, vlan,
5481 /* If we failed to insert promiscuous filters, don't
5482 * rollback. Regardless, also insert the mc_list,
5483 * unless it's incomplete due to overflow
5485 efx_ef10_filter_insert_def(efx, vlan,
5486 EFX_ENCAP_TYPE_NONE,
5488 if (!table->mc_overflow)
5489 efx_ef10_filter_insert_addr_list(efx, vlan,
5493 /* If any filters failed to insert, rollback and fall back to
5494 * promiscuous mode - mc_def filter and maybe broadcast. If
5495 * that fails, roll back again and insert as many of our
5496 * individual multicast filters as we can.
5498 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
5499 /* Changing promisc state, so remove old filters */
5500 if (nic_data->workaround_26807)
5501 efx_ef10_filter_remove_old(efx);
5502 if (efx_ef10_filter_insert_def(efx, vlan,
5503 EFX_ENCAP_TYPE_NONE,
5505 efx_ef10_filter_insert_addr_list(efx, vlan,
5509 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5511 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5512 EFX_ENCAP_FLAG_IPV6,
5514 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5516 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5517 EFX_ENCAP_FLAG_IPV6,
5519 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5521 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5522 EFX_ENCAP_FLAG_IPV6,
5526 /* Caller must hold efx->filter_sem for read if race against
5527 * efx_ef10_filter_table_remove() is possible
5529 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
5531 struct efx_ef10_filter_table *table = efx->filter_state;
5532 struct net_device *net_dev = efx->net_dev;
5533 struct efx_ef10_filter_vlan *vlan;
5536 if (!efx_dev_registered(efx))
5542 efx_ef10_filter_mark_old(efx);
5544 /* Copy/convert the address lists; add the primary station
5545 * address and broadcast address
5547 netif_addr_lock_bh(net_dev);
5548 efx_ef10_filter_uc_addr_list(efx);
5549 efx_ef10_filter_mc_addr_list(efx);
5550 netif_addr_unlock_bh(net_dev);
5552 /* If VLAN filtering changes, all old filters are finally removed.
5553 * Do it in advance to avoid conflicts for unicast untagged and
5554 * VLAN 0 tagged filters.
5556 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5557 if (table->vlan_filter != vlan_filter) {
5558 table->vlan_filter = vlan_filter;
5559 efx_ef10_filter_remove_old(efx);
5562 list_for_each_entry(vlan, &table->vlan_list, list)
5563 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5565 efx_ef10_filter_remove_old(efx);
5566 table->mc_promisc_last = table->mc_promisc;
5569 static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5571 struct efx_ef10_filter_table *table = efx->filter_state;
5572 struct efx_ef10_filter_vlan *vlan;
5574 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5576 list_for_each_entry(vlan, &table->vlan_list, list) {
5577 if (vlan->vid == vid)
5584 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5586 struct efx_ef10_filter_table *table = efx->filter_state;
5587 struct efx_ef10_filter_vlan *vlan;
5590 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5593 vlan = efx_ef10_filter_find_vlan(efx, vid);
5594 if (WARN_ON(vlan)) {
5595 netif_err(efx, drv, efx->net_dev,
5596 "VLAN %u already added\n", vid);
5600 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5606 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5607 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5608 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5609 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
5610 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5611 vlan->default_filters[i] = EFX_EF10_FILTER_ID_INVALID;
5613 list_add_tail(&vlan->list, &table->vlan_list);
5615 if (efx_dev_registered(efx))
5616 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5621 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5622 struct efx_ef10_filter_vlan *vlan)
5626 /* See comment in efx_ef10_filter_table_remove() */
5627 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5630 list_del(&vlan->list);
5632 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5633 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5635 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5636 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5638 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5639 if (vlan->default_filters[i] != EFX_EF10_FILTER_ID_INVALID)
5640 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5641 vlan->default_filters[i]);
5646 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5648 struct efx_ef10_filter_vlan *vlan;
5650 /* See comment in efx_ef10_filter_table_remove() */
5651 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5654 vlan = efx_ef10_filter_find_vlan(efx, vid);
5656 netif_err(efx, drv, efx->net_dev,
5657 "VLAN %u not found in filter state\n", vid);
5661 efx_ef10_filter_del_vlan_internal(efx, vlan);
5664 static int efx_ef10_set_mac_address(struct efx_nic *efx)
5666 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5667 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5668 bool was_enabled = efx->port_enabled;
5671 efx_device_detach_sync(efx);
5672 efx_net_stop(efx->net_dev);
5674 mutex_lock(&efx->mac_lock);
5675 down_write(&efx->filter_sem);
5676 efx_ef10_filter_table_remove(efx);
5678 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5679 efx->net_dev->dev_addr);
5680 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5681 nic_data->vport_id);
5682 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5683 sizeof(inbuf), NULL, 0, NULL);
5685 efx_ef10_filter_table_probe(efx);
5686 up_write(&efx->filter_sem);
5687 mutex_unlock(&efx->mac_lock);
5690 efx_net_open(efx->net_dev);
5691 efx_device_attach_if_not_resetting(efx);
5693 #ifdef CONFIG_SFC_SRIOV
5694 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
5695 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5698 struct efx_nic *efx_pf;
5700 /* Switch to PF and change MAC address on vport */
5701 efx_pf = pci_get_drvdata(pci_dev_pf);
5703 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5705 efx->net_dev->dev_addr);
5707 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5708 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5711 /* MAC address successfully changed by VF (with MAC
5712 * spoofing) so update the parent PF if possible.
5714 for (i = 0; i < efx_pf->vf_count; ++i) {
5715 struct ef10_vf *vf = nic_data->vf + i;
5717 if (vf->efx == efx) {
5718 ether_addr_copy(vf->mac,
5719 efx->net_dev->dev_addr);
5727 netif_err(efx, drv, efx->net_dev,
5728 "Cannot change MAC address; use sfboot to enable"
5729 " mac-spoofing on this interface\n");
5730 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5731 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5732 * fall-back to the method of changing the MAC address on the
5733 * vport. This only applies to PFs because such versions of
5734 * MCFW do not support VFs.
5736 rc = efx_ef10_vport_set_mac_address(efx);
5738 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5739 sizeof(inbuf), NULL, 0, rc);
5745 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5747 efx_ef10_filter_sync_rx_mode(efx);
5749 return efx_mcdi_set_mac(efx);
5752 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5754 efx_ef10_filter_sync_rx_mode(efx);
5759 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5761 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5763 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5764 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5768 /* MC BISTs follow a different poll mechanism to phy BISTs.
5769 * The BIST is done in the poll handler on the MC, and the MCDI command
5770 * will block until the BIST is done.
5772 static int efx_ef10_poll_bist(struct efx_nic *efx)
5775 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5779 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5780 outbuf, sizeof(outbuf), &outlen);
5784 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5787 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5789 case MC_CMD_POLL_BIST_PASSED:
5790 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5792 case MC_CMD_POLL_BIST_TIMEOUT:
5793 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5795 case MC_CMD_POLL_BIST_FAILED:
5796 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5799 netif_err(efx, hw, efx->net_dev,
5800 "BIST returned unknown result %u", result);
5805 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5809 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5811 rc = efx_ef10_start_bist(efx, bist_type);
5815 return efx_ef10_poll_bist(efx);
5819 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5823 efx_reset_down(efx, RESET_TYPE_WORLD);
5825 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5826 NULL, 0, NULL, 0, NULL);
5830 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5831 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5833 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5838 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5839 return rc ? rc : rc2;
5842 #ifdef CONFIG_SFC_MTD
5844 struct efx_ef10_nvram_type_info {
5845 u16 type, type_mask;
5850 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5851 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
5852 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
5853 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
5854 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
5855 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
5856 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
5857 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
5858 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
5859 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
5860 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
5861 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
5864 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5865 struct efx_mcdi_mtd_partition *part,
5868 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5869 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5870 const struct efx_ef10_nvram_type_info *info;
5871 size_t size, erase_size, outlen;
5875 for (info = efx_ef10_nvram_types; ; info++) {
5877 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
5879 if ((type & ~info->type_mask) == info->type)
5882 if (info->port != efx_port_num(efx))
5885 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5889 return -ENODEV; /* hide it */
5891 part->nvram_type = type;
5893 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5894 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5895 outbuf, sizeof(outbuf), &outlen);
5898 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5900 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5901 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5902 part->fw_subtype = MCDI_DWORD(outbuf,
5903 NVRAM_METADATA_OUT_SUBTYPE);
5905 part->common.dev_type_name = "EF10 NVRAM manager";
5906 part->common.type_name = info->name;
5908 part->common.mtd.type = MTD_NORFLASH;
5909 part->common.mtd.flags = MTD_CAP_NORFLASH;
5910 part->common.mtd.size = size;
5911 part->common.mtd.erasesize = erase_size;
5916 static int efx_ef10_mtd_probe(struct efx_nic *efx)
5918 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5919 struct efx_mcdi_mtd_partition *parts;
5920 size_t outlen, n_parts_total, i, n_parts;
5926 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5927 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5928 outbuf, sizeof(outbuf), &outlen);
5931 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5934 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5936 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5939 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5944 for (i = 0; i < n_parts_total; i++) {
5945 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5947 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
5950 else if (rc != -ENODEV)
5954 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
5961 #endif /* CONFIG_SFC_MTD */
5963 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
5965 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
5968 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
5971 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
5974 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
5977 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
5978 channel->sync_events_state == SYNC_EVENTS_VALID ||
5979 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
5981 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
5983 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
5984 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5985 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
5988 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5989 inbuf, sizeof(inbuf), NULL, 0, NULL);
5992 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5993 SYNC_EVENTS_DISABLED;
5998 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
6001 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
6004 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
6005 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
6007 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
6008 channel->sync_events_state = SYNC_EVENTS_DISABLED;
6011 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6012 SYNC_EVENTS_DISABLED;
6014 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
6015 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6016 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
6017 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
6018 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
6021 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6022 inbuf, sizeof(inbuf), NULL, 0, NULL);
6027 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
6030 int (*set)(struct efx_channel *channel, bool temp);
6031 struct efx_channel *channel;
6034 efx_ef10_rx_enable_timestamping :
6035 efx_ef10_rx_disable_timestamping;
6037 efx_for_each_channel(channel, efx) {
6038 int rc = set(channel, temp);
6039 if (en && rc != 0) {
6040 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
6048 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
6049 struct hwtstamp_config *init)
6054 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
6055 struct hwtstamp_config *init)
6059 switch (init->rx_filter) {
6060 case HWTSTAMP_FILTER_NONE:
6061 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
6062 /* if TX timestamping is still requested then leave PTP on */
6063 return efx_ptp_change_mode(efx,
6064 init->tx_type != HWTSTAMP_TX_OFF, 0);
6065 case HWTSTAMP_FILTER_ALL:
6066 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6067 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
6068 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
6069 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6070 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6071 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6072 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6073 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6074 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6075 case HWTSTAMP_FILTER_PTP_V2_EVENT:
6076 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6077 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6078 case HWTSTAMP_FILTER_NTP_ALL:
6079 init->rx_filter = HWTSTAMP_FILTER_ALL;
6080 rc = efx_ptp_change_mode(efx, true, 0);
6082 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
6084 efx_ptp_change_mode(efx, false, 0);
6091 static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
6092 struct netdev_phys_item_id *ppid)
6094 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6096 if (!is_valid_ether_addr(nic_data->port_id))
6099 ppid->id_len = ETH_ALEN;
6100 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
6105 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6107 if (proto != htons(ETH_P_8021Q))
6110 return efx_ef10_add_vlan(efx, vid);
6113 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6115 if (proto != htons(ETH_P_8021Q))
6118 return efx_ef10_del_vlan(efx, vid);
6121 /* We rely on the MCDI wiping out our TX rings if it made any changes to the
6122 * ports table, ensuring that any TSO descriptors that were made on a now-
6123 * removed tunnel port will be blown away and won't break things when we try
6124 * to transmit them using the new ports table.
6126 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
6128 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6129 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX);
6130 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN);
6131 bool will_reset = false;
6132 size_t num_entries = 0;
6133 size_t inlen, outlen;
6136 efx_dword_t flags_and_num_entries;
6138 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock));
6140 nic_data->udp_tunnels_dirty = false;
6142 if (!(nic_data->datapath_caps &
6143 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) {
6144 efx_device_attach_if_not_resetting(efx);
6148 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) >
6149 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
6151 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6152 if (nic_data->udp_tunnels[i].count &&
6153 nic_data->udp_tunnels[i].port) {
6156 EFX_POPULATE_DWORD_2(entry,
6157 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT,
6158 ntohs(nic_data->udp_tunnels[i].port),
6159 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL,
6160 nic_data->udp_tunnels[i].type);
6161 *_MCDI_ARRAY_DWORD(inbuf,
6162 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES,
6163 num_entries++) = entry;
6167 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST -
6168 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 !=
6170 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 !=
6172 EFX_POPULATE_DWORD_2(flags_and_num_entries,
6173 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING,
6175 EFX_WORD_1, num_entries);
6176 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) =
6177 flags_and_num_entries;
6179 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries);
6181 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS,
6182 inbuf, inlen, outbuf, sizeof(outbuf), &outlen);
6184 /* Most likely the MC rebooted due to another function also
6185 * setting its tunnel port list. Mark the tunnel port list as
6186 * dirty, so it will be pushed upon coming up from the reboot.
6188 nic_data->udp_tunnels_dirty = true;
6193 /* expected not available on unprivileged functions */
6195 netif_warn(efx, drv, efx->net_dev,
6196 "Unable to set UDP tunnel ports; rc=%d.\n", rc);
6197 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) &
6198 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) {
6199 netif_info(efx, drv, efx->net_dev,
6200 "Rebooting MC due to UDP tunnel port list change\n");
6203 /* Delay for the MC reset to complete. This will make
6204 * unloading other functions a bit smoother. This is a
6205 * race, but the other unload will work whichever way
6206 * it goes, this just avoids an unnecessary error
6211 if (!will_reset && !unloading) {
6212 /* The caller will have detached, relying on the MC reset to
6213 * trigger a re-attach. Since there won't be an MC reset, we
6214 * have to do the attach ourselves.
6216 efx_device_attach_if_not_resetting(efx);
6222 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx)
6224 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6227 mutex_lock(&nic_data->udp_tunnels_lock);
6228 if (nic_data->udp_tunnels_dirty) {
6229 /* Make sure all TX are stopped while we modify the table, else
6230 * we might race against an efx_features_check().
6232 efx_device_detach_sync(efx);
6233 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6235 mutex_unlock(&nic_data->udp_tunnels_lock);
6239 static struct efx_udp_tunnel *__efx_ef10_udp_tnl_lookup_port(struct efx_nic *efx,
6242 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6245 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6246 if (!nic_data->udp_tunnels[i].count)
6248 if (nic_data->udp_tunnels[i].port == port)
6249 return &nic_data->udp_tunnels[i];
6254 static int efx_ef10_udp_tnl_add_port(struct efx_nic *efx,
6255 struct efx_udp_tunnel tnl)
6257 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6258 struct efx_udp_tunnel *match;
6263 if (!(nic_data->datapath_caps &
6264 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6267 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6268 netif_dbg(efx, drv, efx->net_dev, "Adding UDP tunnel (%s) port %d\n",
6269 typebuf, ntohs(tnl.port));
6271 mutex_lock(&nic_data->udp_tunnels_lock);
6272 /* Make sure all TX are stopped while we add to the table, else we
6273 * might race against an efx_features_check().
6275 efx_device_detach_sync(efx);
6277 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6278 if (match != NULL) {
6279 if (match->type == tnl.type) {
6280 netif_dbg(efx, drv, efx->net_dev,
6281 "Referencing existing tunnel entry\n");
6283 /* No need to cause an MCDI update */
6287 efx_get_udp_tunnel_type_name(match->type,
6288 typebuf, sizeof(typebuf));
6289 netif_dbg(efx, drv, efx->net_dev,
6290 "UDP port %d is already in use by %s\n",
6291 ntohs(tnl.port), typebuf);
6296 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
6297 if (!nic_data->udp_tunnels[i].count) {
6298 nic_data->udp_tunnels[i] = tnl;
6299 nic_data->udp_tunnels[i].count = 1;
6300 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6304 netif_dbg(efx, drv, efx->net_dev,
6305 "Unable to add UDP tunnel (%s) port %d; insufficient resources.\n",
6306 typebuf, ntohs(tnl.port));
6311 mutex_unlock(&nic_data->udp_tunnels_lock);
6315 /* Called under the TX lock with the TX queue running, hence no-one can be
6316 * in the middle of updating the UDP tunnels table. However, they could
6317 * have tried and failed the MCDI, in which case they'll have set the dirty
6318 * flag before dropping their locks.
6320 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port)
6322 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6324 if (!(nic_data->datapath_caps &
6325 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6328 if (nic_data->udp_tunnels_dirty)
6329 /* SW table may not match HW state, so just assume we can't
6330 * use any UDP tunnel offloads.
6334 return __efx_ef10_udp_tnl_lookup_port(efx, port) != NULL;
6337 static int efx_ef10_udp_tnl_del_port(struct efx_nic *efx,
6338 struct efx_udp_tunnel tnl)
6340 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6341 struct efx_udp_tunnel *match;
6345 if (!(nic_data->datapath_caps &
6346 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6349 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6350 netif_dbg(efx, drv, efx->net_dev, "Removing UDP tunnel (%s) port %d\n",
6351 typebuf, ntohs(tnl.port));
6353 mutex_lock(&nic_data->udp_tunnels_lock);
6354 /* Make sure all TX are stopped while we remove from the table, else we
6355 * might race against an efx_features_check().
6357 efx_device_detach_sync(efx);
6359 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6360 if (match != NULL) {
6361 if (match->type == tnl.type) {
6362 if (--match->count) {
6363 /* Port is still in use, so nothing to do */
6364 netif_dbg(efx, drv, efx->net_dev,
6365 "UDP tunnel port %d remains active\n",
6370 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6373 efx_get_udp_tunnel_type_name(match->type,
6374 typebuf, sizeof(typebuf));
6375 netif_warn(efx, drv, efx->net_dev,
6376 "UDP port %d is actually in use by %s, not removing\n",
6377 ntohs(tnl.port), typebuf);
6382 mutex_unlock(&nic_data->udp_tunnels_lock);
6386 #define EF10_OFFLOAD_FEATURES \
6387 (NETIF_F_IP_CSUM | \
6388 NETIF_F_HW_VLAN_CTAG_FILTER | \
6389 NETIF_F_IPV6_CSUM | \
6393 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6395 .mem_bar = EFX_MEM_VF_BAR,
6396 .mem_map_size = efx_ef10_mem_map_size,
6397 .probe = efx_ef10_probe_vf,
6398 .remove = efx_ef10_remove,
6399 .dimension_resources = efx_ef10_dimension_resources,
6400 .init = efx_ef10_init_nic,
6401 .fini = efx_port_dummy_op_void,
6402 .map_reset_reason = efx_ef10_map_reset_reason,
6403 .map_reset_flags = efx_ef10_map_reset_flags,
6404 .reset = efx_ef10_reset,
6405 .probe_port = efx_mcdi_port_probe,
6406 .remove_port = efx_mcdi_port_remove,
6407 .fini_dmaq = efx_ef10_fini_dmaq,
6408 .prepare_flr = efx_ef10_prepare_flr,
6409 .finish_flr = efx_port_dummy_op_void,
6410 .describe_stats = efx_ef10_describe_stats,
6411 .update_stats = efx_ef10_update_stats_vf,
6412 .start_stats = efx_port_dummy_op_void,
6413 .pull_stats = efx_port_dummy_op_void,
6414 .stop_stats = efx_port_dummy_op_void,
6415 .set_id_led = efx_mcdi_set_id_led,
6416 .push_irq_moderation = efx_ef10_push_irq_moderation,
6417 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
6418 .check_mac_fault = efx_mcdi_mac_check_fault,
6419 .reconfigure_port = efx_mcdi_port_reconfigure,
6420 .get_wol = efx_ef10_get_wol_vf,
6421 .set_wol = efx_ef10_set_wol_vf,
6422 .resume_wol = efx_port_dummy_op_void,
6423 .mcdi_request = efx_ef10_mcdi_request,
6424 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6425 .mcdi_read_response = efx_ef10_mcdi_read_response,
6426 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6427 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6428 .irq_enable_master = efx_port_dummy_op_void,
6429 .irq_test_generate = efx_ef10_irq_test_generate,
6430 .irq_disable_non_ev = efx_port_dummy_op_void,
6431 .irq_handle_msi = efx_ef10_msi_interrupt,
6432 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6433 .tx_probe = efx_ef10_tx_probe,
6434 .tx_init = efx_ef10_tx_init,
6435 .tx_remove = efx_ef10_tx_remove,
6436 .tx_write = efx_ef10_tx_write,
6437 .tx_limit_len = efx_ef10_tx_limit_len,
6438 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
6439 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6440 .rx_probe = efx_ef10_rx_probe,
6441 .rx_init = efx_ef10_rx_init,
6442 .rx_remove = efx_ef10_rx_remove,
6443 .rx_write = efx_ef10_rx_write,
6444 .rx_defer_refill = efx_ef10_rx_defer_refill,
6445 .ev_probe = efx_ef10_ev_probe,
6446 .ev_init = efx_ef10_ev_init,
6447 .ev_fini = efx_ef10_ev_fini,
6448 .ev_remove = efx_ef10_ev_remove,
6449 .ev_process = efx_ef10_ev_process,
6450 .ev_read_ack = efx_ef10_ev_read_ack,
6451 .ev_test_generate = efx_ef10_ev_test_generate,
6452 .filter_table_probe = efx_ef10_filter_table_probe,
6453 .filter_table_restore = efx_ef10_filter_table_restore,
6454 .filter_table_remove = efx_ef10_filter_table_remove,
6455 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6456 .filter_insert = efx_ef10_filter_insert,
6457 .filter_remove_safe = efx_ef10_filter_remove_safe,
6458 .filter_get_safe = efx_ef10_filter_get_safe,
6459 .filter_clear_rx = efx_ef10_filter_clear_rx,
6460 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6461 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6462 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6463 #ifdef CONFIG_RFS_ACCEL
6464 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6465 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6467 #ifdef CONFIG_SFC_MTD
6468 .mtd_probe = efx_port_dummy_op_int,
6470 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
6471 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
6472 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6473 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6474 #ifdef CONFIG_SFC_SRIOV
6475 .vswitching_probe = efx_ef10_vswitching_probe_vf,
6476 .vswitching_restore = efx_ef10_vswitching_restore_vf,
6477 .vswitching_remove = efx_ef10_vswitching_remove_vf,
6479 .get_mac_address = efx_ef10_get_mac_address_vf,
6480 .set_mac_address = efx_ef10_set_mac_address,
6482 .get_phys_port_id = efx_ef10_get_phys_port_id,
6483 .revision = EFX_REV_HUNT_A0,
6484 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6485 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6486 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6487 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6488 .can_rx_scatter = true,
6489 .always_rx_scatter = true,
6490 .min_interrupt_mode = EFX_INT_MODE_MSIX,
6491 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6492 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6493 .offload_features = EF10_OFFLOAD_FEATURES,
6495 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6496 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6497 1 << HWTSTAMP_FILTER_ALL,
6498 .rx_hash_key_size = 40,
6501 const struct efx_nic_type efx_hunt_a0_nic_type = {
6503 .mem_bar = EFX_MEM_BAR,
6504 .mem_map_size = efx_ef10_mem_map_size,
6505 .probe = efx_ef10_probe_pf,
6506 .remove = efx_ef10_remove,
6507 .dimension_resources = efx_ef10_dimension_resources,
6508 .init = efx_ef10_init_nic,
6509 .fini = efx_port_dummy_op_void,
6510 .map_reset_reason = efx_ef10_map_reset_reason,
6511 .map_reset_flags = efx_ef10_map_reset_flags,
6512 .reset = efx_ef10_reset,
6513 .probe_port = efx_mcdi_port_probe,
6514 .remove_port = efx_mcdi_port_remove,
6515 .fini_dmaq = efx_ef10_fini_dmaq,
6516 .prepare_flr = efx_ef10_prepare_flr,
6517 .finish_flr = efx_port_dummy_op_void,
6518 .describe_stats = efx_ef10_describe_stats,
6519 .update_stats = efx_ef10_update_stats_pf,
6520 .start_stats = efx_mcdi_mac_start_stats,
6521 .pull_stats = efx_mcdi_mac_pull_stats,
6522 .stop_stats = efx_mcdi_mac_stop_stats,
6523 .set_id_led = efx_mcdi_set_id_led,
6524 .push_irq_moderation = efx_ef10_push_irq_moderation,
6525 .reconfigure_mac = efx_ef10_mac_reconfigure,
6526 .check_mac_fault = efx_mcdi_mac_check_fault,
6527 .reconfigure_port = efx_mcdi_port_reconfigure,
6528 .get_wol = efx_ef10_get_wol,
6529 .set_wol = efx_ef10_set_wol,
6530 .resume_wol = efx_port_dummy_op_void,
6531 .test_chip = efx_ef10_test_chip,
6532 .test_nvram = efx_mcdi_nvram_test_all,
6533 .mcdi_request = efx_ef10_mcdi_request,
6534 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6535 .mcdi_read_response = efx_ef10_mcdi_read_response,
6536 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6537 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6538 .irq_enable_master = efx_port_dummy_op_void,
6539 .irq_test_generate = efx_ef10_irq_test_generate,
6540 .irq_disable_non_ev = efx_port_dummy_op_void,
6541 .irq_handle_msi = efx_ef10_msi_interrupt,
6542 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6543 .tx_probe = efx_ef10_tx_probe,
6544 .tx_init = efx_ef10_tx_init,
6545 .tx_remove = efx_ef10_tx_remove,
6546 .tx_write = efx_ef10_tx_write,
6547 .tx_limit_len = efx_ef10_tx_limit_len,
6548 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
6549 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6550 .rx_probe = efx_ef10_rx_probe,
6551 .rx_init = efx_ef10_rx_init,
6552 .rx_remove = efx_ef10_rx_remove,
6553 .rx_write = efx_ef10_rx_write,
6554 .rx_defer_refill = efx_ef10_rx_defer_refill,
6555 .ev_probe = efx_ef10_ev_probe,
6556 .ev_init = efx_ef10_ev_init,
6557 .ev_fini = efx_ef10_ev_fini,
6558 .ev_remove = efx_ef10_ev_remove,
6559 .ev_process = efx_ef10_ev_process,
6560 .ev_read_ack = efx_ef10_ev_read_ack,
6561 .ev_test_generate = efx_ef10_ev_test_generate,
6562 .filter_table_probe = efx_ef10_filter_table_probe,
6563 .filter_table_restore = efx_ef10_filter_table_restore,
6564 .filter_table_remove = efx_ef10_filter_table_remove,
6565 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6566 .filter_insert = efx_ef10_filter_insert,
6567 .filter_remove_safe = efx_ef10_filter_remove_safe,
6568 .filter_get_safe = efx_ef10_filter_get_safe,
6569 .filter_clear_rx = efx_ef10_filter_clear_rx,
6570 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6571 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6572 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6573 #ifdef CONFIG_RFS_ACCEL
6574 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6575 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6577 #ifdef CONFIG_SFC_MTD
6578 .mtd_probe = efx_ef10_mtd_probe,
6579 .mtd_rename = efx_mcdi_mtd_rename,
6580 .mtd_read = efx_mcdi_mtd_read,
6581 .mtd_erase = efx_mcdi_mtd_erase,
6582 .mtd_write = efx_mcdi_mtd_write,
6583 .mtd_sync = efx_mcdi_mtd_sync,
6585 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
6586 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
6587 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
6588 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6589 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6590 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports,
6591 .udp_tnl_add_port = efx_ef10_udp_tnl_add_port,
6592 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port,
6593 .udp_tnl_del_port = efx_ef10_udp_tnl_del_port,
6594 #ifdef CONFIG_SFC_SRIOV
6595 .sriov_configure = efx_ef10_sriov_configure,
6596 .sriov_init = efx_ef10_sriov_init,
6597 .sriov_fini = efx_ef10_sriov_fini,
6598 .sriov_wanted = efx_ef10_sriov_wanted,
6599 .sriov_reset = efx_ef10_sriov_reset,
6600 .sriov_flr = efx_ef10_sriov_flr,
6601 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
6602 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
6603 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
6604 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
6605 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
6606 .vswitching_probe = efx_ef10_vswitching_probe_pf,
6607 .vswitching_restore = efx_ef10_vswitching_restore_pf,
6608 .vswitching_remove = efx_ef10_vswitching_remove_pf,
6610 .get_mac_address = efx_ef10_get_mac_address_pf,
6611 .set_mac_address = efx_ef10_set_mac_address,
6612 .tso_versions = efx_ef10_tso_versions,
6614 .get_phys_port_id = efx_ef10_get_phys_port_id,
6615 .revision = EFX_REV_HUNT_A0,
6616 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6617 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6618 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6619 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6620 .can_rx_scatter = true,
6621 .always_rx_scatter = true,
6622 .option_descriptors = true,
6623 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
6624 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6625 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6626 .offload_features = EF10_OFFLOAD_FEATURES,
6628 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6629 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6630 1 << HWTSTAMP_FILTER_ALL,
6631 .rx_hash_key_size = 40,