drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include <linux/slab.h>
   9 #include <net/ip.h>
  10 #include <linux/bitops.h>
  11
  12 #include "qlcnic.h"
  13 #include "qlcnic_hdr.h"
  14
  15 #define MASK(n) ((1ULL<<(n))-1)
  16 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  17
  18 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  19
  20 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  21 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  22 #define CRB_WINDOW_2M   (0x130060)
  23 #define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  24 #define CRB_INDIRECT_2M (0x1e0000UL)
  25
  26 struct qlcnic_ms_reg_ctrl {
  27         u32 ocm_window;
  28         u32 control;
  29         u32 hi;
  30         u32 low;
  31         u32 rd[4];
  32         u32 wd[4];
  33         u64 off;
  34 };
  35
  36 #ifndef readq
  37 static inline u64 readq(void __iomem *addr)
  38 {
  39         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  40 }
  41 #endif
  42
  43 #ifndef writeq
  44 static inline void writeq(u64 val, void __iomem *addr)
  45 {
  46         writel(((u32) (val)), (addr));
  47         writel(((u32) (val >> 32)), (addr + 4));
  48 }
  49 #endif
  50
  51 static struct crb_128M_2M_block_map
  52 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  53     {{{0, 0,         0,         0} } },         /* 0: PCI */
  54     {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
  55           {1, 0x0110000, 0x0120000, 0x130000},
  56           {1, 0x0120000, 0x0122000, 0x124000},
  57           {1, 0x0130000, 0x0132000, 0x126000},
  58           {1, 0x0140000, 0x0142000, 0x128000},
  59           {1, 0x0150000, 0x0152000, 0x12a000},
  60           {1, 0x0160000, 0x0170000, 0x110000},
  61           {1, 0x0170000, 0x0172000, 0x12e000},
  62           {0, 0x0000000, 0x0000000, 0x000000},
  63           {0, 0x0000000, 0x0000000, 0x000000},
  64           {0, 0x0000000, 0x0000000, 0x000000},
  65           {0, 0x0000000, 0x0000000, 0x000000},
  66           {0, 0x0000000, 0x0000000, 0x000000},
  67           {0, 0x0000000, 0x0000000, 0x000000},
  68           {1, 0x01e0000, 0x01e0800, 0x122000},
  69           {0, 0x0000000, 0x0000000, 0x000000} } },
  70         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  71     {{{0, 0,         0,         0} } },     /* 3: */
  72     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  73     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
  74     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
  75     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
  76     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
  77       {0, 0x0000000, 0x0000000, 0x000000},
  78       {0, 0x0000000, 0x0000000, 0x000000},
  79       {0, 0x0000000, 0x0000000, 0x000000},
  80       {0, 0x0000000, 0x0000000, 0x000000},
  81       {0, 0x0000000, 0x0000000, 0x000000},
  82       {0, 0x0000000, 0x0000000, 0x000000},
  83       {0, 0x0000000, 0x0000000, 0x000000},
  84       {0, 0x0000000, 0x0000000, 0x000000},
  85       {0, 0x0000000, 0x0000000, 0x000000},
  86       {0, 0x0000000, 0x0000000, 0x000000},
  87       {0, 0x0000000, 0x0000000, 0x000000},
  88       {0, 0x0000000, 0x0000000, 0x000000},
  89       {0, 0x0000000, 0x0000000, 0x000000},
  90       {0, 0x0000000, 0x0000000, 0x000000},
  91       {1, 0x08f0000, 0x08f2000, 0x172000} } },
  92     {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
  93       {0, 0x0000000, 0x0000000, 0x000000},
  94       {0, 0x0000000, 0x0000000, 0x000000},
  95       {0, 0x0000000, 0x0000000, 0x000000},
  96       {0, 0x0000000, 0x0000000, 0x000000},
  97       {0, 0x0000000, 0x0000000, 0x000000},
  98       {0, 0x0000000, 0x0000000, 0x000000},
  99       {0, 0x0000000, 0x0000000, 0x000000},
 100       {0, 0x0000000, 0x0000000, 0x000000},
 101       {0, 0x0000000, 0x0000000, 0x000000},
 102       {0, 0x0000000, 0x0000000, 0x000000},
 103       {0, 0x0000000, 0x0000000, 0x000000},
 104       {0, 0x0000000, 0x0000000, 0x000000},
 105       {0, 0x0000000, 0x0000000, 0x000000},
 106       {0, 0x0000000, 0x0000000, 0x000000},
 107       {1, 0x09f0000, 0x09f2000, 0x176000} } },
 108     {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
 109       {0, 0x0000000, 0x0000000, 0x000000},
 110       {0, 0x0000000, 0x0000000, 0x000000},
 111       {0, 0x0000000, 0x0000000, 0x000000},
 112       {0, 0x0000000, 0x0000000, 0x000000},
 113       {0, 0x0000000, 0x0000000, 0x000000},
 114       {0, 0x0000000, 0x0000000, 0x000000},
 115       {0, 0x0000000, 0x0000000, 0x000000},
 116       {0, 0x0000000, 0x0000000, 0x000000},
 117       {0, 0x0000000, 0x0000000, 0x000000},
 118       {0, 0x0000000, 0x0000000, 0x000000},
 119       {0, 0x0000000, 0x0000000, 0x000000},
 120       {0, 0x0000000, 0x0000000, 0x000000},
 121       {0, 0x0000000, 0x0000000, 0x000000},
 122       {0, 0x0000000, 0x0000000, 0x000000},
 123       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 124     {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
 125       {0, 0x0000000, 0x0000000, 0x000000},
 126       {0, 0x0000000, 0x0000000, 0x000000},
 127       {0, 0x0000000, 0x0000000, 0x000000},
 128       {0, 0x0000000, 0x0000000, 0x000000},
 129       {0, 0x0000000, 0x0000000, 0x000000},
 130       {0, 0x0000000, 0x0000000, 0x000000},
 131       {0, 0x0000000, 0x0000000, 0x000000},
 132       {0, 0x0000000, 0x0000000, 0x000000},
 133       {0, 0x0000000, 0x0000000, 0x000000},
 134       {0, 0x0000000, 0x0000000, 0x000000},
 135       {0, 0x0000000, 0x0000000, 0x000000},
 136       {0, 0x0000000, 0x0000000, 0x000000},
 137       {0, 0x0000000, 0x0000000, 0x000000},
 138       {0, 0x0000000, 0x0000000, 0x000000},
 139       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 140         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 141         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 142         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 143         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 144         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 145         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 146         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 147         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 148         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 149         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 150         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 151         {{{0, 0,         0,         0} } },     /* 23: */
 152         {{{0, 0,         0,         0} } },     /* 24: */
 153         {{{0, 0,         0,         0} } },     /* 25: */
 154         {{{0, 0,         0,         0} } },     /* 26: */
 155         {{{0, 0,         0,         0} } },     /* 27: */
 156         {{{0, 0,         0,         0} } },     /* 28: */
 157         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 158     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 159     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 160         {{{0} } },                              /* 32: PCI */
 161         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 162           {1, 0x2110000, 0x2120000, 0x130000},
 163           {1, 0x2120000, 0x2122000, 0x124000},
 164           {1, 0x2130000, 0x2132000, 0x126000},
 165           {1, 0x2140000, 0x2142000, 0x128000},
 166           {1, 0x2150000, 0x2152000, 0x12a000},
 167           {1, 0x2160000, 0x2170000, 0x110000},
 168           {1, 0x2170000, 0x2172000, 0x12e000},
 169           {0, 0x0000000, 0x0000000, 0x000000},
 170           {0, 0x0000000, 0x0000000, 0x000000},
 171           {0, 0x0000000, 0x0000000, 0x000000},
 172           {0, 0x0000000, 0x0000000, 0x000000},
 173           {0, 0x0000000, 0x0000000, 0x000000},
 174           {0, 0x0000000, 0x0000000, 0x000000},
 175           {0, 0x0000000, 0x0000000, 0x000000},
 176           {0, 0x0000000, 0x0000000, 0x000000} } },
 177         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 178         {{{0} } },                              /* 35: */
 179         {{{0} } },                              /* 36: */
 180         {{{0} } },                              /* 37: */
 181         {{{0} } },                              /* 38: */
 182         {{{0} } },                              /* 39: */
 183         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 184         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 185         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 186         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 187         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 188         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 189         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 190         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 191         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 192         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 193         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 194         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 195         {{{0} } },                              /* 52: */
 196         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 197         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 198         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 199         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 200         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 201         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 202         {{{0} } },                              /* 59: I2C0 */
 203         {{{0} } },                              /* 60: I2C1 */
 204         {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
 205         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 206         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 207 };
 208
 209 /*
 210  * top 12 bits of crb internal address (hub, agent)
 211  */
 212 static const unsigned crb_hub_agt[64] = {
 213         0,
 214         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 215         QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
 216         QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
 217         0,
 218         QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
 219         QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
 220         QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
 221         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
 222         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
 223         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
 224         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
 225         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 226         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 227         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 228         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
 229         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 230         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
 231         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
 232         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
 233         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
 234         QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
 235         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
 236         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
 237         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
 238         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
 239         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
 240         0,
 241         QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
 242         QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
 243         0,
 244         QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
 245         0,
 246         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 247         QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
 248         0,
 249         0,
 250         0,
 251         0,
 252         0,
 253         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 254         0,
 255         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
 256         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
 257         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
 258         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
 259         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
 260         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
 261         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
 262         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 263         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 264         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 265         0,
 266         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
 267         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
 268         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
 269         QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
 270         0,
 271         QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
 272         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
 273         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
 274         0,
 275         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
 276         0,
 277 };
 278
 279 /*  PCI Windowing for DDR regions.  */
 280
 281 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
 282
 283 static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data)
 284 {
 285         u32 dest;
 286         void __iomem *val;
 287
 288         dest = addr & 0xFFFF0000;
 289         val = bar0 + QLCNIC_FW_DUMP_REG1;
 290         writel(dest, val);
 291         readl(val);
 292         val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
 293         *data = readl(val);
 294 }
 295
 296 static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data)
 297 {
 298         u32 dest;
 299         void __iomem *val;
 300
 301         dest = addr & 0xFFFF0000;
 302         val = bar0 + QLCNIC_FW_DUMP_REG1;
 303         writel(dest, val);
 304         readl(val);
 305         val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
 306         writel(data, val);
 307         readl(val);
 308 }
 309
 310 int
 311 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
 312 {
 313         int timeout = 0, err = 0, done = 0;
 314
 315         while (!done) {
 316                 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)),
 317                                &err);
 318                 if (done == 1)
 319                         break;
 320                 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
 321                         if (id_reg) {
 322                                 done = QLCRD32(adapter, id_reg, &err);
 323                                 if (done != -1)
 324                                         dev_err(&adapter->pdev->dev,
 325                                                 "Failed to acquire sem=%d lock held by=%d\n",
 326                                                 sem, done);
 327                                 else
 328                                         dev_err(&adapter->pdev->dev,
 329                                                 "Failed to acquire sem=%d lock",
 330                                                 sem);
 331                         } else {
 332                                 dev_err(&adapter->pdev->dev,
 333                                         "Failed to acquire sem=%d lock", sem);
 334                         }
 335                         return -EIO;
 336                 }
 337                 udelay(1200);
 338         }
 339
 340         if (id_reg)
 341                 QLCWR32(adapter, id_reg, adapter->portnum);
 342
 343         return 0;
 344 }
 345
 346 void
 347 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
 348 {
 349         int err = 0;
 350
 351         QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)), &err);
 352 }
 353
 354 int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr)
 355 {
 356         int err = 0;
 357         u32 data;
 358
 359         if (qlcnic_82xx_check(adapter))
 360                 qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data);
 361         else {
 362                 data = QLCRD32(adapter, addr, &err);
 363                 if (err == -EIO)
 364                         return err;
 365         }
 366         return data;
 367 }
 368
 369 int qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data)
 370 {
 371         int ret = 0;
 372
 373         if (qlcnic_82xx_check(adapter))
 374                 qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data);
 375         else
 376                 ret = qlcnic_83xx_wrt_reg_indirect(adapter, addr, data);
 377
 378         return ret;
 379 }
 380
 381 static int
 382 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
 383                 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
 384 {
 385         u32 i, producer;
 386         struct qlcnic_cmd_buffer *pbuf;
 387         struct cmd_desc_type0 *cmd_desc;
 388         struct qlcnic_host_tx_ring *tx_ring;
 389
 390         i = 0;
 391
 392         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 393                 return -EIO;
 394
 395         tx_ring = &adapter->tx_ring[0];
 396         __netif_tx_lock_bh(tx_ring->txq);
 397
 398         producer = tx_ring->producer;
 399
 400         if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
 401                 netif_tx_stop_queue(tx_ring->txq);
 402                 smp_mb();
 403                 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
 404                         if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
 405                                 netif_tx_wake_queue(tx_ring->txq);
 406                 } else {
 407                         adapter->stats.xmit_off++;
 408                         __netif_tx_unlock_bh(tx_ring->txq);
 409                         return -EBUSY;
 410                 }
 411         }
 412
 413         do {
 414                 cmd_desc = &cmd_desc_arr[i];
 415
 416                 pbuf = &tx_ring->cmd_buf_arr[producer];
 417                 pbuf->skb = NULL;
 418                 pbuf->frag_count = 0;
 419
 420                 memcpy(&tx_ring->desc_head[producer],
 421                        cmd_desc, sizeof(struct cmd_desc_type0));
 422
 423                 producer = get_next_index(producer, tx_ring->num_desc);
 424                 i++;
 425
 426         } while (i != nr_desc);
 427
 428         tx_ring->producer = producer;
 429
 430         qlcnic_update_cmd_producer(tx_ring);
 431
 432         __netif_tx_unlock_bh(tx_ring->txq);
 433
 434         return 0;
 435 }
 436
 437 int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
 438                                    u16 vlan_id, u8 op)
 439 {
 440         struct qlcnic_nic_req req;
 441         struct qlcnic_mac_req *mac_req;
 442         struct qlcnic_vlan_req *vlan_req;
 443         u64 word;
 444
 445         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 446         req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
 447
 448         word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
 449         req.req_hdr = cpu_to_le64(word);
 450
 451         mac_req = (struct qlcnic_mac_req *)&req.words[0];
 452         mac_req->op = op;
 453         memcpy(mac_req->mac_addr, addr, ETH_ALEN);
 454
 455         vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
 456         vlan_req->vlan_id = cpu_to_le16(vlan_id);
 457
 458         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 459 }
 460
 461 int qlcnic_nic_del_mac(struct qlcnic_adapter *adapter, const u8 *addr)
 462 {
 463         struct qlcnic_mac_vlan_list *cur;
 464         struct list_head *head;
 465         int err = -EINVAL;
 466
 467         /* Delete MAC from the existing list */
 468         list_for_each(head, &adapter->mac_list) {
 469                 cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
 470                 if (ether_addr_equal(addr, cur->mac_addr)) {
 471                         err = qlcnic_sre_macaddr_change(adapter, cur->mac_addr,
 472                                                         0, QLCNIC_MAC_DEL);
 473                         if (err)
 474                                 return err;
 475                         list_del(&cur->list);
 476                         kfree(cur);
 477                         return err;
 478                 }
 479         }
 480         return err;
 481 }
 482
 483 int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr, u16 vlan,
 484                        enum qlcnic_mac_type mac_type)
 485 {
 486         struct qlcnic_mac_vlan_list *cur;
 487         struct list_head *head;
 488
 489         /* look up if already exists */
 490         list_for_each(head, &adapter->mac_list) {
 491                 cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
 492                 if (ether_addr_equal(addr, cur->mac_addr) &&
 493                     cur->vlan_id == vlan)
 494                         return 0;
 495         }
 496
 497         cur = kzalloc(sizeof(*cur), GFP_ATOMIC);
 498         if (cur == NULL)
 499                 return -ENOMEM;
 500
 501         memcpy(cur->mac_addr, addr, ETH_ALEN);
 502
 503         if (qlcnic_sre_macaddr_change(adapter,
 504                                 cur->mac_addr, vlan, QLCNIC_MAC_ADD)) {
 505                 kfree(cur);
 506                 return -EIO;
 507         }
 508
 509         cur->vlan_id = vlan;
 510         cur->mac_type = mac_type;
 511
 512         list_add_tail(&cur->list, &adapter->mac_list);
 513         return 0;
 514 }
 515
 516 void qlcnic_flush_mcast_mac(struct qlcnic_adapter *adapter)
 517 {
 518         struct qlcnic_mac_vlan_list *cur;
 519         struct list_head *head, *tmp;
 520
 521         list_for_each_safe(head, tmp, &adapter->mac_list) {
 522                 cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
 523                 if (cur->mac_type != QLCNIC_MULTICAST_MAC)
 524                         continue;
 525
 526                 qlcnic_sre_macaddr_change(adapter, cur->mac_addr,
 527                                           cur->vlan_id, QLCNIC_MAC_DEL);
 528                 list_del(&cur->list);
 529                 kfree(cur);
 530         }
 531 }
 532
 533 static void __qlcnic_set_multi(struct net_device *netdev, u16 vlan)
 534 {
 535         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 536         struct qlcnic_hardware_context *ahw = adapter->ahw;
 537         struct netdev_hw_addr *ha;
 538         static const u8 bcast_addr[ETH_ALEN] = {
 539                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
 540         };
 541         u32 mode = VPORT_MISS_MODE_DROP;
 542
 543         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 544                 return;
 545
 546         qlcnic_nic_add_mac(adapter, adapter->mac_addr, vlan,
 547                            QLCNIC_UNICAST_MAC);
 548         qlcnic_nic_add_mac(adapter, bcast_addr, vlan, QLCNIC_BROADCAST_MAC);
 549
 550         if (netdev->flags & IFF_PROMISC) {
 551                 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
 552                         mode = VPORT_MISS_MODE_ACCEPT_ALL;
 553         } else if ((netdev->flags & IFF_ALLMULTI) ||
 554                    (netdev_mc_count(netdev) > ahw->max_mc_count)) {
 555                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 556         } else if (!netdev_mc_empty(netdev)) {
 557                 qlcnic_flush_mcast_mac(adapter);
 558                 netdev_for_each_mc_addr(ha, netdev)
 559                         qlcnic_nic_add_mac(adapter, ha->addr, vlan,
 560                                            QLCNIC_MULTICAST_MAC);
 561         }
 562
 563         /* configure unicast MAC address, if there is not sufficient space
 564          * to store all the unicast addresses then enable promiscuous mode
 565          */
 566         if (netdev_uc_count(netdev) > ahw->max_uc_count) {
 567                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 568         } else if (!netdev_uc_empty(netdev)) {
 569                 netdev_for_each_uc_addr(ha, netdev)
 570                         qlcnic_nic_add_mac(adapter, ha->addr, vlan,
 571                                            QLCNIC_UNICAST_MAC);
 572         }
 573
 574         if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
 575             !adapter->fdb_mac_learn) {
 576                 qlcnic_alloc_lb_filters_mem(adapter);
 577                 adapter->drv_mac_learn = 1;
 578                 if (adapter->flags & QLCNIC_ESWITCH_ENABLED)
 579                         adapter->rx_mac_learn = true;
 580         } else {
 581                 adapter->drv_mac_learn = 0;
 582                 adapter->rx_mac_learn = false;
 583         }
 584
 585         qlcnic_nic_set_promisc(adapter, mode);
 586 }
 587
 588 void qlcnic_set_multi(struct net_device *netdev)
 589 {
 590         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 591
 592         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 593                 return;
 594
 595         if (qlcnic_sriov_vf_check(adapter))
 596                 qlcnic_sriov_vf_set_multi(netdev);
 597         else
 598                 __qlcnic_set_multi(netdev, 0);
 599 }
 600
 601 int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
 602 {
 603         struct qlcnic_nic_req req;
 604         u64 word;
 605
 606         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 607
 608         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 609
 610         word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
 611                         ((u64)adapter->portnum << 16);
 612         req.req_hdr = cpu_to_le64(word);
 613
 614         req.words[0] = cpu_to_le64(mode);
 615
 616         return qlcnic_send_cmd_descs(adapter,
 617                                 (struct cmd_desc_type0 *)&req, 1);
 618 }
 619
 620 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter)
 621 {
 622         struct list_head *head = &adapter->mac_list;
 623         struct qlcnic_mac_vlan_list *cur;
 624
 625         while (!list_empty(head)) {
 626                 cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list);
 627                 qlcnic_sre_macaddr_change(adapter,
 628                                 cur->mac_addr, 0, QLCNIC_MAC_DEL);
 629                 list_del(&cur->list);
 630                 kfree(cur);
 631         }
 632 }
 633
 634 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
 635 {
 636         struct qlcnic_filter *tmp_fil;
 637         struct hlist_node *n;
 638         struct hlist_head *head;
 639         int i;
 640         unsigned long expires;
 641         u8 cmd;
 642
 643         for (i = 0; i < adapter->fhash.fbucket_size; i++) {
 644                 head = &(adapter->fhash.fhead[i]);
 645                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
 646                         cmd =  tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 647                                                   QLCNIC_MAC_DEL;
 648                         expires = tmp_fil->ftime + QLCNIC_FILTER_AGE * HZ;
 649                         if (time_before(expires, jiffies)) {
 650                                 qlcnic_sre_macaddr_change(adapter,
 651                                                           tmp_fil->faddr,
 652                                                           tmp_fil->vlan_id,
 653                                                           cmd);
 654                                 spin_lock_bh(&adapter->mac_learn_lock);
 655                                 adapter->fhash.fnum--;
 656                                 hlist_del(&tmp_fil->fnode);
 657                                 spin_unlock_bh(&adapter->mac_learn_lock);
 658                                 kfree(tmp_fil);
 659                         }
 660                 }
 661         }
 662         for (i = 0; i < adapter->rx_fhash.fbucket_size; i++) {
 663                 head = &(adapter->rx_fhash.fhead[i]);
 664
 665                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode)
 666                 {
 667                         expires = tmp_fil->ftime + QLCNIC_FILTER_AGE * HZ;
 668                         if (time_before(expires, jiffies)) {
 669                                 spin_lock_bh(&adapter->rx_mac_learn_lock);
 670                                 adapter->rx_fhash.fnum--;
 671                                 hlist_del(&tmp_fil->fnode);
 672                                 spin_unlock_bh(&adapter->rx_mac_learn_lock);
 673                                 kfree(tmp_fil);
 674                         }
 675                 }
 676         }
 677 }
 678
 679 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
 680 {
 681         struct qlcnic_filter *tmp_fil;
 682         struct hlist_node *n;
 683         struct hlist_head *head;
 684         int i;
 685         u8 cmd;
 686
 687         for (i = 0; i < adapter->fhash.fbucket_size; i++) {
 688                 head = &(adapter->fhash.fhead[i]);
 689                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
 690                         cmd =  tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 691                                                   QLCNIC_MAC_DEL;
 692                         qlcnic_sre_macaddr_change(adapter,
 693                                                   tmp_fil->faddr,
 694                                                   tmp_fil->vlan_id,
 695                                                   cmd);
 696                         spin_lock_bh(&adapter->mac_learn_lock);
 697                         adapter->fhash.fnum--;
 698                         hlist_del(&tmp_fil->fnode);
 699                         spin_unlock_bh(&adapter->mac_learn_lock);
 700                         kfree(tmp_fil);
 701                 }
 702         }
 703 }
 704
 705 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
 706 {
 707         struct qlcnic_nic_req req;
 708         int rv;
 709
 710         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 711
 712         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 713         req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
 714                 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
 715
 716         req.words[0] = cpu_to_le64(flag);
 717
 718         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 719         if (rv != 0)
 720                 dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
 721                                 flag ? "Set" : "Reset");
 722         return rv;
 723 }
 724
 725 int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
 726 {
 727         if (qlcnic_set_fw_loopback(adapter, mode))
 728                 return -EIO;
 729
 730         if (qlcnic_nic_set_promisc(adapter,
 731                                    VPORT_MISS_MODE_ACCEPT_ALL)) {
 732                 qlcnic_set_fw_loopback(adapter, 0);
 733                 return -EIO;
 734         }
 735
 736         msleep(1000);
 737         return 0;
 738 }
 739
 740 int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
 741 {
 742         struct net_device *netdev = adapter->netdev;
 743
 744         mode = VPORT_MISS_MODE_DROP;
 745         qlcnic_set_fw_loopback(adapter, 0);
 746
 747         if (netdev->flags & IFF_PROMISC)
 748                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 749         else if (netdev->flags & IFF_ALLMULTI)
 750                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 751
 752         qlcnic_nic_set_promisc(adapter, mode);
 753         msleep(1000);
 754         return 0;
 755 }
 756
 757 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *adapter)
 758 {
 759         u8 mac[ETH_ALEN];
 760         int ret;
 761
 762         ret = qlcnic_get_mac_address(adapter, mac,
 763                                      adapter->ahw->physical_port);
 764         if (ret)
 765                 return ret;
 766
 767         memcpy(adapter->ahw->phys_port_id, mac, ETH_ALEN);
 768         adapter->flags |= QLCNIC_HAS_PHYS_PORT_ID;
 769
 770         return 0;
 771 }
 772
 773 int qlcnic_82xx_set_rx_coalesce(struct qlcnic_adapter *adapter)
 774 {
 775         struct qlcnic_nic_req req;
 776         int rv;
 777
 778         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 779
 780         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 781
 782         req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
 783                 ((u64) adapter->portnum << 16));
 784
 785         req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
 786         req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
 787                         ((u64) adapter->ahw->coal.rx_time_us) << 16);
 788         req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
 789                         ((u64) adapter->ahw->coal.type) << 32 |
 790                         ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
 791         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 792         if (rv != 0)
 793                 dev_err(&adapter->netdev->dev,
 794                         "Could not send interrupt coalescing parameters\n");
 795
 796         return rv;
 797 }
 798
 799 /* Send the interrupt coalescing parameter set by ethtool to the card. */
 800 int qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter,
 801                                      struct ethtool_coalesce *ethcoal)
 802 {
 803         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
 804         int rv;
 805
 806         coal->flag = QLCNIC_INTR_DEFAULT;
 807         coal->rx_time_us = ethcoal->rx_coalesce_usecs;
 808         coal->rx_packets = ethcoal->rx_max_coalesced_frames;
 809
 810         rv = qlcnic_82xx_set_rx_coalesce(adapter);
 811
 812         if (rv)
 813                 netdev_err(adapter->netdev,
 814                            "Failed to set Rx coalescing parameters\n");
 815
 816         return rv;
 817 }
 818
 819 #define QLCNIC_ENABLE_IPV4_LRO          BIT_0
 820 #define QLCNIC_ENABLE_IPV6_LRO          (BIT_1 | BIT_9)
 821
 822 int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
 823 {
 824         struct qlcnic_nic_req req;
 825         u64 word;
 826         int rv;
 827
 828         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 829                 return 0;
 830
 831         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 832
 833         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 834
 835         word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
 836         req.req_hdr = cpu_to_le64(word);
 837
 838         word = 0;
 839         if (enable) {
 840                 word = QLCNIC_ENABLE_IPV4_LRO;
 841                 if (adapter->ahw->extra_capability[0] &
 842                     QLCNIC_FW_CAP2_HW_LRO_IPV6)
 843                         word |= QLCNIC_ENABLE_IPV6_LRO;
 844         }
 845
 846         req.words[0] = cpu_to_le64(word);
 847
 848         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 849         if (rv != 0)
 850                 dev_err(&adapter->netdev->dev,
 851                         "Could not send configure hw lro request\n");
 852
 853         return rv;
 854 }
 855
 856 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
 857 {
 858         struct qlcnic_nic_req req;
 859         u64 word;
 860         int rv;
 861
 862         if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
 863                 return 0;
 864
 865         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 866
 867         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 868
 869         word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
 870                 ((u64)adapter->portnum << 16);
 871         req.req_hdr = cpu_to_le64(word);
 872
 873         req.words[0] = cpu_to_le64(enable);
 874
 875         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 876         if (rv != 0)
 877                 dev_err(&adapter->netdev->dev,
 878                         "Could not send configure bridge mode request\n");
 879
 880         adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
 881
 882         return rv;
 883 }
 884
 885
 886 #define QLCNIC_RSS_HASHTYPE_IP_TCP      0x3
 887 #define QLCNIC_ENABLE_TYPE_C_RSS        BIT_10
 888 #define QLCNIC_RSS_FEATURE_FLAG (1ULL << 63)
 889 #define QLCNIC_RSS_IND_TABLE_MASK       0x7ULL
 890
 891 int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int enable)
 892 {
 893         struct qlcnic_nic_req req;
 894         u64 word;
 895         int i, rv;
 896
 897         static const u64 key[] = {
 898                 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 899                 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 900                 0x255b0ec26d5a56daULL
 901         };
 902
 903         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 904         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 905
 906         word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
 907         req.req_hdr = cpu_to_le64(word);
 908
 909         /*
 910          * RSS request:
 911          * bits 3-0: hash_method
 912          *      5-4: hash_type_ipv4
 913          *      7-6: hash_type_ipv6
 914          *        8: enable
 915          *        9: use indirection table
 916          *       10: type-c rss
 917          *       11: udp rss
 918          *    47-12: reserved
 919          *    62-48: indirection table mask
 920          *       63: feature flag
 921          */
 922         word =  ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
 923                 ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
 924                 ((u64)(enable & 0x1) << 8) |
 925                 ((u64)QLCNIC_RSS_IND_TABLE_MASK << 48) |
 926                 (u64)QLCNIC_ENABLE_TYPE_C_RSS |
 927                 (u64)QLCNIC_RSS_FEATURE_FLAG;
 928
 929         req.words[0] = cpu_to_le64(word);
 930         for (i = 0; i < 5; i++)
 931                 req.words[i+1] = cpu_to_le64(key[i]);
 932
 933         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 934         if (rv != 0)
 935                 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
 936
 937         return rv;
 938 }
 939
 940 void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
 941                                __be32 ip, int cmd)
 942 {
 943         struct qlcnic_nic_req req;
 944         struct qlcnic_ipaddr *ipa;
 945         u64 word;
 946         int rv;
 947
 948         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 949         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 950
 951         word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
 952         req.req_hdr = cpu_to_le64(word);
 953
 954         req.words[0] = cpu_to_le64(cmd);
 955         ipa = (struct qlcnic_ipaddr *)&req.words[1];
 956         ipa->ipv4 = ip;
 957
 958         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 959         if (rv != 0)
 960                 dev_err(&adapter->netdev->dev,
 961                                 "could not notify %s IP 0x%x request\n",
 962                                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
 963 }
 964
 965 int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int enable)
 966 {
 967         struct qlcnic_nic_req req;
 968         u64 word;
 969         int rv;
 970         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 971         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 972
 973         word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
 974         req.req_hdr = cpu_to_le64(word);
 975         req.words[0] = cpu_to_le64(enable | (enable << 8));
 976         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 977         if (rv != 0)
 978                 dev_err(&adapter->netdev->dev,
 979                                 "could not configure link notification\n");
 980
 981         return rv;
 982 }
 983
 984 static int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
 985 {
 986         struct qlcnic_nic_req req;
 987         u64 word;
 988         int rv;
 989
 990         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 991                 return 0;
 992
 993         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 994         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 995
 996         word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
 997                 ((u64)adapter->portnum << 16) |
 998                 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
 999
1000         req.req_hdr = cpu_to_le64(word);
1001
1002         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1003         if (rv != 0)
1004                 dev_err(&adapter->netdev->dev,
1005                                  "could not cleanup lro flows\n");
1006
1007         return rv;
1008 }
1009
1010 /*
1011  * qlcnic_change_mtu - Change the Maximum Transfer Unit
1012  * @returns 0 on success, negative on failure
1013  */
1014
1015 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
1016 {
1017         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1018         int rc = 0;
1019
1020         rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
1021
1022         if (!rc)
1023                 netdev->mtu = mtu;
1024
1025         return rc;
1026 }
1027
1028 static netdev_features_t qlcnic_process_flags(struct qlcnic_adapter *adapter,
1029                                               netdev_features_t features)
1030 {
1031         u32 offload_flags = adapter->offload_flags;
1032
1033         if (offload_flags & BIT_0) {
1034                 features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
1035                             NETIF_F_IPV6_CSUM;
1036                 adapter->rx_csum = 1;
1037                 if (QLCNIC_IS_TSO_CAPABLE(adapter)) {
1038                         if (!(offload_flags & BIT_1))
1039                                 features &= ~NETIF_F_TSO;
1040                         else
1041                                 features |= NETIF_F_TSO;
1042
1043                         if (!(offload_flags & BIT_2))
1044                                 features &= ~NETIF_F_TSO6;
1045                         else
1046                                 features |= NETIF_F_TSO6;
1047                 }
1048         } else {
1049                 features &= ~(NETIF_F_RXCSUM |
1050                               NETIF_F_IP_CSUM |
1051                               NETIF_F_IPV6_CSUM);
1052
1053                 if (QLCNIC_IS_TSO_CAPABLE(adapter))
1054                         features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
1055                 adapter->rx_csum = 0;
1056         }
1057
1058         return features;
1059 }
1060
1061 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1062         netdev_features_t features)
1063 {
1064         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1065         netdev_features_t changed;
1066
1067         if (qlcnic_82xx_check(adapter) &&
1068             (adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
1069                 if (adapter->flags & QLCNIC_APP_CHANGED_FLAGS) {
1070                         features = qlcnic_process_flags(adapter, features);
1071                 } else {
1072                         changed = features ^ netdev->features;
1073                         features ^= changed & (NETIF_F_RXCSUM |
1074                                                NETIF_F_IP_CSUM |
1075                                                NETIF_F_IPV6_CSUM |
1076                                                NETIF_F_TSO |
1077                                                NETIF_F_TSO6);
1078                 }
1079         }
1080
1081         if (!(features & NETIF_F_RXCSUM))
1082                 features &= ~NETIF_F_LRO;
1083
1084         return features;
1085 }
1086
1087
1088 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features)
1089 {
1090         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1091         netdev_features_t changed = netdev->features ^ features;
1092         int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
1093
1094         if (!(changed & NETIF_F_LRO))
1095                 return 0;
1096
1097         netdev->features ^= NETIF_F_LRO;
1098
1099         if (qlcnic_config_hw_lro(adapter, hw_lro))
1100                 return -EIO;
1101
1102         if (!hw_lro && qlcnic_82xx_check(adapter)) {
1103                 if (qlcnic_send_lro_cleanup(adapter))
1104                         return -EIO;
1105         }
1106
1107         return 0;
1108 }
1109
1110 /*
1111  * Changes the CRB window to the specified window.
1112  */
1113  /* Returns < 0 if off is not valid,
1114  *       1 if window access is needed. 'off' is set to offset from
1115  *         CRB space in 128M pci map
1116  *       0 if no window access is needed. 'off' is set to 2M addr
1117  * In: 'off' is offset from base in 128M pci map
1118  */
1119 static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw,
1120                                       ulong off, void __iomem **addr)
1121 {
1122         const struct crb_128M_2M_sub_block_map *m;
1123
1124         if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
1125                 return -EINVAL;
1126
1127         off -= QLCNIC_PCI_CRBSPACE;
1128
1129         /*
1130          * Try direct map
1131          */
1132         m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1133
1134         if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1135                 *addr = ahw->pci_base0 + m->start_2M +
1136                         (off - m->start_128M);
1137                 return 0;
1138         }
1139
1140         /*
1141          * Not in direct map, use crb window
1142          */
1143         *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
1144         return 1;
1145 }
1146
1147 /*
1148  * In: 'off' is offset from CRB space in 128M pci map
1149  * Out: 'off' is 2M pci map addr
1150  * side effect: lock crb window
1151  */
1152 static int
1153 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
1154 {
1155         u32 window;
1156         void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
1157
1158         off -= QLCNIC_PCI_CRBSPACE;
1159
1160         window = CRB_HI(off);
1161         if (window == 0) {
1162                 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
1163                 return -EIO;
1164         }
1165
1166         writel(window, addr);
1167         if (readl(addr) != window) {
1168                 if (printk_ratelimit())
1169                         dev_warn(&adapter->pdev->dev,
1170                                 "failed to set CRB window to %d off 0x%lx\n",
1171                                 window, off);
1172                 return -EIO;
1173         }
1174         return 0;
1175 }
1176
1177 int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1178                                u32 data)
1179 {
1180         unsigned long flags;
1181         int rv;
1182         void __iomem *addr = NULL;
1183
1184         rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1185
1186         if (rv == 0) {
1187                 writel(data, addr);
1188                 return 0;
1189         }
1190
1191         if (rv > 0) {
1192                 /* indirect access */
1193                 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1194                 crb_win_lock(adapter);
1195                 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
1196                 if (!rv)
1197                         writel(data, addr);
1198                 crb_win_unlock(adapter);
1199                 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1200                 return rv;
1201         }
1202
1203         dev_err(&adapter->pdev->dev,
1204                         "%s: invalid offset: 0x%016lx\n", __func__, off);
1205         dump_stack();
1206         return -EIO;
1207 }
1208
1209 int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1210                               int *err)
1211 {
1212         unsigned long flags;
1213         int rv;
1214         u32 data = -1;
1215         void __iomem *addr = NULL;
1216
1217         rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1218
1219         if (rv == 0)
1220                 return readl(addr);
1221
1222         if (rv > 0) {
1223                 /* indirect access */
1224                 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1225                 crb_win_lock(adapter);
1226                 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
1227                         data = readl(addr);
1228                 crb_win_unlock(adapter);
1229                 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1230                 return data;
1231         }
1232
1233         dev_err(&adapter->pdev->dev,
1234                         "%s: invalid offset: 0x%016lx\n", __func__, off);
1235         dump_stack();
1236         return -1;
1237 }
1238
1239 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw,
1240                                 u32 offset)
1241 {
1242         void __iomem *addr = NULL;
1243
1244         WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr));
1245
1246         return addr;
1247 }
1248
1249 static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter,
1250                                         u32 window, u64 off, u64 *data, int op)
1251 {
1252         void __iomem *addr;
1253         u32 start;
1254
1255         mutex_lock(&adapter->ahw->mem_lock);
1256
1257         writel(window, adapter->ahw->ocm_win_crb);
1258         /* read back to flush */
1259         readl(adapter->ahw->ocm_win_crb);
1260         start = QLCNIC_PCI_OCM0_2M + off;
1261
1262         addr = adapter->ahw->pci_base0 + start;
1263
1264         if (op == 0)    /* read */
1265                 *data = readq(addr);
1266         else            /* write */
1267                 writeq(*data, addr);
1268
1269         /* Set window to 0 */
1270         writel(0, adapter->ahw->ocm_win_crb);
1271         readl(adapter->ahw->ocm_win_crb);
1272
1273         mutex_unlock(&adapter->ahw->mem_lock);
1274         return 0;
1275 }
1276
1277 static void
1278 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1279 {
1280         void __iomem *addr = adapter->ahw->pci_base0 +
1281                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1282
1283         mutex_lock(&adapter->ahw->mem_lock);
1284         *data = readq(addr);
1285         mutex_unlock(&adapter->ahw->mem_lock);
1286 }
1287
1288 static void
1289 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1290 {
1291         void __iomem *addr = adapter->ahw->pci_base0 +
1292                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1293
1294         mutex_lock(&adapter->ahw->mem_lock);
1295         writeq(data, addr);
1296         mutex_unlock(&adapter->ahw->mem_lock);
1297 }
1298
1299
1300
1301 /* Set MS memory control data for different adapters */
1302 static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off,
1303                                    struct qlcnic_ms_reg_ctrl *ms)
1304 {
1305         ms->control = QLCNIC_MS_CTRL;
1306         ms->low = QLCNIC_MS_ADDR_LO;
1307         ms->hi = QLCNIC_MS_ADDR_HI;
1308         if (off & 0xf) {
1309                 ms->wd[0] = QLCNIC_MS_WRTDATA_LO;
1310                 ms->rd[0] = QLCNIC_MS_RDDATA_LO;
1311                 ms->wd[1] = QLCNIC_MS_WRTDATA_HI;
1312                 ms->rd[1] = QLCNIC_MS_RDDATA_HI;
1313                 ms->wd[2] = QLCNIC_MS_WRTDATA_ULO;
1314                 ms->wd[3] = QLCNIC_MS_WRTDATA_UHI;
1315                 ms->rd[2] = QLCNIC_MS_RDDATA_ULO;
1316                 ms->rd[3] = QLCNIC_MS_RDDATA_UHI;
1317         } else {
1318                 ms->wd[0] = QLCNIC_MS_WRTDATA_ULO;
1319                 ms->rd[0] = QLCNIC_MS_RDDATA_ULO;
1320                 ms->wd[1] = QLCNIC_MS_WRTDATA_UHI;
1321                 ms->rd[1] = QLCNIC_MS_RDDATA_UHI;
1322                 ms->wd[2] = QLCNIC_MS_WRTDATA_LO;
1323                 ms->wd[3] = QLCNIC_MS_WRTDATA_HI;
1324                 ms->rd[2] = QLCNIC_MS_RDDATA_LO;
1325                 ms->rd[3] = QLCNIC_MS_RDDATA_HI;
1326         }
1327
1328         ms->ocm_window = OCM_WIN_P3P(off);
1329         ms->off = GET_MEM_OFFS_2M(off);
1330 }
1331
1332 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1333 {
1334         int j, ret = 0;
1335         u32 temp, off8;
1336         struct qlcnic_ms_reg_ctrl ms;
1337
1338         /* Only 64-bit aligned access */
1339         if (off & 7)
1340                 return -EIO;
1341
1342         memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1343         if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1344                             QLCNIC_ADDR_QDR_NET_MAX) ||
1345               ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1346                             QLCNIC_ADDR_DDR_NET_MAX)))
1347                 return -EIO;
1348
1349         qlcnic_set_ms_controls(adapter, off, &ms);
1350
1351         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1352                 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1353                                                     ms.off, &data, 1);
1354
1355         off8 = off & ~0xf;
1356
1357         mutex_lock(&adapter->ahw->mem_lock);
1358
1359         qlcnic_ind_wr(adapter, ms.low, off8);
1360         qlcnic_ind_wr(adapter, ms.hi, 0);
1361
1362         qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1363         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1364
1365         for (j = 0; j < MAX_CTL_CHECK; j++) {
1366                 temp = qlcnic_ind_rd(adapter, ms.control);
1367                 if ((temp & TA_CTL_BUSY) == 0)
1368                         break;
1369         }
1370
1371         if (j >= MAX_CTL_CHECK) {
1372                 ret = -EIO;
1373                 goto done;
1374         }
1375
1376         /* This is the modify part of read-modify-write */
1377         qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0]));
1378         qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1]));
1379         /* This is the write part of read-modify-write */
1380         qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff);
1381         qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff);
1382
1383         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE);
1384         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START);
1385
1386         for (j = 0; j < MAX_CTL_CHECK; j++) {
1387                 temp = qlcnic_ind_rd(adapter, ms.control);
1388                 if ((temp & TA_CTL_BUSY) == 0)
1389                         break;
1390         }
1391
1392         if (j >= MAX_CTL_CHECK) {
1393                 if (printk_ratelimit())
1394                         dev_err(&adapter->pdev->dev,
1395                                         "failed to write through agent\n");
1396                 ret = -EIO;
1397         } else
1398                 ret = 0;
1399
1400 done:
1401         mutex_unlock(&adapter->ahw->mem_lock);
1402
1403         return ret;
1404 }
1405
1406 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1407 {
1408         int j, ret;
1409         u32 temp, off8;
1410         u64 val;
1411         struct qlcnic_ms_reg_ctrl ms;
1412
1413         /* Only 64-bit aligned access */
1414         if (off & 7)
1415                 return -EIO;
1416         if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1417                             QLCNIC_ADDR_QDR_NET_MAX) ||
1418               ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1419                             QLCNIC_ADDR_DDR_NET_MAX)))
1420                 return -EIO;
1421
1422         memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1423         qlcnic_set_ms_controls(adapter, off, &ms);
1424
1425         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1426                 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1427                                                     ms.off, data, 0);
1428
1429         mutex_lock(&adapter->ahw->mem_lock);
1430
1431         off8 = off & ~0xf;
1432
1433         qlcnic_ind_wr(adapter, ms.low, off8);
1434         qlcnic_ind_wr(adapter, ms.hi, 0);
1435
1436         qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1437         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1438
1439         for (j = 0; j < MAX_CTL_CHECK; j++) {
1440                 temp = qlcnic_ind_rd(adapter, ms.control);
1441                 if ((temp & TA_CTL_BUSY) == 0)
1442                         break;
1443         }
1444
1445         if (j >= MAX_CTL_CHECK) {
1446                 if (printk_ratelimit())
1447                         dev_err(&adapter->pdev->dev,
1448                                         "failed to read through agent\n");
1449                 ret = -EIO;
1450         } else {
1451
1452                 temp = qlcnic_ind_rd(adapter, ms.rd[3]);
1453                 val = (u64)temp << 32;
1454                 val |= qlcnic_ind_rd(adapter, ms.rd[2]);
1455                 *data = val;
1456                 ret = 0;
1457         }
1458
1459         mutex_unlock(&adapter->ahw->mem_lock);
1460
1461         return ret;
1462 }
1463
1464 int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter)
1465 {
1466         int offset, board_type, magic, err = 0;
1467         struct pci_dev *pdev = adapter->pdev;
1468
1469         offset = QLCNIC_FW_MAGIC_OFFSET;
1470         if (qlcnic_rom_fast_read(adapter, offset, &magic))
1471                 return -EIO;
1472
1473         if (magic != QLCNIC_BDINFO_MAGIC) {
1474                 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1475                         magic);
1476                 return -EIO;
1477         }
1478
1479         offset = QLCNIC_BRDTYPE_OFFSET;
1480         if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1481                 return -EIO;
1482
1483         adapter->ahw->board_type = board_type;
1484
1485         if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
1486                 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I, &err);
1487                 if (err == -EIO)
1488                         return err;
1489                 if ((gpio & 0x8000) == 0)
1490                         board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
1491         }
1492
1493         switch (board_type) {
1494         case QLCNIC_BRDTYPE_P3P_HMEZ:
1495         case QLCNIC_BRDTYPE_P3P_XG_LOM:
1496         case QLCNIC_BRDTYPE_P3P_10G_CX4:
1497         case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1498         case QLCNIC_BRDTYPE_P3P_IMEZ:
1499         case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1500         case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1501         case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1502         case QLCNIC_BRDTYPE_P3P_10G_XFP:
1503         case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
1504                 adapter->ahw->port_type = QLCNIC_XGBE;
1505                 break;
1506         case QLCNIC_BRDTYPE_P3P_REF_QG:
1507         case QLCNIC_BRDTYPE_P3P_4_GB:
1508         case QLCNIC_BRDTYPE_P3P_4_GB_MM:
1509                 adapter->ahw->port_type = QLCNIC_GBE;
1510                 break;
1511         case QLCNIC_BRDTYPE_P3P_10G_TP:
1512                 adapter->ahw->port_type = (adapter->portnum < 2) ?
1513                         QLCNIC_XGBE : QLCNIC_GBE;
1514                 break;
1515         default:
1516                 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1517                 adapter->ahw->port_type = QLCNIC_XGBE;
1518                 break;
1519         }
1520
1521         return 0;
1522 }
1523
1524 static int
1525 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1526 {
1527         u32 wol_cfg;
1528         int err = 0;
1529
1530         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV, &err);
1531         if (wol_cfg & (1UL << adapter->portnum)) {
1532                 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG, &err);
1533                 if (err == -EIO)
1534                         return err;
1535                 if (wol_cfg & (1 << adapter->portnum))
1536                         return 1;
1537         }
1538
1539         return 0;
1540 }
1541
1542 int qlcnic_82xx_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1543 {
1544         struct qlcnic_nic_req   req;
1545         int rv;
1546         u64 word;
1547
1548         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1549         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1550
1551         word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1552         req.req_hdr = cpu_to_le64(word);
1553
1554         req.words[0] = cpu_to_le64(((u64)rate << 32) | adapter->portnum);
1555         req.words[1] = cpu_to_le64(state);
1556
1557         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1558         if (rv)
1559                 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1560
1561         return rv;
1562 }
1563
1564 void qlcnic_82xx_get_beacon_state(struct qlcnic_adapter *adapter)
1565 {
1566         struct qlcnic_hardware_context *ahw = adapter->ahw;
1567         struct qlcnic_cmd_args cmd;
1568         u8 beacon_state;
1569         int err = 0;
1570
1571         if (ahw->extra_capability[0] & QLCNIC_FW_CAPABILITY_2_BEACON) {
1572                 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1573                                             QLCNIC_CMD_GET_LED_STATUS);
1574                 if (!err) {
1575                         err = qlcnic_issue_cmd(adapter, &cmd);
1576                         if (err) {
1577                                 netdev_err(adapter->netdev,
1578                                            "Failed to get current beacon state, err=%d\n",
1579                                            err);
1580                         } else {
1581                                 beacon_state = cmd.rsp.arg[1];
1582                                 if (beacon_state == QLCNIC_BEACON_DISABLE)
1583                                         ahw->beacon_state = QLCNIC_BEACON_OFF;
1584                                 else if (beacon_state == QLCNIC_BEACON_EANBLE)
1585                                         ahw->beacon_state = QLCNIC_BEACON_ON;
1586                         }
1587                 }
1588                 qlcnic_free_mbx_args(&cmd);
1589         }
1590
1591         return;
1592 }
1593
1594 void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter)
1595 {
1596         void __iomem *msix_base_addr;
1597         u32 func;
1598         u32 msix_base;
1599
1600         pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func);
1601         msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE;
1602         msix_base = readl(msix_base_addr);
1603         func = (func - msix_base) / QLCNIC_MSIX_TBL_PGSIZE;
1604         adapter->ahw->pci_func = func;
1605 }
1606
1607 void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
1608                           loff_t offset, size_t size)
1609 {
1610         int err = 0;
1611         u32 data;
1612         u64 qmdata;
1613
1614         if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1615                 qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata);
1616                 memcpy(buf, &qmdata, size);
1617         } else {
1618                 data = QLCRD32(adapter, offset, &err);
1619                 memcpy(buf, &data, size);
1620         }
1621 }
1622
1623 void qlcnic_82xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
1624                            loff_t offset, size_t size)
1625 {
1626         u32 data;
1627         u64 qmdata;
1628
1629         if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1630                 memcpy(&qmdata, buf, size);
1631                 qlcnic_pci_camqm_write_2M(adapter, offset, qmdata);
1632         } else {
1633                 memcpy(&data, buf, size);
1634                 QLCWR32(adapter, offset, data);
1635         }
1636 }
1637
1638 int qlcnic_82xx_api_lock(struct qlcnic_adapter *adapter)
1639 {
1640         return qlcnic_pcie_sem_lock(adapter, 5, 0);
1641 }
1642
1643 void qlcnic_82xx_api_unlock(struct qlcnic_adapter *adapter)
1644 {
1645         qlcnic_pcie_sem_unlock(adapter, 5);
1646 }
1647
1648 int qlcnic_82xx_shutdown(struct pci_dev *pdev)
1649 {
1650         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
1651         struct net_device *netdev = adapter->netdev;
1652         int retval;
1653
1654         netif_device_detach(netdev);
1655
1656         qlcnic_cancel_idc_work(adapter);
1657
1658         if (netif_running(netdev))
1659                 qlcnic_down(adapter, netdev);
1660
1661         qlcnic_clr_all_drv_state(adapter, 0);
1662
1663         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1664
1665         retval = pci_save_state(pdev);
1666         if (retval)
1667                 return retval;
1668
1669         if (qlcnic_wol_supported(adapter)) {
1670                 pci_enable_wake(pdev, PCI_D3cold, 1);
1671                 pci_enable_wake(pdev, PCI_D3hot, 1);
1672         }
1673
1674         return 0;
1675 }
1676
1677 int qlcnic_82xx_resume(struct qlcnic_adapter *adapter)
1678 {
1679         struct net_device *netdev = adapter->netdev;
1680         int err;
1681
1682         err = qlcnic_start_firmware(adapter);
1683         if (err) {
1684                 dev_err(&adapter->pdev->dev, "failed to start firmware\n");
1685                 return err;
1686         }
1687
1688         if (netif_running(netdev)) {
1689                 err = qlcnic_up(adapter, netdev);
1690                 if (!err)
1691                         qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1692         }
1693
1694         netif_device_attach(netdev);
1695         qlcnic_schedule_work(adapter, qlcnic_fw_poll_work, FW_POLL_DELAY);
1696         return err;
1697 }