drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mutex.h>
  41 #include <linux/pci.h>
  42 #include <linux/slab.h>
  43 #include <linux/string.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/qed/qed_chain.h>
  47 #include <linux/qed/qed_if.h>
  48 #include "qed.h"
  49 #include "qed_cxt.h"
  50 #include "qed_dcbx.h"
  51 #include "qed_dev_api.h"
  52 #include "qed_fcoe.h"
  53 #include "qed_hsi.h"
  54 #include "qed_hw.h"
  55 #include "qed_init_ops.h"
  56 #include "qed_int.h"
  57 #include "qed_iscsi.h"
  58 #include "qed_ll2.h"
  59 #include "qed_mcp.h"
  60 #include "qed_ooo.h"
  61 #include "qed_reg_addr.h"
  62 #include "qed_sp.h"
  63 #include "qed_sriov.h"
  64 #include "qed_vf.h"
  65 #include "qed_rdma.h"
  66
  67 static DEFINE_SPINLOCK(qm_lock);
  68
  69 /******************** Doorbell Recovery *******************/
  70 /* The doorbell recovery mechanism consists of a list of entries which represent
  71  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  72  * entity needs to register with the mechanism and provide the parameters
  73  * describing it's doorbell, including a location where last used doorbell data
  74  * can be found. The doorbell execute function will traverse the list and
  75  * doorbell all of the registered entries.
  76  */
  77 struct qed_db_recovery_entry {
  78         struct list_head list_entry;
  79         void __iomem *db_addr;
  80         void *db_data;
  81         enum qed_db_rec_width db_width;
  82         enum qed_db_rec_space db_space;
  83         u8 hwfn_idx;
  84 };
  85
  86 /* Display a single doorbell recovery entry */
  87 static void qed_db_recovery_dp_entry(struct qed_hwfn *p_hwfn,
  88                                      struct qed_db_recovery_entry *db_entry,
  89                                      char *action)
  90 {
  91         DP_VERBOSE(p_hwfn,
  92                    QED_MSG_SPQ,
  93                    "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  94                    action,
  95                    db_entry,
  96                    db_entry->db_addr,
  97                    db_entry->db_data,
  98                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  99                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
 100                    db_entry->hwfn_idx);
 101 }
 102
 103 /* Doorbell address sanity (address within doorbell bar range) */
 104 static bool qed_db_rec_sanity(struct qed_dev *cdev,
 105                               void __iomem *db_addr,
 106                               enum qed_db_rec_width db_width,
 107                               void *db_data)
 108 {
 109         u32 width = (db_width == DB_REC_WIDTH_32B) ? 32 : 64;
 110
 111         /* Make sure doorbell address is within the doorbell bar */
 112         if (db_addr < cdev->doorbells ||
 113             (u8 __iomem *)db_addr + width >
 114             (u8 __iomem *)cdev->doorbells + cdev->db_size) {
 115                 WARN(true,
 116                      "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
 117                      db_addr,
 118                      cdev->doorbells,
 119                      (u8 __iomem *)cdev->doorbells + cdev->db_size);
 120                 return false;
 121         }
 122
 123         /* ake sure doorbell data pointer is not null */
 124         if (!db_data) {
 125                 WARN(true, "Illegal doorbell data pointer: %p", db_data);
 126                 return false;
 127         }
 128
 129         return true;
 130 }
 131
 132 /* Find hwfn according to the doorbell address */
 133 static struct qed_hwfn *qed_db_rec_find_hwfn(struct qed_dev *cdev,
 134                                              void __iomem *db_addr)
 135 {
 136         struct qed_hwfn *p_hwfn;
 137
 138         /* In CMT doorbell bar is split down the middle between engine 0 and enigne 1 */
 139         if (cdev->num_hwfns > 1)
 140                 p_hwfn = db_addr < cdev->hwfns[1].doorbells ?
 141                     &cdev->hwfns[0] : &cdev->hwfns[1];
 142         else
 143                 p_hwfn = QED_LEADING_HWFN(cdev);
 144
 145         return p_hwfn;
 146 }
 147
 148 /* Add a new entry to the doorbell recovery mechanism */
 149 int qed_db_recovery_add(struct qed_dev *cdev,
 150                         void __iomem *db_addr,
 151                         void *db_data,
 152                         enum qed_db_rec_width db_width,
 153                         enum qed_db_rec_space db_space)
 154 {
 155         struct qed_db_recovery_entry *db_entry;
 156         struct qed_hwfn *p_hwfn;
 157
 158         /* Shortcircuit VFs, for now */
 159         if (IS_VF(cdev)) {
 160                 DP_VERBOSE(cdev,
 161                            QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
 162                 return 0;
 163         }
 164
 165         /* Sanitize doorbell address */
 166         if (!qed_db_rec_sanity(cdev, db_addr, db_width, db_data))
 167                 return -EINVAL;
 168
 169         /* Obtain hwfn from doorbell address */
 170         p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
 171
 172         /* Create entry */
 173         db_entry = kzalloc(sizeof(*db_entry), GFP_KERNEL);
 174         if (!db_entry) {
 175                 DP_NOTICE(cdev, "Failed to allocate a db recovery entry\n");
 176                 return -ENOMEM;
 177         }
 178
 179         /* Populate entry */
 180         db_entry->db_addr = db_addr;
 181         db_entry->db_data = db_data;
 182         db_entry->db_width = db_width;
 183         db_entry->db_space = db_space;
 184         db_entry->hwfn_idx = p_hwfn->my_id;
 185
 186         /* Display */
 187         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 188
 189         /* Protect the list */
 190         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 191         list_add_tail(&db_entry->list_entry, &p_hwfn->db_recovery_info.list);
 192         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 193
 194         return 0;
 195 }
 196
 197 /* Remove an entry from the doorbell recovery mechanism */
 198 int qed_db_recovery_del(struct qed_dev *cdev,
 199                         void __iomem *db_addr, void *db_data)
 200 {
 201         struct qed_db_recovery_entry *db_entry = NULL;
 202         struct qed_hwfn *p_hwfn;
 203         int rc = -EINVAL;
 204
 205         /* Shortcircuit VFs, for now */
 206         if (IS_VF(cdev)) {
 207                 DP_VERBOSE(cdev,
 208                            QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
 209                 return 0;
 210         }
 211
 212         /* Obtain hwfn from doorbell address */
 213         p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
 214
 215         /* Protect the list */
 216         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 217         list_for_each_entry(db_entry,
 218                             &p_hwfn->db_recovery_info.list, list_entry) {
 219                 /* search according to db_data addr since db_addr is not unique (roce) */
 220                 if (db_entry->db_data == db_data) {
 221                         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting");
 222                         list_del(&db_entry->list_entry);
 223                         rc = 0;
 224                         break;
 225                 }
 226         }
 227
 228         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 229
 230         if (rc == -EINVAL)
 231
 232                 DP_NOTICE(p_hwfn,
 233                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 234                           db_data, db_addr);
 235         else
 236                 kfree(db_entry);
 237
 238         return rc;
 239 }
 240
 241 /* Initialize the doorbell recovery mechanism */
 242 static int qed_db_recovery_setup(struct qed_hwfn *p_hwfn)
 243 {
 244         DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Setting up db recovery\n");
 245
 246         /* Make sure db_size was set in cdev */
 247         if (!p_hwfn->cdev->db_size) {
 248                 DP_ERR(p_hwfn->cdev, "db_size not set\n");
 249                 return -EINVAL;
 250         }
 251
 252         INIT_LIST_HEAD(&p_hwfn->db_recovery_info.list);
 253         spin_lock_init(&p_hwfn->db_recovery_info.lock);
 254         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 255
 256         return 0;
 257 }
 258
 259 /* Destroy the doorbell recovery mechanism */
 260 static void qed_db_recovery_teardown(struct qed_hwfn *p_hwfn)
 261 {
 262         struct qed_db_recovery_entry *db_entry = NULL;
 263
 264         DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Tearing down db recovery\n");
 265         if (!list_empty(&p_hwfn->db_recovery_info.list)) {
 266                 DP_VERBOSE(p_hwfn,
 267                            QED_MSG_SPQ,
 268                            "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 269                 while (!list_empty(&p_hwfn->db_recovery_info.list)) {
 270                         db_entry =
 271                             list_first_entry(&p_hwfn->db_recovery_info.list,
 272                                              struct qed_db_recovery_entry,
 273                                              list_entry);
 274                         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 275                         list_del(&db_entry->list_entry);
 276                         kfree(db_entry);
 277                 }
 278         }
 279         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 280 }
 281
 282 /* Print the content of the doorbell recovery mechanism */
 283 void qed_db_recovery_dp(struct qed_hwfn *p_hwfn)
 284 {
 285         struct qed_db_recovery_entry *db_entry = NULL;
 286
 287         DP_NOTICE(p_hwfn,
 288                   "Displaying doorbell recovery database. Counter was %d\n",
 289                   p_hwfn->db_recovery_info.db_recovery_counter);
 290
 291         /* Protect the list */
 292         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 293         list_for_each_entry(db_entry,
 294                             &p_hwfn->db_recovery_info.list, list_entry) {
 295                 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 296         }
 297
 298         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 299 }
 300
 301 /* Ring the doorbell of a single doorbell recovery entry */
 302 static void qed_db_recovery_ring(struct qed_hwfn *p_hwfn,
 303                                  struct qed_db_recovery_entry *db_entry)
 304 {
 305         /* Print according to width */
 306         if (db_entry->db_width == DB_REC_WIDTH_32B) {
 307                 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
 308                            "ringing doorbell address %p data %x\n",
 309                            db_entry->db_addr,
 310                            *(u32 *)db_entry->db_data);
 311         } else {
 312                 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
 313                            "ringing doorbell address %p data %llx\n",
 314                            db_entry->db_addr,
 315                            *(u64 *)(db_entry->db_data));
 316         }
 317
 318         /* Sanity */
 319         if (!qed_db_rec_sanity(p_hwfn->cdev, db_entry->db_addr,
 320                                db_entry->db_width, db_entry->db_data))
 321                 return;
 322
 323         /* Flush the write combined buffer. Since there are multiple doorbelling
 324          * entities using the same address, if we don't flush, a transaction
 325          * could be lost.
 326          */
 327         wmb();
 328
 329         /* Ring the doorbell */
 330         if (db_entry->db_width == DB_REC_WIDTH_32B)
 331                 DIRECT_REG_WR(db_entry->db_addr,
 332                               *(u32 *)(db_entry->db_data));
 333         else
 334                 DIRECT_REG_WR64(db_entry->db_addr,
 335                                 *(u64 *)(db_entry->db_data));
 336
 337         /* Flush the write combined buffer. Next doorbell may come from a
 338          * different entity to the same address...
 339          */
 340         wmb();
 341 }
 342
 343 /* Traverse the doorbell recovery entry list and ring all the doorbells */
 344 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn)
 345 {
 346         struct qed_db_recovery_entry *db_entry = NULL;
 347
 348         DP_NOTICE(p_hwfn, "Executing doorbell recovery. Counter was %d\n",
 349                   p_hwfn->db_recovery_info.db_recovery_counter);
 350
 351         /* Track amount of times recovery was executed */
 352         p_hwfn->db_recovery_info.db_recovery_counter++;
 353
 354         /* Protect the list */
 355         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 356         list_for_each_entry(db_entry,
 357                             &p_hwfn->db_recovery_info.list, list_entry)
 358                 qed_db_recovery_ring(p_hwfn, db_entry);
 359         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 360 }
 361
 362 /******************** Doorbell Recovery end ****************/
 363
 364 /********************************** NIG LLH ***********************************/
 365
 366 enum qed_llh_filter_type {
 367         QED_LLH_FILTER_TYPE_MAC,
 368         QED_LLH_FILTER_TYPE_PROTOCOL,
 369 };
 370
 371 struct qed_llh_mac_filter {
 372         u8 addr[ETH_ALEN];
 373 };
 374
 375 struct qed_llh_protocol_filter {
 376         enum qed_llh_prot_filter_type_t type;
 377         u16 source_port_or_eth_type;
 378         u16 dest_port;
 379 };
 380
 381 union qed_llh_filter {
 382         struct qed_llh_mac_filter mac;
 383         struct qed_llh_protocol_filter protocol;
 384 };
 385
 386 struct qed_llh_filter_info {
 387         bool b_enabled;
 388         u32 ref_cnt;
 389         enum qed_llh_filter_type type;
 390         union qed_llh_filter filter;
 391 };
 392
 393 struct qed_llh_info {
 394         /* Number of LLH filters banks */
 395         u8 num_ppfid;
 396
 397 #define MAX_NUM_PPFID   8
 398         u8 ppfid_array[MAX_NUM_PPFID];
 399
 400         /* Array of filters arrays:
 401          * "num_ppfid" elements of filters banks, where each is an array of
 402          * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters.
 403          */
 404         struct qed_llh_filter_info **pp_filters;
 405 };
 406
 407 static void qed_llh_free(struct qed_dev *cdev)
 408 {
 409         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 410         u32 i;
 411
 412         if (p_llh_info) {
 413                 if (p_llh_info->pp_filters)
 414                         for (i = 0; i < p_llh_info->num_ppfid; i++)
 415                                 kfree(p_llh_info->pp_filters[i]);
 416
 417                 kfree(p_llh_info->pp_filters);
 418         }
 419
 420         kfree(p_llh_info);
 421         cdev->p_llh_info = NULL;
 422 }
 423
 424 static int qed_llh_alloc(struct qed_dev *cdev)
 425 {
 426         struct qed_llh_info *p_llh_info;
 427         u32 size, i;
 428
 429         p_llh_info = kzalloc(sizeof(*p_llh_info), GFP_KERNEL);
 430         if (!p_llh_info)
 431                 return -ENOMEM;
 432         cdev->p_llh_info = p_llh_info;
 433
 434         for (i = 0; i < MAX_NUM_PPFID; i++) {
 435                 if (!(cdev->ppfid_bitmap & (0x1 << i)))
 436                         continue;
 437
 438                 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;
 439                 DP_VERBOSE(cdev, QED_MSG_SP, "ppfid_array[%d] = %hhd\n",
 440                            p_llh_info->num_ppfid, i);
 441                 p_llh_info->num_ppfid++;
 442         }
 443
 444         size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);
 445         p_llh_info->pp_filters = kzalloc(size, GFP_KERNEL);
 446         if (!p_llh_info->pp_filters)
 447                 return -ENOMEM;
 448
 449         size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
 450             sizeof(**p_llh_info->pp_filters);
 451         for (i = 0; i < p_llh_info->num_ppfid; i++) {
 452                 p_llh_info->pp_filters[i] = kzalloc(size, GFP_KERNEL);
 453                 if (!p_llh_info->pp_filters[i])
 454                         return -ENOMEM;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static int qed_llh_shadow_sanity(struct qed_dev *cdev,
 461                                  u8 ppfid, u8 filter_idx, const char *action)
 462 {
 463         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 464
 465         if (ppfid >= p_llh_info->num_ppfid) {
 466                 DP_NOTICE(cdev,
 467                           "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n",
 468                           action, ppfid, p_llh_info->num_ppfid);
 469                 return -EINVAL;
 470         }
 471
 472         if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
 473                 DP_NOTICE(cdev,
 474                           "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n",
 475                           action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);
 476                 return -EINVAL;
 477         }
 478
 479         return 0;
 480 }
 481
 482 #define QED_LLH_INVALID_FILTER_IDX      0xff
 483
 484 static int
 485 qed_llh_shadow_search_filter(struct qed_dev *cdev,
 486                              u8 ppfid,
 487                              union qed_llh_filter *p_filter, u8 *p_filter_idx)
 488 {
 489         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 490         struct qed_llh_filter_info *p_filters;
 491         int rc;
 492         u8 i;
 493
 494         rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "search");
 495         if (rc)
 496                 return rc;
 497
 498         *p_filter_idx = QED_LLH_INVALID_FILTER_IDX;
 499
 500         p_filters = p_llh_info->pp_filters[ppfid];
 501         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
 502                 if (!memcmp(p_filter, &p_filters[i].filter,
 503                             sizeof(*p_filter))) {
 504                         *p_filter_idx = i;
 505                         break;
 506                 }
 507         }
 508
 509         return 0;
 510 }
 511
 512 static int
 513 qed_llh_shadow_get_free_idx(struct qed_dev *cdev, u8 ppfid, u8 *p_filter_idx)
 514 {
 515         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 516         struct qed_llh_filter_info *p_filters;
 517         int rc;
 518         u8 i;
 519
 520         rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "get_free_idx");
 521         if (rc)
 522                 return rc;
 523
 524         *p_filter_idx = QED_LLH_INVALID_FILTER_IDX;
 525
 526         p_filters = p_llh_info->pp_filters[ppfid];
 527         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
 528                 if (!p_filters[i].b_enabled) {
 529                         *p_filter_idx = i;
 530                         break;
 531                 }
 532         }
 533
 534         return 0;
 535 }
 536
 537 static int
 538 __qed_llh_shadow_add_filter(struct qed_dev *cdev,
 539                             u8 ppfid,
 540                             u8 filter_idx,
 541                             enum qed_llh_filter_type type,
 542                             union qed_llh_filter *p_filter, u32 *p_ref_cnt)
 543 {
 544         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 545         struct qed_llh_filter_info *p_filters;
 546         int rc;
 547
 548         rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "add");
 549         if (rc)
 550                 return rc;
 551
 552         p_filters = p_llh_info->pp_filters[ppfid];
 553         if (!p_filters[filter_idx].ref_cnt) {
 554                 p_filters[filter_idx].b_enabled = true;
 555                 p_filters[filter_idx].type = type;
 556                 memcpy(&p_filters[filter_idx].filter, p_filter,
 557                        sizeof(p_filters[filter_idx].filter));
 558         }
 559
 560         *p_ref_cnt = ++p_filters[filter_idx].ref_cnt;
 561
 562         return 0;
 563 }
 564
 565 static int
 566 qed_llh_shadow_add_filter(struct qed_dev *cdev,
 567                           u8 ppfid,
 568                           enum qed_llh_filter_type type,
 569                           union qed_llh_filter *p_filter,
 570                           u8 *p_filter_idx, u32 *p_ref_cnt)
 571 {
 572         int rc;
 573
 574         /* Check if the same filter already exist */
 575         rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx);
 576         if (rc)
 577                 return rc;
 578
 579         /* Find a new entry in case of a new filter */
 580         if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
 581                 rc = qed_llh_shadow_get_free_idx(cdev, ppfid, p_filter_idx);
 582                 if (rc)
 583                         return rc;
 584         }
 585
 586         /* No free entry was found */
 587         if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
 588                 DP_NOTICE(cdev,
 589                           "Failed to find an empty LLH filter to utilize [ppfid %d]\n",
 590                           ppfid);
 591                 return -EINVAL;
 592         }
 593
 594         return __qed_llh_shadow_add_filter(cdev, ppfid, *p_filter_idx, type,
 595                                            p_filter, p_ref_cnt);
 596 }
 597
 598 static int
 599 __qed_llh_shadow_remove_filter(struct qed_dev *cdev,
 600                                u8 ppfid, u8 filter_idx, u32 *p_ref_cnt)
 601 {
 602         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 603         struct qed_llh_filter_info *p_filters;
 604         int rc;
 605
 606         rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "remove");
 607         if (rc)
 608                 return rc;
 609
 610         p_filters = p_llh_info->pp_filters[ppfid];
 611         if (!p_filters[filter_idx].ref_cnt) {
 612                 DP_NOTICE(cdev,
 613                           "LLH shadow: trying to remove a filter with ref_cnt=0\n");
 614                 return -EINVAL;
 615         }
 616
 617         *p_ref_cnt = --p_filters[filter_idx].ref_cnt;
 618         if (!p_filters[filter_idx].ref_cnt)
 619                 memset(&p_filters[filter_idx],
 620                        0, sizeof(p_filters[filter_idx]));
 621
 622         return 0;
 623 }
 624
 625 static int
 626 qed_llh_shadow_remove_filter(struct qed_dev *cdev,
 627                              u8 ppfid,
 628                              union qed_llh_filter *p_filter,
 629                              u8 *p_filter_idx, u32 *p_ref_cnt)
 630 {
 631         int rc;
 632
 633         rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx);
 634         if (rc)
 635                 return rc;
 636
 637         /* No matching filter was found */
 638         if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
 639                 DP_NOTICE(cdev, "Failed to find a filter in the LLH shadow\n");
 640                 return -EINVAL;
 641         }
 642
 643         return __qed_llh_shadow_remove_filter(cdev, ppfid, *p_filter_idx,
 644                                               p_ref_cnt);
 645 }
 646
 647 static int qed_llh_abs_ppfid(struct qed_dev *cdev, u8 ppfid, u8 *p_abs_ppfid)
 648 {
 649         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 650
 651         if (ppfid >= p_llh_info->num_ppfid) {
 652                 DP_NOTICE(cdev,
 653                           "ppfid %d is not valid, available indices are 0..%hhd\n",
 654                           ppfid, p_llh_info->num_ppfid - 1);
 655                 *p_abs_ppfid = 0;
 656                 return -EINVAL;
 657         }
 658
 659         *p_abs_ppfid = p_llh_info->ppfid_array[ppfid];
 660
 661         return 0;
 662 }
 663
 664 static int
 665 qed_llh_set_engine_affin(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 666 {
 667         struct qed_dev *cdev = p_hwfn->cdev;
 668         enum qed_eng eng;
 669         u8 ppfid;
 670         int rc;
 671
 672         rc = qed_mcp_get_engine_config(p_hwfn, p_ptt);
 673         if (rc != 0 && rc != -EOPNOTSUPP) {
 674                 DP_NOTICE(p_hwfn,
 675                           "Failed to get the engine affinity configuration\n");
 676                 return rc;
 677         }
 678
 679         /* RoCE PF is bound to a single engine */
 680         if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
 681                 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0;
 682                 rc = qed_llh_set_roce_affinity(cdev, eng);
 683                 if (rc) {
 684                         DP_NOTICE(cdev,
 685                                   "Failed to set the RoCE engine affinity\n");
 686                         return rc;
 687                 }
 688
 689                 DP_VERBOSE(cdev,
 690                            QED_MSG_SP,
 691                            "LLH: Set the engine affinity of RoCE packets as %d\n",
 692                            eng);
 693         }
 694
 695         /* Storage PF is bound to a single engine while L2 PF uses both */
 696         if (QED_IS_FCOE_PERSONALITY(p_hwfn) || QED_IS_ISCSI_PERSONALITY(p_hwfn))
 697                 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0;
 698         else                    /* L2_PERSONALITY */
 699                 eng = QED_BOTH_ENG;
 700
 701         for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
 702                 rc = qed_llh_set_ppfid_affinity(cdev, ppfid, eng);
 703                 if (rc) {
 704                         DP_NOTICE(cdev,
 705                                   "Failed to set the engine affinity of ppfid %d\n",
 706                                   ppfid);
 707                         return rc;
 708                 }
 709         }
 710
 711         DP_VERBOSE(cdev, QED_MSG_SP,
 712                    "LLH: Set the engine affinity of non-RoCE packets as %d\n",
 713                    eng);
 714
 715         return 0;
 716 }
 717
 718 static int qed_llh_hw_init_pf(struct qed_hwfn *p_hwfn,
 719                               struct qed_ptt *p_ptt)
 720 {
 721         struct qed_dev *cdev = p_hwfn->cdev;
 722         u8 ppfid, abs_ppfid;
 723         int rc;
 724
 725         for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
 726                 u32 addr;
 727
 728                 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
 729                 if (rc)
 730                         return rc;
 731
 732                 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;
 733                 qed_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
 734         }
 735
 736         if (test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) &&
 737             !QED_IS_FCOE_PERSONALITY(p_hwfn)) {
 738                 rc = qed_llh_add_mac_filter(cdev, 0,
 739                                             p_hwfn->hw_info.hw_mac_addr);
 740                 if (rc)
 741                         DP_NOTICE(cdev,
 742                                   "Failed to add an LLH filter with the primary MAC\n");
 743         }
 744
 745         if (QED_IS_CMT(cdev)) {
 746                 rc = qed_llh_set_engine_affin(p_hwfn, p_ptt);
 747                 if (rc)
 748                         return rc;
 749         }
 750
 751         return 0;
 752 }
 753
 754 u8 qed_llh_get_num_ppfid(struct qed_dev *cdev)
 755 {
 756         return cdev->p_llh_info->num_ppfid;
 757 }
 758
 759 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK             0x3
 760 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT            0
 761 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK         0x3
 762 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT        2
 763
 764 int qed_llh_set_ppfid_affinity(struct qed_dev *cdev, u8 ppfid, enum qed_eng eng)
 765 {
 766         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
 767         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
 768         u32 addr, val, eng_sel;
 769         u8 abs_ppfid;
 770         int rc = 0;
 771
 772         if (!p_ptt)
 773                 return -EAGAIN;
 774
 775         if (!QED_IS_CMT(cdev))
 776                 goto out;
 777
 778         rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
 779         if (rc)
 780                 goto out;
 781
 782         switch (eng) {
 783         case QED_ENG0:
 784                 eng_sel = 0;
 785                 break;
 786         case QED_ENG1:
 787                 eng_sel = 1;
 788                 break;
 789         case QED_BOTH_ENG:
 790                 eng_sel = 2;
 791                 break;
 792         default:
 793                 DP_NOTICE(cdev, "Invalid affinity value for ppfid [%d]\n", eng);
 794                 rc = -EINVAL;
 795                 goto out;
 796         }
 797
 798         addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
 799         val = qed_rd(p_hwfn, p_ptt, addr);
 800         SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);
 801         qed_wr(p_hwfn, p_ptt, addr, val);
 802
 803         /* The iWARP affinity is set as the affinity of ppfid 0 */
 804         if (!ppfid && QED_IS_IWARP_PERSONALITY(p_hwfn))
 805                 cdev->iwarp_affin = (eng == QED_ENG1) ? 1 : 0;
 806 out:
 807         qed_ptt_release(p_hwfn, p_ptt);
 808
 809         return rc;
 810 }
 811
 812 int qed_llh_set_roce_affinity(struct qed_dev *cdev, enum qed_eng eng)
 813 {
 814         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
 815         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
 816         u32 addr, val, eng_sel;
 817         u8 ppfid, abs_ppfid;
 818         int rc = 0;
 819
 820         if (!p_ptt)
 821                 return -EAGAIN;
 822
 823         if (!QED_IS_CMT(cdev))
 824                 goto out;
 825
 826         switch (eng) {
 827         case QED_ENG0:
 828                 eng_sel = 0;
 829                 break;
 830         case QED_ENG1:
 831                 eng_sel = 1;
 832                 break;
 833         case QED_BOTH_ENG:
 834                 eng_sel = 2;
 835                 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,
 836                        0xf);  /* QP bit 15 */
 837                 break;
 838         default:
 839                 DP_NOTICE(cdev, "Invalid affinity value for RoCE [%d]\n", eng);
 840                 rc = -EINVAL;
 841                 goto out;
 842         }
 843
 844         for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
 845                 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
 846                 if (rc)
 847                         goto out;
 848
 849                 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
 850                 val = qed_rd(p_hwfn, p_ptt, addr);
 851                 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);
 852                 qed_wr(p_hwfn, p_ptt, addr, val);
 853         }
 854 out:
 855         qed_ptt_release(p_hwfn, p_ptt);
 856
 857         return rc;
 858 }
 859
 860 struct qed_llh_filter_details {
 861         u64 value;
 862         u32 mode;
 863         u32 protocol_type;
 864         u32 hdr_sel;
 865         u32 enable;
 866 };
 867
 868 static int
 869 qed_llh_access_filter(struct qed_hwfn *p_hwfn,
 870                       struct qed_ptt *p_ptt,
 871                       u8 abs_ppfid,
 872                       u8 filter_idx,
 873                       struct qed_llh_filter_details *p_details)
 874 {
 875         struct qed_dmae_params params = {0};
 876         u32 addr;
 877         u8 pfid;
 878         int rc;
 879
 880         /* The NIG/LLH registers that are accessed in this function have only 16
 881          * rows which are exposed to a PF. I.e. only the 16 filters of its
 882          * default ppfid. Accessing filters of other ppfids requires pretending
 883          * to another PFs.
 884          * The calculation of PPFID->PFID in AH is based on the relative index
 885          * of a PF on its port.
 886          * For BB the pfid is actually the abs_ppfid.
 887          */
 888         if (QED_IS_BB(p_hwfn->cdev))
 889                 pfid = abs_ppfid;
 890         else
 891                 pfid = abs_ppfid * p_hwfn->cdev->num_ports_in_engine +
 892                     MFW_PORT(p_hwfn);
 893
 894         /* Filter enable - should be done first when removing a filter */
 895         if (!p_details->enable) {
 896                 qed_fid_pretend(p_hwfn, p_ptt,
 897                                 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
 898
 899                 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
 900                 qed_wr(p_hwfn, p_ptt, addr, p_details->enable);
 901
 902                 qed_fid_pretend(p_hwfn, p_ptt,
 903                                 p_hwfn->rel_pf_id <<
 904                                 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
 905         }
 906
 907         /* Filter value */
 908         addr = NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * filter_idx * 0x4;
 909
 910         params.flags = QED_DMAE_FLAG_PF_DST;
 911         params.dst_pfid = pfid;
 912         rc = qed_dmae_host2grc(p_hwfn,
 913                                p_ptt,
 914                                (u64)(uintptr_t)&p_details->value,
 915                                addr, 2 /* size_in_dwords */,
 916                                &params);
 917         if (rc)
 918                 return rc;
 919
 920         qed_fid_pretend(p_hwfn, p_ptt,
 921                         pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
 922
 923         /* Filter mode */
 924         addr = NIG_REG_LLH_FUNC_FILTER_MODE + filter_idx * 0x4;
 925         qed_wr(p_hwfn, p_ptt, addr, p_details->mode);
 926
 927         /* Filter protocol type */
 928         addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + filter_idx * 0x4;
 929         qed_wr(p_hwfn, p_ptt, addr, p_details->protocol_type);
 930
 931         /* Filter header select */
 932         addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4;
 933         qed_wr(p_hwfn, p_ptt, addr, p_details->hdr_sel);
 934
 935         /* Filter enable - should be done last when adding a filter */
 936         if (p_details->enable) {
 937                 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
 938                 qed_wr(p_hwfn, p_ptt, addr, p_details->enable);
 939         }
 940
 941         qed_fid_pretend(p_hwfn, p_ptt,
 942                         p_hwfn->rel_pf_id <<
 943                         PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
 944
 945         return 0;
 946 }
 947
 948 static int
 949 qed_llh_add_filter(struct qed_hwfn *p_hwfn,
 950                    struct qed_ptt *p_ptt,
 951                    u8 abs_ppfid,
 952                    u8 filter_idx, u8 filter_prot_type, u32 high, u32 low)
 953 {
 954         struct qed_llh_filter_details filter_details;
 955
 956         filter_details.enable = 1;
 957         filter_details.value = ((u64)high << 32) | low;
 958         filter_details.hdr_sel = 0;
 959         filter_details.protocol_type = filter_prot_type;
 960         /* Mode: 0: MAC-address classification 1: protocol classification */
 961         filter_details.mode = filter_prot_type ? 1 : 0;
 962
 963         return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
 964                                      &filter_details);
 965 }
 966
 967 static int
 968 qed_llh_remove_filter(struct qed_hwfn *p_hwfn,
 969                       struct qed_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)
 970 {
 971         struct qed_llh_filter_details filter_details = {0};
 972
 973         return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
 974                                      &filter_details);
 975 }
 976
 977 int qed_llh_add_mac_filter(struct qed_dev *cdev,
 978                            u8 ppfid, u8 mac_addr[ETH_ALEN])
 979 {
 980         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
 981         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
 982         union qed_llh_filter filter = {};
 983         u8 filter_idx, abs_ppfid;
 984         u32 high, low, ref_cnt;
 985         int rc = 0;
 986
 987         if (!p_ptt)
 988                 return -EAGAIN;
 989
 990         if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
 991                 goto out;
 992
 993         memcpy(filter.mac.addr, mac_addr, ETH_ALEN);
 994         rc = qed_llh_shadow_add_filter(cdev, ppfid,
 995                                        QED_LLH_FILTER_TYPE_MAC,
 996                                        &filter, &filter_idx, &ref_cnt);
 997         if (rc)
 998                 goto err;
 999
1000         /* Configure the LLH only in case of a new the filter */
1001         if (ref_cnt == 1) {
1002                 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1003                 if (rc)
1004                         goto err;
1005
1006                 high = mac_addr[1] | (mac_addr[0] << 8);
1007                 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |
1008                       (mac_addr[2] << 24);
1009                 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1010                                         0, high, low);
1011                 if (rc)
1012                         goto err;
1013         }
1014
1015         DP_VERBOSE(cdev,
1016                    QED_MSG_SP,
1017                    "LLH: Added MAC filter [%pM] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1018                    mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt);
1019
1020         goto out;
1021
1022 err:    DP_NOTICE(cdev,
1023                   "LLH: Failed to add MAC filter [%pM] to ppfid %hhd\n",
1024                   mac_addr, ppfid);
1025 out:
1026         qed_ptt_release(p_hwfn, p_ptt);
1027
1028         return rc;
1029 }
1030
1031 static int
1032 qed_llh_protocol_filter_stringify(struct qed_dev *cdev,
1033                                   enum qed_llh_prot_filter_type_t type,
1034                                   u16 source_port_or_eth_type,
1035                                   u16 dest_port, u8 *str, size_t str_len)
1036 {
1037         switch (type) {
1038         case QED_LLH_FILTER_ETHERTYPE:
1039                 snprintf(str, str_len, "Ethertype 0x%04x",
1040                          source_port_or_eth_type);
1041                 break;
1042         case QED_LLH_FILTER_TCP_SRC_PORT:
1043                 snprintf(str, str_len, "TCP src port 0x%04x",
1044                          source_port_or_eth_type);
1045                 break;
1046         case QED_LLH_FILTER_UDP_SRC_PORT:
1047                 snprintf(str, str_len, "UDP src port 0x%04x",
1048                          source_port_or_eth_type);
1049                 break;
1050         case QED_LLH_FILTER_TCP_DEST_PORT:
1051                 snprintf(str, str_len, "TCP dst port 0x%04x", dest_port);
1052                 break;
1053         case QED_LLH_FILTER_UDP_DEST_PORT:
1054                 snprintf(str, str_len, "UDP dst port 0x%04x", dest_port);
1055                 break;
1056         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1057                 snprintf(str, str_len, "TCP src/dst ports 0x%04x/0x%04x",
1058                          source_port_or_eth_type, dest_port);
1059                 break;
1060         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1061                 snprintf(str, str_len, "UDP src/dst ports 0x%04x/0x%04x",
1062                          source_port_or_eth_type, dest_port);
1063                 break;
1064         default:
1065                 DP_NOTICE(cdev,
1066                           "Non valid LLH protocol filter type %d\n", type);
1067                 return -EINVAL;
1068         }
1069
1070         return 0;
1071 }
1072
1073 static int
1074 qed_llh_protocol_filter_to_hilo(struct qed_dev *cdev,
1075                                 enum qed_llh_prot_filter_type_t type,
1076                                 u16 source_port_or_eth_type,
1077                                 u16 dest_port, u32 *p_high, u32 *p_low)
1078 {
1079         *p_high = 0;
1080         *p_low = 0;
1081
1082         switch (type) {
1083         case QED_LLH_FILTER_ETHERTYPE:
1084                 *p_high = source_port_or_eth_type;
1085                 break;
1086         case QED_LLH_FILTER_TCP_SRC_PORT:
1087         case QED_LLH_FILTER_UDP_SRC_PORT:
1088                 *p_low = source_port_or_eth_type << 16;
1089                 break;
1090         case QED_LLH_FILTER_TCP_DEST_PORT:
1091         case QED_LLH_FILTER_UDP_DEST_PORT:
1092                 *p_low = dest_port;
1093                 break;
1094         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1095         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1096                 *p_low = (source_port_or_eth_type << 16) | dest_port;
1097                 break;
1098         default:
1099                 DP_NOTICE(cdev,
1100                           "Non valid LLH protocol filter type %d\n", type);
1101                 return -EINVAL;
1102         }
1103
1104         return 0;
1105 }
1106
1107 int
1108 qed_llh_add_protocol_filter(struct qed_dev *cdev,
1109                             u8 ppfid,
1110                             enum qed_llh_prot_filter_type_t type,
1111                             u16 source_port_or_eth_type, u16 dest_port)
1112 {
1113         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1114         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1115         u8 filter_idx, abs_ppfid, str[32], type_bitmap;
1116         union qed_llh_filter filter = {};
1117         u32 high, low, ref_cnt;
1118         int rc = 0;
1119
1120         if (!p_ptt)
1121                 return -EAGAIN;
1122
1123         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits))
1124                 goto out;
1125
1126         rc = qed_llh_protocol_filter_stringify(cdev, type,
1127                                                source_port_or_eth_type,
1128                                                dest_port, str, sizeof(str));
1129         if (rc)
1130                 goto err;
1131
1132         filter.protocol.type = type;
1133         filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1134         filter.protocol.dest_port = dest_port;
1135         rc = qed_llh_shadow_add_filter(cdev,
1136                                        ppfid,
1137                                        QED_LLH_FILTER_TYPE_PROTOCOL,
1138                                        &filter, &filter_idx, &ref_cnt);
1139         if (rc)
1140                 goto err;
1141
1142         rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1143         if (rc)
1144                 goto err;
1145
1146         /* Configure the LLH only in case of a new the filter */
1147         if (ref_cnt == 1) {
1148                 rc = qed_llh_protocol_filter_to_hilo(cdev, type,
1149                                                      source_port_or_eth_type,
1150                                                      dest_port, &high, &low);
1151                 if (rc)
1152                         goto err;
1153
1154                 type_bitmap = 0x1 << type;
1155                 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid,
1156                                         filter_idx, type_bitmap, high, low);
1157                 if (rc)
1158                         goto err;
1159         }
1160
1161         DP_VERBOSE(cdev,
1162                    QED_MSG_SP,
1163                    "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1164                    str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1165
1166         goto out;
1167
1168 err:    DP_NOTICE(p_hwfn,
1169                   "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n",
1170                   str, ppfid);
1171 out:
1172         qed_ptt_release(p_hwfn, p_ptt);
1173
1174         return rc;
1175 }
1176
1177 void qed_llh_remove_mac_filter(struct qed_dev *cdev,
1178                                u8 ppfid, u8 mac_addr[ETH_ALEN])
1179 {
1180         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1181         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1182         union qed_llh_filter filter = {};
1183         u8 filter_idx, abs_ppfid;
1184         int rc = 0;
1185         u32 ref_cnt;
1186
1187         if (!p_ptt)
1188                 return;
1189
1190         if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
1191                 goto out;
1192
1193         ether_addr_copy(filter.mac.addr, mac_addr);
1194         rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx,
1195                                           &ref_cnt);
1196         if (rc)
1197                 goto err;
1198
1199         rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1200         if (rc)
1201                 goto err;
1202
1203         /* Remove from the LLH in case the filter is not in use */
1204         if (!ref_cnt) {
1205                 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1206                                            filter_idx);
1207                 if (rc)
1208                         goto err;
1209         }
1210
1211         DP_VERBOSE(cdev,
1212                    QED_MSG_SP,
1213                    "LLH: Removed MAC filter [%pM] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1214                    mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt);
1215
1216         goto out;
1217
1218 err:    DP_NOTICE(cdev,
1219                   "LLH: Failed to remove MAC filter [%pM] from ppfid %hhd\n",
1220                   mac_addr, ppfid);
1221 out:
1222         qed_ptt_release(p_hwfn, p_ptt);
1223 }
1224
1225 void qed_llh_remove_protocol_filter(struct qed_dev *cdev,
1226                                     u8 ppfid,
1227                                     enum qed_llh_prot_filter_type_t type,
1228                                     u16 source_port_or_eth_type, u16 dest_port)
1229 {
1230         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1231         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1232         u8 filter_idx, abs_ppfid, str[32];
1233         union qed_llh_filter filter = {};
1234         int rc = 0;
1235         u32 ref_cnt;
1236
1237         if (!p_ptt)
1238                 return;
1239
1240         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits))
1241                 goto out;
1242
1243         rc = qed_llh_protocol_filter_stringify(cdev, type,
1244                                                source_port_or_eth_type,
1245                                                dest_port, str, sizeof(str));
1246         if (rc)
1247                 goto err;
1248
1249         filter.protocol.type = type;
1250         filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1251         filter.protocol.dest_port = dest_port;
1252         rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx,
1253                                           &ref_cnt);
1254         if (rc)
1255                 goto err;
1256
1257         rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1258         if (rc)
1259                 goto err;
1260
1261         /* Remove from the LLH in case the filter is not in use */
1262         if (!ref_cnt) {
1263                 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1264                                            filter_idx);
1265                 if (rc)
1266                         goto err;
1267         }
1268
1269         DP_VERBOSE(cdev,
1270                    QED_MSG_SP,
1271                    "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1272                    str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1273
1274         goto out;
1275
1276 err:    DP_NOTICE(cdev,
1277                   "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n",
1278                   str, ppfid);
1279 out:
1280         qed_ptt_release(p_hwfn, p_ptt);
1281 }
1282
1283 /******************************* NIG LLH - End ********************************/
1284
1285 #define QED_MIN_DPIS            (4)
1286 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
1287
1288 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
1289                            struct qed_ptt *p_ptt, enum BAR_ID bar_id)
1290 {
1291         u32 bar_reg = (bar_id == BAR_ID_0 ?
1292                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
1293         u32 val;
1294
1295         if (IS_VF(p_hwfn->cdev))
1296                 return qed_vf_hw_bar_size(p_hwfn, bar_id);
1297
1298         val = qed_rd(p_hwfn, p_ptt, bar_reg);
1299         if (val)
1300                 return 1 << (val + 15);
1301
1302         /* Old MFW initialized above registered only conditionally */
1303         if (p_hwfn->cdev->num_hwfns > 1) {
1304                 DP_INFO(p_hwfn,
1305                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
1306                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
1307         } else {
1308                 DP_INFO(p_hwfn,
1309                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
1310                         return 512 * 1024;
1311         }
1312 }
1313
1314 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
1315 {
1316         u32 i;
1317
1318         cdev->dp_level = dp_level;
1319         cdev->dp_module = dp_module;
1320         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1321                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1322
1323                 p_hwfn->dp_level = dp_level;
1324                 p_hwfn->dp_module = dp_module;
1325         }
1326 }
1327
1328 void qed_init_struct(struct qed_dev *cdev)
1329 {
1330         u8 i;
1331
1332         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1333                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1334
1335                 p_hwfn->cdev = cdev;
1336                 p_hwfn->my_id = i;
1337                 p_hwfn->b_active = false;
1338
1339                 mutex_init(&p_hwfn->dmae_info.mutex);
1340         }
1341
1342         /* hwfn 0 is always active */
1343         cdev->hwfns[0].b_active = true;
1344
1345         /* set the default cache alignment to 128 */
1346         cdev->cache_shift = 7;
1347 }
1348
1349 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
1350 {
1351         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1352
1353         kfree(qm_info->qm_pq_params);
1354         qm_info->qm_pq_params = NULL;
1355         kfree(qm_info->qm_vport_params);
1356         qm_info->qm_vport_params = NULL;
1357         kfree(qm_info->qm_port_params);
1358         qm_info->qm_port_params = NULL;
1359         kfree(qm_info->wfq_data);
1360         qm_info->wfq_data = NULL;
1361 }
1362
1363 static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn)
1364 {
1365         kfree(p_hwfn->dbg_user_info);
1366         p_hwfn->dbg_user_info = NULL;
1367 }
1368
1369 void qed_resc_free(struct qed_dev *cdev)
1370 {
1371         int i;
1372
1373         if (IS_VF(cdev)) {
1374                 for_each_hwfn(cdev, i)
1375                         qed_l2_free(&cdev->hwfns[i]);
1376                 return;
1377         }
1378
1379         kfree(cdev->fw_data);
1380         cdev->fw_data = NULL;
1381
1382         kfree(cdev->reset_stats);
1383         cdev->reset_stats = NULL;
1384
1385         qed_llh_free(cdev);
1386
1387         for_each_hwfn(cdev, i) {
1388                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1389
1390                 qed_cxt_mngr_free(p_hwfn);
1391                 qed_qm_info_free(p_hwfn);
1392                 qed_spq_free(p_hwfn);
1393                 qed_eq_free(p_hwfn);
1394                 qed_consq_free(p_hwfn);
1395                 qed_int_free(p_hwfn);
1396 #ifdef CONFIG_QED_LL2
1397                 qed_ll2_free(p_hwfn);
1398 #endif
1399                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1400                         qed_fcoe_free(p_hwfn);
1401
1402                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1403                         qed_iscsi_free(p_hwfn);
1404                         qed_ooo_free(p_hwfn);
1405                 }
1406
1407                 if (QED_IS_RDMA_PERSONALITY(p_hwfn))
1408                         qed_rdma_info_free(p_hwfn);
1409
1410                 qed_iov_free(p_hwfn);
1411                 qed_l2_free(p_hwfn);
1412                 qed_dmae_info_free(p_hwfn);
1413                 qed_dcbx_info_free(p_hwfn);
1414                 qed_dbg_user_data_free(p_hwfn);
1415
1416                 /* Destroy doorbell recovery mechanism */
1417                 qed_db_recovery_teardown(p_hwfn);
1418         }
1419 }
1420
1421 /******************** QM initialization *******************/
1422 #define ACTIVE_TCS_BMAP 0x9f
1423 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
1424
1425 /* determines the physical queue flags for a given PF. */
1426 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
1427 {
1428         u32 flags;
1429
1430         /* common flags */
1431         flags = PQ_FLAGS_LB;
1432
1433         /* feature flags */
1434         if (IS_QED_SRIOV(p_hwfn->cdev))
1435                 flags |= PQ_FLAGS_VFS;
1436
1437         /* protocol flags */
1438         switch (p_hwfn->hw_info.personality) {
1439         case QED_PCI_ETH:
1440                 flags |= PQ_FLAGS_MCOS;
1441                 break;
1442         case QED_PCI_FCOE:
1443                 flags |= PQ_FLAGS_OFLD;
1444                 break;
1445         case QED_PCI_ISCSI:
1446                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1447                 break;
1448         case QED_PCI_ETH_ROCE:
1449                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
1450                 if (IS_QED_MULTI_TC_ROCE(p_hwfn))
1451                         flags |= PQ_FLAGS_MTC;
1452                 break;
1453         case QED_PCI_ETH_IWARP:
1454                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
1455                     PQ_FLAGS_OFLD;
1456                 break;
1457         default:
1458                 DP_ERR(p_hwfn,
1459                        "unknown personality %d\n", p_hwfn->hw_info.personality);
1460                 return 0;
1461         }
1462
1463         return flags;
1464 }
1465
1466 /* Getters for resource amounts necessary for qm initialization */
1467 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
1468 {
1469         return p_hwfn->hw_info.num_hw_tc;
1470 }
1471
1472 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
1473 {
1474         return IS_QED_SRIOV(p_hwfn->cdev) ?
1475                p_hwfn->cdev->p_iov_info->total_vfs : 0;
1476 }
1477
1478 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn)
1479 {
1480         u32 pq_flags = qed_get_pq_flags(p_hwfn);
1481
1482         if (!(PQ_FLAGS_MTC & pq_flags))
1483                 return 1;
1484
1485         return qed_init_qm_get_num_tcs(p_hwfn);
1486 }
1487
1488 #define NUM_DEFAULT_RLS 1
1489
1490 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
1491 {
1492         u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
1493
1494         /* num RLs can't exceed resource amount of rls or vports */
1495         num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
1496                                  RESC_NUM(p_hwfn, QED_VPORT));
1497
1498         /* Make sure after we reserve there's something left */
1499         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
1500                 return 0;
1501
1502         /* subtract rls necessary for VFs and one default one for the PF */
1503         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
1504
1505         return num_pf_rls;
1506 }
1507
1508 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
1509 {
1510         u32 pq_flags = qed_get_pq_flags(p_hwfn);
1511
1512         /* all pqs share the same vport, except for vfs and pf_rl pqs */
1513         return (!!(PQ_FLAGS_RLS & pq_flags)) *
1514                qed_init_qm_get_num_pf_rls(p_hwfn) +
1515                (!!(PQ_FLAGS_VFS & pq_flags)) *
1516                qed_init_qm_get_num_vfs(p_hwfn) + 1;
1517 }
1518
1519 /* calc amount of PQs according to the requested flags */
1520 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
1521 {
1522         u32 pq_flags = qed_get_pq_flags(p_hwfn);
1523
1524         return (!!(PQ_FLAGS_RLS & pq_flags)) *
1525                qed_init_qm_get_num_pf_rls(p_hwfn) +
1526                (!!(PQ_FLAGS_MCOS & pq_flags)) *
1527                qed_init_qm_get_num_tcs(p_hwfn) +
1528                (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
1529                (!!(PQ_FLAGS_ACK & pq_flags)) +
1530                (!!(PQ_FLAGS_OFLD & pq_flags)) *
1531                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
1532                (!!(PQ_FLAGS_LLT & pq_flags)) *
1533                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
1534                (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
1535 }
1536
1537 /* initialize the top level QM params */
1538 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
1539 {
1540         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1541         bool four_port;
1542
1543         /* pq and vport bases for this PF */
1544         qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
1545         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
1546
1547         /* rate limiting and weighted fair queueing are always enabled */
1548         qm_info->vport_rl_en = true;
1549         qm_info->vport_wfq_en = true;
1550
1551         /* TC config is different for AH 4 port */
1552         four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
1553
1554         /* in AH 4 port we have fewer TCs per port */
1555         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
1556                                                      NUM_OF_PHYS_TCS;
1557
1558         /* unless MFW indicated otherwise, ooo_tc == 3 for
1559          * AH 4-port and 4 otherwise.
1560          */
1561         if (!qm_info->ooo_tc)
1562                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
1563                                               DCBX_TCP_OOO_TC;
1564 }
1565
1566 /* initialize qm vport params */
1567 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
1568 {
1569         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1570         u8 i;
1571
1572         /* all vports participate in weighted fair queueing */
1573         for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
1574                 qm_info->qm_vport_params[i].vport_wfq = 1;
1575 }
1576
1577 /* initialize qm port params */
1578 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
1579 {
1580         /* Initialize qm port parameters */
1581         u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
1582
1583         /* indicate how ooo and high pri traffic is dealt with */
1584         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
1585                           ACTIVE_TCS_BMAP_4PORT_K2 :
1586                           ACTIVE_TCS_BMAP;
1587
1588         for (i = 0; i < num_ports; i++) {
1589                 struct init_qm_port_params *p_qm_port =
1590                     &p_hwfn->qm_info.qm_port_params[i];
1591
1592                 p_qm_port->active = 1;
1593                 p_qm_port->active_phys_tcs = active_phys_tcs;
1594                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
1595                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
1596         }
1597 }
1598
1599 /* Reset the params which must be reset for qm init. QM init may be called as
1600  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
1601  * params may be affected by the init but would simply recalculate to the same
1602  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
1603  * affected as these amounts stay the same.
1604  */
1605 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
1606 {
1607         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1608
1609         qm_info->num_pqs = 0;
1610         qm_info->num_vports = 0;
1611         qm_info->num_pf_rls = 0;
1612         qm_info->num_vf_pqs = 0;
1613         qm_info->first_vf_pq = 0;
1614         qm_info->first_mcos_pq = 0;
1615         qm_info->first_rl_pq = 0;
1616 }
1617
1618 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
1619 {
1620         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1621
1622         qm_info->num_vports++;
1623
1624         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
1625                 DP_ERR(p_hwfn,
1626                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
1627                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
1628 }
1629
1630 /* initialize a single pq and manage qm_info resources accounting.
1631  * The pq_init_flags param determines whether the PQ is rate limited
1632  * (for VF or PF) and whether a new vport is allocated to the pq or not
1633  * (i.e. vport will be shared).
1634  */
1635
1636 /* flags for pq init */
1637 #define PQ_INIT_SHARE_VPORT     (1 << 0)
1638 #define PQ_INIT_PF_RL           (1 << 1)
1639 #define PQ_INIT_VF_RL           (1 << 2)
1640
1641 /* defines for pq init */
1642 #define PQ_INIT_DEFAULT_WRR_GROUP       1
1643 #define PQ_INIT_DEFAULT_TC              0
1644
1645 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc)
1646 {
1647         p_info->offload_tc = tc;
1648         p_info->offload_tc_set = true;
1649 }
1650
1651 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn)
1652 {
1653         return p_hwfn->hw_info.offload_tc_set;
1654 }
1655
1656 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn)
1657 {
1658         if (qed_is_offload_tc_set(p_hwfn))
1659                 return p_hwfn->hw_info.offload_tc;
1660
1661         return PQ_INIT_DEFAULT_TC;
1662 }
1663
1664 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
1665                            struct qed_qm_info *qm_info,
1666                            u8 tc, u32 pq_init_flags)
1667 {
1668         u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
1669
1670         if (pq_idx > max_pq)
1671                 DP_ERR(p_hwfn,
1672                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
1673
1674         /* init pq params */
1675         qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
1676         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
1677             qm_info->num_vports;
1678         qm_info->qm_pq_params[pq_idx].tc_id = tc;
1679         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
1680         qm_info->qm_pq_params[pq_idx].rl_valid =
1681             (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
1682
1683         /* qm params accounting */
1684         qm_info->num_pqs++;
1685         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
1686                 qm_info->num_vports++;
1687
1688         if (pq_init_flags & PQ_INIT_PF_RL)
1689                 qm_info->num_pf_rls++;
1690
1691         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
1692                 DP_ERR(p_hwfn,
1693                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
1694                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
1695
1696         if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
1697                 DP_ERR(p_hwfn,
1698                        "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
1699                        qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
1700 }
1701
1702 /* get pq index according to PQ_FLAGS */
1703 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
1704                                            unsigned long pq_flags)
1705 {
1706         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1707
1708         /* Can't have multiple flags set here */
1709         if (bitmap_weight(&pq_flags,
1710                           sizeof(pq_flags) * BITS_PER_BYTE) > 1) {
1711                 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags);
1712                 goto err;
1713         }
1714
1715         if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) {
1716                 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags);
1717                 goto err;
1718         }
1719
1720         switch (pq_flags) {
1721         case PQ_FLAGS_RLS:
1722                 return &qm_info->first_rl_pq;
1723         case PQ_FLAGS_MCOS:
1724                 return &qm_info->first_mcos_pq;
1725         case PQ_FLAGS_LB:
1726                 return &qm_info->pure_lb_pq;
1727         case PQ_FLAGS_OOO:
1728                 return &qm_info->ooo_pq;
1729         case PQ_FLAGS_ACK:
1730                 return &qm_info->pure_ack_pq;
1731         case PQ_FLAGS_OFLD:
1732                 return &qm_info->first_ofld_pq;
1733         case PQ_FLAGS_LLT:
1734                 return &qm_info->first_llt_pq;
1735         case PQ_FLAGS_VFS:
1736                 return &qm_info->first_vf_pq;
1737         default:
1738                 goto err;
1739         }
1740
1741 err:
1742         return &qm_info->start_pq;
1743 }
1744
1745 /* save pq index in qm info */
1746 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
1747                                 u32 pq_flags, u16 pq_val)
1748 {
1749         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1750
1751         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
1752 }
1753
1754 /* get tx pq index, with the PQ TX base already set (ready for context init) */
1755 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
1756 {
1757         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1758
1759         return *base_pq_idx + CM_TX_PQ_BASE;
1760 }
1761
1762 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
1763 {
1764         u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
1765
1766         if (max_tc == 0) {
1767                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
1768                        PQ_FLAGS_MCOS);
1769                 return p_hwfn->qm_info.start_pq;
1770         }
1771
1772         if (tc > max_tc)
1773                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
1774
1775         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
1776 }
1777
1778 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
1779 {
1780         u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
1781
1782         if (max_vf == 0) {
1783                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
1784                        PQ_FLAGS_VFS);
1785                 return p_hwfn->qm_info.start_pq;
1786         }
1787
1788         if (vf > max_vf)
1789                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
1790
1791         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
1792 }
1793
1794 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc)
1795 {
1796         u16 first_ofld_pq, pq_offset;
1797
1798         first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
1799         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
1800                     tc : PQ_INIT_DEFAULT_TC;
1801
1802         return first_ofld_pq + pq_offset;
1803 }
1804
1805 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc)
1806 {
1807         u16 first_llt_pq, pq_offset;
1808
1809         first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT);
1810         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
1811                     tc : PQ_INIT_DEFAULT_TC;
1812
1813         return first_llt_pq + pq_offset;
1814 }
1815
1816 /* Functions for creating specific types of pqs */
1817 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
1818 {
1819         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1820
1821         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
1822                 return;
1823
1824         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
1825         qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
1826 }
1827
1828 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
1829 {
1830         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1831
1832         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
1833                 return;
1834
1835         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
1836         qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
1837 }
1838
1839 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
1840 {
1841         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1842
1843         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
1844                 return;
1845
1846         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
1847         qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1848                        PQ_INIT_SHARE_VPORT);
1849 }
1850
1851 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn)
1852 {
1853         u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn);
1854         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1855         u8 tc;
1856
1857         /* override pq's TC if offload TC is set */
1858         for (tc = 0; tc < num_tcs; tc++)
1859                 qed_init_qm_pq(p_hwfn, qm_info,
1860                                qed_is_offload_tc_set(p_hwfn) ?
1861                                p_hwfn->hw_info.offload_tc : tc,
1862                                PQ_INIT_SHARE_VPORT);
1863 }
1864
1865 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
1866 {
1867         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1868
1869         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
1870                 return;
1871
1872         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
1873         qed_init_qm_mtc_pqs(p_hwfn);
1874 }
1875
1876 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
1877 {
1878         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1879
1880         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
1881                 return;
1882
1883         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
1884         qed_init_qm_mtc_pqs(p_hwfn);
1885 }
1886
1887 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
1888 {
1889         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1890         u8 tc_idx;
1891
1892         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
1893                 return;
1894
1895         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
1896         for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
1897                 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
1898 }
1899
1900 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
1901 {
1902         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1903         u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
1904
1905         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
1906                 return;
1907
1908         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
1909         qm_info->num_vf_pqs = num_vfs;
1910         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
1911                 qed_init_qm_pq(p_hwfn,
1912                                qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
1913 }
1914
1915 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
1916 {
1917         u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
1918         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1919
1920         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
1921                 return;
1922
1923         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
1924         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
1925                 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1926                                PQ_INIT_PF_RL);
1927 }
1928
1929 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
1930 {
1931         /* rate limited pqs, must come first (FW assumption) */
1932         qed_init_qm_rl_pqs(p_hwfn);
1933
1934         /* pqs for multi cos */
1935         qed_init_qm_mcos_pqs(p_hwfn);
1936
1937         /* pure loopback pq */
1938         qed_init_qm_lb_pq(p_hwfn);
1939
1940         /* out of order pq */
1941         qed_init_qm_ooo_pq(p_hwfn);
1942
1943         /* pure ack pq */
1944         qed_init_qm_pure_ack_pq(p_hwfn);
1945
1946         /* pq for offloaded protocol */
1947         qed_init_qm_offload_pq(p_hwfn);
1948
1949         /* low latency pq */
1950         qed_init_qm_low_latency_pq(p_hwfn);
1951
1952         /* done sharing vports */
1953         qed_init_qm_advance_vport(p_hwfn);
1954
1955         /* pqs for vfs */
1956         qed_init_qm_vf_pqs(p_hwfn);
1957 }
1958
1959 /* compare values of getters against resources amounts */
1960 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
1961 {
1962         if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
1963                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
1964                 return -EINVAL;
1965         }
1966
1967         if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1968                 return 0;
1969
1970         if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
1971                 p_hwfn->hw_info.multi_tc_roce_en = 0;
1972                 DP_NOTICE(p_hwfn,
1973                           "multi-tc roce was disabled to reduce requested amount of pqs\n");
1974                 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1975                         return 0;
1976         }
1977
1978         DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1979         return -EINVAL;
1980 }
1981
1982 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
1983 {
1984         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1985         struct init_qm_vport_params *vport;
1986         struct init_qm_port_params *port;
1987         struct init_qm_pq_params *pq;
1988         int i, tc;
1989
1990         /* top level params */
1991         DP_VERBOSE(p_hwfn,
1992                    NETIF_MSG_HW,
1993                    "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n",
1994                    qm_info->start_pq,
1995                    qm_info->start_vport,
1996                    qm_info->pure_lb_pq,
1997                    qm_info->first_ofld_pq,
1998                    qm_info->first_llt_pq,
1999                    qm_info->pure_ack_pq);
2000         DP_VERBOSE(p_hwfn,
2001                    NETIF_MSG_HW,
2002                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
2003                    qm_info->ooo_pq,
2004                    qm_info->first_vf_pq,
2005                    qm_info->num_pqs,
2006                    qm_info->num_vf_pqs,
2007                    qm_info->num_vports, qm_info->max_phys_tcs_per_port);
2008         DP_VERBOSE(p_hwfn,
2009                    NETIF_MSG_HW,
2010                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
2011                    qm_info->pf_rl_en,
2012                    qm_info->pf_wfq_en,
2013                    qm_info->vport_rl_en,
2014                    qm_info->vport_wfq_en,
2015                    qm_info->pf_wfq,
2016                    qm_info->pf_rl,
2017                    qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
2018
2019         /* port table */
2020         for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
2021                 port = &(qm_info->qm_port_params[i]);
2022                 DP_VERBOSE(p_hwfn,
2023                            NETIF_MSG_HW,
2024                            "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
2025                            i,
2026                            port->active,
2027                            port->active_phys_tcs,
2028                            port->num_pbf_cmd_lines,
2029                            port->num_btb_blocks, port->reserved);
2030         }
2031
2032         /* vport table */
2033         for (i = 0; i < qm_info->num_vports; i++) {
2034                 vport = &(qm_info->qm_vport_params[i]);
2035                 DP_VERBOSE(p_hwfn,
2036                            NETIF_MSG_HW,
2037                            "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
2038                            qm_info->start_vport + i,
2039                            vport->vport_rl, vport->vport_wfq);
2040                 for (tc = 0; tc < NUM_OF_TCS; tc++)
2041                         DP_VERBOSE(p_hwfn,
2042                                    NETIF_MSG_HW,
2043                                    "%d ", vport->first_tx_pq_id[tc]);
2044                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
2045         }
2046
2047         /* pq table */
2048         for (i = 0; i < qm_info->num_pqs; i++) {
2049                 pq = &(qm_info->qm_pq_params[i]);
2050                 DP_VERBOSE(p_hwfn,
2051                            NETIF_MSG_HW,
2052                            "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
2053                            qm_info->start_pq + i,
2054                            pq->port_id,
2055                            pq->vport_id,
2056                            pq->tc_id, pq->wrr_group, pq->rl_valid);
2057         }
2058 }
2059
2060 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
2061 {
2062         /* reset params required for init run */
2063         qed_init_qm_reset_params(p_hwfn);
2064
2065         /* init QM top level params */
2066         qed_init_qm_params(p_hwfn);
2067
2068         /* init QM port params */
2069         qed_init_qm_port_params(p_hwfn);
2070
2071         /* init QM vport params */
2072         qed_init_qm_vport_params(p_hwfn);
2073
2074         /* init QM physical queue params */
2075         qed_init_qm_pq_params(p_hwfn);
2076
2077         /* display all that init */
2078         qed_dp_init_qm_params(p_hwfn);
2079 }
2080
2081 /* This function reconfigures the QM pf on the fly.
2082  * For this purpose we:
2083  * 1. reconfigure the QM database
2084  * 2. set new values to runtime array
2085  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
2086  * 4. activate init tool in QM_PF stage
2087  * 5. send an sdm_qm_cmd through rbc interface to release the QM
2088  */
2089 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2090 {
2091         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2092         bool b_rc;
2093         int rc;
2094
2095         /* initialize qed's qm data structure */
2096         qed_init_qm_info(p_hwfn);
2097
2098         /* stop PF's qm queues */
2099         spin_lock_bh(&qm_lock);
2100         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
2101                                     qm_info->start_pq, qm_info->num_pqs);
2102         spin_unlock_bh(&qm_lock);
2103         if (!b_rc)
2104                 return -EINVAL;
2105
2106         /* clear the QM_PF runtime phase leftovers from previous init */
2107         qed_init_clear_rt_data(p_hwfn);
2108
2109         /* prepare QM portion of runtime array */
2110         qed_qm_init_pf(p_hwfn, p_ptt, false);
2111
2112         /* activate init tool on runtime array */
2113         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
2114                           p_hwfn->hw_info.hw_mode);
2115         if (rc)
2116                 return rc;
2117
2118         /* start PF's qm queues */
2119         spin_lock_bh(&qm_lock);
2120         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
2121                                     qm_info->start_pq, qm_info->num_pqs);
2122         spin_unlock_bh(&qm_lock);
2123         if (!b_rc)
2124                 return -EINVAL;
2125
2126         return 0;
2127 }
2128
2129 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
2130 {
2131         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2132         int rc;
2133
2134         rc = qed_init_qm_sanity(p_hwfn);
2135         if (rc)
2136                 goto alloc_err;
2137
2138         qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn),
2139                                         sizeof(*qm_info->qm_pq_params),
2140                                         GFP_KERNEL);
2141         if (!qm_info->qm_pq_params)
2142                 goto alloc_err;
2143
2144         qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
2145                                            sizeof(*qm_info->qm_vport_params),
2146                                            GFP_KERNEL);
2147         if (!qm_info->qm_vport_params)
2148                 goto alloc_err;
2149
2150         qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine,
2151                                           sizeof(*qm_info->qm_port_params),
2152                                           GFP_KERNEL);
2153         if (!qm_info->qm_port_params)
2154                 goto alloc_err;
2155
2156         qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
2157                                     sizeof(*qm_info->wfq_data),
2158                                     GFP_KERNEL);
2159         if (!qm_info->wfq_data)
2160                 goto alloc_err;
2161
2162         return 0;
2163
2164 alloc_err:
2165         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
2166         qed_qm_info_free(p_hwfn);
2167         return -ENOMEM;
2168 }
2169
2170 int qed_resc_alloc(struct qed_dev *cdev)
2171 {
2172         u32 rdma_tasks, excess_tasks;
2173         u32 line_count;
2174         int i, rc = 0;
2175
2176         if (IS_VF(cdev)) {
2177                 for_each_hwfn(cdev, i) {
2178                         rc = qed_l2_alloc(&cdev->hwfns[i]);
2179                         if (rc)
2180                                 return rc;
2181                 }
2182                 return rc;
2183         }
2184
2185         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
2186         if (!cdev->fw_data)
2187                 return -ENOMEM;
2188
2189         for_each_hwfn(cdev, i) {
2190                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2191                 u32 n_eqes, num_cons;
2192
2193                 /* Initialize the doorbell recovery mechanism */
2194                 rc = qed_db_recovery_setup(p_hwfn);
2195                 if (rc)
2196                         goto alloc_err;
2197
2198                 /* First allocate the context manager structure */
2199                 rc = qed_cxt_mngr_alloc(p_hwfn);
2200                 if (rc)
2201                         goto alloc_err;
2202
2203                 /* Set the HW cid/tid numbers (in the contest manager)
2204                  * Must be done prior to any further computations.
2205                  */
2206                 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
2207                 if (rc)
2208                         goto alloc_err;
2209
2210                 rc = qed_alloc_qm_data(p_hwfn);
2211                 if (rc)
2212                         goto alloc_err;
2213
2214                 /* init qm info */
2215                 qed_init_qm_info(p_hwfn);
2216
2217                 /* Compute the ILT client partition */
2218                 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2219                 if (rc) {
2220                         DP_NOTICE(p_hwfn,
2221                                   "too many ILT lines; re-computing with less lines\n");
2222                         /* In case there are not enough ILT lines we reduce the
2223                          * number of RDMA tasks and re-compute.
2224                          */
2225                         excess_tasks =
2226                             qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
2227                         if (!excess_tasks)
2228                                 goto alloc_err;
2229
2230                         rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
2231                         rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
2232                         if (rc)
2233                                 goto alloc_err;
2234
2235                         rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2236                         if (rc) {
2237                                 DP_ERR(p_hwfn,
2238                                        "failed ILT compute. Requested too many lines: %u\n",
2239                                        line_count);
2240
2241                                 goto alloc_err;
2242                         }
2243                 }
2244
2245                 /* CID map / ILT shadow table / T2
2246                  * The talbes sizes are determined by the computations above
2247                  */
2248                 rc = qed_cxt_tables_alloc(p_hwfn);
2249                 if (rc)
2250                         goto alloc_err;
2251
2252                 /* SPQ, must follow ILT because initializes SPQ context */
2253                 rc = qed_spq_alloc(p_hwfn);
2254                 if (rc)
2255                         goto alloc_err;
2256
2257                 /* SP status block allocation */
2258                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
2259                                                          RESERVED_PTT_DPC);
2260
2261                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
2262                 if (rc)
2263                         goto alloc_err;
2264
2265                 rc = qed_iov_alloc(p_hwfn);
2266                 if (rc)
2267                         goto alloc_err;
2268
2269                 /* EQ */
2270                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
2271                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2272                         enum protocol_type rdma_proto;
2273
2274                         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
2275                                 rdma_proto = PROTOCOLID_ROCE;
2276                         else
2277                                 rdma_proto = PROTOCOLID_IWARP;
2278
2279                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
2280                                                                rdma_proto,
2281                                                                NULL) * 2;
2282                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
2283                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2284                         num_cons =
2285                             qed_cxt_get_proto_cid_count(p_hwfn,
2286                                                         PROTOCOLID_ISCSI,
2287                                                         NULL);
2288                         n_eqes += 2 * num_cons;
2289                 }
2290
2291                 if (n_eqes > 0xFFFF) {
2292                         DP_ERR(p_hwfn,
2293                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
2294                                n_eqes, 0xFFFF);
2295                         goto alloc_no_mem;
2296                 }
2297
2298                 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
2299                 if (rc)
2300                         goto alloc_err;
2301
2302                 rc = qed_consq_alloc(p_hwfn);
2303                 if (rc)
2304                         goto alloc_err;
2305
2306                 rc = qed_l2_alloc(p_hwfn);
2307                 if (rc)
2308                         goto alloc_err;
2309
2310 #ifdef CONFIG_QED_LL2
2311                 if (p_hwfn->using_ll2) {
2312                         rc = qed_ll2_alloc(p_hwfn);
2313                         if (rc)
2314                                 goto alloc_err;
2315                 }
2316 #endif
2317
2318                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2319                         rc = qed_fcoe_alloc(p_hwfn);
2320                         if (rc)
2321                                 goto alloc_err;
2322                 }
2323
2324                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2325                         rc = qed_iscsi_alloc(p_hwfn);
2326                         if (rc)
2327                                 goto alloc_err;
2328                         rc = qed_ooo_alloc(p_hwfn);
2329                         if (rc)
2330                                 goto alloc_err;
2331                 }
2332
2333                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2334                         rc = qed_rdma_info_alloc(p_hwfn);
2335                         if (rc)
2336                                 goto alloc_err;
2337                 }
2338
2339                 /* DMA info initialization */
2340                 rc = qed_dmae_info_alloc(p_hwfn);
2341                 if (rc)
2342                         goto alloc_err;
2343
2344                 /* DCBX initialization */
2345                 rc = qed_dcbx_info_alloc(p_hwfn);
2346                 if (rc)
2347                         goto alloc_err;
2348
2349                 rc = qed_dbg_alloc_user_data(p_hwfn);
2350                 if (rc)
2351                         goto alloc_err;
2352         }
2353
2354         rc = qed_llh_alloc(cdev);
2355         if (rc) {
2356                 DP_NOTICE(cdev,
2357                           "Failed to allocate memory for the llh_info structure\n");
2358                 goto alloc_err;
2359         }
2360
2361         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
2362         if (!cdev->reset_stats)
2363                 goto alloc_no_mem;
2364
2365         return 0;
2366
2367 alloc_no_mem:
2368         rc = -ENOMEM;
2369 alloc_err:
2370         qed_resc_free(cdev);
2371         return rc;
2372 }
2373
2374 void qed_resc_setup(struct qed_dev *cdev)
2375 {
2376         int i;
2377
2378         if (IS_VF(cdev)) {
2379                 for_each_hwfn(cdev, i)
2380                         qed_l2_setup(&cdev->hwfns[i]);
2381                 return;
2382         }
2383
2384         for_each_hwfn(cdev, i) {
2385                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2386
2387                 qed_cxt_mngr_setup(p_hwfn);
2388                 qed_spq_setup(p_hwfn);
2389                 qed_eq_setup(p_hwfn);
2390                 qed_consq_setup(p_hwfn);
2391
2392                 /* Read shadow of current MFW mailbox */
2393                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
2394                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2395                        p_hwfn->mcp_info->mfw_mb_cur,
2396                        p_hwfn->mcp_info->mfw_mb_length);
2397
2398                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
2399
2400                 qed_l2_setup(p_hwfn);
2401                 qed_iov_setup(p_hwfn);
2402 #ifdef CONFIG_QED_LL2
2403                 if (p_hwfn->using_ll2)
2404                         qed_ll2_setup(p_hwfn);
2405 #endif
2406                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2407                         qed_fcoe_setup(p_hwfn);
2408
2409                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2410                         qed_iscsi_setup(p_hwfn);
2411                         qed_ooo_setup(p_hwfn);
2412                 }
2413         }
2414 }
2415
2416 #define FINAL_CLEANUP_POLL_CNT          (100)
2417 #define FINAL_CLEANUP_POLL_TIME         (10)
2418 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
2419                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
2420 {
2421         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
2422         int rc = -EBUSY;
2423
2424         addr = GTT_BAR0_MAP_REG_USDM_RAM +
2425                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
2426
2427         if (is_vf)
2428                 id += 0x10;
2429
2430         command |= X_FINAL_CLEANUP_AGG_INT <<
2431                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
2432         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
2433         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
2434         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
2435
2436         /* Make sure notification is not set before initiating final cleanup */
2437         if (REG_RD(p_hwfn, addr)) {
2438                 DP_NOTICE(p_hwfn,
2439                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
2440                 REG_WR(p_hwfn, addr, 0);
2441         }
2442
2443         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2444                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
2445                    id, command);
2446
2447         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
2448
2449         /* Poll until completion */
2450         while (!REG_RD(p_hwfn, addr) && count--)
2451                 msleep(FINAL_CLEANUP_POLL_TIME);
2452
2453         if (REG_RD(p_hwfn, addr))
2454                 rc = 0;
2455         else
2456                 DP_NOTICE(p_hwfn,
2457                           "Failed to receive FW final cleanup notification\n");
2458
2459         /* Cleanup afterwards */
2460         REG_WR(p_hwfn, addr, 0);
2461
2462         return rc;
2463 }
2464
2465 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
2466 {
2467         int hw_mode = 0;
2468
2469         if (QED_IS_BB_B0(p_hwfn->cdev)) {
2470                 hw_mode |= 1 << MODE_BB;
2471         } else if (QED_IS_AH(p_hwfn->cdev)) {
2472                 hw_mode |= 1 << MODE_K2;
2473         } else {
2474                 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
2475                           p_hwfn->cdev->type);
2476                 return -EINVAL;
2477         }
2478
2479         switch (p_hwfn->cdev->num_ports_in_engine) {
2480         case 1:
2481                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
2482                 break;
2483         case 2:
2484                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
2485                 break;
2486         case 4:
2487                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
2488                 break;
2489         default:
2490                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
2491                           p_hwfn->cdev->num_ports_in_engine);
2492                 return -EINVAL;
2493         }
2494
2495         if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
2496                 hw_mode |= 1 << MODE_MF_SD;
2497         else
2498                 hw_mode |= 1 << MODE_MF_SI;
2499
2500         hw_mode |= 1 << MODE_ASIC;
2501
2502         if (p_hwfn->cdev->num_hwfns > 1)
2503                 hw_mode |= 1 << MODE_100G;
2504
2505         p_hwfn->hw_info.hw_mode = hw_mode;
2506
2507         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
2508                    "Configuring function for hw_mode: 0x%08x\n",
2509                    p_hwfn->hw_info.hw_mode);
2510
2511         return 0;
2512 }
2513
2514 /* Init run time data for all PFs on an engine. */
2515 static void qed_init_cau_rt_data(struct qed_dev *cdev)
2516 {
2517         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
2518         int i, igu_sb_id;
2519
2520         for_each_hwfn(cdev, i) {
2521                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2522                 struct qed_igu_info *p_igu_info;
2523                 struct qed_igu_block *p_block;
2524                 struct cau_sb_entry sb_entry;
2525
2526                 p_igu_info = p_hwfn->hw_info.p_igu_info;
2527
2528                 for (igu_sb_id = 0;
2529                      igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
2530                         p_block = &p_igu_info->entry[igu_sb_id];
2531
2532                         if (!p_block->is_pf)
2533                                 continue;
2534
2535                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
2536                                               p_block->function_id, 0, 0);
2537                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
2538                                          sb_entry);
2539                 }
2540         }
2541 }
2542
2543 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
2544                                      struct qed_ptt *p_ptt)
2545 {
2546         u32 val, wr_mbs, cache_line_size;
2547
2548         val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
2549         switch (val) {
2550         case 0:
2551                 wr_mbs = 128;
2552                 break;
2553         case 1:
2554                 wr_mbs = 256;
2555                 break;
2556         case 2:
2557                 wr_mbs = 512;
2558                 break;
2559         default:
2560                 DP_INFO(p_hwfn,
2561                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2562                         val);
2563                 return;
2564         }
2565
2566         cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
2567         switch (cache_line_size) {
2568         case 32:
2569                 val = 0;
2570                 break;
2571         case 64:
2572                 val = 1;
2573                 break;
2574         case 128:
2575                 val = 2;
2576                 break;
2577         case 256:
2578                 val = 3;
2579                 break;
2580         default:
2581                 DP_INFO(p_hwfn,
2582                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2583                         cache_line_size);
2584         }
2585
2586         if (L1_CACHE_BYTES > wr_mbs)
2587                 DP_INFO(p_hwfn,
2588                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
2589                         L1_CACHE_BYTES, wr_mbs);
2590
2591         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
2592         if (val > 0) {
2593                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
2594                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
2595         }
2596 }
2597
2598 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
2599                               struct qed_ptt *p_ptt, int hw_mode)
2600 {
2601         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2602         struct qed_qm_common_rt_init_params params;
2603         struct qed_dev *cdev = p_hwfn->cdev;
2604         u8 vf_id, max_num_vfs;
2605         u16 num_pfs, pf_id;
2606         u32 concrete_fid;
2607         int rc = 0;
2608
2609         qed_init_cau_rt_data(cdev);
2610
2611         /* Program GTT windows */
2612         qed_gtt_init(p_hwfn);
2613
2614         if (p_hwfn->mcp_info) {
2615                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
2616                         qm_info->pf_rl_en = true;
2617                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
2618                         qm_info->pf_wfq_en = true;
2619         }
2620
2621         memset(&params, 0, sizeof(params));
2622         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
2623         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
2624         params.pf_rl_en = qm_info->pf_rl_en;
2625         params.pf_wfq_en = qm_info->pf_wfq_en;
2626         params.vport_rl_en = qm_info->vport_rl_en;
2627         params.vport_wfq_en = qm_info->vport_wfq_en;
2628         params.port_params = qm_info->qm_port_params;
2629
2630         qed_qm_common_rt_init(p_hwfn, &params);
2631
2632         qed_cxt_hw_init_common(p_hwfn);
2633
2634         qed_init_cache_line_size(p_hwfn, p_ptt);
2635
2636         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
2637         if (rc)
2638                 return rc;
2639
2640         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
2641         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
2642
2643         if (QED_IS_BB(p_hwfn->cdev)) {
2644                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
2645                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
2646                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
2647                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2648                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2649                 }
2650                 /* pretend to original PF */
2651                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2652         }
2653
2654         max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
2655         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
2656                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
2657                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
2658                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
2659                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
2660                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
2661                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
2662         }
2663         /* pretend to original PF */
2664         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2665
2666         return rc;
2667 }
2668
2669 static int
2670 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
2671                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
2672 {
2673         u32 dpi_bit_shift, dpi_count, dpi_page_size;
2674         u32 min_dpis;
2675         u32 n_wids;
2676
2677         /* Calculate DPI size */
2678         n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
2679         dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
2680         dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
2681         dpi_bit_shift = ilog2(dpi_page_size / 4096);
2682         dpi_count = pwm_region_size / dpi_page_size;
2683
2684         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
2685         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
2686
2687         p_hwfn->dpi_size = dpi_page_size;
2688         p_hwfn->dpi_count = dpi_count;
2689
2690         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
2691
2692         if (dpi_count < min_dpis)
2693                 return -EINVAL;
2694
2695         return 0;
2696 }
2697
2698 enum QED_ROCE_EDPM_MODE {
2699         QED_ROCE_EDPM_MODE_ENABLE = 0,
2700         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
2701         QED_ROCE_EDPM_MODE_DISABLE = 2,
2702 };
2703
2704 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn)
2705 {
2706         if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
2707                 return false;
2708
2709         return true;
2710 }
2711
2712 static int
2713 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2714 {
2715         u32 pwm_regsize, norm_regsize;
2716         u32 non_pwm_conn, min_addr_reg1;
2717         u32 db_bar_size, n_cpus = 1;
2718         u32 roce_edpm_mode;
2719         u32 pf_dems_shift;
2720         int rc = 0;
2721         u8 cond;
2722
2723         db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
2724         if (p_hwfn->cdev->num_hwfns > 1)
2725                 db_bar_size /= 2;
2726
2727         /* Calculate doorbell regions */
2728         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
2729                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
2730                                                    NULL) +
2731                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2732                                                    NULL);
2733         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
2734         min_addr_reg1 = norm_regsize / 4096;
2735         pwm_regsize = db_bar_size - norm_regsize;
2736
2737         /* Check that the normal and PWM sizes are valid */
2738         if (db_bar_size < norm_regsize) {
2739                 DP_ERR(p_hwfn->cdev,
2740                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
2741                        db_bar_size, norm_regsize);
2742                 return -EINVAL;
2743         }
2744
2745         if (pwm_regsize < QED_MIN_PWM_REGION) {
2746                 DP_ERR(p_hwfn->cdev,
2747                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
2748                        pwm_regsize,
2749                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
2750                 return -EINVAL;
2751         }
2752
2753         /* Calculate number of DPIs */
2754         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2755         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
2756             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
2757                 /* Either EDPM is mandatory, or we are attempting to allocate a
2758                  * WID per CPU.
2759                  */
2760                 n_cpus = num_present_cpus();
2761                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2762         }
2763
2764         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
2765                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
2766         if (cond || p_hwfn->dcbx_no_edpm) {
2767                 /* Either EDPM is disabled from user configuration, or it is
2768                  * disabled via DCBx, or it is not mandatory and we failed to
2769                  * allocated a WID per CPU.
2770                  */
2771                 n_cpus = 1;
2772                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2773
2774                 if (cond)
2775                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
2776         }
2777
2778         p_hwfn->wid_count = (u16) n_cpus;
2779
2780         DP_INFO(p_hwfn,
2781                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n",
2782                 norm_regsize,
2783                 pwm_regsize,
2784                 p_hwfn->dpi_size,
2785                 p_hwfn->dpi_count,
2786                 (!qed_edpm_enabled(p_hwfn)) ?
2787                 "disabled" : "enabled", PAGE_SIZE);
2788
2789         if (rc) {
2790                 DP_ERR(p_hwfn,
2791                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
2792                        p_hwfn->dpi_count,
2793                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
2794                 return -EINVAL;
2795         }
2796
2797         p_hwfn->dpi_start_offset = norm_regsize;
2798
2799         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2800         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
2801         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2802         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2803
2804         return 0;
2805 }
2806
2807 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
2808                             struct qed_ptt *p_ptt, int hw_mode)
2809 {
2810         int rc = 0;
2811
2812         /* In CMT the gate should be cleared by the 2nd hwfn */
2813         if (!QED_IS_CMT(p_hwfn->cdev) || !IS_LEAD_HWFN(p_hwfn))
2814                 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2815
2816         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
2817         if (rc)
2818                 return rc;
2819
2820         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2821
2822         return 0;
2823 }
2824
2825 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
2826                           struct qed_ptt *p_ptt,
2827                           struct qed_tunnel_info *p_tunn,
2828                           int hw_mode,
2829                           bool b_hw_start,
2830                           enum qed_int_mode int_mode,
2831                           bool allow_npar_tx_switch)
2832 {
2833         u8 rel_pf_id = p_hwfn->rel_pf_id;
2834         int rc = 0;
2835
2836         if (p_hwfn->mcp_info) {
2837                 struct qed_mcp_function_info *p_info;
2838
2839                 p_info = &p_hwfn->mcp_info->func_info;
2840                 if (p_info->bandwidth_min)
2841                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2842
2843                 /* Update rate limit once we'll actually have a link */
2844                 p_hwfn->qm_info.pf_rl = 100000;
2845         }
2846
2847         qed_cxt_hw_init_pf(p_hwfn, p_ptt);
2848
2849         qed_int_igu_init_rt(p_hwfn);
2850
2851         /* Set VLAN in NIG if needed */
2852         if (hw_mode & BIT(MODE_MF_SD)) {
2853                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2854                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2855                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2856                              p_hwfn->hw_info.ovlan);
2857
2858                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2859                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2860                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2861                              1);
2862         }
2863
2864         /* Enable classification by MAC if needed */
2865         if (hw_mode & BIT(MODE_MF_SI)) {
2866                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2867                            "Configuring TAGMAC_CLS_TYPE\n");
2868                 STORE_RT_REG(p_hwfn,
2869                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
2870         }
2871
2872         /* Protocol Configuration */
2873         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2874                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
2875         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2876                      (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
2877         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2878
2879         /* Sanity check before the PF init sequence that uses DMAE */
2880         rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2881         if (rc)
2882                 return rc;
2883
2884         /* PF Init sequence */
2885         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2886         if (rc)
2887                 return rc;
2888
2889         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2890         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2891         if (rc)
2892                 return rc;
2893
2894         /* Pure runtime initializations - directly to the HW  */
2895         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2896
2897         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2898         if (rc)
2899                 return rc;
2900
2901         /* Use the leading hwfn since in CMT only NIG #0 is operational */
2902         if (IS_LEAD_HWFN(p_hwfn)) {
2903                 rc = qed_llh_hw_init_pf(p_hwfn, p_ptt);
2904                 if (rc)
2905                         return rc;
2906         }
2907
2908         if (b_hw_start) {
2909                 /* enable interrupts */
2910                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
2911
2912                 /* send function start command */
2913                 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2914                                      allow_npar_tx_switch);
2915                 if (rc) {
2916                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
2917                         return rc;
2918                 }
2919                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2920                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
2921                         qed_wr(p_hwfn, p_ptt,
2922                                PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2923                                0x100);
2924                 }
2925         }
2926         return rc;
2927 }
2928
2929 int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn,
2930                                struct qed_ptt *p_ptt, bool b_enable)
2931 {
2932         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2933
2934         /* Configure the PF's internal FID_enable for master transactions */
2935         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2936
2937         /* Wait until value is set - try for 1 second every 50us */
2938         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2939                 val = qed_rd(p_hwfn, p_ptt,
2940                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2941                 if (val == set_val)
2942                         break;
2943
2944                 usleep_range(50, 60);
2945         }
2946
2947         if (val != set_val) {
2948                 DP_NOTICE(p_hwfn,
2949                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
2950                 return -EAGAIN;
2951         }
2952
2953         return 0;
2954 }
2955
2956 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
2957                                 struct qed_ptt *p_main_ptt)
2958 {
2959         /* Read shadow of current MFW mailbox */
2960         qed_mcp_read_mb(p_hwfn, p_main_ptt);
2961         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2962                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
2963 }
2964
2965 static void
2966 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
2967                          struct qed_drv_load_params *p_drv_load)
2968 {
2969         memset(p_load_req, 0, sizeof(*p_load_req));
2970
2971         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2972                                QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
2973         p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2974         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2975         p_load_req->override_force_load = p_drv_load->override_force_load;
2976 }
2977
2978 static int qed_vf_start(struct qed_hwfn *p_hwfn,
2979                         struct qed_hw_init_params *p_params)
2980 {
2981         if (p_params->p_tunn) {
2982                 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2983                 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2984         }
2985
2986         p_hwfn->b_int_enabled = true;
2987
2988         return 0;
2989 }
2990
2991 static void qed_pglueb_clear_err(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2992 {
2993         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2994                BIT(p_hwfn->abs_pf_id));
2995 }
2996
2997 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
2998 {
2999         struct qed_load_req_params load_req_params;
3000         u32 load_code, resp, param, drv_mb_param;
3001         bool b_default_mtu = true;
3002         struct qed_hwfn *p_hwfn;
3003         int rc = 0, i;
3004         u16 ether_type;
3005
3006         if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
3007                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
3008                 return -EINVAL;
3009         }
3010
3011         if (IS_PF(cdev)) {
3012                 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
3013                 if (rc)
3014                         return rc;
3015         }
3016
3017         for_each_hwfn(cdev, i) {
3018                 p_hwfn = &cdev->hwfns[i];
3019
3020                 /* If management didn't provide a default, set one of our own */
3021                 if (!p_hwfn->hw_info.mtu) {
3022                         p_hwfn->hw_info.mtu = 1500;
3023                         b_default_mtu = false;
3024                 }
3025
3026                 if (IS_VF(cdev)) {
3027                         qed_vf_start(p_hwfn, p_params);
3028                         continue;
3029                 }
3030
3031                 rc = qed_calc_hw_mode(p_hwfn);
3032                 if (rc)
3033                         return rc;
3034
3035                 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
3036                                              &cdev->mf_bits) ||
3037                                     test_bit(QED_MF_8021AD_TAGGING,
3038                                              &cdev->mf_bits))) {
3039                         if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
3040                                 ether_type = ETH_P_8021Q;
3041                         else
3042                                 ether_type = ETH_P_8021AD;
3043                         STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3044                                      ether_type);
3045                         STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3046                                      ether_type);
3047                         STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3048                                      ether_type);
3049                         STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
3050                                      ether_type);
3051                 }
3052
3053                 qed_fill_load_req_params(&load_req_params,
3054                                          p_params->p_drv_load_params);
3055                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
3056                                       &load_req_params);
3057                 if (rc) {
3058                         DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
3059                         return rc;
3060                 }
3061
3062                 load_code = load_req_params.load_code;
3063                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
3064                            "Load request was sent. Load code: 0x%x\n",
3065                            load_code);
3066
3067                 /* Only relevant for recovery:
3068                  * Clear the indication after LOAD_REQ is responded by the MFW.
3069                  */
3070                 cdev->recov_in_prog = false;
3071
3072                 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
3073
3074                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
3075
3076                 /* Clean up chip from previous driver if such remains exist.
3077                  * This is not needed when the PF is the first one on the
3078                  * engine, since afterwards we are going to init the FW.
3079                  */
3080                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
3081                         rc = qed_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
3082                                                p_hwfn->rel_pf_id, false);
3083                         if (rc) {
3084                                 DP_NOTICE(p_hwfn, "Final cleanup failed\n");
3085                                 goto load_err;
3086                         }
3087                 }
3088
3089                 /* Log and clear previous pglue_b errors if such exist */
3090                 qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
3091
3092                 /* Enable the PF's internal FID_enable in the PXP */
3093                 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
3094                                                 true);
3095                 if (rc)
3096                         goto load_err;
3097
3098                 /* Clear the pglue_b was_error indication.
3099                  * In E4 it must be done after the BME and the internal
3100                  * FID_enable for the PF are set, since VDMs may cause the
3101                  * indication to be set again.
3102                  */
3103                 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3104
3105                 switch (load_code) {
3106                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
3107                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
3108                                                 p_hwfn->hw_info.hw_mode);
3109                         if (rc)
3110                                 break;
3111                 /* Fall through */
3112                 case FW_MSG_CODE_DRV_LOAD_PORT:
3113                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
3114                                               p_hwfn->hw_info.hw_mode);
3115                         if (rc)
3116                                 break;
3117
3118                 /* Fall through */
3119                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
3120                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
3121                                             p_params->p_tunn,
3122                                             p_hwfn->hw_info.hw_mode,
3123                                             p_params->b_hw_start,
3124                                             p_params->int_mode,
3125                                             p_params->allow_npar_tx_switch);
3126                         break;
3127                 default:
3128                         DP_NOTICE(p_hwfn,
3129                                   "Unexpected load code [0x%08x]", load_code);
3130                         rc = -EINVAL;
3131                         break;
3132                 }
3133
3134                 if (rc) {
3135                         DP_NOTICE(p_hwfn,
3136                                   "init phase failed for loadcode 0x%x (rc %d)\n",
3137                                   load_code, rc);
3138                         goto load_err;
3139                 }
3140
3141                 rc = qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3142                 if (rc)
3143                         return rc;
3144
3145                 /* send DCBX attention request command */
3146                 DP_VERBOSE(p_hwfn,
3147                            QED_MSG_DCB,
3148                            "sending phony dcbx set command to trigger DCBx attention handling\n");
3149                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3150                                  DRV_MSG_CODE_SET_DCBX,
3151                                  1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
3152                                  &resp, &param);
3153                 if (rc) {
3154                         DP_NOTICE(p_hwfn,
3155                                   "Failed to send DCBX attention request\n");
3156                         return rc;
3157                 }
3158
3159                 p_hwfn->hw_init_done = true;
3160         }
3161
3162         if (IS_PF(cdev)) {
3163                 p_hwfn = QED_LEADING_HWFN(cdev);
3164
3165                 /* Get pre-negotiated values for stag, bandwidth etc. */
3166                 DP_VERBOSE(p_hwfn,
3167                            QED_MSG_SPQ,
3168                            "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3169                 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET;
3170                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3171                                  DRV_MSG_CODE_GET_OEM_UPDATES,
3172                                  drv_mb_param, &resp, &param);
3173                 if (rc)
3174                         DP_NOTICE(p_hwfn,
3175                                   "Failed to send GET_OEM_UPDATES attention request\n");
3176
3177                 drv_mb_param = STORM_FW_VERSION;
3178                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3179                                  DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
3180                                  drv_mb_param, &load_code, &param);
3181                 if (rc)
3182                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
3183
3184                 if (!b_default_mtu) {
3185                         rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
3186                                                    p_hwfn->hw_info.mtu);
3187                         if (rc)
3188                                 DP_INFO(p_hwfn,
3189                                         "Failed to update default mtu\n");
3190                 }
3191
3192                 rc = qed_mcp_ov_update_driver_state(p_hwfn,
3193                                                     p_hwfn->p_main_ptt,
3194                                                   QED_OV_DRIVER_STATE_DISABLED);
3195                 if (rc)
3196                         DP_INFO(p_hwfn, "Failed to update driver state\n");
3197
3198                 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
3199                                                QED_OV_ESWITCH_NONE);
3200                 if (rc)
3201                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
3202         }
3203
3204         return 0;
3205
3206 load_err:
3207         /* The MFW load lock should be released also when initialization fails.
3208          */
3209         qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3210         return rc;
3211 }
3212
3213 #define QED_HW_STOP_RETRY_LIMIT (10)
3214 static void qed_hw_timers_stop(struct qed_dev *cdev,
3215                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3216 {
3217         int i;
3218
3219         /* close timers */
3220         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
3221         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
3222
3223         if (cdev->recov_in_prog)
3224                 return;
3225
3226         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
3227                 if ((!qed_rd(p_hwfn, p_ptt,
3228                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
3229                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
3230                         break;
3231
3232                 /* Dependent on number of connection/tasks, possibly
3233                  * 1ms sleep is required between polls
3234                  */
3235                 usleep_range(1000, 2000);
3236         }
3237
3238         if (i < QED_HW_STOP_RETRY_LIMIT)
3239                 return;
3240
3241         DP_NOTICE(p_hwfn,
3242                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
3243                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
3244                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
3245 }
3246
3247 void qed_hw_timers_stop_all(struct qed_dev *cdev)
3248 {
3249         int j;
3250
3251         for_each_hwfn(cdev, j) {
3252                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
3253                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
3254
3255                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
3256         }
3257 }
3258
3259 int qed_hw_stop(struct qed_dev *cdev)
3260 {
3261         struct qed_hwfn *p_hwfn;
3262         struct qed_ptt *p_ptt;
3263         int rc, rc2 = 0;
3264         int j;
3265
3266         for_each_hwfn(cdev, j) {
3267                 p_hwfn = &cdev->hwfns[j];
3268                 p_ptt = p_hwfn->p_main_ptt;
3269
3270                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
3271
3272                 if (IS_VF(cdev)) {
3273                         qed_vf_pf_int_cleanup(p_hwfn);
3274                         rc = qed_vf_pf_reset(p_hwfn);
3275                         if (rc) {
3276                                 DP_NOTICE(p_hwfn,
3277                                           "qed_vf_pf_reset failed. rc = %d.\n",
3278                                           rc);
3279                                 rc2 = -EINVAL;
3280                         }
3281                         continue;
3282                 }
3283
3284                 /* mark the hw as uninitialized... */
3285                 p_hwfn->hw_init_done = false;
3286
3287                 /* Send unload command to MCP */
3288                 if (!cdev->recov_in_prog) {
3289                         rc = qed_mcp_unload_req(p_hwfn, p_ptt);
3290                         if (rc) {
3291                                 DP_NOTICE(p_hwfn,
3292                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
3293                                           rc);
3294                                 rc2 = -EINVAL;
3295                         }
3296                 }
3297
3298                 qed_slowpath_irq_sync(p_hwfn);
3299
3300                 /* After this point no MFW attentions are expected, e.g. prevent
3301                  * race between pf stop and dcbx pf update.
3302                  */
3303                 rc = qed_sp_pf_stop(p_hwfn);
3304                 if (rc) {
3305                         DP_NOTICE(p_hwfn,
3306                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
3307                                   rc);
3308                         rc2 = -EINVAL;
3309                 }
3310
3311                 qed_wr(p_hwfn, p_ptt,
3312                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
3313
3314                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3315                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
3316                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
3317                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3318                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
3319
3320                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
3321
3322                 /* Disable Attention Generation */
3323                 qed_int_igu_disable_int(p_hwfn, p_ptt);
3324
3325                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
3326                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
3327
3328                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
3329
3330                 /* Need to wait 1ms to guarantee SBs are cleared */
3331                 usleep_range(1000, 2000);
3332
3333                 /* Disable PF in HW blocks */
3334                 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
3335                 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
3336
3337                 if (IS_LEAD_HWFN(p_hwfn) &&
3338                     test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) &&
3339                     !QED_IS_FCOE_PERSONALITY(p_hwfn))
3340                         qed_llh_remove_mac_filter(cdev, 0,
3341                                                   p_hwfn->hw_info.hw_mac_addr);
3342
3343                 if (!cdev->recov_in_prog) {
3344                         rc = qed_mcp_unload_done(p_hwfn, p_ptt);
3345                         if (rc) {
3346                                 DP_NOTICE(p_hwfn,
3347                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
3348                                           rc);
3349                                 rc2 = -EINVAL;
3350                         }
3351                 }
3352         }
3353
3354         if (IS_PF(cdev) && !cdev->recov_in_prog) {
3355                 p_hwfn = QED_LEADING_HWFN(cdev);
3356                 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
3357
3358                 /* Clear the PF's internal FID_enable in the PXP.
3359                  * In CMT this should only be done for first hw-function, and
3360                  * only after all transactions have stopped for all active
3361                  * hw-functions.
3362                  */
3363                 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3364                 if (rc) {
3365                         DP_NOTICE(p_hwfn,
3366                                   "qed_pglueb_set_pfid_enable() failed. rc = %d.\n",
3367                                   rc);
3368                         rc2 = -EINVAL;
3369                 }
3370         }
3371
3372         return rc2;
3373 }
3374
3375 int qed_hw_stop_fastpath(struct qed_dev *cdev)
3376 {
3377         int j;
3378
3379         for_each_hwfn(cdev, j) {
3380                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
3381                 struct qed_ptt *p_ptt;
3382
3383                 if (IS_VF(cdev)) {
3384                         qed_vf_pf_int_cleanup(p_hwfn);
3385                         continue;
3386                 }
3387                 p_ptt = qed_ptt_acquire(p_hwfn);
3388                 if (!p_ptt)
3389                         return -EAGAIN;
3390
3391                 DP_VERBOSE(p_hwfn,
3392                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
3393
3394                 qed_wr(p_hwfn, p_ptt,
3395                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
3396
3397                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3398                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
3399                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
3400                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3401                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
3402
3403                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
3404
3405                 /* Need to wait 1ms to guarantee SBs are cleared */
3406                 usleep_range(1000, 2000);
3407                 qed_ptt_release(p_hwfn, p_ptt);
3408         }
3409
3410         return 0;
3411 }
3412
3413 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
3414 {
3415         struct qed_ptt *p_ptt;
3416
3417         if (IS_VF(p_hwfn->cdev))
3418                 return 0;
3419
3420         p_ptt = qed_ptt_acquire(p_hwfn);
3421         if (!p_ptt)
3422                 return -EAGAIN;
3423
3424         if (p_hwfn->p_rdma_info &&
3425             p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs)
3426                 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
3427
3428         /* Re-open incoming traffic */
3429         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
3430         qed_ptt_release(p_hwfn, p_ptt);
3431
3432         return 0;
3433 }
3434
3435 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
3436 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
3437 {
3438         qed_ptt_pool_free(p_hwfn);
3439         kfree(p_hwfn->hw_info.p_igu_info);
3440         p_hwfn->hw_info.p_igu_info = NULL;
3441 }
3442
3443 /* Setup bar access */
3444 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
3445 {
3446         /* clear indirect access */
3447         if (QED_IS_AH(p_hwfn->cdev)) {
3448                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3449                        PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
3450                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3451                        PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
3452                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3453                        PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
3454                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3455                        PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
3456         } else {
3457                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3458                        PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
3459                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3460                        PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
3461                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3462                        PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
3463                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3464                        PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
3465         }
3466
3467         /* Clean previous pglue_b errors if such exist */
3468         qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3469
3470         /* enable internal target-read */
3471         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3472                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
3473 }
3474
3475 static void get_function_id(struct qed_hwfn *p_hwfn)
3476 {
3477         /* ME Register */
3478         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
3479                                                   PXP_PF_ME_OPAQUE_ADDR);
3480
3481         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
3482
3483         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
3484         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3485                                       PXP_CONCRETE_FID_PFID);
3486         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3487                                     PXP_CONCRETE_FID_PORT);
3488
3489         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
3490                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
3491                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
3492 }
3493
3494 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
3495 {
3496         u32 *feat_num = p_hwfn->hw_info.feat_num;
3497         struct qed_sb_cnt_info sb_cnt;
3498         u32 non_l2_sbs = 0;
3499
3500         memset(&sb_cnt, 0, sizeof(sb_cnt));
3501         qed_int_get_num_sbs(p_hwfn, &sb_cnt);
3502
3503         if (IS_ENABLED(CONFIG_QED_RDMA) &&
3504             QED_IS_RDMA_PERSONALITY(p_hwfn)) {
3505                 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
3506                  * the status blocks equally between L2 / RoCE but with
3507                  * consideration as to how many l2 queues / cnqs we have.
3508                  */
3509                 feat_num[QED_RDMA_CNQ] =
3510                         min_t(u32, sb_cnt.cnt / 2,
3511                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
3512
3513                 non_l2_sbs = feat_num[QED_RDMA_CNQ];
3514         }
3515         if (QED_IS_L2_PERSONALITY(p_hwfn)) {
3516                 /* Start by allocating VF queues, then PF's */
3517                 feat_num[QED_VF_L2_QUE] = min_t(u32,
3518                                                 RESC_NUM(p_hwfn, QED_L2_QUEUE),
3519                                                 sb_cnt.iov_cnt);
3520                 feat_num[QED_PF_L2_QUE] = min_t(u32,
3521                                                 sb_cnt.cnt - non_l2_sbs,
3522                                                 RESC_NUM(p_hwfn,
3523                                                          QED_L2_QUEUE) -
3524                                                 FEAT_NUM(p_hwfn,
3525                                                          QED_VF_L2_QUE));
3526         }
3527
3528         if (QED_IS_FCOE_PERSONALITY(p_hwfn))
3529                 feat_num[QED_FCOE_CQ] =  min_t(u32, sb_cnt.cnt,
3530                                                RESC_NUM(p_hwfn,
3531                                                         QED_CMDQS_CQS));
3532
3533         if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
3534                 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
3535                                                RESC_NUM(p_hwfn,
3536                                                         QED_CMDQS_CQS));
3537         DP_VERBOSE(p_hwfn,
3538                    NETIF_MSG_PROBE,
3539                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
3540                    (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
3541                    (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
3542                    (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
3543                    (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
3544                    (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
3545                    (int)sb_cnt.cnt);
3546 }
3547
3548 const char *qed_hw_get_resc_name(enum qed_resources res_id)
3549 {
3550         switch (res_id) {
3551         case QED_L2_QUEUE:
3552                 return "L2_QUEUE";
3553         case QED_VPORT:
3554                 return "VPORT";
3555         case QED_RSS_ENG:
3556                 return "RSS_ENG";
3557         case QED_PQ:
3558                 return "PQ";
3559         case QED_RL:
3560                 return "RL";
3561         case QED_MAC:
3562                 return "MAC";
3563         case QED_VLAN:
3564                 return "VLAN";
3565         case QED_RDMA_CNQ_RAM:
3566                 return "RDMA_CNQ_RAM";
3567         case QED_ILT:
3568                 return "ILT";
3569         case QED_LL2_QUEUE:
3570                 return "LL2_QUEUE";
3571         case QED_CMDQS_CQS:
3572                 return "CMDQS_CQS";
3573         case QED_RDMA_STATS_QUEUE:
3574                 return "RDMA_STATS_QUEUE";
3575         case QED_BDQ:
3576                 return "BDQ";
3577         case QED_SB:
3578                 return "SB";
3579         default:
3580                 return "UNKNOWN_RESOURCE";
3581         }
3582 }
3583
3584 static int
3585 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
3586                             struct qed_ptt *p_ptt,
3587                             enum qed_resources res_id,
3588                             u32 resc_max_val, u32 *p_mcp_resp)
3589 {
3590         int rc;
3591
3592         rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
3593                                       resc_max_val, p_mcp_resp);
3594         if (rc) {
3595                 DP_NOTICE(p_hwfn,
3596                           "MFW response failure for a max value setting of resource %d [%s]\n",
3597                           res_id, qed_hw_get_resc_name(res_id));
3598                 return rc;
3599         }
3600
3601         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
3602                 DP_INFO(p_hwfn,
3603                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
3604                         res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
3605
3606         return 0;
3607 }
3608
3609 static int
3610 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3611 {
3612         bool b_ah = QED_IS_AH(p_hwfn->cdev);
3613         u32 resc_max_val, mcp_resp;
3614         u8 res_id;
3615         int rc;
3616
3617         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
3618                 switch (res_id) {
3619                 case QED_LL2_QUEUE:
3620                         resc_max_val = MAX_NUM_LL2_RX_QUEUES;
3621                         break;
3622                 case QED_RDMA_CNQ_RAM:
3623                         /* No need for a case for QED_CMDQS_CQS since
3624                          * CNQ/CMDQS are the same resource.
3625                          */
3626                         resc_max_val = NUM_OF_GLOBAL_QUEUES;
3627                         break;
3628                 case QED_RDMA_STATS_QUEUE:
3629                         resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
3630                             : RDMA_NUM_STATISTIC_COUNTERS_BB;
3631                         break;
3632                 case QED_BDQ:
3633                         resc_max_val = BDQ_NUM_RESOURCES;
3634                         break;
3635                 default:
3636                         continue;
3637                 }
3638
3639                 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
3640                                                  resc_max_val, &mcp_resp);
3641                 if (rc)
3642                         return rc;
3643
3644                 /* There's no point to continue to the next resource if the
3645                  * command is not supported by the MFW.
3646                  * We do continue if the command is supported but the resource
3647                  * is unknown to the MFW. Such a resource will be later
3648                  * configured with the default allocation values.
3649                  */
3650                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
3651                         return -EINVAL;
3652         }
3653
3654         return 0;
3655 }
3656
3657 static
3658 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
3659                          enum qed_resources res_id,
3660                          u32 *p_resc_num, u32 *p_resc_start)
3661 {
3662         u8 num_funcs = p_hwfn->num_funcs_on_engine;
3663         bool b_ah = QED_IS_AH(p_hwfn->cdev);
3664
3665         switch (res_id) {
3666         case QED_L2_QUEUE:
3667                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3668                                MAX_NUM_L2_QUEUES_BB) / num_funcs;
3669                 break;
3670         case QED_VPORT:
3671                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3672                                MAX_NUM_VPORTS_BB) / num_funcs;
3673                 break;
3674         case QED_RSS_ENG:
3675                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3676                                ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3677                 break;
3678         case QED_PQ:
3679                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3680                                MAX_QM_TX_QUEUES_BB) / num_funcs;
3681                 *p_resc_num &= ~0x7;    /* The granularity of the PQs is 8 */
3682                 break;
3683         case QED_RL:
3684                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3685                 break;
3686         case QED_MAC:
3687         case QED_VLAN:
3688                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3689                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3690                 break;
3691         case QED_ILT:
3692                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3693                                PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3694                 break;
3695         case QED_LL2_QUEUE:
3696                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3697                 break;
3698         case QED_RDMA_CNQ_RAM:
3699         case QED_CMDQS_CQS:
3700                 /* CNQ/CMDQS are the same resource */
3701                 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
3702                 break;
3703         case QED_RDMA_STATS_QUEUE:
3704                 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
3705                                RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
3706                 break;
3707         case QED_BDQ:
3708                 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
3709                     p_hwfn->hw_info.personality != QED_PCI_FCOE)
3710                         *p_resc_num = 0;
3711                 else
3712                         *p_resc_num = 1;
3713                 break;
3714         case QED_SB:
3715                 /* Since we want its value to reflect whether MFW supports
3716                  * the new scheme, have a default of 0.
3717                  */
3718                 *p_resc_num = 0;
3719                 break;
3720         default:
3721                 return -EINVAL;
3722         }
3723
3724         switch (res_id) {
3725         case QED_BDQ:
3726                 if (!*p_resc_num)
3727                         *p_resc_start = 0;
3728                 else if (p_hwfn->cdev->num_ports_in_engine == 4)
3729                         *p_resc_start = p_hwfn->port_id;
3730                 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
3731                         *p_resc_start = p_hwfn->port_id;
3732                 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
3733                         *p_resc_start = p_hwfn->port_id + 2;
3734                 break;
3735         default:
3736                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3737                 break;
3738         }
3739
3740         return 0;
3741 }
3742
3743 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
3744                                   enum qed_resources res_id)
3745 {
3746         u32 dflt_resc_num = 0, dflt_resc_start = 0;
3747         u32 mcp_resp, *p_resc_num, *p_resc_start;
3748         int rc;
3749
3750         p_resc_num = &RESC_NUM(p_hwfn, res_id);
3751         p_resc_start = &RESC_START(p_hwfn, res_id);
3752
3753         rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3754                                   &dflt_resc_start);
3755         if (rc) {
3756                 DP_ERR(p_hwfn,
3757                        "Failed to get default amount for resource %d [%s]\n",
3758                        res_id, qed_hw_get_resc_name(res_id));
3759                 return rc;
3760         }
3761
3762         rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3763                                    &mcp_resp, p_resc_num, p_resc_start);
3764         if (rc) {
3765                 DP_NOTICE(p_hwfn,
3766                           "MFW response failure for an allocation request for resource %d [%s]\n",
3767                           res_id, qed_hw_get_resc_name(res_id));
3768                 return rc;
3769         }
3770
3771         /* Default driver values are applied in the following cases:
3772          * - The resource allocation MB command is not supported by the MFW
3773          * - There is an internal error in the MFW while processing the request
3774          * - The resource ID is unknown to the MFW
3775          */
3776         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3777                 DP_INFO(p_hwfn,
3778                         "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
3779                         res_id,
3780                         qed_hw_get_resc_name(res_id),
3781                         mcp_resp, dflt_resc_num, dflt_resc_start);
3782                 *p_resc_num = dflt_resc_num;
3783                 *p_resc_start = dflt_resc_start;
3784                 goto out;
3785         }
3786
3787 out:
3788         /* PQs have to divide by 8 [that's the HW granularity].
3789          * Reduce number so it would fit.
3790          */
3791         if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
3792                 DP_INFO(p_hwfn,
3793                         "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
3794                         *p_resc_num,
3795                         (*p_resc_num) & ~0x7,
3796                         *p_resc_start, (*p_resc_start) & ~0x7);
3797                 *p_resc_num &= ~0x7;
3798                 *p_resc_start &= ~0x7;
3799         }
3800
3801         return 0;
3802 }
3803
3804 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
3805 {
3806         int rc;
3807         u8 res_id;
3808
3809         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
3810                 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
3811                 if (rc)
3812                         return rc;
3813         }
3814
3815         return 0;
3816 }
3817
3818 static int qed_hw_get_ppfid_bitmap(struct qed_hwfn *p_hwfn,
3819                                    struct qed_ptt *p_ptt)
3820 {
3821         struct qed_dev *cdev = p_hwfn->cdev;
3822         u8 native_ppfid_idx;
3823         int rc;
3824
3825         /* Calculation of BB/AH is different for native_ppfid_idx */
3826         if (QED_IS_BB(cdev))
3827                 native_ppfid_idx = p_hwfn->rel_pf_id;
3828         else
3829                 native_ppfid_idx = p_hwfn->rel_pf_id /
3830                     cdev->num_ports_in_engine;
3831
3832         rc = qed_mcp_get_ppfid_bitmap(p_hwfn, p_ptt);
3833         if (rc != 0 && rc != -EOPNOTSUPP)
3834                 return rc;
3835         else if (rc == -EOPNOTSUPP)
3836                 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx;
3837
3838         if (!(cdev->ppfid_bitmap & (0x1 << native_ppfid_idx))) {
3839                 DP_INFO(p_hwfn,
3840                         "Fix the PPFID bitmap to include the native PPFID [native_ppfid_idx %hhd, orig_bitmap 0x%hhx]\n",
3841                         native_ppfid_idx, cdev->ppfid_bitmap);
3842                 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx;
3843         }
3844
3845         return 0;
3846 }
3847
3848 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3849 {
3850         struct qed_resc_unlock_params resc_unlock_params;
3851         struct qed_resc_lock_params resc_lock_params;
3852         bool b_ah = QED_IS_AH(p_hwfn->cdev);
3853         u8 res_id;
3854         int rc;
3855
3856         /* Setting the max values of the soft resources and the following
3857          * resources allocation queries should be atomic. Since several PFs can
3858          * run in parallel - a resource lock is needed.
3859          * If either the resource lock or resource set value commands are not
3860          * supported - skip the the max values setting, release the lock if
3861          * needed, and proceed to the queries. Other failures, including a
3862          * failure to acquire the lock, will cause this function to fail.
3863          */
3864         qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3865                                        QED_RESC_LOCK_RESC_ALLOC, false);
3866
3867         rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3868         if (rc && rc != -EINVAL) {
3869                 return rc;
3870         } else if (rc == -EINVAL) {
3871                 DP_INFO(p_hwfn,
3872                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3873         } else if (!rc && !resc_lock_params.b_granted) {
3874                 DP_NOTICE(p_hwfn,
3875                           "Failed to acquire the resource lock for the resource allocation commands\n");
3876                 return -EBUSY;
3877         } else {
3878                 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
3879                 if (rc && rc != -EINVAL) {
3880                         DP_NOTICE(p_hwfn,
3881                                   "Failed to set the max values of the soft resources\n");
3882                         goto unlock_and_exit;
3883                 } else if (rc == -EINVAL) {
3884                         DP_INFO(p_hwfn,
3885                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3886                         rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
3887                                                  &resc_unlock_params);
3888                         if (rc)
3889                                 DP_INFO(p_hwfn,
3890                                         "Failed to release the resource lock for the resource allocation commands\n");
3891                 }
3892         }
3893
3894         rc = qed_hw_set_resc_info(p_hwfn);
3895         if (rc)
3896                 goto unlock_and_exit;
3897
3898         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3899                 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
3900                 if (rc)
3901                         DP_INFO(p_hwfn,
3902                                 "Failed to release the resource lock for the resource allocation commands\n");
3903         }
3904
3905         /* PPFID bitmap */
3906         if (IS_LEAD_HWFN(p_hwfn)) {
3907                 rc = qed_hw_get_ppfid_bitmap(p_hwfn, p_ptt);
3908                 if (rc)
3909                         return rc;
3910         }
3911
3912         /* Sanity for ILT */
3913         if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3914             (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3915                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
3916                           RESC_START(p_hwfn, QED_ILT),
3917                           RESC_END(p_hwfn, QED_ILT) - 1);
3918                 return -EINVAL;
3919         }
3920
3921         /* This will also learn the number of SBs from MFW */
3922         if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
3923                 return -EINVAL;
3924
3925         qed_hw_set_feat(p_hwfn);
3926
3927         for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
3928                 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
3929                            qed_hw_get_resc_name(res_id),
3930                            RESC_NUM(p_hwfn, res_id),
3931                            RESC_START(p_hwfn, res_id));
3932
3933         return 0;
3934
3935 unlock_and_exit:
3936         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3937                 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
3938         return rc;
3939 }
3940
3941 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3942 {
3943         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3944         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
3945         struct qed_mcp_link_capabilities *p_caps;
3946         struct qed_mcp_link_params *link;
3947
3948         /* Read global nvm_cfg address */
3949         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3950
3951         /* Verify MCP has initialized it */
3952         if (!nvm_cfg_addr) {
3953                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
3954                 return -EINVAL;
3955         }
3956
3957         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
3958         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3959
3960         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3961                offsetof(struct nvm_cfg1, glob) +
3962                offsetof(struct nvm_cfg1_glob, core_cfg);
3963
3964         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
3965
3966         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3967                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3968         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3969                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
3970                 break;
3971         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3972                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
3973                 break;
3974         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3975                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
3976                 break;
3977         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3978                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
3979                 break;
3980         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3981                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
3982                 break;
3983         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3984                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
3985                 break;
3986         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3987                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
3988                 break;
3989         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3990                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
3991                 break;
3992         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3993                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
3994                 break;
3995         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3996                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
3997                 break;
3998         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3999                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
4000                 break;
4001         default:
4002                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
4003                 break;
4004         }
4005
4006         /* Read default link configuration */
4007         link = &p_hwfn->mcp_info->link_input;
4008         p_caps = &p_hwfn->mcp_info->link_capabilities;
4009         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4010                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4011         link_temp = qed_rd(p_hwfn, p_ptt,
4012                            port_cfg_addr +
4013                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
4014         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
4015         link->speed.advertised_speeds = link_temp;
4016
4017         link_temp = link->speed.advertised_speeds;
4018         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
4019
4020         link_temp = qed_rd(p_hwfn, p_ptt,
4021                            port_cfg_addr +
4022                            offsetof(struct nvm_cfg1_port, link_settings));
4023         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
4024                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
4025         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
4026                 link->speed.autoneg = true;
4027                 break;
4028         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
4029                 link->speed.forced_speed = 1000;
4030                 break;
4031         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
4032                 link->speed.forced_speed = 10000;
4033                 break;
4034         case NVM_CFG1_PORT_DRV_LINK_SPEED_20G:
4035                 link->speed.forced_speed = 20000;
4036                 break;
4037         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
4038                 link->speed.forced_speed = 25000;
4039                 break;
4040         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
4041                 link->speed.forced_speed = 40000;
4042                 break;
4043         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
4044                 link->speed.forced_speed = 50000;
4045                 break;
4046         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
4047                 link->speed.forced_speed = 100000;
4048                 break;
4049         default:
4050                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
4051         }
4052
4053         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
4054                 link->speed.autoneg;
4055
4056         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
4057         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
4058         link->pause.autoneg = !!(link_temp &
4059                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
4060         link->pause.forced_rx = !!(link_temp &
4061                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
4062         link->pause.forced_tx = !!(link_temp &
4063                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
4064         link->loopback_mode = 0;
4065
4066         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
4067                 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
4068                                    offsetof(struct nvm_cfg1_port, ext_phy));
4069                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
4070                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
4071                 p_caps->default_eee = QED_MCP_EEE_ENABLED;
4072                 link->eee.enable = true;
4073                 switch (link_temp) {
4074                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
4075                         p_caps->default_eee = QED_MCP_EEE_DISABLED;
4076                         link->eee.enable = false;
4077                         break;
4078                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
4079                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
4080                         break;
4081                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
4082                         p_caps->eee_lpi_timer =
4083                             EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
4084                         break;
4085                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
4086                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
4087                         break;
4088                 }
4089
4090                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
4091                 link->eee.tx_lpi_enable = link->eee.enable;
4092                 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
4093         } else {
4094                 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
4095         }
4096
4097         DP_VERBOSE(p_hwfn,
4098                    NETIF_MSG_LINK,
4099                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
4100                    link->speed.forced_speed,
4101                    link->speed.advertised_speeds,
4102                    link->speed.autoneg,
4103                    link->pause.autoneg,
4104                    p_caps->default_eee, p_caps->eee_lpi_timer);
4105
4106         if (IS_LEAD_HWFN(p_hwfn)) {
4107                 struct qed_dev *cdev = p_hwfn->cdev;
4108
4109                 /* Read Multi-function information from shmem */
4110                 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4111                        offsetof(struct nvm_cfg1, glob) +
4112                        offsetof(struct nvm_cfg1_glob, generic_cont0);
4113
4114                 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
4115
4116                 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
4117                           NVM_CFG1_GLOB_MF_MODE_OFFSET;
4118
4119                 switch (mf_mode) {
4120                 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
4121                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
4122                         break;
4123                 case NVM_CFG1_GLOB_MF_MODE_UFP:
4124                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
4125                                         BIT(QED_MF_LLH_PROTO_CLSS) |
4126                                         BIT(QED_MF_UFP_SPECIFIC) |
4127                                         BIT(QED_MF_8021Q_TAGGING) |
4128                                         BIT(QED_MF_DONT_ADD_VLAN0_TAG);
4129                         break;
4130                 case NVM_CFG1_GLOB_MF_MODE_BD:
4131                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
4132                                         BIT(QED_MF_LLH_PROTO_CLSS) |
4133                                         BIT(QED_MF_8021AD_TAGGING) |
4134                                         BIT(QED_MF_DONT_ADD_VLAN0_TAG);
4135                         break;
4136                 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
4137                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
4138                                         BIT(QED_MF_LLH_PROTO_CLSS) |
4139                                         BIT(QED_MF_LL2_NON_UNICAST) |
4140                                         BIT(QED_MF_INTER_PF_SWITCH);
4141                         break;
4142                 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
4143                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
4144                                         BIT(QED_MF_LLH_PROTO_CLSS) |
4145                                         BIT(QED_MF_LL2_NON_UNICAST);
4146                         if (QED_IS_BB(p_hwfn->cdev))
4147                                 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
4148                         break;
4149                 }
4150
4151                 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4152                         cdev->mf_bits);
4153         }
4154
4155         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4156                 p_hwfn->cdev->mf_bits);
4157
4158         /* Read device capabilities information from shmem */
4159         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4160                 offsetof(struct nvm_cfg1, glob) +
4161                 offsetof(struct nvm_cfg1_glob, device_capabilities);
4162
4163         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
4164         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
4165                 __set_bit(QED_DEV_CAP_ETH,
4166                           &p_hwfn->hw_info.device_capabilities);
4167         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
4168                 __set_bit(QED_DEV_CAP_FCOE,
4169                           &p_hwfn->hw_info.device_capabilities);
4170         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
4171                 __set_bit(QED_DEV_CAP_ISCSI,
4172                           &p_hwfn->hw_info.device_capabilities);
4173         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
4174                 __set_bit(QED_DEV_CAP_ROCE,
4175                           &p_hwfn->hw_info.device_capabilities);
4176
4177         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
4178 }
4179
4180 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4181 {
4182         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
4183         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
4184         struct qed_dev *cdev = p_hwfn->cdev;
4185
4186         num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
4187
4188         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
4189          * in the other bits are selected.
4190          * Bits 1-15 are for functions 1-15, respectively, and their value is
4191          * '0' only for enabled functions (function 0 always exists and
4192          * enabled).
4193          * In case of CMT, only the "even" functions are enabled, and thus the
4194          * number of functions for both hwfns is learnt from the same bits.
4195          */
4196         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
4197
4198         if (reg_function_hide & 0x1) {
4199                 if (QED_IS_BB(cdev)) {
4200                         if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
4201                                 num_funcs = 0;
4202                                 eng_mask = 0xaaaa;
4203                         } else {
4204                                 num_funcs = 1;
4205                                 eng_mask = 0x5554;
4206                         }
4207                 } else {
4208                         num_funcs = 1;
4209                         eng_mask = 0xfffe;
4210                 }
4211
4212                 /* Get the number of the enabled functions on the engine */
4213                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
4214                 while (tmp) {
4215                         if (tmp & 0x1)
4216                                 num_funcs++;
4217                         tmp >>= 0x1;
4218                 }
4219
4220                 /* Get the PF index within the enabled functions */
4221                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
4222                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
4223                 while (tmp) {
4224                         if (tmp & 0x1)
4225                                 enabled_func_idx--;
4226                         tmp >>= 0x1;
4227                 }
4228         }
4229
4230         p_hwfn->num_funcs_on_engine = num_funcs;
4231         p_hwfn->enabled_func_idx = enabled_func_idx;
4232
4233         DP_VERBOSE(p_hwfn,
4234                    NETIF_MSG_PROBE,
4235                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
4236                    p_hwfn->rel_pf_id,
4237                    p_hwfn->abs_pf_id,
4238                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
4239 }
4240
4241 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4242 {
4243         u32 addr, global_offsize, global_addr, port_mode;
4244         struct qed_dev *cdev = p_hwfn->cdev;
4245
4246         /* In CMT there is always only one port */
4247         if (cdev->num_hwfns > 1) {
4248                 cdev->num_ports_in_engine = 1;
4249                 cdev->num_ports = 1;
4250                 return;
4251         }
4252
4253         /* Determine the number of ports per engine */
4254         port_mode = qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE);
4255         switch (port_mode) {
4256         case 0x0:
4257                 cdev->num_ports_in_engine = 1;
4258                 break;
4259         case 0x1:
4260                 cdev->num_ports_in_engine = 2;
4261                 break;
4262         case 0x2:
4263                 cdev->num_ports_in_engine = 4;
4264                 break;
4265         default:
4266                 DP_NOTICE(p_hwfn, "Unknown port mode 0x%08x\n", port_mode);
4267                 cdev->num_ports_in_engine = 1;  /* Default to something */
4268                 break;
4269         }
4270
4271         /* Get the total number of ports of the device */
4272         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
4273                                     PUBLIC_GLOBAL);
4274         global_offsize = qed_rd(p_hwfn, p_ptt, addr);
4275         global_addr = SECTION_ADDR(global_offsize, 0);
4276         addr = global_addr + offsetof(struct public_global, max_ports);
4277         cdev->num_ports = (u8)qed_rd(p_hwfn, p_ptt, addr);
4278 }
4279
4280 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4281 {
4282         struct qed_mcp_link_capabilities *p_caps;
4283         u32 eee_status;
4284
4285         p_caps = &p_hwfn->mcp_info->link_capabilities;
4286         if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
4287                 return;
4288
4289         p_caps->eee_speed_caps = 0;
4290         eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
4291                             offsetof(struct public_port, eee_status));
4292         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
4293                         EEE_SUPPORTED_SPEED_OFFSET;
4294
4295         if (eee_status & EEE_1G_SUPPORTED)
4296                 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
4297         if (eee_status & EEE_10G_ADV)
4298                 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
4299 }
4300
4301 static int
4302 qed_get_hw_info(struct qed_hwfn *p_hwfn,
4303                 struct qed_ptt *p_ptt,
4304                 enum qed_pci_personality personality)
4305 {
4306         int rc;
4307
4308         /* Since all information is common, only first hwfns should do this */
4309         if (IS_LEAD_HWFN(p_hwfn)) {
4310                 rc = qed_iov_hw_info(p_hwfn);
4311                 if (rc)
4312                         return rc;
4313         }
4314
4315         if (IS_LEAD_HWFN(p_hwfn))
4316                 qed_hw_info_port_num(p_hwfn, p_ptt);
4317
4318         qed_mcp_get_capabilities(p_hwfn, p_ptt);
4319
4320         qed_hw_get_nvm_info(p_hwfn, p_ptt);
4321
4322         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
4323         if (rc)
4324                 return rc;
4325
4326         if (qed_mcp_is_init(p_hwfn))
4327                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
4328                                 p_hwfn->mcp_info->func_info.mac);
4329         else
4330                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
4331
4332         if (qed_mcp_is_init(p_hwfn)) {
4333                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
4334                         p_hwfn->hw_info.ovlan =
4335                                 p_hwfn->mcp_info->func_info.ovlan;
4336
4337                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
4338
4339                 qed_get_eee_caps(p_hwfn, p_ptt);
4340
4341                 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
4342         }
4343
4344         if (qed_mcp_is_init(p_hwfn)) {
4345                 enum qed_pci_personality protocol;
4346
4347                 protocol = p_hwfn->mcp_info->func_info.protocol;
4348                 p_hwfn->hw_info.personality = protocol;
4349         }
4350
4351         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
4352                 p_hwfn->hw_info.multi_tc_roce_en = 1;
4353
4354         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
4355         p_hwfn->hw_info.num_active_tc = 1;
4356
4357         qed_get_num_funcs(p_hwfn, p_ptt);
4358
4359         if (qed_mcp_is_init(p_hwfn))
4360                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
4361
4362         return qed_hw_get_resc(p_hwfn, p_ptt);
4363 }
4364
4365 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4366 {
4367         struct qed_dev *cdev = p_hwfn->cdev;
4368         u16 device_id_mask;
4369         u32 tmp;
4370
4371         /* Read Vendor Id / Device Id */
4372         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
4373         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
4374
4375         /* Determine type */
4376         device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
4377         switch (device_id_mask) {
4378         case QED_DEV_ID_MASK_BB:
4379                 cdev->type = QED_DEV_TYPE_BB;
4380                 break;
4381         case QED_DEV_ID_MASK_AH:
4382                 cdev->type = QED_DEV_TYPE_AH;
4383                 break;
4384         default:
4385                 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
4386                 return -EBUSY;
4387         }
4388
4389         cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
4390         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
4391
4392         MASK_FIELD(CHIP_REV, cdev->chip_rev);
4393
4394         /* Learn number of HW-functions */
4395         tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
4396
4397         if (tmp & (1 << p_hwfn->rel_pf_id)) {
4398                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
4399                 cdev->num_hwfns = 2;
4400         } else {
4401                 cdev->num_hwfns = 1;
4402         }
4403
4404         cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
4405                                     MISCS_REG_CHIP_TEST_REG) >> 4;
4406         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
4407         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
4408         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
4409
4410         DP_INFO(cdev->hwfns,
4411                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
4412                 QED_IS_BB(cdev) ? "BB" : "AH",
4413                 'A' + cdev->chip_rev,
4414                 (int)cdev->chip_metal,
4415                 cdev->chip_num, cdev->chip_rev,
4416                 cdev->chip_bond_id, cdev->chip_metal);
4417
4418         return 0;
4419 }
4420
4421 static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
4422 {
4423         kfree(p_hwfn->nvm_info.image_att);
4424         p_hwfn->nvm_info.image_att = NULL;
4425 }
4426
4427 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
4428                                  void __iomem *p_regview,
4429                                  void __iomem *p_doorbells,
4430                                  u64 db_phys_addr,
4431                                  enum qed_pci_personality personality)
4432 {
4433         struct qed_dev *cdev = p_hwfn->cdev;
4434         int rc = 0;
4435
4436         /* Split PCI bars evenly between hwfns */
4437         p_hwfn->regview = p_regview;
4438         p_hwfn->doorbells = p_doorbells;
4439         p_hwfn->db_phys_addr = db_phys_addr;
4440
4441         if (IS_VF(p_hwfn->cdev))
4442                 return qed_vf_hw_prepare(p_hwfn);
4443
4444         /* Validate that chip access is feasible */
4445         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4446                 DP_ERR(p_hwfn,
4447                        "Reading the ME register returns all Fs; Preventing further chip access\n");
4448                 return -EINVAL;
4449         }
4450
4451         get_function_id(p_hwfn);
4452
4453         /* Allocate PTT pool */
4454         rc = qed_ptt_pool_alloc(p_hwfn);
4455         if (rc)
4456                 goto err0;
4457
4458         /* Allocate the main PTT */
4459         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4460
4461         /* First hwfn learns basic information, e.g., number of hwfns */
4462         if (!p_hwfn->my_id) {
4463                 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4464                 if (rc)
4465                         goto err1;
4466         }
4467
4468         qed_hw_hwfn_prepare(p_hwfn);
4469
4470         /* Initialize MCP structure */
4471         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4472         if (rc) {
4473                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
4474                 goto err1;
4475         }
4476
4477         /* Read the device configuration information from the HW and SHMEM */
4478         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
4479         if (rc) {
4480                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
4481                 goto err2;
4482         }
4483
4484         /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
4485          * is called as it sets the ports number in an engine.
4486          */
4487         if (IS_LEAD_HWFN(p_hwfn) && !cdev->recov_in_prog) {
4488                 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4489                 if (rc)
4490                         DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
4491         }
4492
4493         /* NVRAM info initialization and population */
4494         if (IS_LEAD_HWFN(p_hwfn)) {
4495                 rc = qed_mcp_nvm_info_populate(p_hwfn);
4496                 if (rc) {
4497                         DP_NOTICE(p_hwfn,
4498                                   "Failed to populate nvm info shadow\n");
4499                         goto err2;
4500                 }
4501         }
4502
4503         /* Allocate the init RT array and initialize the init-ops engine */
4504         rc = qed_init_alloc(p_hwfn);
4505         if (rc)
4506                 goto err3;
4507
4508         return rc;
4509 err3:
4510         if (IS_LEAD_HWFN(p_hwfn))
4511                 qed_nvm_info_free(p_hwfn);
4512 err2:
4513         if (IS_LEAD_HWFN(p_hwfn))
4514                 qed_iov_free_hw_info(p_hwfn->cdev);
4515         qed_mcp_free(p_hwfn);
4516 err1:
4517         qed_hw_hwfn_free(p_hwfn);
4518 err0:
4519         return rc;
4520 }
4521
4522 int qed_hw_prepare(struct qed_dev *cdev,
4523                    int personality)
4524 {
4525         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
4526         int rc;
4527
4528         /* Store the precompiled init data ptrs */
4529         if (IS_PF(cdev))
4530                 qed_init_iro_array(cdev);
4531
4532         /* Initialize the first hwfn - will learn number of hwfns */
4533         rc = qed_hw_prepare_single(p_hwfn,
4534                                    cdev->regview,
4535                                    cdev->doorbells,
4536                                    cdev->db_phys_addr,
4537                                    personality);
4538         if (rc)
4539                 return rc;
4540
4541         personality = p_hwfn->hw_info.personality;
4542
4543         /* Initialize the rest of the hwfns */
4544         if (cdev->num_hwfns > 1) {
4545                 void __iomem *p_regview, *p_doorbell;
4546                 u64 db_phys_addr;
4547                 u32 offset;
4548
4549                 /* adjust bar offset for second engine */
4550                 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
4551                                          BAR_ID_0) / 2;
4552                 p_regview = cdev->regview + offset;
4553
4554                 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
4555                                          BAR_ID_1) / 2;
4556
4557                 p_doorbell = cdev->doorbells + offset;
4558
4559                 db_phys_addr = cdev->db_phys_addr + offset;
4560
4561                 /* prepare second hw function */
4562                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
4563                                            p_doorbell, db_phys_addr,
4564                                            personality);
4565
4566                 /* in case of error, need to free the previously
4567                  * initiliazed hwfn 0.
4568                  */
4569                 if (rc) {
4570                         if (IS_PF(cdev)) {
4571                                 qed_init_free(p_hwfn);
4572                                 qed_nvm_info_free(p_hwfn);
4573                                 qed_mcp_free(p_hwfn);
4574                                 qed_hw_hwfn_free(p_hwfn);
4575                         }
4576                 }
4577         }
4578
4579         return rc;
4580 }
4581
4582 void qed_hw_remove(struct qed_dev *cdev)
4583 {
4584         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
4585         int i;
4586
4587         if (IS_PF(cdev))
4588                 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4589                                                QED_OV_DRIVER_STATE_NOT_LOADED);
4590
4591         for_each_hwfn(cdev, i) {
4592                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4593
4594                 if (IS_VF(cdev)) {
4595                         qed_vf_pf_release(p_hwfn);
4596                         continue;
4597                 }
4598
4599                 qed_init_free(p_hwfn);
4600                 qed_hw_hwfn_free(p_hwfn);
4601                 qed_mcp_free(p_hwfn);
4602         }
4603
4604         qed_iov_free_hw_info(cdev);
4605
4606         qed_nvm_info_free(p_hwfn);
4607 }
4608
4609 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
4610                                     struct qed_chain *p_chain)
4611 {
4612         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
4613         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4614         struct qed_chain_next *p_next;
4615         u32 size, i;
4616
4617         if (!p_virt)
4618                 return;
4619
4620         size = p_chain->elem_size * p_chain->usable_per_page;
4621
4622         for (i = 0; i < p_chain->page_cnt; i++) {
4623                 if (!p_virt)
4624                         break;
4625
4626                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
4627                 p_virt_next = p_next->next_virt;
4628                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4629
4630                 dma_free_coherent(&cdev->pdev->dev,
4631                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
4632
4633                 p_virt = p_virt_next;
4634                 p_phys = p_phys_next;
4635         }
4636 }
4637
4638 static void qed_chain_free_single(struct qed_dev *cdev,
4639                                   struct qed_chain *p_chain)
4640 {
4641         if (!p_chain->p_virt_addr)
4642                 return;
4643
4644         dma_free_coherent(&cdev->pdev->dev,
4645                           QED_CHAIN_PAGE_SIZE,
4646                           p_chain->p_virt_addr, p_chain->p_phys_addr);
4647 }
4648
4649 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
4650 {
4651         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4652         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4653         u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
4654
4655         if (!pp_virt_addr_tbl)
4656                 return;
4657
4658         if (!p_pbl_virt)
4659                 goto out;
4660
4661         for (i = 0; i < page_cnt; i++) {
4662                 if (!pp_virt_addr_tbl[i])
4663                         break;
4664
4665                 dma_free_coherent(&cdev->pdev->dev,
4666                                   QED_CHAIN_PAGE_SIZE,
4667                                   pp_virt_addr_tbl[i],
4668                                   *(dma_addr_t *)p_pbl_virt);
4669
4670                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
4671         }
4672
4673         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
4674
4675         if (!p_chain->b_external_pbl)
4676                 dma_free_coherent(&cdev->pdev->dev,
4677                                   pbl_size,
4678                                   p_chain->pbl_sp.p_virt_table,
4679                                   p_chain->pbl_sp.p_phys_table);
4680 out:
4681         vfree(p_chain->pbl.pp_virt_addr_tbl);
4682         p_chain->pbl.pp_virt_addr_tbl = NULL;
4683 }
4684
4685 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
4686 {
4687         switch (p_chain->mode) {
4688         case QED_CHAIN_MODE_NEXT_PTR:
4689                 qed_chain_free_next_ptr(cdev, p_chain);
4690                 break;
4691         case QED_CHAIN_MODE_SINGLE:
4692                 qed_chain_free_single(cdev, p_chain);
4693                 break;
4694         case QED_CHAIN_MODE_PBL:
4695                 qed_chain_free_pbl(cdev, p_chain);
4696                 break;
4697         }
4698 }
4699
4700 static int
4701 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
4702                              enum qed_chain_cnt_type cnt_type,
4703                              size_t elem_size, u32 page_cnt)
4704 {
4705         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4706
4707         /* The actual chain size can be larger than the maximal possible value
4708          * after rounding up the requested elements number to pages, and after
4709          * taking into acount the unusuable elements (next-ptr elements).
4710          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4711          * size/capacity fields are of a u32 type.
4712          */
4713         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
4714              chain_size > ((u32)U16_MAX + 1)) ||
4715             (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
4716                 DP_NOTICE(cdev,
4717                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
4718                           chain_size);
4719                 return -EINVAL;
4720         }
4721
4722         return 0;
4723 }
4724
4725 static int
4726 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
4727 {
4728         void *p_virt = NULL, *p_virt_prev = NULL;
4729         dma_addr_t p_phys = 0;
4730         u32 i;
4731
4732         for (i = 0; i < p_chain->page_cnt; i++) {
4733                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4734                                             QED_CHAIN_PAGE_SIZE,
4735                                             &p_phys, GFP_KERNEL);
4736                 if (!p_virt)
4737                         return -ENOMEM;
4738
4739                 if (i == 0) {
4740                         qed_chain_init_mem(p_chain, p_virt, p_phys);
4741                         qed_chain_reset(p_chain);
4742                 } else {
4743                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4744                                                      p_virt, p_phys);
4745                 }
4746
4747                 p_virt_prev = p_virt;
4748         }
4749         /* Last page's next element should point to the beginning of the
4750          * chain.
4751          */
4752         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4753                                      p_chain->p_virt_addr,
4754                                      p_chain->p_phys_addr);
4755
4756         return 0;
4757 }
4758
4759 static int
4760 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
4761 {
4762         dma_addr_t p_phys = 0;
4763         void *p_virt = NULL;
4764
4765         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4766                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
4767         if (!p_virt)
4768                 return -ENOMEM;
4769
4770         qed_chain_init_mem(p_chain, p_virt, p_phys);
4771         qed_chain_reset(p_chain);
4772
4773         return 0;
4774 }
4775
4776 static int
4777 qed_chain_alloc_pbl(struct qed_dev *cdev,
4778                     struct qed_chain *p_chain,
4779                     struct qed_chain_ext_pbl *ext_pbl)
4780 {
4781         u32 page_cnt = p_chain->page_cnt, size, i;
4782         dma_addr_t p_phys = 0, p_pbl_phys = 0;
4783         void **pp_virt_addr_tbl = NULL;
4784         u8 *p_pbl_virt = NULL;
4785         void *p_virt = NULL;
4786
4787         size = page_cnt * sizeof(*pp_virt_addr_tbl);
4788         pp_virt_addr_tbl = vzalloc(size);
4789         if (!pp_virt_addr_tbl)
4790                 return -ENOMEM;
4791
4792         /* The allocation of the PBL table is done with its full size, since it
4793          * is expected to be successive.
4794          * qed_chain_init_pbl_mem() is called even in a case of an allocation
4795          * failure, since pp_virt_addr_tbl was previously allocated, and it
4796          * should be saved to allow its freeing during the error flow.
4797          */
4798         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
4799
4800         if (!ext_pbl) {
4801                 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
4802                                                 size, &p_pbl_phys, GFP_KERNEL);
4803         } else {
4804                 p_pbl_virt = ext_pbl->p_pbl_virt;
4805                 p_pbl_phys = ext_pbl->p_pbl_phys;
4806                 p_chain->b_external_pbl = true;
4807         }
4808
4809         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4810                                pp_virt_addr_tbl);
4811         if (!p_pbl_virt)
4812                 return -ENOMEM;
4813
4814         for (i = 0; i < page_cnt; i++) {
4815                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4816                                             QED_CHAIN_PAGE_SIZE,
4817                                             &p_phys, GFP_KERNEL);
4818                 if (!p_virt)
4819                         return -ENOMEM;
4820
4821                 if (i == 0) {
4822                         qed_chain_init_mem(p_chain, p_virt, p_phys);
4823                         qed_chain_reset(p_chain);
4824                 }
4825
4826                 /* Fill the PBL table with the physical address of the page */
4827                 *(dma_addr_t *)p_pbl_virt = p_phys;
4828                 /* Keep the virtual address of the page */
4829                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4830
4831                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
4832         }
4833
4834         return 0;
4835 }
4836
4837 int qed_chain_alloc(struct qed_dev *cdev,
4838                     enum qed_chain_use_mode intended_use,
4839                     enum qed_chain_mode mode,
4840                     enum qed_chain_cnt_type cnt_type,
4841                     u32 num_elems,
4842                     size_t elem_size,
4843                     struct qed_chain *p_chain,
4844                     struct qed_chain_ext_pbl *ext_pbl)
4845 {
4846         u32 page_cnt;
4847         int rc = 0;
4848
4849         if (mode == QED_CHAIN_MODE_SINGLE)
4850                 page_cnt = 1;
4851         else
4852                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4853
4854         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
4855         if (rc) {
4856                 DP_NOTICE(cdev,
4857                           "Cannot allocate a chain with the given arguments:\n");
4858                 DP_NOTICE(cdev,
4859                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4860                           intended_use, mode, cnt_type, num_elems, elem_size);
4861                 return rc;
4862         }
4863
4864         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
4865                               mode, cnt_type);
4866
4867         switch (mode) {
4868         case QED_CHAIN_MODE_NEXT_PTR:
4869                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
4870                 break;
4871         case QED_CHAIN_MODE_SINGLE:
4872                 rc = qed_chain_alloc_single(cdev, p_chain);
4873                 break;
4874         case QED_CHAIN_MODE_PBL:
4875                 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
4876                 break;
4877         }
4878         if (rc)
4879                 goto nomem;
4880
4881         return 0;
4882
4883 nomem:
4884         qed_chain_free(cdev, p_chain);
4885         return rc;
4886 }
4887
4888 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
4889 {
4890         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
4891                 u16 min, max;
4892
4893                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
4894                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
4895                 DP_NOTICE(p_hwfn,
4896                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4897                           src_id, min, max);
4898
4899                 return -EINVAL;
4900         }
4901
4902         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
4903
4904         return 0;
4905 }
4906
4907 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
4908 {
4909         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
4910                 u8 min, max;
4911
4912                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
4913                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
4914                 DP_NOTICE(p_hwfn,
4915                           "vport id [%d] is not valid, available indices [%d - %d]\n",
4916                           src_id, min, max);
4917
4918                 return -EINVAL;
4919         }
4920
4921         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
4922
4923         return 0;
4924 }
4925
4926 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
4927 {
4928         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
4929                 u8 min, max;
4930
4931                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
4932                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
4933                 DP_NOTICE(p_hwfn,
4934                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4935                           src_id, min, max);
4936
4937                 return -EINVAL;
4938         }
4939
4940         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
4941
4942         return 0;
4943 }
4944
4945 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
4946                             u32 hw_addr, void *p_eth_qzone,
4947                             size_t eth_qzone_size, u8 timeset)
4948 {
4949         struct coalescing_timeset *p_coal_timeset;
4950
4951         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
4952                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
4953                 return -EINVAL;
4954         }
4955
4956         p_coal_timeset = p_eth_qzone;
4957         memset(p_eth_qzone, 0, eth_qzone_size);
4958         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4959         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4960         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4961
4962         return 0;
4963 }
4964
4965 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
4966 {
4967         struct qed_queue_cid *p_cid = p_handle;
4968         struct qed_hwfn *p_hwfn;
4969         struct qed_ptt *p_ptt;
4970         int rc = 0;
4971
4972         p_hwfn = p_cid->p_owner;
4973
4974         if (IS_VF(p_hwfn->cdev))
4975                 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
4976
4977         p_ptt = qed_ptt_acquire(p_hwfn);
4978         if (!p_ptt)
4979                 return -EAGAIN;
4980
4981         if (rx_coal) {
4982                 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4983                 if (rc)
4984                         goto out;
4985                 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
4986         }
4987
4988         if (tx_coal) {
4989                 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4990                 if (rc)
4991                         goto out;
4992                 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
4993         }
4994 out:
4995         qed_ptt_release(p_hwfn, p_ptt);
4996         return rc;
4997 }
4998
4999 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
5000                          struct qed_ptt *p_ptt,
5001                          u16 coalesce, struct qed_queue_cid *p_cid)
5002 {
5003         struct ustorm_eth_queue_zone eth_qzone;
5004         u8 timeset, timer_res;
5005         u32 address;
5006         int rc;
5007
5008         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5009         if (coalesce <= 0x7F) {
5010                 timer_res = 0;
5011         } else if (coalesce <= 0xFF) {
5012                 timer_res = 1;
5013         } else if (coalesce <= 0x1FF) {
5014                 timer_res = 2;
5015         } else {
5016                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5017                 return -EINVAL;
5018         }
5019         timeset = (u8)(coalesce >> timer_res);
5020
5021         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5022                                    p_cid->sb_igu_id, false);
5023         if (rc)
5024                 goto out;
5025
5026         address = BAR0_MAP_REG_USDM_RAM +
5027                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5028
5029         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5030                               sizeof(struct ustorm_eth_queue_zone), timeset);
5031         if (rc)
5032                 goto out;
5033
5034 out:
5035         return rc;
5036 }
5037
5038 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
5039                          struct qed_ptt *p_ptt,
5040                          u16 coalesce, struct qed_queue_cid *p_cid)
5041 {
5042         struct xstorm_eth_queue_zone eth_qzone;
5043         u8 timeset, timer_res;
5044         u32 address;
5045         int rc;
5046
5047         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5048         if (coalesce <= 0x7F) {
5049                 timer_res = 0;
5050         } else if (coalesce <= 0xFF) {
5051                 timer_res = 1;
5052         } else if (coalesce <= 0x1FF) {
5053                 timer_res = 2;
5054         } else {
5055                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5056                 return -EINVAL;
5057         }
5058         timeset = (u8)(coalesce >> timer_res);
5059
5060         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5061                                    p_cid->sb_igu_id, true);
5062         if (rc)
5063                 goto out;
5064
5065         address = BAR0_MAP_REG_XSDM_RAM +
5066                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5067
5068         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5069                               sizeof(struct xstorm_eth_queue_zone), timeset);
5070 out:
5071         return rc;
5072 }
5073
5074 /* Calculate final WFQ values for all vports and configure them.
5075  * After this configuration each vport will have
5076  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
5077  */
5078 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
5079                                              struct qed_ptt *p_ptt,
5080                                              u32 min_pf_rate)
5081 {
5082         struct init_qm_vport_params *vport_params;
5083         int i;
5084
5085         vport_params = p_hwfn->qm_info.qm_vport_params;
5086
5087         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5088                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5089
5090                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
5091                                                 min_pf_rate;
5092                 qed_init_vport_wfq(p_hwfn, p_ptt,
5093                                    vport_params[i].first_tx_pq_id,
5094                                    vport_params[i].vport_wfq);
5095         }
5096 }
5097
5098 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
5099                                        u32 min_pf_rate)
5100
5101 {
5102         int i;
5103
5104         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5105                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5106 }
5107
5108 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
5109                                            struct qed_ptt *p_ptt,
5110                                            u32 min_pf_rate)
5111 {
5112         struct init_qm_vport_params *vport_params;
5113         int i;
5114
5115         vport_params = p_hwfn->qm_info.qm_vport_params;
5116
5117         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5118                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
5119                 qed_init_vport_wfq(p_hwfn, p_ptt,
5120                                    vport_params[i].first_tx_pq_id,
5121                                    vport_params[i].vport_wfq);
5122         }
5123 }
5124
5125 /* This function performs several validations for WFQ
5126  * configuration and required min rate for a given vport
5127  * 1. req_rate must be greater than one percent of min_pf_rate.
5128  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5129  *    rates to get less than one percent of min_pf_rate.
5130  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5131  */
5132 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
5133                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
5134 {
5135         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5136         int non_requested_count = 0, req_count = 0, i, num_vports;
5137
5138         num_vports = p_hwfn->qm_info.num_vports;
5139
5140         /* Accounting for the vports which are configured for WFQ explicitly */
5141         for (i = 0; i < num_vports; i++) {
5142                 u32 tmp_speed;
5143
5144                 if ((i != vport_id) &&
5145                     p_hwfn->qm_info.wfq_data[i].configured) {
5146                         req_count++;
5147                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5148                         total_req_min_rate += tmp_speed;
5149                 }
5150         }
5151
5152         /* Include current vport data as well */
5153         req_count++;
5154         total_req_min_rate += req_rate;
5155         non_requested_count = num_vports - req_count;
5156
5157         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
5158                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5159                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5160                            vport_id, req_rate, min_pf_rate);
5161                 return -EINVAL;
5162         }
5163
5164         if (num_vports > QED_WFQ_UNIT) {
5165                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5166                            "Number of vports is greater than %d\n",
5167                            QED_WFQ_UNIT);
5168                 return -EINVAL;
5169         }
5170
5171         if (total_req_min_rate > min_pf_rate) {
5172                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5173                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5174                            total_req_min_rate, min_pf_rate);
5175                 return -EINVAL;
5176         }
5177
5178         total_left_rate = min_pf_rate - total_req_min_rate;
5179
5180         left_rate_per_vp = total_left_rate / non_requested_count;
5181         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
5182                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5183                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5184                            left_rate_per_vp, min_pf_rate);
5185                 return -EINVAL;
5186         }
5187
5188         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5189         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5190
5191         for (i = 0; i < num_vports; i++) {
5192                 if (p_hwfn->qm_info.wfq_data[i].configured)
5193                         continue;
5194
5195                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5196         }
5197
5198         return 0;
5199 }
5200
5201 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
5202                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
5203 {
5204         struct qed_mcp_link_state *p_link;
5205         int rc = 0;
5206
5207         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
5208
5209         if (!p_link->min_pf_rate) {
5210                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5211                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5212                 return rc;
5213         }
5214
5215         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5216
5217         if (!rc)
5218                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5219                                                  p_link->min_pf_rate);
5220         else
5221                 DP_NOTICE(p_hwfn,
5222                           "Validation failed while configuring min rate\n");
5223
5224         return rc;
5225 }
5226
5227 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
5228                                                  struct qed_ptt *p_ptt,
5229                                                  u32 min_pf_rate)
5230 {
5231         bool use_wfq = false;
5232         int rc = 0;
5233         u16 i;
5234
5235         /* Validate all pre configured vports for wfq */
5236         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5237                 u32 rate;
5238
5239                 if (!p_hwfn->qm_info.wfq_data[i].configured)
5240                         continue;
5241
5242                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5243                 use_wfq = true;
5244
5245                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5246                 if (rc) {
5247                         DP_NOTICE(p_hwfn,
5248                                   "WFQ validation failed while configuring min rate\n");
5249                         break;
5250                 }
5251         }
5252
5253         if (!rc && use_wfq)
5254                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5255         else
5256                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5257
5258         return rc;
5259 }
5260
5261 /* Main API for qed clients to configure vport min rate.
5262  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5263  * rate - Speed in Mbps needs to be assigned to a given vport.
5264  */
5265 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
5266 {
5267         int i, rc = -EINVAL;
5268
5269         /* Currently not supported; Might change in future */
5270         if (cdev->num_hwfns > 1) {
5271                 DP_NOTICE(cdev,
5272                           "WFQ configuration is not supported for this device\n");
5273                 return rc;
5274         }
5275
5276         for_each_hwfn(cdev, i) {
5277                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5278                 struct qed_ptt *p_ptt;
5279
5280                 p_ptt = qed_ptt_acquire(p_hwfn);
5281                 if (!p_ptt)
5282                         return -EBUSY;
5283
5284                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5285
5286                 if (rc) {
5287                         qed_ptt_release(p_hwfn, p_ptt);
5288                         return rc;
5289                 }
5290
5291                 qed_ptt_release(p_hwfn, p_ptt);
5292         }
5293
5294         return rc;
5295 }
5296
5297 /* API to configure WFQ from mcp link change */
5298 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
5299                                          struct qed_ptt *p_ptt, u32 min_pf_rate)
5300 {
5301         int i;
5302
5303         if (cdev->num_hwfns > 1) {
5304                 DP_VERBOSE(cdev,
5305                            NETIF_MSG_LINK,
5306                            "WFQ configuration is not supported for this device\n");
5307                 return;
5308         }
5309
5310         for_each_hwfn(cdev, i) {
5311                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5312
5313                 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5314                                                       min_pf_rate);
5315         }
5316 }
5317
5318 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
5319                                      struct qed_ptt *p_ptt,
5320                                      struct qed_mcp_link_state *p_link,
5321                                      u8 max_bw)
5322 {
5323         int rc = 0;
5324
5325         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5326
5327         if (!p_link->line_speed && (max_bw != 100))
5328                 return rc;
5329
5330         p_link->speed = (p_link->line_speed * max_bw) / 100;
5331         p_hwfn->qm_info.pf_rl = p_link->speed;
5332
5333         /* Since the limiter also affects Tx-switched traffic, we don't want it
5334          * to limit such traffic in case there's no actual limit.
5335          * In that case, set limit to imaginary high boundary.
5336          */
5337         if (max_bw == 100)
5338                 p_hwfn->qm_info.pf_rl = 100000;
5339
5340         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5341                             p_hwfn->qm_info.pf_rl);
5342
5343         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5344                    "Configured MAX bandwidth to be %08x Mb/sec\n",
5345                    p_link->speed);
5346
5347         return rc;
5348 }
5349
5350 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5351 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
5352 {
5353         int i, rc = -EINVAL;
5354
5355         if (max_bw < 1 || max_bw > 100) {
5356                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
5357                 return rc;
5358         }
5359
5360         for_each_hwfn(cdev, i) {
5361                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5362                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
5363                 struct qed_mcp_link_state *p_link;
5364                 struct qed_ptt *p_ptt;
5365
5366                 p_link = &p_lead->mcp_info->link_output;
5367
5368                 p_ptt = qed_ptt_acquire(p_hwfn);
5369                 if (!p_ptt)
5370                         return -EBUSY;
5371
5372                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5373                                                       p_link, max_bw);
5374
5375                 qed_ptt_release(p_hwfn, p_ptt);
5376
5377                 if (rc)
5378                         break;
5379         }
5380
5381         return rc;
5382 }
5383
5384 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
5385                                      struct qed_ptt *p_ptt,
5386                                      struct qed_mcp_link_state *p_link,
5387                                      u8 min_bw)
5388 {
5389         int rc = 0;
5390
5391         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5392         p_hwfn->qm_info.pf_wfq = min_bw;
5393
5394         if (!p_link->line_speed)
5395                 return rc;
5396
5397         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5398
5399         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5400
5401         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5402                    "Configured MIN bandwidth to be %d Mb/sec\n",
5403                    p_link->min_pf_rate);
5404
5405         return rc;
5406 }
5407
5408 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5409 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
5410 {
5411         int i, rc = -EINVAL;
5412
5413         if (min_bw < 1 || min_bw > 100) {
5414                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
5415                 return rc;
5416         }
5417
5418         for_each_hwfn(cdev, i) {
5419                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5420                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
5421                 struct qed_mcp_link_state *p_link;
5422                 struct qed_ptt *p_ptt;
5423
5424                 p_link = &p_lead->mcp_info->link_output;
5425
5426                 p_ptt = qed_ptt_acquire(p_hwfn);
5427                 if (!p_ptt)
5428                         return -EBUSY;
5429
5430                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5431                                                       p_link, min_bw);
5432                 if (rc) {
5433                         qed_ptt_release(p_hwfn, p_ptt);
5434                         return rc;
5435                 }
5436
5437                 if (p_link->min_pf_rate) {
5438                         u32 min_rate = p_link->min_pf_rate;
5439
5440                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
5441                                                                    p_ptt,
5442                                                                    min_rate);
5443                 }
5444
5445                 qed_ptt_release(p_hwfn, p_ptt);
5446         }
5447
5448         return rc;
5449 }
5450
5451 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
5452 {
5453         struct qed_mcp_link_state *p_link;
5454
5455         p_link = &p_hwfn->mcp_info->link_output;
5456
5457         if (p_link->min_pf_rate)
5458                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
5459                                                p_link->min_pf_rate);
5460
5461         memset(p_hwfn->qm_info.wfq_data, 0,
5462                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
5463 }
5464
5465 int qed_device_num_ports(struct qed_dev *cdev)
5466 {
5467         return cdev->num_ports;
5468 }
5469
5470 void qed_set_fw_mac_addr(__le16 *fw_msb,
5471                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
5472 {
5473         ((u8 *)fw_msb)[0] = mac[1];
5474         ((u8 *)fw_msb)[1] = mac[0];
5475         ((u8 *)fw_mid)[0] = mac[3];
5476         ((u8 *)fw_mid)[1] = mac[2];
5477         ((u8 *)fw_lsb)[0] = mac[5];
5478         ((u8 *)fw_lsb)[1] = mac[4];
5479 }