drivers/net/ethernet/neterion/vxge/vxge-config.c

   1 /******************************************************************************
   2  * This software may be used and distributed according to the terms of
   3  * the GNU General Public License (GPL), incorporated herein by reference.
   4  * Drivers based on or derived from this code fall under the GPL and must
   5  * retain the authorship, copyright and license notice.  This file is not
   6  * a complete program and may only be used when the entire operating
   7  * system is licensed under the GPL.
   8  * See the file COPYING in this distribution for more information.
   9  *
  10  * vxge-config.c: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
  11  *                Virtualized Server Adapter.
  12  * Copyright(c) 2002-2010 Exar Corp.
  13  ******************************************************************************/
  14 #include <linux/vmalloc.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/io-64-nonatomic-lo-hi.h>
  17 #include <linux/pci.h>
  18 #include <linux/slab.h>
  19
  20 #include "vxge-traffic.h"
  21 #include "vxge-config.h"
  22 #include "vxge-main.h"
  23
  24 #define VXGE_HW_VPATH_STATS_PIO_READ(offset) {                          \
  25         status = __vxge_hw_vpath_stats_access(vpath,                    \
  26                                               VXGE_HW_STATS_OP_READ,    \
  27                                               offset,                   \
  28                                               &val64);                  \
  29         if (status != VXGE_HW_OK)                                       \
  30                 return status;                                          \
  31 }
  32
  33 static void
  34 vxge_hw_vpath_set_zero_rx_frm_len(struct vxge_hw_vpath_reg __iomem *vp_reg)
  35 {
  36         u64 val64;
  37
  38         val64 = readq(&vp_reg->rxmac_vcfg0);
  39         val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
  40         writeq(val64, &vp_reg->rxmac_vcfg0);
  41         val64 = readq(&vp_reg->rxmac_vcfg0);
  42 }
  43
  44 /*
  45  * vxge_hw_vpath_wait_receive_idle - Wait for Rx to become idle
  46  */
  47 int vxge_hw_vpath_wait_receive_idle(struct __vxge_hw_device *hldev, u32 vp_id)
  48 {
  49         struct vxge_hw_vpath_reg __iomem *vp_reg;
  50         struct __vxge_hw_virtualpath *vpath;
  51         u64 val64, rxd_count, rxd_spat;
  52         int count = 0, total_count = 0;
  53
  54         vpath = &hldev->virtual_paths[vp_id];
  55         vp_reg = vpath->vp_reg;
  56
  57         vxge_hw_vpath_set_zero_rx_frm_len(vp_reg);
  58
  59         /* Check that the ring controller for this vpath has enough free RxDs
  60          * to send frames to the host.  This is done by reading the
  61          * PRC_RXD_DOORBELL_VPn register and comparing the read value to the
  62          * RXD_SPAT value for the vpath.
  63          */
  64         val64 = readq(&vp_reg->prc_cfg6);
  65         rxd_spat = VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val64) + 1;
  66         /* Use a factor of 2 when comparing rxd_count against rxd_spat for some
  67          * leg room.
  68          */
  69         rxd_spat *= 2;
  70
  71         do {
  72                 mdelay(1);
  73
  74                 rxd_count = readq(&vp_reg->prc_rxd_doorbell);
  75
  76                 /* Check that the ring controller for this vpath does
  77                  * not have any frame in its pipeline.
  78                  */
  79                 val64 = readq(&vp_reg->frm_in_progress_cnt);
  80                 if ((rxd_count <= rxd_spat) || (val64 > 0))
  81                         count = 0;
  82                 else
  83                         count++;
  84                 total_count++;
  85         } while ((count < VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT) &&
  86                         (total_count < VXGE_HW_MAX_POLLING_COUNT));
  87
  88         if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
  89                 printk(KERN_ALERT "%s: Still Receiving traffic. Abort wait\n",
  90                         __func__);
  91
  92         return total_count;
  93 }
  94
  95 /* vxge_hw_device_wait_receive_idle - This function waits until all frames
  96  * stored in the frame buffer for each vpath assigned to the given
  97  * function (hldev) have been sent to the host.
  98  */
  99 void vxge_hw_device_wait_receive_idle(struct __vxge_hw_device *hldev)
 100 {
 101         int i, total_count = 0;
 102
 103         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
 104                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
 105                         continue;
 106
 107                 total_count += vxge_hw_vpath_wait_receive_idle(hldev, i);
 108                 if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
 109                         break;
 110         }
 111 }
 112
 113 /*
 114  * __vxge_hw_device_register_poll
 115  * Will poll certain register for specified amount of time.
 116  * Will poll until masked bit is not cleared.
 117  */
 118 static enum vxge_hw_status
 119 __vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
 120 {
 121         u64 val64;
 122         u32 i = 0;
 123
 124         udelay(10);
 125
 126         do {
 127                 val64 = readq(reg);
 128                 if (!(val64 & mask))
 129                         return VXGE_HW_OK;
 130                 udelay(100);
 131         } while (++i <= 9);
 132
 133         i = 0;
 134         do {
 135                 val64 = readq(reg);
 136                 if (!(val64 & mask))
 137                         return VXGE_HW_OK;
 138                 mdelay(1);
 139         } while (++i <= max_millis);
 140
 141         return VXGE_HW_FAIL;
 142 }
 143
 144 static inline enum vxge_hw_status
 145 __vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr,
 146                           u64 mask, u32 max_millis)
 147 {
 148         __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr);
 149         wmb();
 150         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr);
 151         wmb();
 152
 153         return __vxge_hw_device_register_poll(addr, mask, max_millis);
 154 }
 155
 156 static enum vxge_hw_status
 157 vxge_hw_vpath_fw_api(struct __vxge_hw_virtualpath *vpath, u32 action,
 158                      u32 fw_memo, u32 offset, u64 *data0, u64 *data1,
 159                      u64 *steer_ctrl)
 160 {
 161         struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
 162         enum vxge_hw_status status;
 163         u64 val64;
 164         u32 retry = 0, max_retry = 3;
 165
 166         spin_lock(&vpath->lock);
 167         if (!vpath->vp_open) {
 168                 spin_unlock(&vpath->lock);
 169                 max_retry = 100;
 170         }
 171
 172         writeq(*data0, &vp_reg->rts_access_steer_data0);
 173         writeq(*data1, &vp_reg->rts_access_steer_data1);
 174         wmb();
 175
 176         val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
 177                 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) |
 178                 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset) |
 179                 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
 180                 *steer_ctrl;
 181
 182         status = __vxge_hw_pio_mem_write64(val64,
 183                                            &vp_reg->rts_access_steer_ctrl,
 184                                            VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
 185                                            VXGE_HW_DEF_DEVICE_POLL_MILLIS);
 186
 187         /* The __vxge_hw_device_register_poll can udelay for a significant
 188          * amount of time, blocking other process from the CPU.  If it delays
 189          * for ~5secs, a NMI error can occur.  A way around this is to give up
 190          * the processor via msleep, but this is not allowed is under lock.
 191          * So, only allow it to sleep for ~4secs if open.  Otherwise, delay for
 192          * 1sec and sleep for 10ms until the firmware operation has completed
 193          * or timed-out.
 194          */
 195         while ((status != VXGE_HW_OK) && retry++ < max_retry) {
 196                 if (!vpath->vp_open)
 197                         msleep(20);
 198                 status = __vxge_hw_device_register_poll(
 199                                         &vp_reg->rts_access_steer_ctrl,
 200                                         VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
 201                                         VXGE_HW_DEF_DEVICE_POLL_MILLIS);
 202         }
 203
 204         if (status != VXGE_HW_OK)
 205                 goto out;
 206
 207         val64 = readq(&vp_reg->rts_access_steer_ctrl);
 208         if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
 209                 *data0 = readq(&vp_reg->rts_access_steer_data0);
 210                 *data1 = readq(&vp_reg->rts_access_steer_data1);
 211                 *steer_ctrl = val64;
 212         } else
 213                 status = VXGE_HW_FAIL;
 214
 215 out:
 216         if (vpath->vp_open)
 217                 spin_unlock(&vpath->lock);
 218         return status;
 219 }
 220
 221 enum vxge_hw_status
 222 vxge_hw_upgrade_read_version(struct __vxge_hw_device *hldev, u32 *major,
 223                              u32 *minor, u32 *build)
 224 {
 225         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
 226         struct __vxge_hw_virtualpath *vpath;
 227         enum vxge_hw_status status;
 228
 229         vpath = &hldev->virtual_paths[hldev->first_vp_id];
 230
 231         status = vxge_hw_vpath_fw_api(vpath,
 232                                       VXGE_HW_FW_UPGRADE_ACTION,
 233                                       VXGE_HW_FW_UPGRADE_MEMO,
 234                                       VXGE_HW_FW_UPGRADE_OFFSET_READ,
 235                                       &data0, &data1, &steer_ctrl);
 236         if (status != VXGE_HW_OK)
 237                 return status;
 238
 239         *major = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
 240         *minor = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
 241         *build = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
 242
 243         return status;
 244 }
 245
 246 enum vxge_hw_status vxge_hw_flash_fw(struct __vxge_hw_device *hldev)
 247 {
 248         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
 249         struct __vxge_hw_virtualpath *vpath;
 250         enum vxge_hw_status status;
 251         u32 ret;
 252
 253         vpath = &hldev->virtual_paths[hldev->first_vp_id];
 254
 255         status = vxge_hw_vpath_fw_api(vpath,
 256                                       VXGE_HW_FW_UPGRADE_ACTION,
 257                                       VXGE_HW_FW_UPGRADE_MEMO,
 258                                       VXGE_HW_FW_UPGRADE_OFFSET_COMMIT,
 259                                       &data0, &data1, &steer_ctrl);
 260         if (status != VXGE_HW_OK) {
 261                 vxge_debug_init(VXGE_ERR, "%s: FW upgrade failed", __func__);
 262                 goto exit;
 263         }
 264
 265         ret = VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(steer_ctrl) & 0x7F;
 266         if (ret != 1) {
 267                 vxge_debug_init(VXGE_ERR, "%s: FW commit failed with error %d",
 268                                 __func__, ret);
 269                 status = VXGE_HW_FAIL;
 270         }
 271
 272 exit:
 273         return status;
 274 }
 275
 276 enum vxge_hw_status
 277 vxge_update_fw_image(struct __vxge_hw_device *hldev, const u8 *fwdata, int size)
 278 {
 279         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
 280         struct __vxge_hw_virtualpath *vpath;
 281         enum vxge_hw_status status;
 282         int ret_code, sec_code;
 283
 284         vpath = &hldev->virtual_paths[hldev->first_vp_id];
 285
 286         /* send upgrade start command */
 287         status = vxge_hw_vpath_fw_api(vpath,
 288                                       VXGE_HW_FW_UPGRADE_ACTION,
 289                                       VXGE_HW_FW_UPGRADE_MEMO,
 290                                       VXGE_HW_FW_UPGRADE_OFFSET_START,
 291                                       &data0, &data1, &steer_ctrl);
 292         if (status != VXGE_HW_OK) {
 293                 vxge_debug_init(VXGE_ERR, " %s: Upgrade start cmd failed",
 294                                 __func__);
 295                 return status;
 296         }
 297
 298         /* Transfer fw image to adapter 16 bytes at a time */
 299         for (; size > 0; size -= VXGE_HW_FW_UPGRADE_BLK_SIZE) {
 300                 steer_ctrl = 0;
 301
 302                 /* The next 128bits of fwdata to be loaded onto the adapter */
 303                 data0 = *((u64 *)fwdata);
 304                 data1 = *((u64 *)fwdata + 1);
 305
 306                 status = vxge_hw_vpath_fw_api(vpath,
 307                                               VXGE_HW_FW_UPGRADE_ACTION,
 308                                               VXGE_HW_FW_UPGRADE_MEMO,
 309                                               VXGE_HW_FW_UPGRADE_OFFSET_SEND,
 310                                               &data0, &data1, &steer_ctrl);
 311                 if (status != VXGE_HW_OK) {
 312                         vxge_debug_init(VXGE_ERR, "%s: Upgrade send failed",
 313                                         __func__);
 314                         goto out;
 315                 }
 316
 317                 ret_code = VXGE_HW_UPGRADE_GET_RET_ERR_CODE(data0);
 318                 switch (ret_code) {
 319                 case VXGE_HW_FW_UPGRADE_OK:
 320                         /* All OK, send next 16 bytes. */
 321                         break;
 322                 case VXGE_FW_UPGRADE_BYTES2SKIP:
 323                         /* skip bytes in the stream */
 324                         fwdata += (data0 >> 8) & 0xFFFFFFFF;
 325                         break;
 326                 case VXGE_HW_FW_UPGRADE_DONE:
 327                         goto out;
 328                 case VXGE_HW_FW_UPGRADE_ERR:
 329                         sec_code = VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(data0);
 330                         switch (sec_code) {
 331                         case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1:
 332                         case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7:
 333                                 printk(KERN_ERR
 334                                        "corrupted data from .ncf file\n");
 335                                 break;
 336                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3:
 337                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4:
 338                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5:
 339                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6:
 340                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8:
 341                                 printk(KERN_ERR "invalid .ncf file\n");
 342                                 break;
 343                         case VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW:
 344                                 printk(KERN_ERR "buffer overflow\n");
 345                                 break;
 346                         case VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH:
 347                                 printk(KERN_ERR "failed to flash the image\n");
 348                                 break;
 349                         case VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN:
 350                                 printk(KERN_ERR
 351                                        "generic error. Unknown error type\n");
 352                                 break;
 353                         default:
 354                                 printk(KERN_ERR "Unknown error of type %d\n",
 355                                        sec_code);
 356                                 break;
 357                         }
 358                         status = VXGE_HW_FAIL;
 359                         goto out;
 360                 default:
 361                         printk(KERN_ERR "Unknown FW error: %d\n", ret_code);
 362                         status = VXGE_HW_FAIL;
 363                         goto out;
 364                 }
 365                 /* point to next 16 bytes */
 366                 fwdata += VXGE_HW_FW_UPGRADE_BLK_SIZE;
 367         }
 368 out:
 369         return status;
 370 }
 371
 372 enum vxge_hw_status
 373 vxge_hw_vpath_eprom_img_ver_get(struct __vxge_hw_device *hldev,
 374                                 struct eprom_image *img)
 375 {
 376         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
 377         struct __vxge_hw_virtualpath *vpath;
 378         enum vxge_hw_status status;
 379         int i;
 380
 381         vpath = &hldev->virtual_paths[hldev->first_vp_id];
 382
 383         for (i = 0; i < VXGE_HW_MAX_ROM_IMAGES; i++) {
 384                 data0 = VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(i);
 385                 data1 = steer_ctrl = 0;
 386
 387                 status = vxge_hw_vpath_fw_api(vpath,
 388                         VXGE_HW_FW_API_GET_EPROM_REV,
 389                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 390                         0, &data0, &data1, &steer_ctrl);
 391                 if (status != VXGE_HW_OK)
 392                         break;
 393
 394                 img[i].is_valid = VXGE_HW_GET_EPROM_IMAGE_VALID(data0);
 395                 img[i].index = VXGE_HW_GET_EPROM_IMAGE_INDEX(data0);
 396                 img[i].type = VXGE_HW_GET_EPROM_IMAGE_TYPE(data0);
 397                 img[i].version = VXGE_HW_GET_EPROM_IMAGE_REV(data0);
 398         }
 399
 400         return status;
 401 }
 402
 403 /*
 404  * __vxge_hw_channel_free - Free memory allocated for channel
 405  * This function deallocates memory from the channel and various arrays
 406  * in the channel
 407  */
 408 static void __vxge_hw_channel_free(struct __vxge_hw_channel *channel)
 409 {
 410         kfree(channel->work_arr);
 411         kfree(channel->free_arr);
 412         kfree(channel->reserve_arr);
 413         kfree(channel->orig_arr);
 414         kfree(channel);
 415 }
 416
 417 /*
 418  * __vxge_hw_channel_initialize - Initialize a channel
 419  * This function initializes a channel by properly setting the
 420  * various references
 421  */
 422 static enum vxge_hw_status
 423 __vxge_hw_channel_initialize(struct __vxge_hw_channel *channel)
 424 {
 425         u32 i;
 426         struct __vxge_hw_virtualpath *vpath;
 427
 428         vpath = channel->vph->vpath;
 429
 430         if ((channel->reserve_arr != NULL) && (channel->orig_arr != NULL)) {
 431                 for (i = 0; i < channel->length; i++)
 432                         channel->orig_arr[i] = channel->reserve_arr[i];
 433         }
 434
 435         switch (channel->type) {
 436         case VXGE_HW_CHANNEL_TYPE_FIFO:
 437                 vpath->fifoh = (struct __vxge_hw_fifo *)channel;
 438                 channel->stats = &((struct __vxge_hw_fifo *)
 439                                 channel)->stats->common_stats;
 440                 break;
 441         case VXGE_HW_CHANNEL_TYPE_RING:
 442                 vpath->ringh = (struct __vxge_hw_ring *)channel;
 443                 channel->stats = &((struct __vxge_hw_ring *)
 444                                 channel)->stats->common_stats;
 445                 break;
 446         default:
 447                 break;
 448         }
 449
 450         return VXGE_HW_OK;
 451 }
 452
 453 /*
 454  * __vxge_hw_channel_reset - Resets a channel
 455  * This function resets a channel by properly setting the various references
 456  */
 457 static enum vxge_hw_status
 458 __vxge_hw_channel_reset(struct __vxge_hw_channel *channel)
 459 {
 460         u32 i;
 461
 462         for (i = 0; i < channel->length; i++) {
 463                 if (channel->reserve_arr != NULL)
 464                         channel->reserve_arr[i] = channel->orig_arr[i];
 465                 if (channel->free_arr != NULL)
 466                         channel->free_arr[i] = NULL;
 467                 if (channel->work_arr != NULL)
 468                         channel->work_arr[i] = NULL;
 469         }
 470         channel->free_ptr = channel->length;
 471         channel->reserve_ptr = channel->length;
 472         channel->reserve_top = 0;
 473         channel->post_index = 0;
 474         channel->compl_index = 0;
 475
 476         return VXGE_HW_OK;
 477 }
 478
 479 /*
 480  * __vxge_hw_device_pci_e_init
 481  * Initialize certain PCI/PCI-X configuration registers
 482  * with recommended values. Save config space for future hw resets.
 483  */
 484 static void __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
 485 {
 486         u16 cmd = 0;
 487
 488         /* Set the PErr Repconse bit and SERR in PCI command register. */
 489         pci_read_config_word(hldev->pdev, PCI_COMMAND, &cmd);
 490         cmd |= 0x140;
 491         pci_write_config_word(hldev->pdev, PCI_COMMAND, cmd);
 492
 493         pci_save_state(hldev->pdev);
 494 }
 495
 496 /* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset
 497  * in progress
 498  * This routine checks the vpath reset in progress register is turned zero
 499  */
 500 static enum vxge_hw_status
 501 __vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog)
 502 {
 503         enum vxge_hw_status status;
 504         status = __vxge_hw_device_register_poll(vpath_rst_in_prog,
 505                         VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff),
 506                         VXGE_HW_DEF_DEVICE_POLL_MILLIS);
 507         return status;
 508 }
 509
 510 /*
 511  * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion.
 512  * Set the swapper bits appropriately for the lagacy section.
 513  */
 514 static enum vxge_hw_status
 515 __vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
 516 {
 517         u64 val64;
 518         enum vxge_hw_status status = VXGE_HW_OK;
 519
 520         val64 = readq(&legacy_reg->toc_swapper_fb);
 521
 522         wmb();
 523
 524         switch (val64) {
 525         case VXGE_HW_SWAPPER_INITIAL_VALUE:
 526                 return status;
 527
 528         case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
 529                 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
 530                         &legacy_reg->pifm_rd_swap_en);
 531                 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
 532                         &legacy_reg->pifm_rd_flip_en);
 533                 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
 534                         &legacy_reg->pifm_wr_swap_en);
 535                 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
 536                         &legacy_reg->pifm_wr_flip_en);
 537                 break;
 538
 539         case VXGE_HW_SWAPPER_BYTE_SWAPPED:
 540                 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
 541                         &legacy_reg->pifm_rd_swap_en);
 542                 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
 543                         &legacy_reg->pifm_wr_swap_en);
 544                 break;
 545
 546         case VXGE_HW_SWAPPER_BIT_FLIPPED:
 547                 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
 548                         &legacy_reg->pifm_rd_flip_en);
 549                 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
 550                         &legacy_reg->pifm_wr_flip_en);
 551                 break;
 552         }
 553
 554         wmb();
 555
 556         val64 = readq(&legacy_reg->toc_swapper_fb);
 557
 558         if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE)
 559                 status = VXGE_HW_ERR_SWAPPER_CTRL;
 560
 561         return status;
 562 }
 563
 564 /*
 565  * __vxge_hw_device_toc_get
 566  * This routine sets the swapper and reads the toc pointer and returns the
 567  * memory mapped address of the toc
 568  */
 569 static struct vxge_hw_toc_reg __iomem *
 570 __vxge_hw_device_toc_get(void __iomem *bar0)
 571 {
 572         u64 val64;
 573         struct vxge_hw_toc_reg __iomem *toc = NULL;
 574         enum vxge_hw_status status;
 575
 576         struct vxge_hw_legacy_reg __iomem *legacy_reg =
 577                 (struct vxge_hw_legacy_reg __iomem *)bar0;
 578
 579         status = __vxge_hw_legacy_swapper_set(legacy_reg);
 580         if (status != VXGE_HW_OK)
 581                 goto exit;
 582
 583         val64 = readq(&legacy_reg->toc_first_pointer);
 584         toc = bar0 + val64;
 585 exit:
 586         return toc;
 587 }
 588
 589 /*
 590  * __vxge_hw_device_reg_addr_get
 591  * This routine sets the swapper and reads the toc pointer and initializes the
 592  * register location pointers in the device object. It waits until the ric is
 593  * completed initializing registers.
 594  */
 595 static enum vxge_hw_status
 596 __vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev)
 597 {
 598         u64 val64;
 599         u32 i;
 600         enum vxge_hw_status status = VXGE_HW_OK;
 601
 602         hldev->legacy_reg = hldev->bar0;
 603
 604         hldev->toc_reg = __vxge_hw_device_toc_get(hldev->bar0);
 605         if (hldev->toc_reg  == NULL) {
 606                 status = VXGE_HW_FAIL;
 607                 goto exit;
 608         }
 609
 610         val64 = readq(&hldev->toc_reg->toc_common_pointer);
 611         hldev->common_reg = hldev->bar0 + val64;
 612
 613         val64 = readq(&hldev->toc_reg->toc_mrpcim_pointer);
 614         hldev->mrpcim_reg = hldev->bar0 + val64;
 615
 616         for (i = 0; i < VXGE_HW_TITAN_SRPCIM_REG_SPACES; i++) {
 617                 val64 = readq(&hldev->toc_reg->toc_srpcim_pointer[i]);
 618                 hldev->srpcim_reg[i] = hldev->bar0 + val64;
 619         }
 620
 621         for (i = 0; i < VXGE_HW_TITAN_VPMGMT_REG_SPACES; i++) {
 622                 val64 = readq(&hldev->toc_reg->toc_vpmgmt_pointer[i]);
 623                 hldev->vpmgmt_reg[i] = hldev->bar0 + val64;
 624         }
 625
 626         for (i = 0; i < VXGE_HW_TITAN_VPATH_REG_SPACES; i++) {
 627                 val64 = readq(&hldev->toc_reg->toc_vpath_pointer[i]);
 628                 hldev->vpath_reg[i] = hldev->bar0 + val64;
 629         }
 630
 631         val64 = readq(&hldev->toc_reg->toc_kdfc);
 632
 633         switch (VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val64)) {
 634         case 0:
 635                 hldev->kdfc = hldev->bar0 + VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val64) ;
 636                 break;
 637         default:
 638                 break;
 639         }
 640
 641         status = __vxge_hw_device_vpath_reset_in_prog_check(
 642                         (u64 __iomem *)&hldev->common_reg->vpath_rst_in_prog);
 643 exit:
 644         return status;
 645 }
 646
 647 /*
 648  * __vxge_hw_device_access_rights_get: Get Access Rights of the driver
 649  * This routine returns the Access Rights of the driver
 650  */
 651 static u32
 652 __vxge_hw_device_access_rights_get(u32 host_type, u32 func_id)
 653 {
 654         u32 access_rights = VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH;
 655
 656         switch (host_type) {
 657         case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION:
 658                 if (func_id == 0) {
 659                         access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
 660                                         VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
 661                 }
 662                 break;
 663         case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION:
 664                 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
 665                                 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
 666                 break;
 667         case VXGE_HW_NO_MR_SR_VH0_FUNCTION0:
 668                 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
 669                                 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
 670                 break;
 671         case VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION:
 672         case VXGE_HW_SR_VH_VIRTUAL_FUNCTION:
 673         case VXGE_HW_MR_SR_VH0_INVALID_CONFIG:
 674                 break;
 675         case VXGE_HW_SR_VH_FUNCTION0:
 676         case VXGE_HW_VH_NORMAL_FUNCTION:
 677                 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
 678                 break;
 679         }
 680
 681         return access_rights;
 682 }
 683 /*
 684  * __vxge_hw_device_is_privilaged
 685  * This routine checks if the device function is privilaged or not
 686  */
 687
 688 enum vxge_hw_status
 689 __vxge_hw_device_is_privilaged(u32 host_type, u32 func_id)
 690 {
 691         if (__vxge_hw_device_access_rights_get(host_type,
 692                 func_id) &
 693                 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)
 694                 return VXGE_HW_OK;
 695         else
 696                 return VXGE_HW_ERR_PRIVILEGED_OPERATION;
 697 }
 698
 699 /*
 700  * __vxge_hw_vpath_func_id_get - Get the function id of the vpath.
 701  * Returns the function number of the vpath.
 702  */
 703 static u32
 704 __vxge_hw_vpath_func_id_get(struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
 705 {
 706         u64 val64;
 707
 708         val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1);
 709
 710         return
 711          (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64);
 712 }
 713
 714 /*
 715  * __vxge_hw_device_host_info_get
 716  * This routine returns the host type assignments
 717  */
 718 static void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
 719 {
 720         u64 val64;
 721         u32 i;
 722
 723         val64 = readq(&hldev->common_reg->host_type_assignments);
 724
 725         hldev->host_type =
 726            (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
 727
 728         hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments);
 729
 730         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
 731                 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
 732                         continue;
 733
 734                 hldev->func_id =
 735                         __vxge_hw_vpath_func_id_get(hldev->vpmgmt_reg[i]);
 736
 737                 hldev->access_rights = __vxge_hw_device_access_rights_get(
 738                         hldev->host_type, hldev->func_id);
 739
 740                 hldev->virtual_paths[i].vp_open = VXGE_HW_VP_NOT_OPEN;
 741                 hldev->virtual_paths[i].vp_reg = hldev->vpath_reg[i];
 742
 743                 hldev->first_vp_id = i;
 744                 break;
 745         }
 746 }
 747
 748 /*
 749  * __vxge_hw_verify_pci_e_info - Validate the pci-e link parameters such as
 750  * link width and signalling rate.
 751  */
 752 static enum vxge_hw_status
 753 __vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
 754 {
 755         struct pci_dev *dev = hldev->pdev;
 756         u16 lnk;
 757
 758         /* Get the negotiated link width and speed from PCI config space */
 759         pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
 760
 761         if ((lnk & PCI_EXP_LNKSTA_CLS) != 1)
 762                 return VXGE_HW_ERR_INVALID_PCI_INFO;
 763
 764         switch ((lnk & PCI_EXP_LNKSTA_NLW) >> 4) {
 765         case PCIE_LNK_WIDTH_RESRV:
 766         case PCIE_LNK_X1:
 767         case PCIE_LNK_X2:
 768         case PCIE_LNK_X4:
 769         case PCIE_LNK_X8:
 770                 break;
 771         default:
 772                 return VXGE_HW_ERR_INVALID_PCI_INFO;
 773         }
 774
 775         return VXGE_HW_OK;
 776 }
 777
 778 /*
 779  * __vxge_hw_device_initialize
 780  * Initialize Titan-V hardware.
 781  */
 782 static enum vxge_hw_status
 783 __vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
 784 {
 785         enum vxge_hw_status status = VXGE_HW_OK;
 786
 787         if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev->host_type,
 788                                 hldev->func_id)) {
 789                 /* Validate the pci-e link width and speed */
 790                 status = __vxge_hw_verify_pci_e_info(hldev);
 791                 if (status != VXGE_HW_OK)
 792                         goto exit;
 793         }
 794
 795 exit:
 796         return status;
 797 }
 798
 799 /*
 800  * __vxge_hw_vpath_fw_ver_get - Get the fw version
 801  * Returns FW Version
 802  */
 803 static enum vxge_hw_status
 804 __vxge_hw_vpath_fw_ver_get(struct __vxge_hw_virtualpath *vpath,
 805                            struct vxge_hw_device_hw_info *hw_info)
 806 {
 807         struct vxge_hw_device_version *fw_version = &hw_info->fw_version;
 808         struct vxge_hw_device_date *fw_date = &hw_info->fw_date;
 809         struct vxge_hw_device_version *flash_version = &hw_info->flash_version;
 810         struct vxge_hw_device_date *flash_date = &hw_info->flash_date;
 811         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
 812         enum vxge_hw_status status;
 813
 814         status = vxge_hw_vpath_fw_api(vpath,
 815                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
 816                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 817                         0, &data0, &data1, &steer_ctrl);
 818         if (status != VXGE_HW_OK)
 819                 goto exit;
 820
 821         fw_date->day =
 822             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(data0);
 823         fw_date->month =
 824             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(data0);
 825         fw_date->year =
 826             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(data0);
 827
 828         snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
 829                  fw_date->month, fw_date->day, fw_date->year);
 830
 831         fw_version->major =
 832             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
 833         fw_version->minor =
 834             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
 835         fw_version->build =
 836             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
 837
 838         snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
 839                  fw_version->major, fw_version->minor, fw_version->build);
 840
 841         flash_date->day =
 842             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data1);
 843         flash_date->month =
 844             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data1);
 845         flash_date->year =
 846             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data1);
 847
 848         snprintf(flash_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
 849                  flash_date->month, flash_date->day, flash_date->year);
 850
 851         flash_version->major =
 852             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data1);
 853         flash_version->minor =
 854             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data1);
 855         flash_version->build =
 856             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data1);
 857
 858         snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
 859                  flash_version->major, flash_version->minor,
 860                  flash_version->build);
 861
 862 exit:
 863         return status;
 864 }
 865
 866 /*
 867  * __vxge_hw_vpath_card_info_get - Get the serial numbers,
 868  * part number and product description.
 869  */
 870 static enum vxge_hw_status
 871 __vxge_hw_vpath_card_info_get(struct __vxge_hw_virtualpath *vpath,
 872                               struct vxge_hw_device_hw_info *hw_info)
 873 {
 874         enum vxge_hw_status status;
 875         u64 data0, data1 = 0, steer_ctrl = 0;
 876         u8 *serial_number = hw_info->serial_number;
 877         u8 *part_number = hw_info->part_number;
 878         u8 *product_desc = hw_info->product_desc;
 879         u32 i, j = 0;
 880
 881         data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER;
 882
 883         status = vxge_hw_vpath_fw_api(vpath,
 884                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
 885                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 886                         0, &data0, &data1, &steer_ctrl);
 887         if (status != VXGE_HW_OK)
 888                 return status;
 889
 890         ((u64 *)serial_number)[0] = be64_to_cpu(data0);
 891         ((u64 *)serial_number)[1] = be64_to_cpu(data1);
 892
 893         data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER;
 894         data1 = steer_ctrl = 0;
 895
 896         status = vxge_hw_vpath_fw_api(vpath,
 897                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
 898                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 899                         0, &data0, &data1, &steer_ctrl);
 900         if (status != VXGE_HW_OK)
 901                 return status;
 902
 903         ((u64 *)part_number)[0] = be64_to_cpu(data0);
 904         ((u64 *)part_number)[1] = be64_to_cpu(data1);
 905
 906         for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
 907              i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) {
 908                 data0 = i;
 909                 data1 = steer_ctrl = 0;
 910
 911                 status = vxge_hw_vpath_fw_api(vpath,
 912                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
 913                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 914                         0, &data0, &data1, &steer_ctrl);
 915                 if (status != VXGE_HW_OK)
 916                         return status;
 917
 918                 ((u64 *)product_desc)[j++] = be64_to_cpu(data0);
 919                 ((u64 *)product_desc)[j++] = be64_to_cpu(data1);
 920         }
 921
 922         return status;
 923 }
 924
 925 /*
 926  * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode
 927  * Returns pci function mode
 928  */
 929 static enum vxge_hw_status
 930 __vxge_hw_vpath_pci_func_mode_get(struct __vxge_hw_virtualpath *vpath,
 931                                   struct vxge_hw_device_hw_info *hw_info)
 932 {
 933         u64 data0, data1 = 0, steer_ctrl = 0;
 934         enum vxge_hw_status status;
 935
 936         data0 = 0;
 937
 938         status = vxge_hw_vpath_fw_api(vpath,
 939                         VXGE_HW_FW_API_GET_FUNC_MODE,
 940                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 941                         0, &data0, &data1, &steer_ctrl);
 942         if (status != VXGE_HW_OK)
 943                 return status;
 944
 945         hw_info->function_mode = VXGE_HW_GET_FUNC_MODE_VAL(data0);
 946         return status;
 947 }
 948
 949 /*
 950  * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath
 951  *               from MAC address table.
 952  */
 953 static enum vxge_hw_status
 954 __vxge_hw_vpath_addr_get(struct __vxge_hw_virtualpath *vpath,
 955                          u8 *macaddr, u8 *macaddr_mask)
 956 {
 957         u64 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
 958             data0 = 0, data1 = 0, steer_ctrl = 0;
 959         enum vxge_hw_status status;
 960         int i;
 961
 962         do {
 963                 status = vxge_hw_vpath_fw_api(vpath, action,
 964                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
 965                         0, &data0, &data1, &steer_ctrl);
 966                 if (status != VXGE_HW_OK)
 967                         goto exit;
 968
 969                 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data0);
 970                 data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(
 971                                                                         data1);
 972
 973                 for (i = ETH_ALEN; i > 0; i--) {
 974                         macaddr[i - 1] = (u8) (data0 & 0xFF);
 975                         data0 >>= 8;
 976
 977                         macaddr_mask[i - 1] = (u8) (data1 & 0xFF);
 978                         data1 >>= 8;
 979                 }
 980
 981                 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY;
 982                 data0 = 0, data1 = 0, steer_ctrl = 0;
 983
 984         } while (!is_valid_ether_addr(macaddr));
 985 exit:
 986         return status;
 987 }
 988
 989 /**
 990  * vxge_hw_device_hw_info_get - Get the hw information
 991  * Returns the vpath mask that has the bits set for each vpath allocated
 992  * for the driver, FW version information, and the first mac address for
 993  * each vpath
 994  */
 995 enum vxge_hw_status
 996 vxge_hw_device_hw_info_get(void __iomem *bar0,
 997                            struct vxge_hw_device_hw_info *hw_info)
 998 {
 999         u32 i;
1000         u64 val64;
1001         struct vxge_hw_toc_reg __iomem *toc;
1002         struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg;
1003         struct vxge_hw_common_reg __iomem *common_reg;
1004         struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
1005         enum vxge_hw_status status;
1006         struct __vxge_hw_virtualpath vpath;
1007
1008         memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info));
1009
1010         toc = __vxge_hw_device_toc_get(bar0);
1011         if (toc == NULL) {
1012                 status = VXGE_HW_ERR_CRITICAL;
1013                 goto exit;
1014         }
1015
1016         val64 = readq(&toc->toc_common_pointer);
1017         common_reg = bar0 + val64;
1018
1019         status = __vxge_hw_device_vpath_reset_in_prog_check(
1020                 (u64 __iomem *)&common_reg->vpath_rst_in_prog);
1021         if (status != VXGE_HW_OK)
1022                 goto exit;
1023
1024         hw_info->vpath_mask = readq(&common_reg->vpath_assignments);
1025
1026         val64 = readq(&common_reg->host_type_assignments);
1027
1028         hw_info->host_type =
1029            (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
1030
1031         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1032                 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1033                         continue;
1034
1035                 val64 = readq(&toc->toc_vpmgmt_pointer[i]);
1036
1037                 vpmgmt_reg = bar0 + val64;
1038
1039                 hw_info->func_id = __vxge_hw_vpath_func_id_get(vpmgmt_reg);
1040                 if (__vxge_hw_device_access_rights_get(hw_info->host_type,
1041                         hw_info->func_id) &
1042                         VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) {
1043
1044                         val64 = readq(&toc->toc_mrpcim_pointer);
1045
1046                         mrpcim_reg = bar0 + val64;
1047
1048                         writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask);
1049                         wmb();
1050                 }
1051
1052                 val64 = readq(&toc->toc_vpath_pointer[i]);
1053
1054                 spin_lock_init(&vpath.lock);
1055                 vpath.vp_reg = bar0 + val64;
1056                 vpath.vp_open = VXGE_HW_VP_NOT_OPEN;
1057
1058                 status = __vxge_hw_vpath_pci_func_mode_get(&vpath, hw_info);
1059                 if (status != VXGE_HW_OK)
1060                         goto exit;
1061
1062                 status = __vxge_hw_vpath_fw_ver_get(&vpath, hw_info);
1063                 if (status != VXGE_HW_OK)
1064                         goto exit;
1065
1066                 status = __vxge_hw_vpath_card_info_get(&vpath, hw_info);
1067                 if (status != VXGE_HW_OK)
1068                         goto exit;
1069
1070                 break;
1071         }
1072
1073         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1074                 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1075                         continue;
1076
1077                 val64 = readq(&toc->toc_vpath_pointer[i]);
1078                 vpath.vp_reg = bar0 + val64;
1079                 vpath.vp_open = VXGE_HW_VP_NOT_OPEN;
1080
1081                 status =  __vxge_hw_vpath_addr_get(&vpath,
1082                                 hw_info->mac_addrs[i],
1083                                 hw_info->mac_addr_masks[i]);
1084                 if (status != VXGE_HW_OK)
1085                         goto exit;
1086         }
1087 exit:
1088         return status;
1089 }
1090
1091 /*
1092  * __vxge_hw_blockpool_destroy - Deallocates the block pool
1093  */
1094 static void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool)
1095 {
1096         struct __vxge_hw_device *hldev;
1097         struct list_head *p, *n;
1098
1099         if (!blockpool)
1100                 return;
1101
1102         hldev = blockpool->hldev;
1103
1104         list_for_each_safe(p, n, &blockpool->free_block_list) {
1105                 pci_unmap_single(hldev->pdev,
1106                         ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
1107                         ((struct __vxge_hw_blockpool_entry *)p)->length,
1108                         PCI_DMA_BIDIRECTIONAL);
1109
1110                 vxge_os_dma_free(hldev->pdev,
1111                         ((struct __vxge_hw_blockpool_entry *)p)->memblock,
1112                         &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
1113
1114                 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
1115                 kfree(p);
1116                 blockpool->pool_size--;
1117         }
1118
1119         list_for_each_safe(p, n, &blockpool->free_entry_list) {
1120                 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
1121                 kfree((void *)p);
1122         }
1123
1124         return;
1125 }
1126
1127 /*
1128  * __vxge_hw_blockpool_create - Create block pool
1129  */
1130 static enum vxge_hw_status
1131 __vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
1132                            struct __vxge_hw_blockpool *blockpool,
1133                            u32 pool_size,
1134                            u32 pool_max)
1135 {
1136         u32 i;
1137         struct __vxge_hw_blockpool_entry *entry = NULL;
1138         void *memblock;
1139         dma_addr_t dma_addr;
1140         struct pci_dev *dma_handle;
1141         struct pci_dev *acc_handle;
1142         enum vxge_hw_status status = VXGE_HW_OK;
1143
1144         if (blockpool == NULL) {
1145                 status = VXGE_HW_FAIL;
1146                 goto blockpool_create_exit;
1147         }
1148
1149         blockpool->hldev = hldev;
1150         blockpool->block_size = VXGE_HW_BLOCK_SIZE;
1151         blockpool->pool_size = 0;
1152         blockpool->pool_max = pool_max;
1153         blockpool->req_out = 0;
1154
1155         INIT_LIST_HEAD(&blockpool->free_block_list);
1156         INIT_LIST_HEAD(&blockpool->free_entry_list);
1157
1158         for (i = 0; i < pool_size + pool_max; i++) {
1159                 entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
1160                                 GFP_KERNEL);
1161                 if (entry == NULL) {
1162                         __vxge_hw_blockpool_destroy(blockpool);
1163                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1164                         goto blockpool_create_exit;
1165                 }
1166                 list_add(&entry->item, &blockpool->free_entry_list);
1167         }
1168
1169         for (i = 0; i < pool_size; i++) {
1170                 memblock = vxge_os_dma_malloc(
1171                                 hldev->pdev,
1172                                 VXGE_HW_BLOCK_SIZE,
1173                                 &dma_handle,
1174                                 &acc_handle);
1175                 if (memblock == NULL) {
1176                         __vxge_hw_blockpool_destroy(blockpool);
1177                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1178                         goto blockpool_create_exit;
1179                 }
1180
1181                 dma_addr = pci_map_single(hldev->pdev, memblock,
1182                                 VXGE_HW_BLOCK_SIZE, PCI_DMA_BIDIRECTIONAL);
1183                 if (unlikely(pci_dma_mapping_error(hldev->pdev,
1184                                 dma_addr))) {
1185                         vxge_os_dma_free(hldev->pdev, memblock, &acc_handle);
1186                         __vxge_hw_blockpool_destroy(blockpool);
1187                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1188                         goto blockpool_create_exit;
1189                 }
1190
1191                 if (!list_empty(&blockpool->free_entry_list))
1192                         entry = (struct __vxge_hw_blockpool_entry *)
1193                                 list_first_entry(&blockpool->free_entry_list,
1194                                         struct __vxge_hw_blockpool_entry,
1195                                         item);
1196
1197                 if (entry == NULL)
1198                         entry =
1199                             kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
1200                                         GFP_KERNEL);
1201                 if (entry != NULL) {
1202                         list_del(&entry->item);
1203                         entry->length = VXGE_HW_BLOCK_SIZE;
1204                         entry->memblock = memblock;
1205                         entry->dma_addr = dma_addr;
1206                         entry->acc_handle = acc_handle;
1207                         entry->dma_handle = dma_handle;
1208                         list_add(&entry->item,
1209                                           &blockpool->free_block_list);
1210                         blockpool->pool_size++;
1211                 } else {
1212                         __vxge_hw_blockpool_destroy(blockpool);
1213                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1214                         goto blockpool_create_exit;
1215                 }
1216         }
1217
1218 blockpool_create_exit:
1219         return status;
1220 }
1221
1222 /*
1223  * __vxge_hw_device_fifo_config_check - Check fifo configuration.
1224  * Check the fifo configuration
1225  */
1226 static enum vxge_hw_status
1227 __vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config)
1228 {
1229         if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) ||
1230             (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS))
1231                 return VXGE_HW_BADCFG_FIFO_BLOCKS;
1232
1233         return VXGE_HW_OK;
1234 }
1235
1236 /*
1237  * __vxge_hw_device_vpath_config_check - Check vpath configuration.
1238  * Check the vpath configuration
1239  */
1240 static enum vxge_hw_status
1241 __vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config)
1242 {
1243         enum vxge_hw_status status;
1244
1245         if ((vp_config->min_bandwidth < VXGE_HW_VPATH_BANDWIDTH_MIN) ||
1246             (vp_config->min_bandwidth > VXGE_HW_VPATH_BANDWIDTH_MAX))
1247                 return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH;
1248
1249         status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
1250         if (status != VXGE_HW_OK)
1251                 return status;
1252
1253         if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
1254                 ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) ||
1255                 (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU)))
1256                 return VXGE_HW_BADCFG_VPATH_MTU;
1257
1258         if ((vp_config->rpa_strip_vlan_tag !=
1259                 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
1260                 (vp_config->rpa_strip_vlan_tag !=
1261                 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
1262                 (vp_config->rpa_strip_vlan_tag !=
1263                 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
1264                 return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG;
1265
1266         return VXGE_HW_OK;
1267 }
1268
1269 /*
1270  * __vxge_hw_device_config_check - Check device configuration.
1271  * Check the device configuration
1272  */
1273 static enum vxge_hw_status
1274 __vxge_hw_device_config_check(struct vxge_hw_device_config *new_config)
1275 {
1276         u32 i;
1277         enum vxge_hw_status status;
1278
1279         if ((new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
1280             (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
1281             (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
1282             (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF))
1283                 return VXGE_HW_BADCFG_INTR_MODE;
1284
1285         if ((new_config->rts_mac_en != VXGE_HW_RTS_MAC_DISABLE) &&
1286             (new_config->rts_mac_en != VXGE_HW_RTS_MAC_ENABLE))
1287                 return VXGE_HW_BADCFG_RTS_MAC_EN;
1288
1289         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1290                 status = __vxge_hw_device_vpath_config_check(
1291                                 &new_config->vp_config[i]);
1292                 if (status != VXGE_HW_OK)
1293                         return status;
1294         }
1295
1296         return VXGE_HW_OK;
1297 }
1298
1299 /*
1300  * vxge_hw_device_initialize - Initialize Titan device.
1301  * Initialize Titan device. Note that all the arguments of this public API
1302  * are 'IN', including @hldev. Driver cooperates with
1303  * OS to find new Titan device, locate its PCI and memory spaces.
1304  *
1305  * When done, the driver allocates sizeof(struct __vxge_hw_device) bytes for HW
1306  * to enable the latter to perform Titan hardware initialization.
1307  */
1308 enum vxge_hw_status
1309 vxge_hw_device_initialize(
1310         struct __vxge_hw_device **devh,
1311         struct vxge_hw_device_attr *attr,
1312         struct vxge_hw_device_config *device_config)
1313 {
1314         u32 i;
1315         u32 nblocks = 0;
1316         struct __vxge_hw_device *hldev = NULL;
1317         enum vxge_hw_status status = VXGE_HW_OK;
1318
1319         status = __vxge_hw_device_config_check(device_config);
1320         if (status != VXGE_HW_OK)
1321                 goto exit;
1322
1323         hldev = vzalloc(sizeof(struct __vxge_hw_device));
1324         if (hldev == NULL) {
1325                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1326                 goto exit;
1327         }
1328
1329         hldev->magic = VXGE_HW_DEVICE_MAGIC;
1330
1331         vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_ALL);
1332
1333         /* apply config */
1334         memcpy(&hldev->config, device_config,
1335                 sizeof(struct vxge_hw_device_config));
1336
1337         hldev->bar0 = attr->bar0;
1338         hldev->pdev = attr->pdev;
1339
1340         hldev->uld_callbacks = attr->uld_callbacks;
1341
1342         __vxge_hw_device_pci_e_init(hldev);
1343
1344         status = __vxge_hw_device_reg_addr_get(hldev);
1345         if (status != VXGE_HW_OK) {
1346                 vfree(hldev);
1347                 goto exit;
1348         }
1349
1350         __vxge_hw_device_host_info_get(hldev);
1351
1352         /* Incrementing for stats blocks */
1353         nblocks++;
1354
1355         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1356                 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
1357                         continue;
1358
1359                 if (device_config->vp_config[i].ring.enable ==
1360                         VXGE_HW_RING_ENABLE)
1361                         nblocks += device_config->vp_config[i].ring.ring_blocks;
1362
1363                 if (device_config->vp_config[i].fifo.enable ==
1364                         VXGE_HW_FIFO_ENABLE)
1365                         nblocks += device_config->vp_config[i].fifo.fifo_blocks;
1366                 nblocks++;
1367         }
1368
1369         if (__vxge_hw_blockpool_create(hldev,
1370                 &hldev->block_pool,
1371                 device_config->dma_blockpool_initial + nblocks,
1372                 device_config->dma_blockpool_max + nblocks) != VXGE_HW_OK) {
1373
1374                 vxge_hw_device_terminate(hldev);
1375                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1376                 goto exit;
1377         }
1378
1379         status = __vxge_hw_device_initialize(hldev);
1380         if (status != VXGE_HW_OK) {
1381                 vxge_hw_device_terminate(hldev);
1382                 goto exit;
1383         }
1384
1385         *devh = hldev;
1386 exit:
1387         return status;
1388 }
1389
1390 /*
1391  * vxge_hw_device_terminate - Terminate Titan device.
1392  * Terminate HW device.
1393  */
1394 void
1395 vxge_hw_device_terminate(struct __vxge_hw_device *hldev)
1396 {
1397         vxge_assert(hldev->magic == VXGE_HW_DEVICE_MAGIC);
1398
1399         hldev->magic = VXGE_HW_DEVICE_DEAD;
1400         __vxge_hw_blockpool_destroy(&hldev->block_pool);
1401         vfree(hldev);
1402 }
1403
1404 /*
1405  * __vxge_hw_vpath_stats_access - Get the statistics from the given location
1406  *                           and offset and perform an operation
1407  */
1408 static enum vxge_hw_status
1409 __vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath,
1410                              u32 operation, u32 offset, u64 *stat)
1411 {
1412         u64 val64;
1413         enum vxge_hw_status status = VXGE_HW_OK;
1414         struct vxge_hw_vpath_reg __iomem *vp_reg;
1415
1416         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1417                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1418                 goto vpath_stats_access_exit;
1419         }
1420
1421         vp_reg = vpath->vp_reg;
1422
1423         val64 =  VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) |
1424                  VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE |
1425                  VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
1426
1427         status = __vxge_hw_pio_mem_write64(val64,
1428                                 &vp_reg->xmac_stats_access_cmd,
1429                                 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE,
1430                                 vpath->hldev->config.device_poll_millis);
1431         if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1432                 *stat = readq(&vp_reg->xmac_stats_access_data);
1433         else
1434                 *stat = 0;
1435
1436 vpath_stats_access_exit:
1437         return status;
1438 }
1439
1440 /*
1441  * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
1442  */
1443 static enum vxge_hw_status
1444 __vxge_hw_vpath_xmac_tx_stats_get(struct __vxge_hw_virtualpath *vpath,
1445                         struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats)
1446 {
1447         u64 *val64;
1448         int i;
1449         u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET;
1450         enum vxge_hw_status status = VXGE_HW_OK;
1451
1452         val64 = (u64 *)vpath_tx_stats;
1453
1454         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1455                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1456                 goto exit;
1457         }
1458
1459         for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) {
1460                 status = __vxge_hw_vpath_stats_access(vpath,
1461                                         VXGE_HW_STATS_OP_READ,
1462                                         offset, val64);
1463                 if (status != VXGE_HW_OK)
1464                         goto exit;
1465                 offset++;
1466                 val64++;
1467         }
1468 exit:
1469         return status;
1470 }
1471
1472 /*
1473  * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
1474  */
1475 static enum vxge_hw_status
1476 __vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
1477                         struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats)
1478 {
1479         u64 *val64;
1480         enum vxge_hw_status status = VXGE_HW_OK;
1481         int i;
1482         u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET;
1483         val64 = (u64 *) vpath_rx_stats;
1484
1485         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1486                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1487                 goto exit;
1488         }
1489         for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) {
1490                 status = __vxge_hw_vpath_stats_access(vpath,
1491                                         VXGE_HW_STATS_OP_READ,
1492                                         offset >> 3, val64);
1493                 if (status != VXGE_HW_OK)
1494                         goto exit;
1495
1496                 offset += 8;
1497                 val64++;
1498         }
1499 exit:
1500         return status;
1501 }
1502
1503 /*
1504  * __vxge_hw_vpath_stats_get - Get the vpath hw statistics.
1505  */
1506 static enum vxge_hw_status
1507 __vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath *vpath,
1508                           struct vxge_hw_vpath_stats_hw_info *hw_stats)
1509 {
1510         u64 val64;
1511         enum vxge_hw_status status = VXGE_HW_OK;
1512         struct vxge_hw_vpath_reg __iomem *vp_reg;
1513
1514         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1515                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1516                 goto exit;
1517         }
1518         vp_reg = vpath->vp_reg;
1519
1520         val64 = readq(&vp_reg->vpath_debug_stats0);
1521         hw_stats->ini_num_mwr_sent =
1522                 (u32)VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
1523
1524         val64 = readq(&vp_reg->vpath_debug_stats1);
1525         hw_stats->ini_num_mrd_sent =
1526                 (u32)VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
1527
1528         val64 = readq(&vp_reg->vpath_debug_stats2);
1529         hw_stats->ini_num_cpl_rcvd =
1530                 (u32)VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
1531
1532         val64 = readq(&vp_reg->vpath_debug_stats3);
1533         hw_stats->ini_num_mwr_byte_sent =
1534                 VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
1535
1536         val64 = readq(&vp_reg->vpath_debug_stats4);
1537         hw_stats->ini_num_cpl_byte_rcvd =
1538                 VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
1539
1540         val64 = readq(&vp_reg->vpath_debug_stats5);
1541         hw_stats->wrcrdtarb_xoff =
1542                 (u32)VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
1543
1544         val64 = readq(&vp_reg->vpath_debug_stats6);
1545         hw_stats->rdcrdtarb_xoff =
1546                 (u32)VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
1547
1548         val64 = readq(&vp_reg->vpath_genstats_count01);
1549         hw_stats->vpath_genstats_count0 =
1550         (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
1551                 val64);
1552
1553         val64 = readq(&vp_reg->vpath_genstats_count01);
1554         hw_stats->vpath_genstats_count1 =
1555         (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
1556                 val64);
1557
1558         val64 = readq(&vp_reg->vpath_genstats_count23);
1559         hw_stats->vpath_genstats_count2 =
1560         (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
1561                 val64);
1562
1563         val64 = readq(&vp_reg->vpath_genstats_count01);
1564         hw_stats->vpath_genstats_count3 =
1565         (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
1566                 val64);
1567
1568         val64 = readq(&vp_reg->vpath_genstats_count4);
1569         hw_stats->vpath_genstats_count4 =
1570         (u32)VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
1571                 val64);
1572
1573         val64 = readq(&vp_reg->vpath_genstats_count5);
1574         hw_stats->vpath_genstats_count5 =
1575         (u32)VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
1576                 val64);
1577
1578         status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
1579         if (status != VXGE_HW_OK)
1580                 goto exit;
1581
1582         status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
1583         if (status != VXGE_HW_OK)
1584                 goto exit;
1585
1586         VXGE_HW_VPATH_STATS_PIO_READ(
1587                 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
1588
1589         hw_stats->prog_event_vnum0 =
1590                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
1591
1592         hw_stats->prog_event_vnum1 =
1593                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
1594
1595         VXGE_HW_VPATH_STATS_PIO_READ(
1596                 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
1597
1598         hw_stats->prog_event_vnum2 =
1599                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
1600
1601         hw_stats->prog_event_vnum3 =
1602                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
1603
1604         val64 = readq(&vp_reg->rx_multi_cast_stats);
1605         hw_stats->rx_multi_cast_frame_discard =
1606                 (u16)VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
1607
1608         val64 = readq(&vp_reg->rx_frm_transferred);
1609         hw_stats->rx_frm_transferred =
1610                 (u32)VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
1611
1612         val64 = readq(&vp_reg->rxd_returned);
1613         hw_stats->rxd_returned =
1614                 (u16)VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(val64);
1615
1616         val64 = readq(&vp_reg->dbg_stats_rx_mpa);
1617         hw_stats->rx_mpa_len_fail_frms =
1618                 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
1619         hw_stats->rx_mpa_mrk_fail_frms =
1620                 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
1621         hw_stats->rx_mpa_crc_fail_frms =
1622                 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
1623
1624         val64 = readq(&vp_reg->dbg_stats_rx_fau);
1625         hw_stats->rx_permitted_frms =
1626                 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
1627         hw_stats->rx_vp_reset_discarded_frms =
1628         (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
1629         hw_stats->rx_wol_frms =
1630                 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
1631
1632         val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);
1633         hw_stats->tx_vp_reset_discarded_frms =
1634         (u16)VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
1635                 val64);
1636 exit:
1637         return status;
1638 }
1639
1640 /*
1641  * vxge_hw_device_stats_get - Get the device hw statistics.
1642  * Returns the vpath h/w stats for the device.
1643  */
1644 enum vxge_hw_status
1645 vxge_hw_device_stats_get(struct __vxge_hw_device *hldev,
1646                         struct vxge_hw_device_stats_hw_info *hw_stats)
1647 {
1648         u32 i;
1649         enum vxge_hw_status status = VXGE_HW_OK;
1650
1651         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1652                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)) ||
1653                         (hldev->virtual_paths[i].vp_open ==
1654                                 VXGE_HW_VP_NOT_OPEN))
1655                         continue;
1656
1657                 memcpy(hldev->virtual_paths[i].hw_stats_sav,
1658                                 hldev->virtual_paths[i].hw_stats,
1659                                 sizeof(struct vxge_hw_vpath_stats_hw_info));
1660
1661                 status = __vxge_hw_vpath_stats_get(
1662                         &hldev->virtual_paths[i],
1663                         hldev->virtual_paths[i].hw_stats);
1664         }
1665
1666         memcpy(hw_stats, &hldev->stats.hw_dev_info_stats,
1667                         sizeof(struct vxge_hw_device_stats_hw_info));
1668
1669         return status;
1670 }
1671
1672 /*
1673  * vxge_hw_driver_stats_get - Get the device sw statistics.
1674  * Returns the vpath s/w stats for the device.
1675  */
1676 enum vxge_hw_status vxge_hw_driver_stats_get(
1677                         struct __vxge_hw_device *hldev,
1678                         struct vxge_hw_device_stats_sw_info *sw_stats)
1679 {
1680         memcpy(sw_stats, &hldev->stats.sw_dev_info_stats,
1681                 sizeof(struct vxge_hw_device_stats_sw_info));
1682
1683         return VXGE_HW_OK;
1684 }
1685
1686 /*
1687  * vxge_hw_mrpcim_stats_access - Access the statistics from the given location
1688  *                           and offset and perform an operation
1689  * Get the statistics from the given location and offset.
1690  */
1691 enum vxge_hw_status
1692 vxge_hw_mrpcim_stats_access(struct __vxge_hw_device *hldev,
1693                             u32 operation, u32 location, u32 offset, u64 *stat)
1694 {
1695         u64 val64;
1696         enum vxge_hw_status status = VXGE_HW_OK;
1697
1698         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1699                         hldev->func_id);
1700         if (status != VXGE_HW_OK)
1701                 goto exit;
1702
1703         val64 = VXGE_HW_XMAC_STATS_SYS_CMD_OP(operation) |
1704                 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE |
1705                 VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(location) |
1706                 VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset);
1707
1708         status = __vxge_hw_pio_mem_write64(val64,
1709                                 &hldev->mrpcim_reg->xmac_stats_sys_cmd,
1710                                 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE,
1711                                 hldev->config.device_poll_millis);
1712
1713         if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1714                 *stat = readq(&hldev->mrpcim_reg->xmac_stats_sys_data);
1715         else
1716                 *stat = 0;
1717 exit:
1718         return status;
1719 }
1720
1721 /*
1722  * vxge_hw_device_xmac_aggr_stats_get - Get the Statistics on aggregate port
1723  * Get the Statistics on aggregate port
1724  */
1725 static enum vxge_hw_status
1726 vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *hldev, u32 port,
1727                                    struct vxge_hw_xmac_aggr_stats *aggr_stats)
1728 {
1729         u64 *val64;
1730         int i;
1731         u32 offset = VXGE_HW_STATS_AGGRn_OFFSET;
1732         enum vxge_hw_status status = VXGE_HW_OK;
1733
1734         val64 = (u64 *)aggr_stats;
1735
1736         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1737                         hldev->func_id);
1738         if (status != VXGE_HW_OK)
1739                 goto exit;
1740
1741         for (i = 0; i < sizeof(struct vxge_hw_xmac_aggr_stats) / 8; i++) {
1742                 status = vxge_hw_mrpcim_stats_access(hldev,
1743                                         VXGE_HW_STATS_OP_READ,
1744                                         VXGE_HW_STATS_LOC_AGGR,
1745                                         ((offset + (104 * port)) >> 3), val64);
1746                 if (status != VXGE_HW_OK)
1747                         goto exit;
1748
1749                 offset += 8;
1750                 val64++;
1751         }
1752 exit:
1753         return status;
1754 }
1755
1756 /*
1757  * vxge_hw_device_xmac_port_stats_get - Get the Statistics on a port
1758  * Get the Statistics on port
1759  */
1760 static enum vxge_hw_status
1761 vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *hldev, u32 port,
1762                                    struct vxge_hw_xmac_port_stats *port_stats)
1763 {
1764         u64 *val64;
1765         enum vxge_hw_status status = VXGE_HW_OK;
1766         int i;
1767         u32 offset = 0x0;
1768         val64 = (u64 *) port_stats;
1769
1770         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1771                         hldev->func_id);
1772         if (status != VXGE_HW_OK)
1773                 goto exit;
1774
1775         for (i = 0; i < sizeof(struct vxge_hw_xmac_port_stats) / 8; i++) {
1776                 status = vxge_hw_mrpcim_stats_access(hldev,
1777                                         VXGE_HW_STATS_OP_READ,
1778                                         VXGE_HW_STATS_LOC_AGGR,
1779                                         ((offset + (608 * port)) >> 3), val64);
1780                 if (status != VXGE_HW_OK)
1781                         goto exit;
1782
1783                 offset += 8;
1784                 val64++;
1785         }
1786
1787 exit:
1788         return status;
1789 }
1790
1791 /*
1792  * vxge_hw_device_xmac_stats_get - Get the XMAC Statistics
1793  * Get the XMAC Statistics
1794  */
1795 enum vxge_hw_status
1796 vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *hldev,
1797                               struct vxge_hw_xmac_stats *xmac_stats)
1798 {
1799         enum vxge_hw_status status = VXGE_HW_OK;
1800         u32 i;
1801
1802         status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1803                                         0, &xmac_stats->aggr_stats[0]);
1804         if (status != VXGE_HW_OK)
1805                 goto exit;
1806
1807         status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1808                                 1, &xmac_stats->aggr_stats[1]);
1809         if (status != VXGE_HW_OK)
1810                 goto exit;
1811
1812         for (i = 0; i <= VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
1813
1814                 status = vxge_hw_device_xmac_port_stats_get(hldev,
1815                                         i, &xmac_stats->port_stats[i]);
1816                 if (status != VXGE_HW_OK)
1817                         goto exit;
1818         }
1819
1820         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1821
1822                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
1823                         continue;
1824
1825                 status = __vxge_hw_vpath_xmac_tx_stats_get(
1826                                         &hldev->virtual_paths[i],
1827                                         &xmac_stats->vpath_tx_stats[i]);
1828                 if (status != VXGE_HW_OK)
1829                         goto exit;
1830
1831                 status = __vxge_hw_vpath_xmac_rx_stats_get(
1832                                         &hldev->virtual_paths[i],
1833                                         &xmac_stats->vpath_rx_stats[i]);
1834                 if (status != VXGE_HW_OK)
1835                         goto exit;
1836         }
1837 exit:
1838         return status;
1839 }
1840
1841 /*
1842  * vxge_hw_device_debug_set - Set the debug module, level and timestamp
1843  * This routine is used to dynamically change the debug output
1844  */
1845 void vxge_hw_device_debug_set(struct __vxge_hw_device *hldev,
1846                               enum vxge_debug_level level, u32 mask)
1847 {
1848         if (hldev == NULL)
1849                 return;
1850
1851 #if defined(VXGE_DEBUG_TRACE_MASK) || \
1852         defined(VXGE_DEBUG_ERR_MASK)
1853         hldev->debug_module_mask = mask;
1854         hldev->debug_level = level;
1855 #endif
1856
1857 #if defined(VXGE_DEBUG_ERR_MASK)
1858         hldev->level_err = level & VXGE_ERR;
1859 #endif
1860
1861 #if defined(VXGE_DEBUG_TRACE_MASK)
1862         hldev->level_trace = level & VXGE_TRACE;
1863 #endif
1864 }
1865
1866 /*
1867  * vxge_hw_device_error_level_get - Get the error level
1868  * This routine returns the current error level set
1869  */
1870 u32 vxge_hw_device_error_level_get(struct __vxge_hw_device *hldev)
1871 {
1872 #if defined(VXGE_DEBUG_ERR_MASK)
1873         if (hldev == NULL)
1874                 return VXGE_ERR;
1875         else
1876                 return hldev->level_err;
1877 #else
1878         return 0;
1879 #endif
1880 }
1881
1882 /*
1883  * vxge_hw_device_trace_level_get - Get the trace level
1884  * This routine returns the current trace level set
1885  */
1886 u32 vxge_hw_device_trace_level_get(struct __vxge_hw_device *hldev)
1887 {
1888 #if defined(VXGE_DEBUG_TRACE_MASK)
1889         if (hldev == NULL)
1890                 return VXGE_TRACE;
1891         else
1892                 return hldev->level_trace;
1893 #else
1894         return 0;
1895 #endif
1896 }
1897
1898 /*
1899  * vxge_hw_getpause_data -Pause frame frame generation and reception.
1900  * Returns the Pause frame generation and reception capability of the NIC.
1901  */
1902 enum vxge_hw_status vxge_hw_device_getpause_data(struct __vxge_hw_device *hldev,
1903                                                  u32 port, u32 *tx, u32 *rx)
1904 {
1905         u64 val64;
1906         enum vxge_hw_status status = VXGE_HW_OK;
1907
1908         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1909                 status = VXGE_HW_ERR_INVALID_DEVICE;
1910                 goto exit;
1911         }
1912
1913         if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1914                 status = VXGE_HW_ERR_INVALID_PORT;
1915                 goto exit;
1916         }
1917
1918         if (!(hldev->access_rights & VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1919                 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
1920                 goto exit;
1921         }
1922
1923         val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1924         if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN)
1925                 *tx = 1;
1926         if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN)
1927                 *rx = 1;
1928 exit:
1929         return status;
1930 }
1931
1932 /*
1933  * vxge_hw_device_setpause_data -  set/reset pause frame generation.
1934  * It can be used to set or reset Pause frame generation or reception
1935  * support of the NIC.
1936  */
1937 enum vxge_hw_status vxge_hw_device_setpause_data(struct __vxge_hw_device *hldev,
1938                                                  u32 port, u32 tx, u32 rx)
1939 {
1940         u64 val64;
1941         enum vxge_hw_status status = VXGE_HW_OK;
1942
1943         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1944                 status = VXGE_HW_ERR_INVALID_DEVICE;
1945                 goto exit;
1946         }
1947
1948         if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1949                 status = VXGE_HW_ERR_INVALID_PORT;
1950                 goto exit;
1951         }
1952
1953         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1954                         hldev->func_id);
1955         if (status != VXGE_HW_OK)
1956                 goto exit;
1957
1958         val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1959         if (tx)
1960                 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1961         else
1962                 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1963         if (rx)
1964                 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1965         else
1966                 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1967
1968         writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1969 exit:
1970         return status;
1971 }
1972
1973 u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev)
1974 {
1975         struct pci_dev *dev = hldev->pdev;
1976         u16 lnk;
1977
1978         pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
1979         return (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4;
1980 }
1981
1982 /*
1983  * __vxge_hw_ring_block_memblock_idx - Return the memblock index
1984  * This function returns the index of memory block
1985  */
1986 static inline u32
1987 __vxge_hw_ring_block_memblock_idx(u8 *block)
1988 {
1989         return (u32)*((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET));
1990 }
1991
1992 /*
1993  * __vxge_hw_ring_block_memblock_idx_set - Sets the memblock index
1994  * This function sets index to a memory block
1995  */
1996 static inline void
1997 __vxge_hw_ring_block_memblock_idx_set(u8 *block, u32 memblock_idx)
1998 {
1999         *((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)) = memblock_idx;
2000 }
2001
2002 /*
2003  * __vxge_hw_ring_block_next_pointer_set - Sets the next block pointer
2004  * in RxD block
2005  * Sets the next block pointer in RxD block
2006  */
2007 static inline void
2008 __vxge_hw_ring_block_next_pointer_set(u8 *block, dma_addr_t dma_next)
2009 {
2010         *((u64 *)(block + VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET)) = dma_next;
2011 }
2012
2013 /*
2014  * __vxge_hw_ring_first_block_address_get - Returns the dma address of the
2015  *             first block
2016  * Returns the dma address of the first RxD block
2017  */
2018 static u64 __vxge_hw_ring_first_block_address_get(struct __vxge_hw_ring *ring)
2019 {
2020         struct vxge_hw_mempool_dma *dma_object;
2021
2022         dma_object = ring->mempool->memblocks_dma_arr;
2023         vxge_assert(dma_object != NULL);
2024
2025         return dma_object->addr;
2026 }
2027
2028 /*
2029  * __vxge_hw_ring_item_dma_addr - Return the dma address of an item
2030  * This function returns the dma address of a given item
2031  */
2032 static dma_addr_t __vxge_hw_ring_item_dma_addr(struct vxge_hw_mempool *mempoolh,
2033                                                void *item)
2034 {
2035         u32 memblock_idx;
2036         void *memblock;
2037         struct vxge_hw_mempool_dma *memblock_dma_object;
2038         ptrdiff_t dma_item_offset;
2039
2040         /* get owner memblock index */
2041         memblock_idx = __vxge_hw_ring_block_memblock_idx(item);
2042
2043         /* get owner memblock by memblock index */
2044         memblock = mempoolh->memblocks_arr[memblock_idx];
2045
2046         /* get memblock DMA object by memblock index */
2047         memblock_dma_object = mempoolh->memblocks_dma_arr + memblock_idx;
2048
2049         /* calculate offset in the memblock of this item */
2050         dma_item_offset = (u8 *)item - (u8 *)memblock;
2051
2052         return memblock_dma_object->addr + dma_item_offset;
2053 }
2054
2055 /*
2056  * __vxge_hw_ring_rxdblock_link - Link the RxD blocks
2057  * This function returns the dma address of a given item
2058  */
2059 static void __vxge_hw_ring_rxdblock_link(struct vxge_hw_mempool *mempoolh,
2060                                          struct __vxge_hw_ring *ring, u32 from,
2061                                          u32 to)
2062 {
2063         u8 *to_item , *from_item;
2064         dma_addr_t to_dma;
2065
2066         /* get "from" RxD block */
2067         from_item = mempoolh->items_arr[from];
2068         vxge_assert(from_item);
2069
2070         /* get "to" RxD block */
2071         to_item = mempoolh->items_arr[to];
2072         vxge_assert(to_item);
2073
2074         /* return address of the beginning of previous RxD block */
2075         to_dma = __vxge_hw_ring_item_dma_addr(mempoolh, to_item);
2076
2077         /* set next pointer for this RxD block to point on
2078          * previous item's DMA start address */
2079         __vxge_hw_ring_block_next_pointer_set(from_item, to_dma);
2080 }
2081
2082 /*
2083  * __vxge_hw_ring_mempool_item_alloc - Allocate List blocks for RxD
2084  * block callback
2085  * This function is callback passed to __vxge_hw_mempool_create to create memory
2086  * pool for RxD block
2087  */
2088 static void
2089 __vxge_hw_ring_mempool_item_alloc(struct vxge_hw_mempool *mempoolh,
2090                                   u32 memblock_index,
2091                                   struct vxge_hw_mempool_dma *dma_object,
2092                                   u32 index, u32 is_last)
2093 {
2094         u32 i;
2095         void *item = mempoolh->items_arr[index];
2096         struct __vxge_hw_ring *ring =
2097                 (struct __vxge_hw_ring *)mempoolh->userdata;
2098
2099         /* format rxds array */
2100         for (i = 0; i < ring->rxds_per_block; i++) {
2101                 void *rxdblock_priv;
2102                 void *uld_priv;
2103                 struct vxge_hw_ring_rxd_1 *rxdp;
2104
2105                 u32 reserve_index = ring->channel.reserve_ptr -
2106                                 (index * ring->rxds_per_block + i + 1);
2107                 u32 memblock_item_idx;
2108
2109                 ring->channel.reserve_arr[reserve_index] = ((u8 *)item) +
2110                                                 i * ring->rxd_size;
2111
2112                 /* Note: memblock_item_idx is index of the item within
2113                  *       the memblock. For instance, in case of three RxD-blocks
2114                  *       per memblock this value can be 0, 1 or 2. */
2115                 rxdblock_priv = __vxge_hw_mempool_item_priv(mempoolh,
2116                                         memblock_index, item,
2117                                         &memblock_item_idx);
2118
2119                 rxdp = ring->channel.reserve_arr[reserve_index];
2120
2121                 uld_priv = ((u8 *)rxdblock_priv + ring->rxd_priv_size * i);
2122
2123                 /* pre-format Host_Control */
2124                 rxdp->host_control = (u64)(size_t)uld_priv;
2125         }
2126
2127         __vxge_hw_ring_block_memblock_idx_set(item, memblock_index);
2128
2129         if (is_last) {
2130                 /* link last one with first one */
2131                 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index, 0);
2132         }
2133
2134         if (index > 0) {
2135                 /* link this RxD block with previous one */
2136                 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index - 1, index);
2137         }
2138 }
2139
2140 /*
2141  * __vxge_hw_ring_replenish - Initial replenish of RxDs
2142  * This function replenishes the RxDs from reserve array to work array
2143  */
2144 static enum vxge_hw_status
2145 vxge_hw_ring_replenish(struct __vxge_hw_ring *ring)
2146 {
2147         void *rxd;
2148         struct __vxge_hw_channel *channel;
2149         enum vxge_hw_status status = VXGE_HW_OK;
2150
2151         channel = &ring->channel;
2152
2153         while (vxge_hw_channel_dtr_count(channel) > 0) {
2154
2155                 status = vxge_hw_ring_rxd_reserve(ring, &rxd);
2156
2157                 vxge_assert(status == VXGE_HW_OK);
2158
2159                 if (ring->rxd_init) {
2160                         status = ring->rxd_init(rxd, channel->userdata);
2161                         if (status != VXGE_HW_OK) {
2162                                 vxge_hw_ring_rxd_free(ring, rxd);
2163                                 goto exit;
2164                         }
2165                 }
2166
2167                 vxge_hw_ring_rxd_post(ring, rxd);
2168         }
2169         status = VXGE_HW_OK;
2170 exit:
2171         return status;
2172 }
2173
2174 /*
2175  * __vxge_hw_channel_allocate - Allocate memory for channel
2176  * This function allocates required memory for the channel and various arrays
2177  * in the channel
2178  */
2179 static struct __vxge_hw_channel *
2180 __vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
2181                            enum __vxge_hw_channel_type type,
2182                            u32 length, u32 per_dtr_space,
2183                            void *userdata)
2184 {
2185         struct __vxge_hw_channel *channel;
2186         struct __vxge_hw_device *hldev;
2187         int size = 0;
2188         u32 vp_id;
2189
2190         hldev = vph->vpath->hldev;
2191         vp_id = vph->vpath->vp_id;
2192
2193         switch (type) {
2194         case VXGE_HW_CHANNEL_TYPE_FIFO:
2195                 size = sizeof(struct __vxge_hw_fifo);
2196                 break;
2197         case VXGE_HW_CHANNEL_TYPE_RING:
2198                 size = sizeof(struct __vxge_hw_ring);
2199                 break;
2200         default:
2201                 break;
2202         }
2203
2204         channel = kzalloc(size, GFP_KERNEL);
2205         if (channel == NULL)
2206                 goto exit0;
2207         INIT_LIST_HEAD(&channel->item);
2208
2209         channel->common_reg = hldev->common_reg;
2210         channel->first_vp_id = hldev->first_vp_id;
2211         channel->type = type;
2212         channel->devh = hldev;
2213         channel->vph = vph;
2214         channel->userdata = userdata;
2215         channel->per_dtr_space = per_dtr_space;
2216         channel->length = length;
2217         channel->vp_id = vp_id;
2218
2219         channel->work_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2220         if (channel->work_arr == NULL)
2221                 goto exit1;
2222
2223         channel->free_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2224         if (channel->free_arr == NULL)
2225                 goto exit1;
2226         channel->free_ptr = length;
2227
2228         channel->reserve_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2229         if (channel->reserve_arr == NULL)
2230                 goto exit1;
2231         channel->reserve_ptr = length;
2232         channel->reserve_top = 0;
2233
2234         channel->orig_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2235         if (channel->orig_arr == NULL)
2236                 goto exit1;
2237
2238         return channel;
2239 exit1:
2240         __vxge_hw_channel_free(channel);
2241
2242 exit0:
2243         return NULL;
2244 }
2245
2246 /*
2247  * vxge_hw_blockpool_block_add - callback for vxge_os_dma_malloc_async
2248  * Adds a block to block pool
2249  */
2250 static void vxge_hw_blockpool_block_add(struct __vxge_hw_device *devh,
2251                                         void *block_addr,
2252                                         u32 length,
2253                                         struct pci_dev *dma_h,
2254                                         struct pci_dev *acc_handle)
2255 {
2256         struct __vxge_hw_blockpool *blockpool;
2257         struct __vxge_hw_blockpool_entry *entry = NULL;
2258         dma_addr_t dma_addr;
2259
2260         blockpool = &devh->block_pool;
2261
2262         if (block_addr == NULL) {
2263                 blockpool->req_out--;
2264                 goto exit;
2265         }
2266
2267         dma_addr = pci_map_single(devh->pdev, block_addr, length,
2268                                 PCI_DMA_BIDIRECTIONAL);
2269
2270         if (unlikely(pci_dma_mapping_error(devh->pdev, dma_addr))) {
2271                 vxge_os_dma_free(devh->pdev, block_addr, &acc_handle);
2272                 blockpool->req_out--;
2273                 goto exit;
2274         }
2275
2276         if (!list_empty(&blockpool->free_entry_list))
2277                 entry = (struct __vxge_hw_blockpool_entry *)
2278                         list_first_entry(&blockpool->free_entry_list,
2279                                 struct __vxge_hw_blockpool_entry,
2280                                 item);
2281
2282         if (entry == NULL)
2283                 entry = vmalloc(sizeof(struct __vxge_hw_blockpool_entry));
2284         else
2285                 list_del(&entry->item);
2286
2287         if (entry) {
2288                 entry->length = length;
2289                 entry->memblock = block_addr;
2290                 entry->dma_addr = dma_addr;
2291                 entry->acc_handle = acc_handle;
2292                 entry->dma_handle = dma_h;
2293                 list_add(&entry->item, &blockpool->free_block_list);
2294                 blockpool->pool_size++;
2295         }
2296
2297         blockpool->req_out--;
2298
2299 exit:
2300         return;
2301 }
2302
2303 static inline void
2304 vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh, unsigned long size)
2305 {
2306         gfp_t flags;
2307         void *vaddr;
2308
2309         if (in_interrupt())
2310                 flags = GFP_ATOMIC | GFP_DMA;
2311         else
2312                 flags = GFP_KERNEL | GFP_DMA;
2313
2314         vaddr = kmalloc((size), flags);
2315
2316         vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev);
2317 }
2318
2319 /*
2320  * __vxge_hw_blockpool_blocks_add - Request additional blocks
2321  */
2322 static
2323 void __vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool *blockpool)
2324 {
2325         u32 nreq = 0, i;
2326
2327         if ((blockpool->pool_size  +  blockpool->req_out) <
2328                 VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE) {
2329                 nreq = VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE;
2330                 blockpool->req_out += nreq;
2331         }
2332
2333         for (i = 0; i < nreq; i++)
2334                 vxge_os_dma_malloc_async(
2335                         (blockpool->hldev)->pdev,
2336                         blockpool->hldev, VXGE_HW_BLOCK_SIZE);
2337 }
2338
2339 /*
2340  * __vxge_hw_blockpool_malloc - Allocate a memory block from pool
2341  * Allocates a block of memory of given size, either from block pool
2342  * or by calling vxge_os_dma_malloc()
2343  */
2344 static void *__vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, u32 size,
2345                                         struct vxge_hw_mempool_dma *dma_object)
2346 {
2347         struct __vxge_hw_blockpool_entry *entry = NULL;
2348         struct __vxge_hw_blockpool  *blockpool;
2349         void *memblock = NULL;
2350
2351         blockpool = &devh->block_pool;
2352
2353         if (size != blockpool->block_size) {
2354
2355                 memblock = vxge_os_dma_malloc(devh->pdev, size,
2356                                                 &dma_object->handle,
2357                                                 &dma_object->acc_handle);
2358
2359                 if (!memblock)
2360                         goto exit;
2361
2362                 dma_object->addr = pci_map_single(devh->pdev, memblock, size,
2363                                         PCI_DMA_BIDIRECTIONAL);
2364
2365                 if (unlikely(pci_dma_mapping_error(devh->pdev,
2366                                 dma_object->addr))) {
2367                         vxge_os_dma_free(devh->pdev, memblock,
2368                                 &dma_object->acc_handle);
2369                         memblock = NULL;
2370                         goto exit;
2371                 }
2372
2373         } else {
2374
2375                 if (!list_empty(&blockpool->free_block_list))
2376                         entry = (struct __vxge_hw_blockpool_entry *)
2377                                 list_first_entry(&blockpool->free_block_list,
2378                                         struct __vxge_hw_blockpool_entry,
2379                                         item);
2380
2381                 if (entry != NULL) {
2382                         list_del(&entry->item);
2383                         dma_object->addr = entry->dma_addr;
2384                         dma_object->handle = entry->dma_handle;
2385                         dma_object->acc_handle = entry->acc_handle;
2386                         memblock = entry->memblock;
2387
2388                         list_add(&entry->item,
2389                                 &blockpool->free_entry_list);
2390                         blockpool->pool_size--;
2391                 }
2392
2393                 if (memblock != NULL)
2394                         __vxge_hw_blockpool_blocks_add(blockpool);
2395         }
2396 exit:
2397         return memblock;
2398 }
2399
2400 /*
2401  * __vxge_hw_blockpool_blocks_remove - Free additional blocks
2402  */
2403 static void
2404 __vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool *blockpool)
2405 {
2406         struct list_head *p, *n;
2407
2408         list_for_each_safe(p, n, &blockpool->free_block_list) {
2409
2410                 if (blockpool->pool_size < blockpool->pool_max)
2411                         break;
2412
2413                 pci_unmap_single(
2414                         (blockpool->hldev)->pdev,
2415                         ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
2416                         ((struct __vxge_hw_blockpool_entry *)p)->length,
2417                         PCI_DMA_BIDIRECTIONAL);
2418
2419                 vxge_os_dma_free(
2420                         (blockpool->hldev)->pdev,
2421                         ((struct __vxge_hw_blockpool_entry *)p)->memblock,
2422                         &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
2423
2424                 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
2425
2426                 list_add(p, &blockpool->free_entry_list);
2427
2428                 blockpool->pool_size--;
2429
2430         }
2431 }
2432
2433 /*
2434  * __vxge_hw_blockpool_free - Frees the memory allcoated with
2435  *                              __vxge_hw_blockpool_malloc
2436  */
2437 static void __vxge_hw_blockpool_free(struct __vxge_hw_device *devh,
2438                                      void *memblock, u32 size,
2439                                      struct vxge_hw_mempool_dma *dma_object)
2440 {
2441         struct __vxge_hw_blockpool_entry *entry = NULL;
2442         struct __vxge_hw_blockpool  *blockpool;
2443         enum vxge_hw_status status = VXGE_HW_OK;
2444
2445         blockpool = &devh->block_pool;
2446
2447         if (size != blockpool->block_size) {
2448                 pci_unmap_single(devh->pdev, dma_object->addr, size,
2449                         PCI_DMA_BIDIRECTIONAL);
2450                 vxge_os_dma_free(devh->pdev, memblock, &dma_object->acc_handle);
2451         } else {
2452
2453                 if (!list_empty(&blockpool->free_entry_list))
2454                         entry = (struct __vxge_hw_blockpool_entry *)
2455                                 list_first_entry(&blockpool->free_entry_list,
2456                                         struct __vxge_hw_blockpool_entry,
2457                                         item);
2458
2459                 if (entry == NULL)
2460                         entry = vmalloc(sizeof(
2461                                         struct __vxge_hw_blockpool_entry));
2462                 else
2463                         list_del(&entry->item);
2464
2465                 if (entry != NULL) {
2466                         entry->length = size;
2467                         entry->memblock = memblock;
2468                         entry->dma_addr = dma_object->addr;
2469                         entry->acc_handle = dma_object->acc_handle;
2470                         entry->dma_handle = dma_object->handle;
2471                         list_add(&entry->item,
2472                                         &blockpool->free_block_list);
2473                         blockpool->pool_size++;
2474                         status = VXGE_HW_OK;
2475                 } else
2476                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2477
2478                 if (status == VXGE_HW_OK)
2479                         __vxge_hw_blockpool_blocks_remove(blockpool);
2480         }
2481 }
2482
2483 /*
2484  * vxge_hw_mempool_destroy
2485  */
2486 static void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool)
2487 {
2488         u32 i, j;
2489         struct __vxge_hw_device *devh = mempool->devh;
2490
2491         for (i = 0; i < mempool->memblocks_allocated; i++) {
2492                 struct vxge_hw_mempool_dma *dma_object;
2493
2494                 vxge_assert(mempool->memblocks_arr[i]);
2495                 vxge_assert(mempool->memblocks_dma_arr + i);
2496
2497                 dma_object = mempool->memblocks_dma_arr + i;
2498
2499                 for (j = 0; j < mempool->items_per_memblock; j++) {
2500                         u32 index = i * mempool->items_per_memblock + j;
2501
2502                         /* to skip last partially filled(if any) memblock */
2503                         if (index >= mempool->items_current)
2504                                 break;
2505                 }
2506
2507                 vfree(mempool->memblocks_priv_arr[i]);
2508
2509                 __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i],
2510                                 mempool->memblock_size, dma_object);
2511         }
2512
2513         vfree(mempool->items_arr);
2514         vfree(mempool->memblocks_dma_arr);
2515         vfree(mempool->memblocks_priv_arr);
2516         vfree(mempool->memblocks_arr);
2517         vfree(mempool);
2518 }
2519
2520 /*
2521  * __vxge_hw_mempool_grow
2522  * Will resize mempool up to %num_allocate value.
2523  */
2524 static enum vxge_hw_status
2525 __vxge_hw_mempool_grow(struct vxge_hw_mempool *mempool, u32 num_allocate,
2526                        u32 *num_allocated)
2527 {
2528         u32 i, first_time = mempool->memblocks_allocated == 0 ? 1 : 0;
2529         u32 n_items = mempool->items_per_memblock;
2530         u32 start_block_idx = mempool->memblocks_allocated;
2531         u32 end_block_idx = mempool->memblocks_allocated + num_allocate;
2532         enum vxge_hw_status status = VXGE_HW_OK;
2533
2534         *num_allocated = 0;
2535
2536         if (end_block_idx > mempool->memblocks_max) {
2537                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2538                 goto exit;
2539         }
2540
2541         for (i = start_block_idx; i < end_block_idx; i++) {
2542                 u32 j;
2543                 u32 is_last = ((end_block_idx - 1) == i);
2544                 struct vxge_hw_mempool_dma *dma_object =
2545                         mempool->memblocks_dma_arr + i;
2546                 void *the_memblock;
2547
2548                 /* allocate memblock's private part. Each DMA memblock
2549                  * has a space allocated for item's private usage upon
2550                  * mempool's user request. Each time mempool grows, it will
2551                  * allocate new memblock and its private part at once.
2552                  * This helps to minimize memory usage a lot. */
2553                 mempool->memblocks_priv_arr[i] =
2554                         vzalloc(array_size(mempool->items_priv_size, n_items));
2555                 if (mempool->memblocks_priv_arr[i] == NULL) {
2556                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2557                         goto exit;
2558                 }
2559
2560                 /* allocate DMA-capable memblock */
2561                 mempool->memblocks_arr[i] =
2562                         __vxge_hw_blockpool_malloc(mempool->devh,
2563                                 mempool->memblock_size, dma_object);
2564                 if (mempool->memblocks_arr[i] == NULL) {
2565                         vfree(mempool->memblocks_priv_arr[i]);
2566                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2567                         goto exit;
2568                 }
2569
2570                 (*num_allocated)++;
2571                 mempool->memblocks_allocated++;
2572
2573                 memset(mempool->memblocks_arr[i], 0, mempool->memblock_size);
2574
2575                 the_memblock = mempool->memblocks_arr[i];
2576
2577                 /* fill the items hash array */
2578                 for (j = 0; j < n_items; j++) {
2579                         u32 index = i * n_items + j;
2580
2581                         if (first_time && index >= mempool->items_initial)
2582                                 break;
2583
2584                         mempool->items_arr[index] =
2585                                 ((char *)the_memblock + j*mempool->item_size);
2586
2587                         /* let caller to do more job on each item */
2588                         if (mempool->item_func_alloc != NULL)
2589                                 mempool->item_func_alloc(mempool, i,
2590                                         dma_object, index, is_last);
2591
2592                         mempool->items_current = index + 1;
2593                 }
2594
2595                 if (first_time && mempool->items_current ==
2596                                         mempool->items_initial)
2597                         break;
2598         }
2599 exit:
2600         return status;
2601 }
2602
2603 /*
2604  * vxge_hw_mempool_create
2605  * This function will create memory pool object. Pool may grow but will
2606  * never shrink. Pool consists of number of dynamically allocated blocks
2607  * with size enough to hold %items_initial number of items. Memory is
2608  * DMA-able but client must map/unmap before interoperating with the device.
2609  */
2610 static struct vxge_hw_mempool *
2611 __vxge_hw_mempool_create(struct __vxge_hw_device *devh,
2612                          u32 memblock_size,
2613                          u32 item_size,
2614                          u32 items_priv_size,
2615                          u32 items_initial,
2616                          u32 items_max,
2617                          const struct vxge_hw_mempool_cbs *mp_callback,
2618                          void *userdata)
2619 {
2620         enum vxge_hw_status status = VXGE_HW_OK;
2621         u32 memblocks_to_allocate;
2622         struct vxge_hw_mempool *mempool = NULL;
2623         u32 allocated;
2624
2625         if (memblock_size < item_size) {
2626                 status = VXGE_HW_FAIL;
2627                 goto exit;
2628         }
2629
2630         mempool = vzalloc(sizeof(struct vxge_hw_mempool));
2631         if (mempool == NULL) {
2632                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2633                 goto exit;
2634         }
2635
2636         mempool->devh                   = devh;
2637         mempool->memblock_size          = memblock_size;
2638         mempool->items_max              = items_max;
2639         mempool->items_initial          = items_initial;
2640         mempool->item_size              = item_size;
2641         mempool->items_priv_size        = items_priv_size;
2642         mempool->item_func_alloc        = mp_callback->item_func_alloc;
2643         mempool->userdata               = userdata;
2644
2645         mempool->memblocks_allocated = 0;
2646
2647         mempool->items_per_memblock = memblock_size / item_size;
2648
2649         mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) /
2650                                         mempool->items_per_memblock;
2651
2652         /* allocate array of memblocks */
2653         mempool->memblocks_arr =
2654                 vzalloc(array_size(sizeof(void *), mempool->memblocks_max));
2655         if (mempool->memblocks_arr == NULL) {
2656                 __vxge_hw_mempool_destroy(mempool);
2657                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2658                 mempool = NULL;
2659                 goto exit;
2660         }
2661
2662         /* allocate array of private parts of items per memblocks */
2663         mempool->memblocks_priv_arr =
2664                 vzalloc(array_size(sizeof(void *), mempool->memblocks_max));
2665         if (mempool->memblocks_priv_arr == NULL) {
2666                 __vxge_hw_mempool_destroy(mempool);
2667                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2668                 mempool = NULL;
2669                 goto exit;
2670         }
2671
2672         /* allocate array of memblocks DMA objects */
2673         mempool->memblocks_dma_arr =
2674                 vzalloc(array_size(sizeof(struct vxge_hw_mempool_dma),
2675                                    mempool->memblocks_max));
2676         if (mempool->memblocks_dma_arr == NULL) {
2677                 __vxge_hw_mempool_destroy(mempool);
2678                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2679                 mempool = NULL;
2680                 goto exit;
2681         }
2682
2683         /* allocate hash array of items */
2684         mempool->items_arr = vzalloc(array_size(sizeof(void *),
2685                                                 mempool->items_max));
2686         if (mempool->items_arr == NULL) {
2687                 __vxge_hw_mempool_destroy(mempool);
2688                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2689                 mempool = NULL;
2690                 goto exit;
2691         }
2692
2693         /* calculate initial number of memblocks */
2694         memblocks_to_allocate = (mempool->items_initial +
2695                                  mempool->items_per_memblock - 1) /
2696                                                 mempool->items_per_memblock;
2697
2698         /* pre-allocate the mempool */
2699         status = __vxge_hw_mempool_grow(mempool, memblocks_to_allocate,
2700                                         &allocated);
2701         if (status != VXGE_HW_OK) {
2702                 __vxge_hw_mempool_destroy(mempool);
2703                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2704                 mempool = NULL;
2705                 goto exit;
2706         }
2707
2708 exit:
2709         return mempool;
2710 }
2711
2712 /*
2713  * __vxge_hw_ring_abort - Returns the RxD
2714  * This function terminates the RxDs of ring
2715  */
2716 static enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring)
2717 {
2718         void *rxdh;
2719         struct __vxge_hw_channel *channel;
2720
2721         channel = &ring->channel;
2722
2723         for (;;) {
2724                 vxge_hw_channel_dtr_try_complete(channel, &rxdh);
2725
2726                 if (rxdh == NULL)
2727                         break;
2728
2729                 vxge_hw_channel_dtr_complete(channel);
2730
2731                 if (ring->rxd_term)
2732                         ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED,
2733                                 channel->userdata);
2734
2735                 vxge_hw_channel_dtr_free(channel, rxdh);
2736         }
2737
2738         return VXGE_HW_OK;
2739 }
2740
2741 /*
2742  * __vxge_hw_ring_reset - Resets the ring
2743  * This function resets the ring during vpath reset operation
2744  */
2745 static enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring)
2746 {
2747         enum vxge_hw_status status = VXGE_HW_OK;
2748         struct __vxge_hw_channel *channel;
2749
2750         channel = &ring->channel;
2751
2752         __vxge_hw_ring_abort(ring);
2753
2754         status = __vxge_hw_channel_reset(channel);
2755
2756         if (status != VXGE_HW_OK)
2757                 goto exit;
2758
2759         if (ring->rxd_init) {
2760                 status = vxge_hw_ring_replenish(ring);
2761                 if (status != VXGE_HW_OK)
2762                         goto exit;
2763         }
2764 exit:
2765         return status;
2766 }
2767
2768 /*
2769  * __vxge_hw_ring_delete - Removes the ring
2770  * This function freeup the memory pool and removes the ring
2771  */
2772 static enum vxge_hw_status
2773 __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp)
2774 {
2775         struct __vxge_hw_ring *ring = vp->vpath->ringh;
2776
2777         __vxge_hw_ring_abort(ring);
2778
2779         if (ring->mempool)
2780                 __vxge_hw_mempool_destroy(ring->mempool);
2781
2782         vp->vpath->ringh = NULL;
2783         __vxge_hw_channel_free(&ring->channel);
2784
2785         return VXGE_HW_OK;
2786 }
2787
2788 /*
2789  * __vxge_hw_ring_create - Create a Ring
2790  * This function creates Ring and initializes it.
2791  */
2792 static enum vxge_hw_status
2793 __vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
2794                       struct vxge_hw_ring_attr *attr)
2795 {
2796         enum vxge_hw_status status = VXGE_HW_OK;
2797         struct __vxge_hw_ring *ring;
2798         u32 ring_length;
2799         struct vxge_hw_ring_config *config;
2800         struct __vxge_hw_device *hldev;
2801         u32 vp_id;
2802         static const struct vxge_hw_mempool_cbs ring_mp_callback = {
2803                 .item_func_alloc = __vxge_hw_ring_mempool_item_alloc,
2804         };
2805
2806         if ((vp == NULL) || (attr == NULL)) {
2807                 status = VXGE_HW_FAIL;
2808                 goto exit;
2809         }
2810
2811         hldev = vp->vpath->hldev;
2812         vp_id = vp->vpath->vp_id;
2813
2814         config = &hldev->config.vp_config[vp_id].ring;
2815
2816         ring_length = config->ring_blocks *
2817                         vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
2818
2819         ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp,
2820                                                 VXGE_HW_CHANNEL_TYPE_RING,
2821                                                 ring_length,
2822                                                 attr->per_rxd_space,
2823                                                 attr->userdata);
2824         if (ring == NULL) {
2825                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2826                 goto exit;
2827         }
2828
2829         vp->vpath->ringh = ring;
2830         ring->vp_id = vp_id;
2831         ring->vp_reg = vp->vpath->vp_reg;
2832         ring->common_reg = hldev->common_reg;
2833         ring->stats = &vp->vpath->sw_stats->ring_stats;
2834         ring->config = config;
2835         ring->callback = attr->callback;
2836         ring->rxd_init = attr->rxd_init;
2837         ring->rxd_term = attr->rxd_term;
2838         ring->buffer_mode = config->buffer_mode;
2839         ring->tim_rti_cfg1_saved = vp->vpath->tim_rti_cfg1_saved;
2840         ring->tim_rti_cfg3_saved = vp->vpath->tim_rti_cfg3_saved;
2841         ring->rxds_limit = config->rxds_limit;
2842
2843         ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
2844         ring->rxd_priv_size =
2845                 sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space;
2846         ring->per_rxd_space = attr->per_rxd_space;
2847
2848         ring->rxd_priv_size =
2849                 ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) /
2850                 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
2851
2852         /* how many RxDs can fit into one block. Depends on configured
2853          * buffer_mode. */
2854         ring->rxds_per_block =
2855                 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
2856
2857         /* calculate actual RxD block private size */
2858         ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
2859         ring->mempool = __vxge_hw_mempool_create(hldev,
2860                                 VXGE_HW_BLOCK_SIZE,
2861                                 VXGE_HW_BLOCK_SIZE,
2862                                 ring->rxdblock_priv_size,
2863                                 ring->config->ring_blocks,
2864                                 ring->config->ring_blocks,
2865                                 &ring_mp_callback,
2866                                 ring);
2867         if (ring->mempool == NULL) {
2868                 __vxge_hw_ring_delete(vp);
2869                 return VXGE_HW_ERR_OUT_OF_MEMORY;
2870         }
2871
2872         status = __vxge_hw_channel_initialize(&ring->channel);
2873         if (status != VXGE_HW_OK) {
2874                 __vxge_hw_ring_delete(vp);
2875                 goto exit;
2876         }
2877
2878         /* Note:
2879          * Specifying rxd_init callback means two things:
2880          * 1) rxds need to be initialized by driver at channel-open time;
2881          * 2) rxds need to be posted at channel-open time
2882          *    (that's what the initial_replenish() below does)
2883          * Currently we don't have a case when the 1) is done without the 2).
2884          */
2885         if (ring->rxd_init) {
2886                 status = vxge_hw_ring_replenish(ring);
2887                 if (status != VXGE_HW_OK) {
2888                         __vxge_hw_ring_delete(vp);
2889                         goto exit;
2890                 }
2891         }
2892
2893         /* initial replenish will increment the counter in its post() routine,
2894          * we have to reset it */
2895         ring->stats->common_stats.usage_cnt = 0;
2896 exit:
2897         return status;
2898 }
2899
2900 /*
2901  * vxge_hw_device_config_default_get - Initialize device config with defaults.
2902  * Initialize Titan device config with default values.
2903  */
2904 enum vxge_hw_status
2905 vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config)
2906 {
2907         u32 i;
2908
2909         device_config->dma_blockpool_initial =
2910                                         VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE;
2911         device_config->dma_blockpool_max = VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE;
2912         device_config->intr_mode = VXGE_HW_INTR_MODE_DEF;
2913         device_config->rth_en = VXGE_HW_RTH_DEFAULT;
2914         device_config->rth_it_type = VXGE_HW_RTH_IT_TYPE_DEFAULT;
2915         device_config->device_poll_millis =  VXGE_HW_DEF_DEVICE_POLL_MILLIS;
2916         device_config->rts_mac_en =  VXGE_HW_RTS_MAC_DEFAULT;
2917
2918         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
2919                 device_config->vp_config[i].vp_id = i;
2920
2921                 device_config->vp_config[i].min_bandwidth =
2922                                 VXGE_HW_VPATH_BANDWIDTH_DEFAULT;
2923
2924                 device_config->vp_config[i].ring.enable = VXGE_HW_RING_DEFAULT;
2925
2926                 device_config->vp_config[i].ring.ring_blocks =
2927                                 VXGE_HW_DEF_RING_BLOCKS;
2928
2929                 device_config->vp_config[i].ring.buffer_mode =
2930                                 VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT;
2931
2932                 device_config->vp_config[i].ring.scatter_mode =
2933                                 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT;
2934
2935                 device_config->vp_config[i].ring.rxds_limit =
2936                                 VXGE_HW_DEF_RING_RXDS_LIMIT;
2937
2938                 device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE;
2939
2940                 device_config->vp_config[i].fifo.fifo_blocks =
2941                                 VXGE_HW_MIN_FIFO_BLOCKS;
2942
2943                 device_config->vp_config[i].fifo.max_frags =
2944                                 VXGE_HW_MAX_FIFO_FRAGS;
2945
2946                 device_config->vp_config[i].fifo.memblock_size =
2947                                 VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE;
2948
2949                 device_config->vp_config[i].fifo.alignment_size =
2950                                 VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE;
2951
2952                 device_config->vp_config[i].fifo.intr =
2953                                 VXGE_HW_FIFO_QUEUE_INTR_DEFAULT;
2954
2955                 device_config->vp_config[i].fifo.no_snoop_bits =
2956                                 VXGE_HW_FIFO_NO_SNOOP_DEFAULT;
2957                 device_config->vp_config[i].tti.intr_enable =
2958                                 VXGE_HW_TIM_INTR_DEFAULT;
2959
2960                 device_config->vp_config[i].tti.btimer_val =
2961                                 VXGE_HW_USE_FLASH_DEFAULT;
2962
2963                 device_config->vp_config[i].tti.timer_ac_en =
2964                                 VXGE_HW_USE_FLASH_DEFAULT;
2965
2966                 device_config->vp_config[i].tti.timer_ci_en =
2967                                 VXGE_HW_USE_FLASH_DEFAULT;
2968
2969                 device_config->vp_config[i].tti.timer_ri_en =
2970                                 VXGE_HW_USE_FLASH_DEFAULT;
2971
2972                 device_config->vp_config[i].tti.rtimer_val =
2973                                 VXGE_HW_USE_FLASH_DEFAULT;
2974
2975                 device_config->vp_config[i].tti.util_sel =
2976                                 VXGE_HW_USE_FLASH_DEFAULT;
2977
2978                 device_config->vp_config[i].tti.ltimer_val =
2979                                 VXGE_HW_USE_FLASH_DEFAULT;
2980
2981                 device_config->vp_config[i].tti.urange_a =
2982                                 VXGE_HW_USE_FLASH_DEFAULT;
2983
2984                 device_config->vp_config[i].tti.uec_a =
2985                                 VXGE_HW_USE_FLASH_DEFAULT;
2986
2987                 device_config->vp_config[i].tti.urange_b =
2988                                 VXGE_HW_USE_FLASH_DEFAULT;
2989
2990                 device_config->vp_config[i].tti.uec_b =
2991                                 VXGE_HW_USE_FLASH_DEFAULT;
2992
2993                 device_config->vp_config[i].tti.urange_c =
2994                                 VXGE_HW_USE_FLASH_DEFAULT;
2995
2996                 device_config->vp_config[i].tti.uec_c =
2997                                 VXGE_HW_USE_FLASH_DEFAULT;
2998
2999                 device_config->vp_config[i].tti.uec_d =
3000                                 VXGE_HW_USE_FLASH_DEFAULT;
3001
3002                 device_config->vp_config[i].rti.intr_enable =
3003                                 VXGE_HW_TIM_INTR_DEFAULT;
3004
3005                 device_config->vp_config[i].rti.btimer_val =
3006                                 VXGE_HW_USE_FLASH_DEFAULT;
3007
3008                 device_config->vp_config[i].rti.timer_ac_en =
3009                                 VXGE_HW_USE_FLASH_DEFAULT;
3010
3011                 device_config->vp_config[i].rti.timer_ci_en =
3012                                 VXGE_HW_USE_FLASH_DEFAULT;
3013
3014                 device_config->vp_config[i].rti.timer_ri_en =
3015                                 VXGE_HW_USE_FLASH_DEFAULT;
3016
3017                 device_config->vp_config[i].rti.rtimer_val =
3018                                 VXGE_HW_USE_FLASH_DEFAULT;
3019
3020                 device_config->vp_config[i].rti.util_sel =
3021                                 VXGE_HW_USE_FLASH_DEFAULT;
3022
3023                 device_config->vp_config[i].rti.ltimer_val =
3024                                 VXGE_HW_USE_FLASH_DEFAULT;
3025
3026                 device_config->vp_config[i].rti.urange_a =
3027                                 VXGE_HW_USE_FLASH_DEFAULT;
3028
3029                 device_config->vp_config[i].rti.uec_a =
3030                                 VXGE_HW_USE_FLASH_DEFAULT;
3031
3032                 device_config->vp_config[i].rti.urange_b =
3033                                 VXGE_HW_USE_FLASH_DEFAULT;
3034
3035                 device_config->vp_config[i].rti.uec_b =
3036                                 VXGE_HW_USE_FLASH_DEFAULT;
3037
3038                 device_config->vp_config[i].rti.urange_c =
3039                                 VXGE_HW_USE_FLASH_DEFAULT;
3040
3041                 device_config->vp_config[i].rti.uec_c =
3042                                 VXGE_HW_USE_FLASH_DEFAULT;
3043
3044                 device_config->vp_config[i].rti.uec_d =
3045                                 VXGE_HW_USE_FLASH_DEFAULT;
3046
3047                 device_config->vp_config[i].mtu =
3048                                 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU;
3049
3050                 device_config->vp_config[i].rpa_strip_vlan_tag =
3051                         VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT;
3052         }
3053
3054         return VXGE_HW_OK;
3055 }
3056
3057 /*
3058  * __vxge_hw_vpath_swapper_set - Set the swapper bits for the vpath.
3059  * Set the swapper bits appropriately for the vpath.
3060  */
3061 static enum vxge_hw_status
3062 __vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
3063 {
3064 #ifndef __BIG_ENDIAN
3065         u64 val64;
3066
3067         val64 = readq(&vpath_reg->vpath_general_cfg1);
3068         wmb();
3069         val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
3070         writeq(val64, &vpath_reg->vpath_general_cfg1);
3071         wmb();
3072 #endif
3073         return VXGE_HW_OK;
3074 }
3075
3076 /*
3077  * __vxge_hw_kdfc_swapper_set - Set the swapper bits for the kdfc.
3078  * Set the swapper bits appropriately for the vpath.
3079  */
3080 static enum vxge_hw_status
3081 __vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg,
3082                            struct vxge_hw_vpath_reg __iomem *vpath_reg)
3083 {
3084         u64 val64;
3085
3086         val64 = readq(&legacy_reg->pifm_wr_swap_en);
3087
3088         if (val64 == VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE) {
3089                 val64 = readq(&vpath_reg->kdfcctl_cfg0);
3090                 wmb();
3091
3092                 val64 |= VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 |
3093                         VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1  |
3094                         VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2;
3095
3096                 writeq(val64, &vpath_reg->kdfcctl_cfg0);
3097                 wmb();
3098         }
3099
3100         return VXGE_HW_OK;
3101 }
3102
3103 /*
3104  * vxge_hw_mgmt_reg_read - Read Titan register.
3105  */
3106 enum vxge_hw_status
3107 vxge_hw_mgmt_reg_read(struct __vxge_hw_device *hldev,
3108                       enum vxge_hw_mgmt_reg_type type,
3109                       u32 index, u32 offset, u64 *value)
3110 {
3111         enum vxge_hw_status status = VXGE_HW_OK;
3112
3113         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
3114                 status = VXGE_HW_ERR_INVALID_DEVICE;
3115                 goto exit;
3116         }
3117
3118         switch (type) {
3119         case vxge_hw_mgmt_reg_type_legacy:
3120                 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
3121                         status = VXGE_HW_ERR_INVALID_OFFSET;
3122                         break;
3123                 }
3124                 *value = readq((void __iomem *)hldev->legacy_reg + offset);
3125                 break;
3126         case vxge_hw_mgmt_reg_type_toc:
3127                 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
3128                         status = VXGE_HW_ERR_INVALID_OFFSET;
3129                         break;
3130                 }
3131                 *value = readq((void __iomem *)hldev->toc_reg + offset);
3132                 break;
3133         case vxge_hw_mgmt_reg_type_common:
3134                 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
3135                         status = VXGE_HW_ERR_INVALID_OFFSET;
3136                         break;
3137                 }
3138                 *value = readq((void __iomem *)hldev->common_reg + offset);
3139                 break;
3140         case vxge_hw_mgmt_reg_type_mrpcim:
3141                 if (!(hldev->access_rights &
3142                         VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
3143                         status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3144                         break;
3145                 }
3146                 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
3147                         status = VXGE_HW_ERR_INVALID_OFFSET;
3148                         break;
3149                 }
3150                 *value = readq((void __iomem *)hldev->mrpcim_reg + offset);
3151                 break;
3152         case vxge_hw_mgmt_reg_type_srpcim:
3153                 if (!(hldev->access_rights &
3154                         VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
3155                         status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3156                         break;
3157                 }
3158                 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
3159                         status = VXGE_HW_ERR_INVALID_INDEX;
3160                         break;
3161                 }
3162                 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
3163                         status = VXGE_HW_ERR_INVALID_OFFSET;
3164                         break;
3165                 }
3166                 *value = readq((void __iomem *)hldev->srpcim_reg[index] +
3167                                 offset);
3168                 break;
3169         case vxge_hw_mgmt_reg_type_vpmgmt:
3170                 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
3171                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3172                         status = VXGE_HW_ERR_INVALID_INDEX;
3173                         break;
3174                 }
3175                 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
3176                         status = VXGE_HW_ERR_INVALID_OFFSET;
3177                         break;
3178                 }
3179                 *value = readq((void __iomem *)hldev->vpmgmt_reg[index] +
3180                                 offset);
3181                 break;
3182         case vxge_hw_mgmt_reg_type_vpath:
3183                 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) ||
3184                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3185                         status = VXGE_HW_ERR_INVALID_INDEX;
3186                         break;
3187                 }
3188                 if (index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) {
3189                         status = VXGE_HW_ERR_INVALID_INDEX;
3190                         break;
3191                 }
3192                 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
3193                         status = VXGE_HW_ERR_INVALID_OFFSET;
3194                         break;
3195                 }
3196                 *value = readq((void __iomem *)hldev->vpath_reg[index] +
3197                                 offset);
3198                 break;
3199         default:
3200                 status = VXGE_HW_ERR_INVALID_TYPE;
3201                 break;
3202         }
3203
3204 exit:
3205         return status;
3206 }
3207
3208 /*
3209  * vxge_hw_vpath_strip_fcs_check - Check for FCS strip.
3210  */
3211 enum vxge_hw_status
3212 vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask)
3213 {
3214         struct vxge_hw_vpmgmt_reg       __iomem *vpmgmt_reg;
3215         int i = 0, j = 0;
3216
3217         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3218                 if (!((vpath_mask) & vxge_mBIT(i)))
3219                         continue;
3220                 vpmgmt_reg = hldev->vpmgmt_reg[i];
3221                 for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) {
3222                         if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j])
3223                         & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS)
3224                                 return VXGE_HW_FAIL;
3225                 }
3226         }
3227         return VXGE_HW_OK;
3228 }
3229 /*
3230  * vxge_hw_mgmt_reg_Write - Write Titan register.
3231  */
3232 enum vxge_hw_status
3233 vxge_hw_mgmt_reg_write(struct __vxge_hw_device *hldev,
3234                       enum vxge_hw_mgmt_reg_type type,
3235                       u32 index, u32 offset, u64 value)
3236 {
3237         enum vxge_hw_status status = VXGE_HW_OK;
3238
3239         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
3240                 status = VXGE_HW_ERR_INVALID_DEVICE;
3241                 goto exit;
3242         }
3243
3244         switch (type) {
3245         case vxge_hw_mgmt_reg_type_legacy:
3246                 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
3247                         status = VXGE_HW_ERR_INVALID_OFFSET;
3248                         break;
3249                 }
3250                 writeq(value, (void __iomem *)hldev->legacy_reg + offset);
3251                 break;
3252         case vxge_hw_mgmt_reg_type_toc:
3253                 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
3254                         status = VXGE_HW_ERR_INVALID_OFFSET;
3255                         break;
3256                 }
3257                 writeq(value, (void __iomem *)hldev->toc_reg + offset);
3258                 break;
3259         case vxge_hw_mgmt_reg_type_common:
3260                 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
3261                         status = VXGE_HW_ERR_INVALID_OFFSET;
3262                         break;
3263                 }
3264                 writeq(value, (void __iomem *)hldev->common_reg + offset);
3265                 break;
3266         case vxge_hw_mgmt_reg_type_mrpcim:
3267                 if (!(hldev->access_rights &
3268                         VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
3269                         status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3270                         break;
3271                 }
3272                 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
3273                         status = VXGE_HW_ERR_INVALID_OFFSET;
3274                         break;
3275                 }
3276                 writeq(value, (void __iomem *)hldev->mrpcim_reg + offset);
3277                 break;
3278         case vxge_hw_mgmt_reg_type_srpcim:
3279                 if (!(hldev->access_rights &
3280                         VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
3281                         status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3282                         break;
3283                 }
3284                 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
3285                         status = VXGE_HW_ERR_INVALID_INDEX;
3286                         break;
3287                 }
3288                 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
3289                         status = VXGE_HW_ERR_INVALID_OFFSET;
3290                         break;
3291                 }
3292                 writeq(value, (void __iomem *)hldev->srpcim_reg[index] +
3293                         offset);
3294
3295                 break;
3296         case vxge_hw_mgmt_reg_type_vpmgmt:
3297                 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
3298                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3299                         status = VXGE_HW_ERR_INVALID_INDEX;
3300                         break;
3301                 }
3302                 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
3303                         status = VXGE_HW_ERR_INVALID_OFFSET;
3304                         break;
3305                 }
3306                 writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] +
3307                         offset);
3308                 break;
3309         case vxge_hw_mgmt_reg_type_vpath:
3310                 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES-1) ||
3311                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3312                         status = VXGE_HW_ERR_INVALID_INDEX;
3313                         break;
3314                 }
3315                 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
3316                         status = VXGE_HW_ERR_INVALID_OFFSET;
3317                         break;
3318                 }
3319                 writeq(value, (void __iomem *)hldev->vpath_reg[index] +
3320                         offset);
3321                 break;
3322         default:
3323                 status = VXGE_HW_ERR_INVALID_TYPE;
3324                 break;
3325         }
3326 exit:
3327         return status;
3328 }
3329
3330 /*
3331  * __vxge_hw_fifo_abort - Returns the TxD
3332  * This function terminates the TxDs of fifo
3333  */
3334 static enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
3335 {
3336         void *txdlh;
3337
3338         for (;;) {
3339                 vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
3340
3341                 if (txdlh == NULL)
3342                         break;
3343
3344                 vxge_hw_channel_dtr_complete(&fifo->channel);
3345
3346                 if (fifo->txdl_term) {
3347                         fifo->txdl_term(txdlh,
3348                         VXGE_HW_TXDL_STATE_POSTED,
3349                         fifo->channel.userdata);
3350                 }
3351
3352                 vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
3353         }
3354
3355         return VXGE_HW_OK;
3356 }
3357
3358 /*
3359  * __vxge_hw_fifo_reset - Resets the fifo
3360  * This function resets the fifo during vpath reset operation
3361  */
3362 static enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
3363 {
3364         enum vxge_hw_status status = VXGE_HW_OK;
3365
3366         __vxge_hw_fifo_abort(fifo);
3367         status = __vxge_hw_channel_reset(&fifo->channel);
3368
3369         return status;
3370 }
3371
3372 /*
3373  * __vxge_hw_fifo_delete - Removes the FIFO
3374  * This function freeup the memory pool and removes the FIFO
3375  */
3376 static enum vxge_hw_status
3377 __vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp)
3378 {
3379         struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
3380
3381         __vxge_hw_fifo_abort(fifo);
3382
3383         if (fifo->mempool)
3384                 __vxge_hw_mempool_destroy(fifo->mempool);
3385
3386         vp->vpath->fifoh = NULL;
3387
3388         __vxge_hw_channel_free(&fifo->channel);
3389
3390         return VXGE_HW_OK;
3391 }
3392
3393 /*
3394  * __vxge_hw_fifo_mempool_item_alloc - Allocate List blocks for TxD
3395  * list callback
3396  * This function is callback passed to __vxge_hw_mempool_create to create memory
3397  * pool for TxD list
3398  */
3399 static void
3400 __vxge_hw_fifo_mempool_item_alloc(
3401         struct vxge_hw_mempool *mempoolh,
3402         u32 memblock_index, struct vxge_hw_mempool_dma *dma_object,
3403         u32 index, u32 is_last)
3404 {
3405         u32 memblock_item_idx;
3406         struct __vxge_hw_fifo_txdl_priv *txdl_priv;
3407         struct vxge_hw_fifo_txd *txdp =
3408                 (struct vxge_hw_fifo_txd *)mempoolh->items_arr[index];
3409         struct __vxge_hw_fifo *fifo =
3410                         (struct __vxge_hw_fifo *)mempoolh->userdata;
3411         void *memblock = mempoolh->memblocks_arr[memblock_index];
3412
3413         vxge_assert(txdp);
3414
3415         txdp->host_control = (u64) (size_t)
3416         __vxge_hw_mempool_item_priv(mempoolh, memblock_index, txdp,
3417                                         &memblock_item_idx);
3418
3419         txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
3420
3421         vxge_assert(txdl_priv);
3422
3423         fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp;
3424
3425         /* pre-format HW's TxDL's private */
3426         txdl_priv->dma_offset = (char *)txdp - (char *)memblock;
3427         txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset;
3428         txdl_priv->dma_handle = dma_object->handle;
3429         txdl_priv->memblock   = memblock;
3430         txdl_priv->first_txdp = txdp;
3431         txdl_priv->next_txdl_priv = NULL;
3432         txdl_priv->alloc_frags = 0;
3433 }
3434
3435 /*
3436  * __vxge_hw_fifo_create - Create a FIFO
3437  * This function creates FIFO and initializes it.
3438  */
3439 static enum vxge_hw_status
3440 __vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp,
3441                       struct vxge_hw_fifo_attr *attr)
3442 {
3443         enum vxge_hw_status status = VXGE_HW_OK;
3444         struct __vxge_hw_fifo *fifo;
3445         struct vxge_hw_fifo_config *config;
3446         u32 txdl_size, txdl_per_memblock;
3447         struct vxge_hw_mempool_cbs fifo_mp_callback;
3448         struct __vxge_hw_virtualpath *vpath;
3449
3450         if ((vp == NULL) || (attr == NULL)) {
3451                 status = VXGE_HW_ERR_INVALID_HANDLE;
3452                 goto exit;
3453         }
3454         vpath = vp->vpath;
3455         config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo;
3456
3457         txdl_size = config->max_frags * sizeof(struct vxge_hw_fifo_txd);
3458
3459         txdl_per_memblock = config->memblock_size / txdl_size;
3460
3461         fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp,
3462                                         VXGE_HW_CHANNEL_TYPE_FIFO,
3463                                         config->fifo_blocks * txdl_per_memblock,
3464                                         attr->per_txdl_space, attr->userdata);
3465
3466         if (fifo == NULL) {
3467                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
3468                 goto exit;
3469         }
3470
3471         vpath->fifoh = fifo;
3472         fifo->nofl_db = vpath->nofl_db;
3473
3474         fifo->vp_id = vpath->vp_id;
3475         fifo->vp_reg = vpath->vp_reg;
3476         fifo->stats = &vpath->sw_stats->fifo_stats;
3477
3478         fifo->config = config;
3479
3480         /* apply "interrupts per txdl" attribute */
3481         fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
3482         fifo->tim_tti_cfg1_saved = vpath->tim_tti_cfg1_saved;
3483         fifo->tim_tti_cfg3_saved = vpath->tim_tti_cfg3_saved;
3484
3485         if (fifo->config->intr)
3486                 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
3487
3488         fifo->no_snoop_bits = config->no_snoop_bits;
3489
3490         /*
3491          * FIFO memory management strategy:
3492          *
3493          * TxDL split into three independent parts:
3494          *      - set of TxD's
3495          *      - TxD HW private part
3496          *      - driver private part
3497          *
3498          * Adaptative memory allocation used. i.e. Memory allocated on
3499          * demand with the size which will fit into one memory block.
3500          * One memory block may contain more than one TxDL.
3501          *
3502          * During "reserve" operations more memory can be allocated on demand
3503          * for example due to FIFO full condition.
3504          *
3505          * Pool of memory memblocks never shrinks except in __vxge_hw_fifo_close
3506          * routine which will essentially stop the channel and free resources.
3507          */
3508
3509         /* TxDL common private size == TxDL private  +  driver private */
3510         fifo->priv_size =
3511                 sizeof(struct __vxge_hw_fifo_txdl_priv) + attr->per_txdl_space;
3512         fifo->priv_size = ((fifo->priv_size  +  VXGE_CACHE_LINE_SIZE - 1) /
3513                         VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
3514
3515         fifo->per_txdl_space = attr->per_txdl_space;
3516
3517         /* recompute txdl size to be cacheline aligned */
3518         fifo->txdl_size = txdl_size;
3519         fifo->txdl_per_memblock = txdl_per_memblock;
3520
3521         fifo->txdl_term = attr->txdl_term;
3522         fifo->callback = attr->callback;
3523
3524         if (fifo->txdl_per_memblock == 0) {
3525                 __vxge_hw_fifo_delete(vp);
3526                 status = VXGE_HW_ERR_INVALID_BLOCK_SIZE;
3527                 goto exit;
3528         }
3529
3530         fifo_mp_callback.item_func_alloc = __vxge_hw_fifo_mempool_item_alloc;
3531
3532         fifo->mempool =
3533                 __vxge_hw_mempool_create(vpath->hldev,
3534                         fifo->config->memblock_size,
3535                         fifo->txdl_size,
3536                         fifo->priv_size,
3537                         (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3538                         (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3539                         &fifo_mp_callback,
3540                         fifo);
3541
3542         if (fifo->mempool == NULL) {
3543                 __vxge_hw_fifo_delete(vp);
3544                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
3545                 goto exit;
3546         }
3547
3548         status = __vxge_hw_channel_initialize(&fifo->channel);
3549         if (status != VXGE_HW_OK) {
3550                 __vxge_hw_fifo_delete(vp);
3551                 goto exit;
3552         }
3553
3554         vxge_assert(fifo->channel.reserve_ptr);
3555 exit:
3556         return status;
3557 }
3558
3559 /*
3560  * __vxge_hw_vpath_pci_read - Read the content of given address
3561  *                          in pci config space.
3562  * Read from the vpath pci config space.
3563  */
3564 static enum vxge_hw_status
3565 __vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath,
3566                          u32 phy_func_0, u32 offset, u32 *val)
3567 {
3568         u64 val64;
3569         enum vxge_hw_status status = VXGE_HW_OK;
3570         struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
3571
3572         val64 = VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(offset);
3573
3574         if (phy_func_0)
3575                 val64 |= VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0;
3576
3577         writeq(val64, &vp_reg->pci_config_access_cfg1);
3578         wmb();
3579         writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ,
3580                         &vp_reg->pci_config_access_cfg2);
3581         wmb();
3582
3583         status = __vxge_hw_device_register_poll(
3584                         &vp_reg->pci_config_access_cfg2,
3585                         VXGE_HW_INTR_MASK_ALL, VXGE_HW_DEF_DEVICE_POLL_MILLIS);
3586
3587         if (status != VXGE_HW_OK)
3588                 goto exit;
3589
3590         val64 = readq(&vp_reg->pci_config_access_status);
3591
3592         if (val64 & VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR) {
3593                 status = VXGE_HW_FAIL;
3594                 *val = 0;
3595         } else
3596                 *val = (u32)vxge_bVALn(val64, 32, 32);
3597 exit:
3598         return status;
3599 }
3600
3601 /**
3602  * vxge_hw_device_flick_link_led - Flick (blink) link LED.
3603  * @hldev: HW device.
3604  * @on_off: TRUE if flickering to be on, FALSE to be off
3605  *
3606  * Flicker the link LED.
3607  */
3608 enum vxge_hw_status
3609 vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev, u64 on_off)
3610 {
3611         struct __vxge_hw_virtualpath *vpath;
3612         u64 data0, data1 = 0, steer_ctrl = 0;
3613         enum vxge_hw_status status;
3614
3615         if (hldev == NULL) {
3616                 status = VXGE_HW_ERR_INVALID_DEVICE;
3617                 goto exit;
3618         }
3619
3620         vpath = &hldev->virtual_paths[hldev->first_vp_id];
3621
3622         data0 = on_off;
3623         status = vxge_hw_vpath_fw_api(vpath,
3624                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL,
3625                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
3626                         0, &data0, &data1, &steer_ctrl);
3627 exit:
3628         return status;
3629 }
3630
3631 /*
3632  * __vxge_hw_vpath_rts_table_get - Get the entries from RTS access tables
3633  */
3634 enum vxge_hw_status
3635 __vxge_hw_vpath_rts_table_get(struct __vxge_hw_vpath_handle *vp,
3636                               u32 action, u32 rts_table, u32 offset,
3637                               u64 *data0, u64 *data1)
3638 {
3639         enum vxge_hw_status status;
3640         u64 steer_ctrl = 0;
3641
3642         if (vp == NULL) {
3643                 status = VXGE_HW_ERR_INVALID_HANDLE;
3644                 goto exit;
3645         }
3646
3647         if ((rts_table ==
3648              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
3649             (rts_table ==
3650              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
3651             (rts_table ==
3652              VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
3653             (rts_table ==
3654              VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
3655                 steer_ctrl = VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
3656         }
3657
3658         status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3659                                       data0, data1, &steer_ctrl);
3660         if (status != VXGE_HW_OK)
3661                 goto exit;
3662
3663         if ((rts_table != VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) &&
3664             (rts_table !=
3665              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3666                 *data1 = 0;
3667 exit:
3668         return status;
3669 }
3670
3671 /*
3672  * __vxge_hw_vpath_rts_table_set - Set the entries of RTS access tables
3673  */
3674 enum vxge_hw_status
3675 __vxge_hw_vpath_rts_table_set(struct __vxge_hw_vpath_handle *vp, u32 action,
3676                               u32 rts_table, u32 offset, u64 steer_data0,
3677                               u64 steer_data1)
3678 {
3679         u64 data0, data1 = 0, steer_ctrl = 0;
3680         enum vxge_hw_status status;
3681
3682         if (vp == NULL) {
3683                 status = VXGE_HW_ERR_INVALID_HANDLE;
3684                 goto exit;
3685         }
3686
3687         data0 = steer_data0;
3688
3689         if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
3690             (rts_table ==
3691              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3692                 data1 = steer_data1;
3693
3694         status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3695                                       &data0, &data1, &steer_ctrl);
3696 exit:
3697         return status;
3698 }
3699
3700 /*
3701  * vxge_hw_vpath_rts_rth_set - Set/configure RTS hashing.
3702  */
3703 enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
3704                         struct __vxge_hw_vpath_handle *vp,
3705                         enum vxge_hw_rth_algoritms algorithm,
3706                         struct vxge_hw_rth_hash_types *hash_type,
3707                         u16 bucket_size)
3708 {
3709         u64 data0, data1;
3710         enum vxge_hw_status status = VXGE_HW_OK;
3711
3712         if (vp == NULL) {
3713                 status = VXGE_HW_ERR_INVALID_HANDLE;
3714                 goto exit;
3715         }
3716
3717         status = __vxge_hw_vpath_rts_table_get(vp,
3718                      VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3719                      VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3720                         0, &data0, &data1);
3721         if (status != VXGE_HW_OK)
3722                 goto exit;
3723
3724         data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) |
3725                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(0x3));
3726
3727         data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN |
3728         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) |
3729         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm);
3730
3731         if (hash_type->hash_type_tcpipv4_en)
3732                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN;
3733
3734         if (hash_type->hash_type_ipv4_en)
3735                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN;
3736
3737         if (hash_type->hash_type_tcpipv6_en)
3738                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN;
3739
3740         if (hash_type->hash_type_ipv6_en)
3741                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN;
3742
3743         if (hash_type->hash_type_tcpipv6ex_en)
3744                 data0 |=
3745                 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN;
3746
3747         if (hash_type->hash_type_ipv6ex_en)
3748                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN;
3749
3750         if (VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(data0))
3751                 data0 &= ~VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3752         else
3753                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3754
3755         status = __vxge_hw_vpath_rts_table_set(vp,
3756                 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3757                 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3758                 0, data0, 0);
3759 exit:
3760         return status;
3761 }
3762
3763 static void
3764 vxge_hw_rts_rth_data0_data1_get(u32 j, u64 *data0, u64 *data1,
3765                                 u16 flag, u8 *itable)
3766 {
3767         switch (flag) {
3768         case 1:
3769                 *data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j)|
3770                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN |
3771                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(
3772                         itable[j]);
3773                 /* fall through */
3774         case 2:
3775                 *data0 |=
3776                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j)|
3777                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN |
3778                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(
3779                         itable[j]);
3780                 /* fall through */
3781         case 3:
3782                 *data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j)|
3783                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN |
3784                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(
3785                         itable[j]);
3786                 /* fall through */
3787         case 4:
3788                 *data1 |=
3789                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j)|
3790                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN |
3791                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(
3792                         itable[j]);
3793         default:
3794                 return;
3795         }
3796 }
3797 /*
3798  * vxge_hw_vpath_rts_rth_itable_set - Set/configure indirection table (IT).
3799  */
3800 enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set(
3801                         struct __vxge_hw_vpath_handle **vpath_handles,
3802                         u32 vpath_count,
3803                         u8 *mtable,
3804                         u8 *itable,
3805                         u32 itable_size)
3806 {
3807         u32 i, j, action, rts_table;
3808         u64 data0;
3809         u64 data1;
3810         u32 max_entries;
3811         enum vxge_hw_status status = VXGE_HW_OK;
3812         struct __vxge_hw_vpath_handle *vp = vpath_handles[0];
3813
3814         if (vp == NULL) {
3815                 status = VXGE_HW_ERR_INVALID_HANDLE;
3816                 goto exit;
3817         }
3818
3819         max_entries = (((u32)1) << itable_size);
3820
3821         if (vp->vpath->hldev->config.rth_it_type
3822                                 == VXGE_HW_RTH_IT_TYPE_SOLO_IT) {
3823                 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3824                 rts_table =
3825                         VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT;
3826
3827                 for (j = 0; j < max_entries; j++) {
3828
3829                         data1 = 0;
3830
3831                         data0 =
3832                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3833                                 itable[j]);
3834
3835                         status = __vxge_hw_vpath_rts_table_set(vpath_handles[0],
3836                                 action, rts_table, j, data0, data1);
3837
3838                         if (status != VXGE_HW_OK)
3839                                 goto exit;
3840                 }
3841
3842                 for (j = 0; j < max_entries; j++) {
3843
3844                         data1 = 0;
3845
3846                         data0 =
3847                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN |
3848                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3849                                 itable[j]);
3850
3851                         status = __vxge_hw_vpath_rts_table_set(
3852                                 vpath_handles[mtable[itable[j]]], action,
3853                                 rts_table, j, data0, data1);
3854
3855                         if (status != VXGE_HW_OK)
3856                                 goto exit;
3857                 }
3858         } else {
3859                 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3860                 rts_table =
3861                         VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT;
3862                 for (i = 0; i < vpath_count; i++) {
3863
3864                         for (j = 0; j < max_entries;) {
3865
3866                                 data0 = 0;
3867                                 data1 = 0;
3868
3869                                 while (j < max_entries) {
3870                                         if (mtable[itable[j]] != i) {
3871                                                 j++;
3872                                                 continue;
3873                                         }
3874                                         vxge_hw_rts_rth_data0_data1_get(j,
3875                                                 &data0, &data1, 1, itable);
3876                                         j++;
3877                                         break;
3878                                 }
3879
3880                                 while (j < max_entries) {
3881                                         if (mtable[itable[j]] != i) {
3882                                                 j++;
3883                                                 continue;
3884                                         }
3885                                         vxge_hw_rts_rth_data0_data1_get(j,
3886                                                 &data0, &data1, 2, itable);
3887                                         j++;
3888                                         break;
3889                                 }
3890
3891                                 while (j < max_entries) {
3892                                         if (mtable[itable[j]] != i) {
3893                                                 j++;
3894                                                 continue;
3895                                         }
3896                                         vxge_hw_rts_rth_data0_data1_get(j,
3897                                                 &data0, &data1, 3, itable);
3898                                         j++;
3899                                         break;
3900                                 }
3901
3902                                 while (j < max_entries) {
3903                                         if (mtable[itable[j]] != i) {
3904                                                 j++;
3905                                                 continue;
3906                                         }
3907                                         vxge_hw_rts_rth_data0_data1_get(j,
3908                                                 &data0, &data1, 4, itable);
3909                                         j++;
3910                                         break;
3911                                 }
3912
3913                                 if (data0 != 0) {
3914                                         status = __vxge_hw_vpath_rts_table_set(
3915                                                         vpath_handles[i],
3916                                                         action, rts_table,
3917                                                         0, data0, data1);
3918
3919                                         if (status != VXGE_HW_OK)
3920                                                 goto exit;
3921                                 }
3922                         }
3923                 }
3924         }
3925 exit:
3926         return status;
3927 }
3928
3929 /**
3930  * vxge_hw_vpath_check_leak - Check for memory leak
3931  * @ringh: Handle to the ring object used for receive
3932  *
3933  * If PRC_RXD_DOORBELL_VPn.NEW_QW_CNT is larger or equal to
3934  * PRC_CFG6_VPn.RXD_SPAT then a leak has occurred.
3935  * Returns: VXGE_HW_FAIL, if leak has occurred.
3936  *
3937  */
3938 enum vxge_hw_status
3939 vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ring)
3940 {
3941         enum vxge_hw_status status = VXGE_HW_OK;
3942         u64 rxd_new_count, rxd_spat;
3943
3944         if (ring == NULL)
3945                 return status;
3946
3947         rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);
3948         rxd_spat = readq(&ring->vp_reg->prc_cfg6);
3949         rxd_spat = VXGE_HW_PRC_CFG6_RXD_SPAT(rxd_spat);
3950
3951         if (rxd_new_count >= rxd_spat)
3952                 status = VXGE_HW_FAIL;
3953
3954         return status;
3955 }
3956
3957 /*
3958  * __vxge_hw_vpath_mgmt_read
3959  * This routine reads the vpath_mgmt registers
3960  */
3961 static enum vxge_hw_status
3962 __vxge_hw_vpath_mgmt_read(
3963         struct __vxge_hw_device *hldev,
3964         struct __vxge_hw_virtualpath *vpath)
3965 {
3966         u32 i, mtu = 0, max_pyld = 0;
3967         u64 val64;
3968
3969         for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
3970
3971                 val64 = readq(&vpath->vpmgmt_reg->
3972                                 rxmac_cfg0_port_vpmgmt_clone[i]);
3973                 max_pyld =
3974                         (u32)
3975                         VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN
3976                         (val64);
3977                 if (mtu < max_pyld)
3978                         mtu = max_pyld;
3979         }
3980
3981         vpath->max_mtu = mtu + VXGE_HW_MAC_HEADER_MAX_SIZE;
3982
3983         val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp);
3984
3985         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3986                 if (val64 & vxge_mBIT(i))
3987                         vpath->vsport_number = i;
3988         }
3989
3990         val64 = readq(&vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
3991
3992         if (val64 & VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK)
3993                 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_UP);
3994         else
3995                 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_DOWN);
3996
3997         return VXGE_HW_OK;
3998 }
3999
4000 /*
4001  * __vxge_hw_vpath_reset_check - Check if resetting the vpath completed
4002  * This routine checks the vpath_rst_in_prog register to see if
4003  * adapter completed the reset process for the vpath
4004  */
4005 static enum vxge_hw_status
4006 __vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath)
4007 {
4008         enum vxge_hw_status status;
4009
4010         status = __vxge_hw_device_register_poll(
4011                         &vpath->hldev->common_reg->vpath_rst_in_prog,
4012                         VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(
4013                                 1 << (16 - vpath->vp_id)),
4014                         vpath->hldev->config.device_poll_millis);
4015
4016         return status;
4017 }
4018
4019 /*
4020  * __vxge_hw_vpath_reset
4021  * This routine resets the vpath on the device
4022  */
4023 static enum vxge_hw_status
4024 __vxge_hw_vpath_reset(struct __vxge_hw_device *hldev, u32 vp_id)
4025 {
4026         u64 val64;
4027
4028         val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
4029
4030         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
4031                                 &hldev->common_reg->cmn_rsthdlr_cfg0);
4032
4033         return VXGE_HW_OK;
4034 }
4035
4036 /*
4037  * __vxge_hw_vpath_sw_reset
4038  * This routine resets the vpath structures
4039  */
4040 static enum vxge_hw_status
4041 __vxge_hw_vpath_sw_reset(struct __vxge_hw_device *hldev, u32 vp_id)
4042 {
4043         enum vxge_hw_status status = VXGE_HW_OK;
4044         struct __vxge_hw_virtualpath *vpath;
4045
4046         vpath = &hldev->virtual_paths[vp_id];
4047
4048         if (vpath->ringh) {
4049                 status = __vxge_hw_ring_reset(vpath->ringh);
4050                 if (status != VXGE_HW_OK)
4051                         goto exit;
4052         }
4053
4054         if (vpath->fifoh)
4055                 status = __vxge_hw_fifo_reset(vpath->fifoh);
4056 exit:
4057         return status;
4058 }
4059
4060 /*
4061  * __vxge_hw_vpath_prc_configure
4062  * This routine configures the prc registers of virtual path using the config
4063  * passed
4064  */
4065 static void
4066 __vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4067 {
4068         u64 val64;
4069         struct __vxge_hw_virtualpath *vpath;
4070         struct vxge_hw_vp_config *vp_config;
4071         struct vxge_hw_vpath_reg __iomem *vp_reg;
4072
4073         vpath = &hldev->virtual_paths[vp_id];
4074         vp_reg = vpath->vp_reg;
4075         vp_config = vpath->vp_config;
4076
4077         if (vp_config->ring.enable == VXGE_HW_RING_DISABLE)
4078                 return;
4079
4080         val64 = readq(&vp_reg->prc_cfg1);
4081         val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE;
4082         writeq(val64, &vp_reg->prc_cfg1);
4083
4084         val64 = readq(&vpath->vp_reg->prc_cfg6);
4085         val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN;
4086         writeq(val64, &vpath->vp_reg->prc_cfg6);
4087
4088         val64 = readq(&vp_reg->prc_cfg7);
4089
4090         if (vpath->vp_config->ring.scatter_mode !=
4091                 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT) {
4092
4093                 val64 &= ~VXGE_HW_PRC_CFG7_SCATTER_MODE(0x3);
4094
4095                 switch (vpath->vp_config->ring.scatter_mode) {
4096                 case VXGE_HW_RING_SCATTER_MODE_A:
4097                         val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4098                                         VXGE_HW_PRC_CFG7_SCATTER_MODE_A);
4099                         break;
4100                 case VXGE_HW_RING_SCATTER_MODE_B:
4101                         val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4102                                         VXGE_HW_PRC_CFG7_SCATTER_MODE_B);
4103                         break;
4104                 case VXGE_HW_RING_SCATTER_MODE_C:
4105                         val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4106                                         VXGE_HW_PRC_CFG7_SCATTER_MODE_C);
4107                         break;
4108                 }
4109         }
4110
4111         writeq(val64, &vp_reg->prc_cfg7);
4112
4113         writeq(VXGE_HW_PRC_CFG5_RXD0_ADD(
4114                                 __vxge_hw_ring_first_block_address_get(
4115                                         vpath->ringh) >> 3), &vp_reg->prc_cfg5);
4116
4117         val64 = readq(&vp_reg->prc_cfg4);
4118         val64 |= VXGE_HW_PRC_CFG4_IN_SVC;
4119         val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3);
4120
4121         val64 |= VXGE_HW_PRC_CFG4_RING_MODE(
4122                         VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER);
4123
4124         if (hldev->config.rth_en == VXGE_HW_RTH_DISABLE)
4125                 val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE;
4126         else
4127                 val64 &= ~VXGE_HW_PRC_CFG4_RTH_DISABLE;
4128
4129         writeq(val64, &vp_reg->prc_cfg4);
4130 }
4131
4132 /*
4133  * __vxge_hw_vpath_kdfc_configure
4134  * This routine configures the kdfc registers of virtual path using the
4135  * config passed
4136  */
4137 static enum vxge_hw_status
4138 __vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4139 {
4140         u64 val64;
4141         u64 vpath_stride;
4142         enum vxge_hw_status status = VXGE_HW_OK;
4143         struct __vxge_hw_virtualpath *vpath;
4144         struct vxge_hw_vpath_reg __iomem *vp_reg;
4145
4146         vpath = &hldev->virtual_paths[vp_id];
4147         vp_reg = vpath->vp_reg;
4148         status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);
4149
4150         if (status != VXGE_HW_OK)
4151                 goto exit;
4152
4153         val64 = readq(&vp_reg->kdfc_drbl_triplet_total);
4154
4155         vpath->max_kdfc_db =
4156                 (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(
4157                         val64+1)/2;
4158
4159         if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4160
4161                 vpath->max_nofl_db = vpath->max_kdfc_db;
4162
4163                 if (vpath->max_nofl_db <
4164                         ((vpath->vp_config->fifo.memblock_size /
4165                         (vpath->vp_config->fifo.max_frags *
4166                         sizeof(struct vxge_hw_fifo_txd))) *
4167                         vpath->vp_config->fifo.fifo_blocks)) {
4168
4169                         return VXGE_HW_BADCFG_FIFO_BLOCKS;
4170                 }
4171                 val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
4172                                 (vpath->max_nofl_db*2)-1);
4173         }
4174
4175         writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);
4176
4177         writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,
4178                 &vp_reg->kdfc_fifo_trpl_ctrl);
4179
4180         val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);
4181
4182         val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
4183                    VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF));
4184
4185         val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(
4186                  VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
4187 #ifndef __BIG_ENDIAN
4188                  VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
4189 #endif
4190                  VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
4191
4192         writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
4193         writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
4194         wmb();
4195         vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride);
4196
4197         vpath->nofl_db =
4198                 (struct __vxge_hw_non_offload_db_wrapper __iomem *)
4199                 (hldev->kdfc + (vp_id *
4200                 VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
4201                                         vpath_stride)));
4202 exit:
4203         return status;
4204 }
4205
4206 /*
4207  * __vxge_hw_vpath_mac_configure
4208  * This routine configures the mac of virtual path using the config passed
4209  */
4210 static enum vxge_hw_status
4211 __vxge_hw_vpath_mac_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4212 {
4213         u64 val64;
4214         struct __vxge_hw_virtualpath *vpath;
4215         struct vxge_hw_vp_config *vp_config;
4216         struct vxge_hw_vpath_reg __iomem *vp_reg;
4217
4218         vpath = &hldev->virtual_paths[vp_id];
4219         vp_reg = vpath->vp_reg;
4220         vp_config = vpath->vp_config;
4221
4222         writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(
4223                         vpath->vsport_number), &vp_reg->xmac_vsport_choice);
4224
4225         if (vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4226
4227                 val64 = readq(&vp_reg->xmac_rpa_vcfg);
4228
4229                 if (vp_config->rpa_strip_vlan_tag !=
4230                         VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) {
4231                         if (vp_config->rpa_strip_vlan_tag)
4232                                 val64 |= VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4233                         else
4234                                 val64 &= ~VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4235                 }
4236
4237                 writeq(val64, &vp_reg->xmac_rpa_vcfg);
4238                 val64 = readq(&vp_reg->rxmac_vcfg0);
4239
4240                 if (vp_config->mtu !=
4241                                 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) {
4242                         val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4243                         if ((vp_config->mtu  +
4244                                 VXGE_HW_MAC_HEADER_MAX_SIZE) < vpath->max_mtu)
4245                                 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
4246                                         vp_config->mtu  +
4247                                         VXGE_HW_MAC_HEADER_MAX_SIZE);
4248                         else
4249                                 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
4250                                         vpath->max_mtu);
4251                 }
4252
4253                 writeq(val64, &vp_reg->rxmac_vcfg0);
4254
4255                 val64 = readq(&vp_reg->rxmac_vcfg1);
4256
4257                 val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
4258                         VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE);
4259
4260                 if (hldev->config.rth_it_type ==
4261                                 VXGE_HW_RTH_IT_TYPE_MULTI_IT) {
4262                         val64 |= VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(
4263                                 0x2) |
4264                                 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE;
4265                 }
4266
4267                 writeq(val64, &vp_reg->rxmac_vcfg1);
4268         }
4269         return VXGE_HW_OK;
4270 }
4271
4272 /*
4273  * __vxge_hw_vpath_tim_configure
4274  * This routine configures the tim registers of virtual path using the config
4275  * passed
4276  */
4277 static enum vxge_hw_status
4278 __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4279 {
4280         u64 val64;
4281         struct __vxge_hw_virtualpath *vpath;
4282         struct vxge_hw_vpath_reg __iomem *vp_reg;
4283         struct vxge_hw_vp_config *config;
4284
4285         vpath = &hldev->virtual_paths[vp_id];
4286         vp_reg = vpath->vp_reg;
4287         config = vpath->vp_config;
4288
4289         writeq(0, &vp_reg->tim_dest_addr);
4290         writeq(0, &vp_reg->tim_vpath_map);
4291         writeq(0, &vp_reg->tim_bitmap);
4292         writeq(0, &vp_reg->tim_remap);
4293
4294         if (config->ring.enable == VXGE_HW_RING_ENABLE)
4295                 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM(
4296                         (vp_id * VXGE_HW_MAX_INTR_PER_VP) +
4297                         VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);
4298
4299         val64 = readq(&vp_reg->tim_pci_cfg);
4300         val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD;
4301         writeq(val64, &vp_reg->tim_pci_cfg);
4302
4303         if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4304
4305                 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4306
4307                 if (config->tti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4308                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4309                                 0x3ffffff);
4310                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4311                                         config->tti.btimer_val);
4312                 }
4313
4314                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
4315
4316                 if (config->tti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
4317                         if (config->tti.timer_ac_en)
4318                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4319                         else
4320                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4321                 }
4322
4323                 if (config->tti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
4324                         if (config->tti.timer_ci_en)
4325                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4326                         else
4327                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4328                 }
4329
4330                 if (config->tti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
4331                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
4332                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
4333                                         config->tti.urange_a);
4334                 }
4335
4336                 if (config->tti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
4337                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
4338                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
4339                                         config->tti.urange_b);
4340                 }
4341
4342                 if (config->tti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
4343                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
4344                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
4345                                         config->tti.urange_c);
4346                 }
4347
4348                 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4349                 vpath->tim_tti_cfg1_saved = val64;
4350
4351                 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
4352
4353                 if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
4354                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
4355                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
4356                                                 config->tti.uec_a);
4357                 }
4358
4359                 if (config->tti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
4360                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
4361                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
4362                                                 config->tti.uec_b);
4363                 }
4364
4365                 if (config->tti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
4366                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
4367                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
4368                                                 config->tti.uec_c);
4369                 }
4370
4371                 if (config->tti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
4372                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
4373                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
4374                                                 config->tti.uec_d);
4375                 }
4376
4377                 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
4378                 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
4379
4380                 if (config->tti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4381                         if (config->tti.timer_ri_en)
4382                                 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4383                         else
4384                                 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4385                 }
4386
4387                 if (config->tti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4388                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4389                                         0x3ffffff);
4390                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4391                                         config->tti.rtimer_val);
4392                 }
4393
4394                 if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4395                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
4396                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
4397                 }
4398
4399                 if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4400                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4401                                         0x3ffffff);
4402                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4403                                         config->tti.ltimer_val);
4404                 }
4405
4406                 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
4407                 vpath->tim_tti_cfg3_saved = val64;
4408         }
4409
4410         if (config->ring.enable == VXGE_HW_RING_ENABLE) {
4411
4412                 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
4413
4414                 if (config->rti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4415                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4416                                         0x3ffffff);
4417                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4418                                         config->rti.btimer_val);
4419                 }
4420
4421                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
4422
4423                 if (config->rti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
4424                         if (config->rti.timer_ac_en)
4425                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4426                         else
4427                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4428                 }
4429
4430                 if (config->rti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
4431                         if (config->rti.timer_ci_en)
4432                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4433                         else
4434                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4435                 }
4436
4437                 if (config->rti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
4438                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
4439                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
4440                                         config->rti.urange_a);
4441                 }
4442
4443                 if (config->rti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
4444                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
4445                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
4446                                         config->rti.urange_b);
4447                 }
4448
4449                 if (config->rti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
4450                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
4451                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
4452                                         config->rti.urange_c);
4453                 }
4454
4455                 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
4456                 vpath->tim_rti_cfg1_saved = val64;
4457
4458                 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
4459
4460                 if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
4461                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
4462                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
4463                                                 config->rti.uec_a);
4464                 }
4465
4466                 if (config->rti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
4467                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
4468                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
4469                                                 config->rti.uec_b);
4470                 }
4471
4472                 if (config->rti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
4473                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
4474                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
4475                                                 config->rti.uec_c);
4476                 }
4477
4478                 if (config->rti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
4479                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
4480                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
4481                                                 config->rti.uec_d);
4482                 }
4483
4484                 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
4485                 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
4486
4487                 if (config->rti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4488                         if (config->rti.timer_ri_en)
4489                                 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4490                         else
4491                                 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4492                 }
4493
4494                 if (config->rti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4495                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4496                                         0x3ffffff);
4497                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4498                                         config->rti.rtimer_val);
4499                 }
4500
4501                 if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4502                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
4503                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
4504                 }
4505
4506                 if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4507                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4508                                         0x3ffffff);
4509                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4510                                         config->rti.ltimer_val);
4511                 }
4512
4513                 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
4514                 vpath->tim_rti_cfg3_saved = val64;
4515         }
4516
4517         val64 = 0;
4518         writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4519         writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4520         writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4521         writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4522         writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4523         writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4524
4525         val64 = VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(150);
4526         val64 |= VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(0);
4527         val64 |= VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(3);
4528         writeq(val64, &vp_reg->tim_wrkld_clc);
4529
4530         return VXGE_HW_OK;
4531 }
4532
4533 /*
4534  * __vxge_hw_vpath_initialize
4535  * This routine is the final phase of init which initializes the
4536  * registers of the vpath using the configuration passed.
4537  */
4538 static enum vxge_hw_status
4539 __vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
4540 {
4541         u64 val64;
4542         u32 val32;
4543         enum vxge_hw_status status = VXGE_HW_OK;
4544         struct __vxge_hw_virtualpath *vpath;
4545         struct vxge_hw_vpath_reg __iomem *vp_reg;
4546
4547         vpath = &hldev->virtual_paths[vp_id];
4548
4549         if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4550                 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4551                 goto exit;
4552         }
4553         vp_reg = vpath->vp_reg;
4554
4555         status =  __vxge_hw_vpath_swapper_set(vpath->vp_reg);
4556         if (status != VXGE_HW_OK)
4557                 goto exit;
4558
4559         status =  __vxge_hw_vpath_mac_configure(hldev, vp_id);
4560         if (status != VXGE_HW_OK)
4561                 goto exit;
4562
4563         status =  __vxge_hw_vpath_kdfc_configure(hldev, vp_id);
4564         if (status != VXGE_HW_OK)
4565                 goto exit;
4566
4567         status = __vxge_hw_vpath_tim_configure(hldev, vp_id);
4568         if (status != VXGE_HW_OK)
4569                 goto exit;
4570
4571         val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
4572
4573         /* Get MRRS value from device control */
4574         status  = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32);
4575         if (status == VXGE_HW_OK) {
4576                 val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12;
4577                 val64 &=
4578                     ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7));
4579                 val64 |=
4580                     VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32);
4581
4582                 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE;
4583         }
4584
4585         val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7));
4586         val64 |=
4587             VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(
4588                     VXGE_HW_MAX_PAYLOAD_SIZE_512);
4589
4590         val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
4591         writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);
4592
4593 exit:
4594         return status;
4595 }
4596
4597 /*
4598  * __vxge_hw_vp_terminate - Terminate Virtual Path structure
4599  * This routine closes all channels it opened and freeup memory
4600  */
4601 static void __vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id)
4602 {
4603         struct __vxge_hw_virtualpath *vpath;
4604
4605         vpath = &hldev->virtual_paths[vp_id];
4606
4607         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN)
4608                 goto exit;
4609
4610         VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0,
4611                 vpath->hldev->tim_int_mask1, vpath->vp_id);
4612         hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL;
4613
4614         /* If the whole struct __vxge_hw_virtualpath is zeroed, nothing will
4615          * work after the interface is brought down.
4616          */
4617         spin_lock(&vpath->lock);
4618         vpath->vp_open = VXGE_HW_VP_NOT_OPEN;
4619         spin_unlock(&vpath->lock);
4620
4621         vpath->vpmgmt_reg = NULL;
4622         vpath->nofl_db = NULL;
4623         vpath->max_mtu = 0;
4624         vpath->vsport_number = 0;
4625         vpath->max_kdfc_db = 0;
4626         vpath->max_nofl_db = 0;
4627         vpath->ringh = NULL;
4628         vpath->fifoh = NULL;
4629         memset(&vpath->vpath_handles, 0, sizeof(struct list_head));
4630         vpath->stats_block = NULL;
4631         vpath->hw_stats = NULL;
4632         vpath->hw_stats_sav = NULL;
4633         vpath->sw_stats = NULL;
4634
4635 exit:
4636         return;
4637 }
4638
4639 /*
4640  * __vxge_hw_vp_initialize - Initialize Virtual Path structure
4641  * This routine is the initial phase of init which resets the vpath and
4642  * initializes the software support structures.
4643  */
4644 static enum vxge_hw_status
4645 __vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id,
4646                         struct vxge_hw_vp_config *config)
4647 {
4648         struct __vxge_hw_virtualpath *vpath;
4649         enum vxge_hw_status status = VXGE_HW_OK;
4650
4651         if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4652                 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4653                 goto exit;
4654         }
4655
4656         vpath = &hldev->virtual_paths[vp_id];
4657
4658         spin_lock_init(&vpath->lock);
4659         vpath->vp_id = vp_id;
4660         vpath->vp_open = VXGE_HW_VP_OPEN;
4661         vpath->hldev = hldev;
4662         vpath->vp_config = config;
4663         vpath->vp_reg = hldev->vpath_reg[vp_id];
4664         vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id];
4665
4666         __vxge_hw_vpath_reset(hldev, vp_id);
4667
4668         status = __vxge_hw_vpath_reset_check(vpath);
4669         if (status != VXGE_HW_OK) {
4670                 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4671                 goto exit;
4672         }
4673
4674         status = __vxge_hw_vpath_mgmt_read(hldev, vpath);
4675         if (status != VXGE_HW_OK) {
4676                 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4677                 goto exit;
4678         }
4679
4680         INIT_LIST_HEAD(&vpath->vpath_handles);
4681
4682         vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id];
4683
4684         VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0,
4685                 hldev->tim_int_mask1, vp_id);
4686
4687         status = __vxge_hw_vpath_initialize(hldev, vp_id);
4688         if (status != VXGE_HW_OK)
4689                 __vxge_hw_vp_terminate(hldev, vp_id);
4690 exit:
4691         return status;
4692 }
4693
4694 /*
4695  * vxge_hw_vpath_mtu_set - Set MTU.
4696  * Set new MTU value. Example, to use jumbo frames:
4697  * vxge_hw_vpath_mtu_set(my_device, 9600);
4698  */
4699 enum vxge_hw_status
4700 vxge_hw_vpath_mtu_set(struct __vxge_hw_vpath_handle *vp, u32 new_mtu)
4701 {
4702         u64 val64;
4703         enum vxge_hw_status status = VXGE_HW_OK;
4704         struct __vxge_hw_virtualpath *vpath;
4705
4706         if (vp == NULL) {
4707                 status = VXGE_HW_ERR_INVALID_HANDLE;
4708                 goto exit;
4709         }
4710         vpath = vp->vpath;
4711
4712         new_mtu += VXGE_HW_MAC_HEADER_MAX_SIZE;
4713
4714         if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > vpath->max_mtu))
4715                 status = VXGE_HW_ERR_INVALID_MTU_SIZE;
4716
4717         val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
4718
4719         val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4720         val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu);
4721
4722         writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
4723
4724         vpath->vp_config->mtu = new_mtu - VXGE_HW_MAC_HEADER_MAX_SIZE;
4725
4726 exit:
4727         return status;
4728 }
4729
4730 /*
4731  * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics.
4732  * Enable the DMA vpath statistics. The function is to be called to re-enable
4733  * the adapter to update stats into the host memory
4734  */
4735 static enum vxge_hw_status
4736 vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp)
4737 {
4738         enum vxge_hw_status status = VXGE_HW_OK;
4739         struct __vxge_hw_virtualpath *vpath;
4740
4741         vpath = vp->vpath;
4742
4743         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4744                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4745                 goto exit;
4746         }
4747
4748         memcpy(vpath->hw_stats_sav, vpath->hw_stats,
4749                         sizeof(struct vxge_hw_vpath_stats_hw_info));
4750
4751         status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats);
4752 exit:
4753         return status;
4754 }
4755
4756 /*
4757  * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool
4758  * This function allocates a block from block pool or from the system
4759  */
4760 static struct __vxge_hw_blockpool_entry *
4761 __vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size)
4762 {
4763         struct __vxge_hw_blockpool_entry *entry = NULL;
4764         struct __vxge_hw_blockpool  *blockpool;
4765
4766         blockpool = &devh->block_pool;
4767
4768         if (size == blockpool->block_size) {
4769
4770                 if (!list_empty(&blockpool->free_block_list))
4771                         entry = (struct __vxge_hw_blockpool_entry *)
4772                                 list_first_entry(&blockpool->free_block_list,
4773                                         struct __vxge_hw_blockpool_entry,
4774                                         item);
4775
4776                 if (entry != NULL) {
4777                         list_del(&entry->item);
4778                         blockpool->pool_size--;
4779                 }
4780         }
4781
4782         if (entry != NULL)
4783                 __vxge_hw_blockpool_blocks_add(blockpool);
4784
4785         return entry;
4786 }
4787
4788 /*
4789  * vxge_hw_vpath_open - Open a virtual path on a given adapter
4790  * This function is used to open access to virtual path of an
4791  * adapter for offload, GRO operations. This function returns
4792  * synchronously.
4793  */
4794 enum vxge_hw_status
4795 vxge_hw_vpath_open(struct __vxge_hw_device *hldev,
4796                    struct vxge_hw_vpath_attr *attr,
4797                    struct __vxge_hw_vpath_handle **vpath_handle)
4798 {
4799         struct __vxge_hw_virtualpath *vpath;
4800         struct __vxge_hw_vpath_handle *vp;
4801         enum vxge_hw_status status;
4802
4803         vpath = &hldev->virtual_paths[attr->vp_id];
4804
4805         if (vpath->vp_open == VXGE_HW_VP_OPEN) {
4806                 status = VXGE_HW_ERR_INVALID_STATE;
4807                 goto vpath_open_exit1;
4808         }
4809
4810         status = __vxge_hw_vp_initialize(hldev, attr->vp_id,
4811                         &hldev->config.vp_config[attr->vp_id]);
4812         if (status != VXGE_HW_OK)
4813                 goto vpath_open_exit1;
4814
4815         vp = vzalloc(sizeof(struct __vxge_hw_vpath_handle));
4816         if (vp == NULL) {
4817                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4818                 goto vpath_open_exit2;
4819         }
4820
4821         vp->vpath = vpath;
4822
4823         if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4824                 status = __vxge_hw_fifo_create(vp, &attr->fifo_attr);
4825                 if (status != VXGE_HW_OK)
4826                         goto vpath_open_exit6;
4827         }
4828
4829         if (vpath->vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4830                 status = __vxge_hw_ring_create(vp, &attr->ring_attr);
4831                 if (status != VXGE_HW_OK)
4832                         goto vpath_open_exit7;
4833
4834                 __vxge_hw_vpath_prc_configure(hldev, attr->vp_id);
4835         }
4836
4837         vpath->fifoh->tx_intr_num =
4838                 (attr->vp_id * VXGE_HW_MAX_INTR_PER_VP)  +
4839                         VXGE_HW_VPATH_INTR_TX;
4840
4841         vpath->stats_block = __vxge_hw_blockpool_block_allocate(hldev,
4842                                 VXGE_HW_BLOCK_SIZE);
4843         if (vpath->stats_block == NULL) {
4844                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4845                 goto vpath_open_exit8;
4846         }
4847
4848         vpath->hw_stats = vpath->stats_block->memblock;
4849         memset(vpath->hw_stats, 0,
4850                 sizeof(struct vxge_hw_vpath_stats_hw_info));
4851
4852         hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] =
4853                                                 vpath->hw_stats;
4854
4855         vpath->hw_stats_sav =
4856                 &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id];
4857         memset(vpath->hw_stats_sav, 0,
4858                         sizeof(struct vxge_hw_vpath_stats_hw_info));
4859
4860         writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);
4861
4862         status = vxge_hw_vpath_stats_enable(vp);
4863         if (status != VXGE_HW_OK)
4864                 goto vpath_open_exit8;
4865
4866         list_add(&vp->item, &vpath->vpath_handles);
4867
4868         hldev->vpaths_deployed |= vxge_mBIT(vpath->vp_id);
4869
4870         *vpath_handle = vp;
4871
4872         attr->fifo_attr.userdata = vpath->fifoh;
4873         attr->ring_attr.userdata = vpath->ringh;
4874
4875         return VXGE_HW_OK;
4876
4877 vpath_open_exit8:
4878         if (vpath->ringh != NULL)
4879                 __vxge_hw_ring_delete(vp);
4880 vpath_open_exit7:
4881         if (vpath->fifoh != NULL)
4882                 __vxge_hw_fifo_delete(vp);
4883 vpath_open_exit6:
4884         vfree(vp);
4885 vpath_open_exit2:
4886         __vxge_hw_vp_terminate(hldev, attr->vp_id);
4887 vpath_open_exit1:
4888
4889         return status;
4890 }
4891
4892 /**
4893  * vxge_hw_vpath_rx_doorbell_post - Close the handle got from previous vpath
4894  * (vpath) open
4895  * @vp: Handle got from previous vpath open
4896  *
4897  * This function is used to close access to virtual path opened
4898  * earlier.
4899  */
4900 void vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
4901 {
4902         struct __vxge_hw_virtualpath *vpath = vp->vpath;
4903         struct __vxge_hw_ring *ring = vpath->ringh;
4904         struct vxgedev *vdev = netdev_priv(vpath->hldev->ndev);
4905         u64 new_count, val64, val164;
4906
4907         if (vdev->titan1) {
4908                 new_count = readq(&vpath->vp_reg->rxdmem_size);
4909                 new_count &= 0x1fff;
4910         } else
4911                 new_count = ring->config->ring_blocks * VXGE_HW_BLOCK_SIZE / 8;
4912
4913         val164 = VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count);
4914
4915         writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164),
4916                 &vpath->vp_reg->prc_rxd_doorbell);
4917         readl(&vpath->vp_reg->prc_rxd_doorbell);
4918
4919         val164 /= 2;
4920         val64 = readq(&vpath->vp_reg->prc_cfg6);
4921         val64 = VXGE_HW_PRC_CFG6_RXD_SPAT(val64);
4922         val64 &= 0x1ff;
4923
4924         /*
4925          * Each RxD is of 4 qwords
4926          */
4927         new_count -= (val64 + 1);
4928         val64 = min(val164, new_count) / 4;
4929
4930         ring->rxds_limit = min(ring->rxds_limit, val64);
4931         if (ring->rxds_limit < 4)
4932                 ring->rxds_limit = 4;
4933 }
4934
4935 /*
4936  * __vxge_hw_blockpool_block_free - Frees a block from block pool
4937  * @devh: Hal device
4938  * @entry: Entry of block to be freed
4939  *
4940  * This function frees a block from block pool
4941  */
4942 static void
4943 __vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh,
4944                                struct __vxge_hw_blockpool_entry *entry)
4945 {
4946         struct __vxge_hw_blockpool  *blockpool;
4947
4948         blockpool = &devh->block_pool;
4949
4950         if (entry->length == blockpool->block_size) {
4951                 list_add(&entry->item, &blockpool->free_block_list);
4952                 blockpool->pool_size++;
4953         }
4954
4955         __vxge_hw_blockpool_blocks_remove(blockpool);
4956 }
4957
4958 /*
4959  * vxge_hw_vpath_close - Close the handle got from previous vpath (vpath) open
4960  * This function is used to close access to virtual path opened
4961  * earlier.
4962  */
4963 enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_vpath_handle *vp)
4964 {
4965         struct __vxge_hw_virtualpath *vpath = NULL;
4966         struct __vxge_hw_device *devh = NULL;
4967         u32 vp_id = vp->vpath->vp_id;
4968         u32 is_empty = TRUE;
4969         enum vxge_hw_status status = VXGE_HW_OK;
4970
4971         vpath = vp->vpath;
4972         devh = vpath->hldev;
4973
4974         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4975                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4976                 goto vpath_close_exit;
4977         }
4978
4979         list_del(&vp->item);
4980
4981         if (!list_empty(&vpath->vpath_handles)) {
4982                 list_add(&vp->item, &vpath->vpath_handles);
4983                 is_empty = FALSE;
4984         }
4985
4986         if (!is_empty) {
4987                 status = VXGE_HW_FAIL;
4988                 goto vpath_close_exit;
4989         }
4990
4991         devh->vpaths_deployed &= ~vxge_mBIT(vp_id);
4992
4993         if (vpath->ringh != NULL)
4994                 __vxge_hw_ring_delete(vp);
4995
4996         if (vpath->fifoh != NULL)
4997                 __vxge_hw_fifo_delete(vp);
4998
4999         if (vpath->stats_block != NULL)
5000                 __vxge_hw_blockpool_block_free(devh, vpath->stats_block);
5001
5002         vfree(vp);
5003
5004         __vxge_hw_vp_terminate(devh, vp_id);
5005
5006 vpath_close_exit:
5007         return status;
5008 }
5009
5010 /*
5011  * vxge_hw_vpath_reset - Resets vpath
5012  * This function is used to request a reset of vpath
5013  */
5014 enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_vpath_handle *vp)
5015 {
5016         enum vxge_hw_status status;
5017         u32 vp_id;
5018         struct __vxge_hw_virtualpath *vpath = vp->vpath;
5019
5020         vp_id = vpath->vp_id;
5021
5022         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
5023                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
5024                 goto exit;
5025         }
5026
5027         status = __vxge_hw_vpath_reset(vpath->hldev, vp_id);
5028         if (status == VXGE_HW_OK)
5029                 vpath->sw_stats->soft_reset_cnt++;
5030 exit:
5031         return status;
5032 }
5033
5034 /*
5035  * vxge_hw_vpath_recover_from_reset - Poll for reset complete and re-initialize.
5036  * This function poll's for the vpath reset completion and re initializes
5037  * the vpath.
5038  */
5039 enum vxge_hw_status
5040 vxge_hw_vpath_recover_from_reset(struct __vxge_hw_vpath_handle *vp)
5041 {
5042         struct __vxge_hw_virtualpath *vpath = NULL;
5043         enum vxge_hw_status status;
5044         struct __vxge_hw_device *hldev;
5045         u32 vp_id;
5046
5047         vp_id = vp->vpath->vp_id;
5048         vpath = vp->vpath;
5049         hldev = vpath->hldev;
5050
5051         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
5052                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
5053                 goto exit;
5054         }
5055
5056         status = __vxge_hw_vpath_reset_check(vpath);
5057         if (status != VXGE_HW_OK)
5058                 goto exit;
5059
5060         status = __vxge_hw_vpath_sw_reset(hldev, vp_id);
5061         if (status != VXGE_HW_OK)
5062                 goto exit;
5063
5064         status = __vxge_hw_vpath_initialize(hldev, vp_id);
5065         if (status != VXGE_HW_OK)
5066                 goto exit;
5067
5068         if (vpath->ringh != NULL)
5069                 __vxge_hw_vpath_prc_configure(hldev, vp_id);
5070
5071         memset(vpath->hw_stats, 0,
5072                 sizeof(struct vxge_hw_vpath_stats_hw_info));
5073
5074         memset(vpath->hw_stats_sav, 0,
5075                 sizeof(struct vxge_hw_vpath_stats_hw_info));
5076
5077         writeq(vpath->stats_block->dma_addr,
5078                 &vpath->vp_reg->stats_cfg);
5079
5080         status = vxge_hw_vpath_stats_enable(vp);
5081
5082 exit:
5083         return status;
5084 }
5085
5086 /*
5087  * vxge_hw_vpath_enable - Enable vpath.
5088  * This routine clears the vpath reset thereby enabling a vpath
5089  * to start forwarding frames and generating interrupts.
5090  */
5091 void
5092 vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp)
5093 {
5094         struct __vxge_hw_device *hldev;
5095         u64 val64;
5096
5097         hldev = vp->vpath->hldev;
5098
5099         val64 = VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(
5100                 1 << (16 - vp->vpath->vp_id));
5101
5102         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
5103                 &hldev->common_reg->cmn_rsthdlr_cfg1);
5104 }