drivers/net/ethernet/mscc/ocelot_dev.h

   1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
   2 /*
   3  * Microsemi Ocelot Switch driver
   4  *
   5  * Copyright (c) 2017 Microsemi Corporation
   6  */
   7
   8 #ifndef _MSCC_OCELOT_DEV_H_
   9 #define _MSCC_OCELOT_DEV_H_
  10
  11 #define DEV_CLOCK_CFG                                     0x0
  12
  13 #define DEV_CLOCK_CFG_MAC_TX_RST                          BIT(7)
  14 #define DEV_CLOCK_CFG_MAC_RX_RST                          BIT(6)
  15 #define DEV_CLOCK_CFG_PCS_TX_RST                          BIT(5)
  16 #define DEV_CLOCK_CFG_PCS_RX_RST                          BIT(4)
  17 #define DEV_CLOCK_CFG_PORT_RST                            BIT(3)
  18 #define DEV_CLOCK_CFG_PHY_RST                             BIT(2)
  19 #define DEV_CLOCK_CFG_LINK_SPEED(x)                       ((x) & GENMASK(1, 0))
  20 #define DEV_CLOCK_CFG_LINK_SPEED_M                        GENMASK(1, 0)
  21
  22 #define DEV_PORT_MISC                                     0x4
  23
  24 #define DEV_PORT_MISC_FWD_ERROR_ENA                       BIT(4)
  25 #define DEV_PORT_MISC_FWD_PAUSE_ENA                       BIT(3)
  26 #define DEV_PORT_MISC_FWD_CTRL_ENA                        BIT(2)
  27 #define DEV_PORT_MISC_DEV_LOOP_ENA                        BIT(1)
  28 #define DEV_PORT_MISC_HDX_FAST_DIS                        BIT(0)
  29
  30 #define DEV_EVENTS                                        0x8
  31
  32 #define DEV_EEE_CFG                                       0xc
  33
  34 #define DEV_EEE_CFG_EEE_ENA                               BIT(22)
  35 #define DEV_EEE_CFG_EEE_TIMER_AGE(x)                      (((x) << 15) & GENMASK(21, 15))
  36 #define DEV_EEE_CFG_EEE_TIMER_AGE_M                       GENMASK(21, 15)
  37 #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x)                    (((x) & GENMASK(21, 15)) >> 15)
  38 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x)                   (((x) << 8) & GENMASK(14, 8))
  39 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M                    GENMASK(14, 8)
  40 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x)                 (((x) & GENMASK(14, 8)) >> 8)
  41 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x)                  (((x) << 1) & GENMASK(7, 1))
  42 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M                   GENMASK(7, 1)
  43 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x)                (((x) & GENMASK(7, 1)) >> 1)
  44 #define DEV_EEE_CFG_PORT_LPI                              BIT(0)
  45
  46 #define DEV_RX_PATH_DELAY                                 0x10
  47
  48 #define DEV_TX_PATH_DELAY                                 0x14
  49
  50 #define DEV_PTP_PREDICT_CFG                               0x18
  51
  52 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x)        (((x) << 4) & GENMASK(11, 4))
  53 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M         GENMASK(11, 4)
  54 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x)      (((x) & GENMASK(11, 4)) >> 4)
  55 #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x)      ((x) & GENMASK(3, 0))
  56 #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M       GENMASK(3, 0)
  57
  58 #define DEV_MAC_ENA_CFG                                   0x1c
  59
  60 #define DEV_MAC_ENA_CFG_RX_ENA                            BIT(4)
  61 #define DEV_MAC_ENA_CFG_TX_ENA                            BIT(0)
  62
  63 #define DEV_MAC_MODE_CFG                                  0x20
  64
  65 #define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA                 BIT(8)
  66 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA                    BIT(4)
  67 #define DEV_MAC_MODE_CFG_FDX_ENA                          BIT(0)
  68
  69 #define DEV_MAC_MAXLEN_CFG                                0x24
  70
  71 #define DEV_MAC_TAGS_CFG                                  0x28
  72
  73 #define DEV_MAC_TAGS_CFG_TAG_ID(x)                        (((x) << 16) & GENMASK(31, 16))
  74 #define DEV_MAC_TAGS_CFG_TAG_ID_M                         GENMASK(31, 16)
  75 #define DEV_MAC_TAGS_CFG_TAG_ID_X(x)                      (((x) & GENMASK(31, 16)) >> 16)
  76 #define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA                 BIT(2)
  77 #define DEV_MAC_TAGS_CFG_PB_ENA                           BIT(1)
  78 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA                     BIT(0)
  79
  80 #define DEV_MAC_ADV_CHK_CFG                               0x2c
  81
  82 #define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA                  BIT(0)
  83
  84 #define DEV_MAC_IFG_CFG                                   0x30
  85
  86 #define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK             BIT(17)
  87 #define DEV_MAC_IFG_CFG_REDUCED_TX_IFG                    BIT(16)
  88 #define DEV_MAC_IFG_CFG_TX_IFG(x)                         (((x) << 8) & GENMASK(12, 8))
  89 #define DEV_MAC_IFG_CFG_TX_IFG_M                          GENMASK(12, 8)
  90 #define DEV_MAC_IFG_CFG_TX_IFG_X(x)                       (((x) & GENMASK(12, 8)) >> 8)
  91 #define DEV_MAC_IFG_CFG_RX_IFG2(x)                        (((x) << 4) & GENMASK(7, 4))
  92 #define DEV_MAC_IFG_CFG_RX_IFG2_M                         GENMASK(7, 4)
  93 #define DEV_MAC_IFG_CFG_RX_IFG2_X(x)                      (((x) & GENMASK(7, 4)) >> 4)
  94 #define DEV_MAC_IFG_CFG_RX_IFG1(x)                        ((x) & GENMASK(3, 0))
  95 #define DEV_MAC_IFG_CFG_RX_IFG1_M                         GENMASK(3, 0)
  96
  97 #define DEV_MAC_HDX_CFG                                   0x34
  98
  99 #define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC                   BIT(26)
 100 #define DEV_MAC_HDX_CFG_OB_ENA                            BIT(25)
 101 #define DEV_MAC_HDX_CFG_WEXC_DIS                          BIT(24)
 102 #define DEV_MAC_HDX_CFG_SEED(x)                           (((x) << 16) & GENMASK(23, 16))
 103 #define DEV_MAC_HDX_CFG_SEED_M                            GENMASK(23, 16)
 104 #define DEV_MAC_HDX_CFG_SEED_X(x)                         (((x) & GENMASK(23, 16)) >> 16)
 105 #define DEV_MAC_HDX_CFG_SEED_LOAD                         BIT(12)
 106 #define DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA           BIT(8)
 107 #define DEV_MAC_HDX_CFG_LATE_COL_POS(x)                   ((x) & GENMASK(6, 0))
 108 #define DEV_MAC_HDX_CFG_LATE_COL_POS_M                    GENMASK(6, 0)
 109
 110 #define DEV_MAC_DBG_CFG                                   0x38
 111
 112 #define DEV_MAC_DBG_CFG_TBI_MODE                          BIT(4)
 113 #define DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA               BIT(0)
 114
 115 #define DEV_MAC_FC_MAC_LOW_CFG                            0x3c
 116
 117 #define DEV_MAC_FC_MAC_HIGH_CFG                           0x40
 118
 119 #define DEV_MAC_STICKY                                    0x44
 120
 121 #define DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY               BIT(9)
 122 #define DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY             BIT(8)
 123 #define DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY              BIT(7)
 124 #define DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY          BIT(6)
 125 #define DEV_MAC_STICKY_RX_JUNK_STICKY                     BIT(5)
 126 #define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY               BIT(4)
 127 #define DEV_MAC_STICKY_TX_JAM_STICKY                      BIT(3)
 128 #define DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY                BIT(2)
 129 #define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY              BIT(1)
 130 #define DEV_MAC_STICKY_TX_ABORT_STICKY                    BIT(0)
 131
 132 #define PCS1G_CFG                                         0x48
 133
 134 #define PCS1G_CFG_LINK_STATUS_TYPE                        BIT(4)
 135 #define PCS1G_CFG_AN_LINK_CTRL_ENA                        BIT(1)
 136 #define PCS1G_CFG_PCS_ENA                                 BIT(0)
 137
 138 #define PCS1G_MODE_CFG                                    0x4c
 139
 140 #define PCS1G_MODE_CFG_UNIDIR_MODE_ENA                    BIT(4)
 141 #define PCS1G_MODE_CFG_SGMII_MODE_ENA                     BIT(0)
 142
 143 #define PCS1G_SD_CFG                                      0x50
 144
 145 #define PCS1G_SD_CFG_SD_SEL                               BIT(8)
 146 #define PCS1G_SD_CFG_SD_POL                               BIT(4)
 147 #define PCS1G_SD_CFG_SD_ENA                               BIT(0)
 148
 149 #define PCS1G_ANEG_CFG                                    0x54
 150
 151 #define PCS1G_ANEG_CFG_ADV_ABILITY(x)                     (((x) << 16) & GENMASK(31, 16))
 152 #define PCS1G_ANEG_CFG_ADV_ABILITY_M                      GENMASK(31, 16)
 153 #define PCS1G_ANEG_CFG_ADV_ABILITY_X(x)                   (((x) & GENMASK(31, 16)) >> 16)
 154 #define PCS1G_ANEG_CFG_SW_RESOLVE_ENA                     BIT(8)
 155 #define PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT              BIT(1)
 156 #define PCS1G_ANEG_CFG_ANEG_ENA                           BIT(0)
 157
 158 #define PCS1G_ANEG_NP_CFG                                 0x58
 159
 160 #define PCS1G_ANEG_NP_CFG_NP_TX(x)                        (((x) << 16) & GENMASK(31, 16))
 161 #define PCS1G_ANEG_NP_CFG_NP_TX_M                         GENMASK(31, 16)
 162 #define PCS1G_ANEG_NP_CFG_NP_TX_X(x)                      (((x) & GENMASK(31, 16)) >> 16)
 163 #define PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT              BIT(0)
 164
 165 #define PCS1G_LB_CFG                                      0x5c
 166
 167 #define PCS1G_LB_CFG_RA_ENA                               BIT(4)
 168 #define PCS1G_LB_CFG_GMII_PHY_LB_ENA                      BIT(1)
 169 #define PCS1G_LB_CFG_TBI_HOST_LB_ENA                      BIT(0)
 170
 171 #define PCS1G_DBG_CFG                                     0x60
 172
 173 #define PCS1G_DBG_CFG_UDLT                                BIT(0)
 174
 175 #define PCS1G_CDET_CFG                                    0x64
 176
 177 #define PCS1G_CDET_CFG_CDET_ENA                           BIT(0)
 178
 179 #define PCS1G_ANEG_STATUS                                 0x68
 180
 181 #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x)               (((x) << 16) & GENMASK(31, 16))
 182 #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M                GENMASK(31, 16)
 183 #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x)             (((x) & GENMASK(31, 16)) >> 16)
 184 #define PCS1G_ANEG_STATUS_PR                              BIT(4)
 185 #define PCS1G_ANEG_STATUS_PAGE_RX_STICKY                  BIT(3)
 186 #define PCS1G_ANEG_STATUS_ANEG_COMPLETE                   BIT(0)
 187
 188 #define PCS1G_ANEG_NP_STATUS                              0x6c
 189
 190 #define PCS1G_LINK_STATUS                                 0x70
 191
 192 #define PCS1G_LINK_STATUS_DELAY_VAR(x)                    (((x) << 12) & GENMASK(15, 12))
 193 #define PCS1G_LINK_STATUS_DELAY_VAR_M                     GENMASK(15, 12)
 194 #define PCS1G_LINK_STATUS_DELAY_VAR_X(x)                  (((x) & GENMASK(15, 12)) >> 12)
 195 #define PCS1G_LINK_STATUS_SIGNAL_DETECT                   BIT(8)
 196 #define PCS1G_LINK_STATUS_LINK_STATUS                     BIT(4)
 197 #define PCS1G_LINK_STATUS_SYNC_STATUS                     BIT(0)
 198
 199 #define PCS1G_LINK_DOWN_CNT                               0x74
 200
 201 #define PCS1G_STICKY                                      0x78
 202
 203 #define PCS1G_STICKY_LINK_DOWN_STICKY                     BIT(4)
 204 #define PCS1G_STICKY_OUT_OF_SYNC_STICKY                   BIT(0)
 205
 206 #define PCS1G_DEBUG_STATUS                                0x7c
 207
 208 #define PCS1G_LPI_CFG                                     0x80
 209
 210 #define PCS1G_LPI_CFG_QSGMII_MS_SEL                       BIT(20)
 211 #define PCS1G_LPI_CFG_RX_LPI_OUT_DIS                      BIT(17)
 212 #define PCS1G_LPI_CFG_LPI_TESTMODE                        BIT(16)
 213 #define PCS1G_LPI_CFG_LPI_RX_WTIM(x)                      (((x) << 4) & GENMASK(5, 4))
 214 #define PCS1G_LPI_CFG_LPI_RX_WTIM_M                       GENMASK(5, 4)
 215 #define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x)                    (((x) & GENMASK(5, 4)) >> 4)
 216 #define PCS1G_LPI_CFG_TX_ASSERT_LPIDLE                    BIT(0)
 217
 218 #define PCS1G_LPI_WAKE_ERROR_CNT                          0x84
 219
 220 #define PCS1G_LPI_STATUS                                  0x88
 221
 222 #define PCS1G_LPI_STATUS_RX_LPI_FAIL                      BIT(16)
 223 #define PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY              BIT(12)
 224 #define PCS1G_LPI_STATUS_RX_QUIET                         BIT(9)
 225 #define PCS1G_LPI_STATUS_RX_LPI_MODE                      BIT(8)
 226 #define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY              BIT(4)
 227 #define PCS1G_LPI_STATUS_TX_QUIET                         BIT(1)
 228 #define PCS1G_LPI_STATUS_TX_LPI_MODE                      BIT(0)
 229
 230 #define PCS1G_TSTPAT_MODE_CFG                             0x8c
 231
 232 #define PCS1G_TSTPAT_STATUS                               0x90
 233
 234 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x)                (((x) << 8) & GENMASK(15, 8))
 235 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M                 GENMASK(15, 8)
 236 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x)              (((x) & GENMASK(15, 8)) >> 8)
 237 #define PCS1G_TSTPAT_STATUS_JTP_ERR                       BIT(4)
 238 #define PCS1G_TSTPAT_STATUS_JTP_LOCK                      BIT(0)
 239
 240 #define DEV_PCS_FX100_CFG                                 0x94
 241
 242 #define DEV_PCS_FX100_CFG_SD_SEL                          BIT(26)
 243 #define DEV_PCS_FX100_CFG_SD_POL                          BIT(25)
 244 #define DEV_PCS_FX100_CFG_SD_ENA                          BIT(24)
 245 #define DEV_PCS_FX100_CFG_LOOPBACK_ENA                    BIT(20)
 246 #define DEV_PCS_FX100_CFG_SWAP_MII_ENA                    BIT(16)
 247 #define DEV_PCS_FX100_CFG_RXBITSEL(x)                     (((x) << 12) & GENMASK(15, 12))
 248 #define DEV_PCS_FX100_CFG_RXBITSEL_M                      GENMASK(15, 12)
 249 #define DEV_PCS_FX100_CFG_RXBITSEL_X(x)                   (((x) & GENMASK(15, 12)) >> 12)
 250 #define DEV_PCS_FX100_CFG_SIGDET_CFG(x)                   (((x) << 9) & GENMASK(10, 9))
 251 #define DEV_PCS_FX100_CFG_SIGDET_CFG_M                    GENMASK(10, 9)
 252 #define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x)                 (((x) & GENMASK(10, 9)) >> 9)
 253 #define DEV_PCS_FX100_CFG_LINKHYST_TM_ENA                 BIT(8)
 254 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x)                (((x) << 4) & GENMASK(7, 4))
 255 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M                 GENMASK(7, 4)
 256 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x)              (((x) & GENMASK(7, 4)) >> 4)
 257 #define DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA                 BIT(3)
 258 #define DEV_PCS_FX100_CFG_FEFCHK_ENA                      BIT(2)
 259 #define DEV_PCS_FX100_CFG_FEFGEN_ENA                      BIT(1)
 260 #define DEV_PCS_FX100_CFG_PCS_ENA                         BIT(0)
 261
 262 #define DEV_PCS_FX100_STATUS                              0x98
 263
 264 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x)              (((x) << 8) & GENMASK(11, 8))
 265 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M               GENMASK(11, 8)
 266 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x)            (((x) & GENMASK(11, 8)) >> 8)
 267 #define DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY             BIT(7)
 268 #define DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY             BIT(6)
 269 #define DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY             BIT(5)
 270 #define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY             BIT(4)
 271 #define DEV_PCS_FX100_STATUS_FEF_STATUS                   BIT(2)
 272 #define DEV_PCS_FX100_STATUS_SIGNAL_DETECT                BIT(1)
 273 #define DEV_PCS_FX100_STATUS_SYNC_STATUS                  BIT(0)
 274
 275 #endif