2 * drivers/net/ethernet/mellanox/mlxsw/switchx2.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/netdevice.h>
41 #include <linux/etherdevice.h>
42 #include <linux/slab.h>
43 #include <linux/device.h>
44 #include <linux/skbuff.h>
45 #include <linux/if_vlan.h>
46 #include <net/switchdev.h>
47 #include <generated/utsrelease.h>
55 static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
56 static const char mlxsw_sx_driver_version[] = "1.0";
61 struct mlxsw_sx_port **ports;
62 struct mlxsw_core *core;
63 const struct mlxsw_bus_info *bus_info;
67 struct mlxsw_sx_port_pcpu_stats {
72 struct u64_stats_sync syncp;
76 struct mlxsw_sx_port {
77 struct mlxsw_core_port core_port; /* must be first */
78 struct net_device *dev;
79 struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
80 struct mlxsw_sx *mlxsw_sx;
88 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
91 * Packet control type.
92 * 0 - Ethernet control (e.g. EMADs, LACP)
95 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
98 * Packet protocol type. Must be set to 1 (Ethernet).
100 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
103 * Egress TClass to be used on the egress device on the egress port.
104 * The MSB is specified in the 'ctclass3' field.
105 * Range is 0-15, where 15 is the highest priority.
107 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
110 * Switch partition ID.
112 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
115 * Destination local port for unicast packets.
116 * Destination multicast ID for multicast packets.
118 * Control packets are directed to a specific egress port, while data
119 * packets are transmitted through the CPU port (0) into the switch partition,
120 * where forwarding rules are applied.
122 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
125 * See field 'etclass'.
127 MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
130 * RDQ for control packets sent to remote CPU.
131 * Must be set to 0x1F for EMADs, otherwise 0.
133 MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
136 * Signature control for packets going to CPU. Must be set to 0.
138 MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
141 * Stacking protocl signature. Must be set to 0xE0E0.
143 MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
148 MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
151 * EMAD bit. Must be set for EMADs.
153 MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
157 * 6 - Control packets
159 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
161 static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
162 const struct mlxsw_tx_info *tx_info)
164 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
165 bool is_emad = tx_info->is_emad;
167 memset(txhdr, 0, MLXSW_TXHDR_LEN);
169 /* We currently set default values for the egress tclass (QoS). */
170 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
171 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
172 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
173 mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
174 MLXSW_TXHDR_ETCLASS_5);
175 mlxsw_tx_hdr_swid_set(txhdr, 0);
176 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
177 mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
178 mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
179 MLXSW_TXHDR_RDQ_OTHER);
180 mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
181 mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
182 mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
183 mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
184 MLXSW_TXHDR_NOT_EMAD);
185 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
188 static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
191 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
192 char paos_pl[MLXSW_REG_PAOS_LEN];
194 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
195 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
196 MLXSW_PORT_ADMIN_STATUS_DOWN);
197 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
200 static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
203 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
204 char paos_pl[MLXSW_REG_PAOS_LEN];
208 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
209 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
212 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
213 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
217 static int mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port, u16 mtu)
219 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
220 char pmtu_pl[MLXSW_REG_PMTU_LEN];
224 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
225 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
226 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
229 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
234 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
235 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
238 static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
240 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
241 char pspa_pl[MLXSW_REG_PSPA_LEN];
243 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
244 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
248 mlxsw_sx_port_system_port_mapping_set(struct mlxsw_sx_port *mlxsw_sx_port)
250 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
251 char sspr_pl[MLXSW_REG_SSPR_LEN];
253 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sx_port->local_port);
254 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sspr), sspr_pl);
257 static int mlxsw_sx_port_module_check(struct mlxsw_sx_port *mlxsw_sx_port,
260 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
261 char pmlp_pl[MLXSW_REG_PMLP_LEN];
264 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sx_port->local_port);
265 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
268 *p_usable = mlxsw_reg_pmlp_width_get(pmlp_pl) ? true : false;
272 static int mlxsw_sx_port_open(struct net_device *dev)
274 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
277 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
280 netif_start_queue(dev);
284 static int mlxsw_sx_port_stop(struct net_device *dev)
286 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
288 netif_stop_queue(dev);
289 return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
292 static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
293 struct net_device *dev)
295 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
296 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
297 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
298 const struct mlxsw_tx_info tx_info = {
299 .local_port = mlxsw_sx_port->local_port,
305 if (mlxsw_core_skb_transmit_busy(mlxsw_sx->core, &tx_info))
306 return NETDEV_TX_BUSY;
308 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
309 struct sk_buff *skb_orig = skb;
311 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
313 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
314 dev_kfree_skb_any(skb_orig);
317 dev_consume_skb_any(skb_orig);
319 mlxsw_sx_txhdr_construct(skb, &tx_info);
320 /* TX header is consumed by HW on the way so we shouldn't count its
321 * bytes as being sent.
323 len = skb->len - MLXSW_TXHDR_LEN;
324 /* Due to a race we might fail here because of a full queue. In that
325 * unlikely case we simply drop the packet.
327 err = mlxsw_core_skb_transmit(mlxsw_sx->core, skb, &tx_info);
330 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
331 u64_stats_update_begin(&pcpu_stats->syncp);
332 pcpu_stats->tx_packets++;
333 pcpu_stats->tx_bytes += len;
334 u64_stats_update_end(&pcpu_stats->syncp);
336 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
337 dev_kfree_skb_any(skb);
342 static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
344 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
347 err = mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
354 static struct rtnl_link_stats64 *
355 mlxsw_sx_port_get_stats64(struct net_device *dev,
356 struct rtnl_link_stats64 *stats)
358 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
359 struct mlxsw_sx_port_pcpu_stats *p;
360 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
365 for_each_possible_cpu(i) {
366 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
368 start = u64_stats_fetch_begin_irq(&p->syncp);
369 rx_packets = p->rx_packets;
370 rx_bytes = p->rx_bytes;
371 tx_packets = p->tx_packets;
372 tx_bytes = p->tx_bytes;
373 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
375 stats->rx_packets += rx_packets;
376 stats->rx_bytes += rx_bytes;
377 stats->tx_packets += tx_packets;
378 stats->tx_bytes += tx_bytes;
379 /* tx_dropped is u32, updated without syncp protection. */
380 tx_dropped += p->tx_dropped;
382 stats->tx_dropped = tx_dropped;
386 static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
387 .ndo_open = mlxsw_sx_port_open,
388 .ndo_stop = mlxsw_sx_port_stop,
389 .ndo_start_xmit = mlxsw_sx_port_xmit,
390 .ndo_change_mtu = mlxsw_sx_port_change_mtu,
391 .ndo_get_stats64 = mlxsw_sx_port_get_stats64,
394 static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
395 struct ethtool_drvinfo *drvinfo)
397 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
398 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
400 strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
401 strlcpy(drvinfo->version, mlxsw_sx_driver_version,
402 sizeof(drvinfo->version));
403 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
405 mlxsw_sx->bus_info->fw_rev.major,
406 mlxsw_sx->bus_info->fw_rev.minor,
407 mlxsw_sx->bus_info->fw_rev.subminor);
408 strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
409 sizeof(drvinfo->bus_info));
412 struct mlxsw_sx_port_hw_stats {
413 char str[ETH_GSTRING_LEN];
414 u64 (*getter)(char *payload);
417 static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
419 .str = "a_frames_transmitted_ok",
420 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
423 .str = "a_frames_received_ok",
424 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
427 .str = "a_frame_check_sequence_errors",
428 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
431 .str = "a_alignment_errors",
432 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
435 .str = "a_octets_transmitted_ok",
436 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
439 .str = "a_octets_received_ok",
440 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
443 .str = "a_multicast_frames_xmitted_ok",
444 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
447 .str = "a_broadcast_frames_xmitted_ok",
448 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
451 .str = "a_multicast_frames_received_ok",
452 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
455 .str = "a_broadcast_frames_received_ok",
456 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
459 .str = "a_in_range_length_errors",
460 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
463 .str = "a_out_of_range_length_field",
464 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
467 .str = "a_frame_too_long_errors",
468 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
471 .str = "a_symbol_error_during_carrier",
472 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
475 .str = "a_mac_control_frames_transmitted",
476 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
479 .str = "a_mac_control_frames_received",
480 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
483 .str = "a_unsupported_opcodes_received",
484 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
487 .str = "a_pause_mac_ctrl_frames_received",
488 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
491 .str = "a_pause_mac_ctrl_frames_xmitted",
492 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
496 #define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
498 static void mlxsw_sx_port_get_strings(struct net_device *dev,
499 u32 stringset, u8 *data)
506 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
507 memcpy(p, mlxsw_sx_port_hw_stats[i].str,
509 p += ETH_GSTRING_LEN;
515 static void mlxsw_sx_port_get_stats(struct net_device *dev,
516 struct ethtool_stats *stats, u64 *data)
518 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
519 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
520 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
524 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port,
525 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
526 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
527 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
528 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
531 static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
535 return MLXSW_SX_PORT_HW_STATS_LEN;
541 struct mlxsw_sx_port_link_mode {
548 static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
550 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
551 .supported = SUPPORTED_100baseT_Full,
552 .advertised = ADVERTISED_100baseT_Full,
556 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
560 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
561 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
562 .supported = SUPPORTED_1000baseKX_Full,
563 .advertised = ADVERTISED_1000baseKX_Full,
567 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
568 .supported = SUPPORTED_10000baseT_Full,
569 .advertised = ADVERTISED_10000baseT_Full,
573 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
574 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
575 .supported = SUPPORTED_10000baseKX4_Full,
576 .advertised = ADVERTISED_10000baseKX4_Full,
580 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
581 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
582 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
583 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
584 .supported = SUPPORTED_10000baseKR_Full,
585 .advertised = ADVERTISED_10000baseKR_Full,
589 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
590 .supported = SUPPORTED_20000baseKR2_Full,
591 .advertised = ADVERTISED_20000baseKR2_Full,
595 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
596 .supported = SUPPORTED_40000baseCR4_Full,
597 .advertised = ADVERTISED_40000baseCR4_Full,
601 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
602 .supported = SUPPORTED_40000baseKR4_Full,
603 .advertised = ADVERTISED_40000baseKR4_Full,
607 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
608 .supported = SUPPORTED_40000baseSR4_Full,
609 .advertised = ADVERTISED_40000baseSR4_Full,
613 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
614 .supported = SUPPORTED_40000baseLR4_Full,
615 .advertised = ADVERTISED_40000baseLR4_Full,
619 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
620 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
621 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
625 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
626 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
627 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
631 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
632 .supported = SUPPORTED_56000baseKR4_Full,
633 .advertised = ADVERTISED_56000baseKR4_Full,
637 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
638 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
639 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
640 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
645 #define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
647 static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
649 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
650 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
651 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
652 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
653 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
654 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
655 return SUPPORTED_FIBRE;
657 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
658 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
659 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
660 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
661 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
662 return SUPPORTED_Backplane;
666 static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
671 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
672 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
673 modes |= mlxsw_sx_port_link_mode[i].supported;
678 static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
683 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
684 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
685 modes |= mlxsw_sx_port_link_mode[i].advertised;
690 static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
691 struct ethtool_cmd *cmd)
693 u32 speed = SPEED_UNKNOWN;
694 u8 duplex = DUPLEX_UNKNOWN;
700 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
701 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
702 speed = mlxsw_sx_port_link_mode[i].speed;
703 duplex = DUPLEX_FULL;
708 ethtool_cmd_speed_set(cmd, speed);
709 cmd->duplex = duplex;
712 static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
714 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
715 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
716 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
717 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
720 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
721 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
722 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
725 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
726 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
727 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
728 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
734 static int mlxsw_sx_port_get_settings(struct net_device *dev,
735 struct ethtool_cmd *cmd)
737 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
738 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
739 char ptys_pl[MLXSW_REG_PTYS_LEN];
745 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
746 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
748 netdev_err(dev, "Failed to get proto");
751 mlxsw_reg_ptys_unpack(ptys_pl, ð_proto_cap,
752 ð_proto_admin, ð_proto_oper);
754 cmd->supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
755 mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
756 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
757 cmd->advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
758 mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
759 eth_proto_oper, cmd);
761 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
762 cmd->port = mlxsw_sx_port_connector_port(eth_proto_oper);
763 cmd->lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
765 cmd->transceiver = XCVR_INTERNAL;
769 static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
774 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
775 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
776 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
781 static u32 mlxsw_sx_to_ptys_speed(u32 speed)
786 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
787 if (speed == mlxsw_sx_port_link_mode[i].speed)
788 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
793 static int mlxsw_sx_port_set_settings(struct net_device *dev,
794 struct ethtool_cmd *cmd)
796 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
797 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
798 char ptys_pl[MLXSW_REG_PTYS_LEN];
806 speed = ethtool_cmd_speed(cmd);
808 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
809 mlxsw_sx_to_ptys_advert_link(cmd->advertising) :
810 mlxsw_sx_to_ptys_speed(speed);
812 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
813 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
815 netdev_err(dev, "Failed to get proto");
818 mlxsw_reg_ptys_unpack(ptys_pl, ð_proto_cap, ð_proto_admin, NULL);
820 eth_proto_new = eth_proto_new & eth_proto_cap;
821 if (!eth_proto_new) {
822 netdev_err(dev, "Not supported proto admin requested");
825 if (eth_proto_new == eth_proto_admin)
828 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, eth_proto_new);
829 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
831 netdev_err(dev, "Failed to set proto admin");
835 err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
837 netdev_err(dev, "Failed to get oper status");
843 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
845 netdev_err(dev, "Failed to set admin status");
849 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
851 netdev_err(dev, "Failed to set admin status");
858 static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
859 .get_drvinfo = mlxsw_sx_port_get_drvinfo,
860 .get_link = ethtool_op_get_link,
861 .get_strings = mlxsw_sx_port_get_strings,
862 .get_ethtool_stats = mlxsw_sx_port_get_stats,
863 .get_sset_count = mlxsw_sx_port_get_sset_count,
864 .get_settings = mlxsw_sx_port_get_settings,
865 .set_settings = mlxsw_sx_port_set_settings,
868 static int mlxsw_sx_port_attr_get(struct net_device *dev,
869 struct switchdev_attr *attr)
871 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
872 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
875 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
876 attr->u.ppid.id_len = sizeof(mlxsw_sx->hw_id);
877 memcpy(&attr->u.ppid.id, &mlxsw_sx->hw_id, attr->u.ppid.id_len);
886 static const struct switchdev_ops mlxsw_sx_port_switchdev_ops = {
887 .switchdev_port_attr_get = mlxsw_sx_port_attr_get,
890 static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
892 char spad_pl[MLXSW_REG_SPAD_LEN];
895 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
898 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
902 static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
904 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
905 struct net_device *dev = mlxsw_sx_port->dev;
906 char ppad_pl[MLXSW_REG_PPAD_LEN];
909 mlxsw_reg_ppad_pack(ppad_pl, false, 0);
910 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
913 mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
914 /* The last byte value in base mac address is guaranteed
915 * to be such it does not overflow when adding local_port
918 dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
922 static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
923 u16 vid, enum mlxsw_reg_spms_state state)
925 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
929 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
932 mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port);
933 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
934 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
939 static int mlxsw_sx_port_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
942 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
943 char ptys_pl[MLXSW_REG_PTYS_LEN];
945 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, speed);
946 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
950 mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
951 enum mlxsw_reg_spmlr_learn_mode mode)
953 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
954 char spmlr_pl[MLXSW_REG_SPMLR_LEN];
956 mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
957 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
960 static int mlxsw_sx_port_create(struct mlxsw_sx *mlxsw_sx, u8 local_port)
962 struct mlxsw_sx_port *mlxsw_sx_port;
963 struct net_device *dev;
967 dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
970 mlxsw_sx_port = netdev_priv(dev);
971 mlxsw_sx_port->dev = dev;
972 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
973 mlxsw_sx_port->local_port = local_port;
975 mlxsw_sx_port->pcpu_stats =
976 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
977 if (!mlxsw_sx_port->pcpu_stats) {
979 goto err_alloc_stats;
982 dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
983 dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
984 dev->switchdev_ops = &mlxsw_sx_port_switchdev_ops;
986 err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
988 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
989 mlxsw_sx_port->local_port);
990 goto err_dev_addr_get;
993 netif_carrier_off(dev);
995 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
996 NETIF_F_VLAN_CHALLENGED;
998 /* Each packet needs to have a Tx header (metadata) on top all other
1001 dev->needed_headroom = MLXSW_TXHDR_LEN;
1003 err = mlxsw_sx_port_module_check(mlxsw_sx_port, &usable);
1005 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to check module\n",
1006 mlxsw_sx_port->local_port);
1007 goto err_port_module_check;
1011 dev_dbg(mlxsw_sx->bus_info->dev, "Port %d: Not usable, skipping initialization\n",
1012 mlxsw_sx_port->local_port);
1013 goto port_not_usable;
1016 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1018 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1019 mlxsw_sx_port->local_port);
1020 goto err_port_system_port_mapping_set;
1023 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1025 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1026 mlxsw_sx_port->local_port);
1027 goto err_port_swid_set;
1030 err = mlxsw_sx_port_speed_set(mlxsw_sx_port,
1031 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4);
1033 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1034 mlxsw_sx_port->local_port);
1035 goto err_port_speed_set;
1038 err = mlxsw_sx_port_mtu_set(mlxsw_sx_port, ETH_DATA_LEN);
1040 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1041 mlxsw_sx_port->local_port);
1042 goto err_port_mtu_set;
1045 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1047 goto err_port_admin_status_set;
1049 err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1050 MLXSW_PORT_DEFAULT_VID,
1051 MLXSW_REG_SPMS_STATE_FORWARDING);
1053 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1054 mlxsw_sx_port->local_port);
1055 goto err_port_stp_state_set;
1058 err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1059 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1061 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1062 mlxsw_sx_port->local_port);
1063 goto err_port_mac_learning_mode_set;
1066 err = register_netdev(dev);
1068 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1069 mlxsw_sx_port->local_port);
1070 goto err_register_netdev;
1073 err = mlxsw_core_port_init(mlxsw_sx->core, &mlxsw_sx_port->core_port,
1074 mlxsw_sx_port->local_port, dev, false, 0);
1076 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to init core port\n",
1077 mlxsw_sx_port->local_port);
1078 goto err_core_port_init;
1081 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1085 unregister_netdev(dev);
1086 err_register_netdev:
1087 err_port_mac_learning_mode_set:
1088 err_port_stp_state_set:
1089 err_port_admin_status_set:
1092 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1094 err_port_system_port_mapping_set:
1096 err_port_module_check:
1098 free_percpu(mlxsw_sx_port->pcpu_stats);
1104 static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1106 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1110 mlxsw_core_port_fini(&mlxsw_sx_port->core_port);
1111 unregister_netdev(mlxsw_sx_port->dev); /* This calls ndo_stop */
1112 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1113 free_percpu(mlxsw_sx_port->pcpu_stats);
1114 free_netdev(mlxsw_sx_port->dev);
1117 static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1121 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1122 mlxsw_sx_port_remove(mlxsw_sx, i);
1123 kfree(mlxsw_sx->ports);
1126 static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1132 alloc_size = sizeof(struct mlxsw_sx_port *) * MLXSW_PORT_MAX_PORTS;
1133 mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1134 if (!mlxsw_sx->ports)
1137 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
1138 err = mlxsw_sx_port_create(mlxsw_sx, i);
1140 goto err_port_create;
1145 for (i--; i >= 1; i--)
1146 mlxsw_sx_port_remove(mlxsw_sx, i);
1147 kfree(mlxsw_sx->ports);
1151 static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1152 char *pude_pl, void *priv)
1154 struct mlxsw_sx *mlxsw_sx = priv;
1155 struct mlxsw_sx_port *mlxsw_sx_port;
1156 enum mlxsw_reg_pude_oper_status status;
1159 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1160 mlxsw_sx_port = mlxsw_sx->ports[local_port];
1161 if (!mlxsw_sx_port) {
1162 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1167 status = mlxsw_reg_pude_oper_status_get(pude_pl);
1168 if (status == MLXSW_PORT_OPER_STATUS_UP) {
1169 netdev_info(mlxsw_sx_port->dev, "link up\n");
1170 netif_carrier_on(mlxsw_sx_port->dev);
1172 netdev_info(mlxsw_sx_port->dev, "link down\n");
1173 netif_carrier_off(mlxsw_sx_port->dev);
1177 static struct mlxsw_event_listener mlxsw_sx_pude_event = {
1178 .func = mlxsw_sx_pude_event_func,
1179 .trap_id = MLXSW_TRAP_ID_PUDE,
1182 static int mlxsw_sx_event_register(struct mlxsw_sx *mlxsw_sx,
1183 enum mlxsw_event_trap_id trap_id)
1185 struct mlxsw_event_listener *el;
1186 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1190 case MLXSW_TRAP_ID_PUDE:
1191 el = &mlxsw_sx_pude_event;
1194 err = mlxsw_core_event_listener_register(mlxsw_sx->core, el, mlxsw_sx);
1198 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
1199 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1201 goto err_event_trap_set;
1206 mlxsw_core_event_listener_unregister(mlxsw_sx->core, el, mlxsw_sx);
1210 static void mlxsw_sx_event_unregister(struct mlxsw_sx *mlxsw_sx,
1211 enum mlxsw_event_trap_id trap_id)
1213 struct mlxsw_event_listener *el;
1216 case MLXSW_TRAP_ID_PUDE:
1217 el = &mlxsw_sx_pude_event;
1220 mlxsw_core_event_listener_unregister(mlxsw_sx->core, el, mlxsw_sx);
1223 static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1226 struct mlxsw_sx *mlxsw_sx = priv;
1227 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1228 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1230 if (unlikely(!mlxsw_sx_port)) {
1231 dev_warn_ratelimited(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1236 skb->dev = mlxsw_sx_port->dev;
1238 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1239 u64_stats_update_begin(&pcpu_stats->syncp);
1240 pcpu_stats->rx_packets++;
1241 pcpu_stats->rx_bytes += skb->len;
1242 u64_stats_update_end(&pcpu_stats->syncp);
1244 skb->protocol = eth_type_trans(skb, skb->dev);
1245 netif_receive_skb(skb);
1248 static const struct mlxsw_rx_listener mlxsw_sx_rx_listener[] = {
1250 .func = mlxsw_sx_rx_listener_func,
1251 .local_port = MLXSW_PORT_DONT_CARE,
1252 .trap_id = MLXSW_TRAP_ID_FDB_MC,
1254 /* Traps for specific L2 packet types, not trapped as FDB MC */
1256 .func = mlxsw_sx_rx_listener_func,
1257 .local_port = MLXSW_PORT_DONT_CARE,
1258 .trap_id = MLXSW_TRAP_ID_STP,
1261 .func = mlxsw_sx_rx_listener_func,
1262 .local_port = MLXSW_PORT_DONT_CARE,
1263 .trap_id = MLXSW_TRAP_ID_LACP,
1266 .func = mlxsw_sx_rx_listener_func,
1267 .local_port = MLXSW_PORT_DONT_CARE,
1268 .trap_id = MLXSW_TRAP_ID_EAPOL,
1271 .func = mlxsw_sx_rx_listener_func,
1272 .local_port = MLXSW_PORT_DONT_CARE,
1273 .trap_id = MLXSW_TRAP_ID_LLDP,
1276 .func = mlxsw_sx_rx_listener_func,
1277 .local_port = MLXSW_PORT_DONT_CARE,
1278 .trap_id = MLXSW_TRAP_ID_MMRP,
1281 .func = mlxsw_sx_rx_listener_func,
1282 .local_port = MLXSW_PORT_DONT_CARE,
1283 .trap_id = MLXSW_TRAP_ID_MVRP,
1286 .func = mlxsw_sx_rx_listener_func,
1287 .local_port = MLXSW_PORT_DONT_CARE,
1288 .trap_id = MLXSW_TRAP_ID_RPVST,
1291 .func = mlxsw_sx_rx_listener_func,
1292 .local_port = MLXSW_PORT_DONT_CARE,
1293 .trap_id = MLXSW_TRAP_ID_DHCP,
1296 .func = mlxsw_sx_rx_listener_func,
1297 .local_port = MLXSW_PORT_DONT_CARE,
1298 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
1301 .func = mlxsw_sx_rx_listener_func,
1302 .local_port = MLXSW_PORT_DONT_CARE,
1303 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
1306 .func = mlxsw_sx_rx_listener_func,
1307 .local_port = MLXSW_PORT_DONT_CARE,
1308 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
1311 .func = mlxsw_sx_rx_listener_func,
1312 .local_port = MLXSW_PORT_DONT_CARE,
1313 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
1316 .func = mlxsw_sx_rx_listener_func,
1317 .local_port = MLXSW_PORT_DONT_CARE,
1318 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
1322 static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1324 char htgt_pl[MLXSW_REG_HTGT_LEN];
1325 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1329 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
1330 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1334 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
1335 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1339 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1340 err = mlxsw_core_rx_listener_register(mlxsw_sx->core,
1341 &mlxsw_sx_rx_listener[i],
1344 goto err_rx_listener_register;
1346 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
1347 mlxsw_sx_rx_listener[i].trap_id);
1348 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1350 goto err_rx_trap_set;
1355 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1356 &mlxsw_sx_rx_listener[i],
1358 err_rx_listener_register:
1359 for (i--; i >= 0; i--) {
1360 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1361 mlxsw_sx_rx_listener[i].trap_id);
1362 mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1364 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1365 &mlxsw_sx_rx_listener[i],
1371 static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1373 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1376 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1377 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1378 mlxsw_sx_rx_listener[i].trap_id);
1379 mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1381 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1382 &mlxsw_sx_rx_listener[i],
1387 static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1389 char sfgc_pl[MLXSW_REG_SFGC_LEN];
1390 char sgcr_pl[MLXSW_REG_SGCR_LEN];
1394 /* Configure a flooding table, which includes only CPU port. */
1395 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1398 mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0,
1399 MLXSW_PORT_CPU_PORT, true);
1400 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1405 /* Flood different packet types using the flooding table. */
1406 mlxsw_reg_sfgc_pack(sfgc_pl,
1407 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1408 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1409 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1411 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1415 mlxsw_reg_sfgc_pack(sfgc_pl,
1416 MLXSW_REG_SFGC_TYPE_BROADCAST,
1417 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1418 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1420 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1424 mlxsw_reg_sfgc_pack(sfgc_pl,
1425 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1426 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1427 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1429 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1433 mlxsw_reg_sfgc_pack(sfgc_pl,
1434 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1435 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1436 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1438 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1442 mlxsw_reg_sfgc_pack(sfgc_pl,
1443 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1444 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1445 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1447 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1451 mlxsw_reg_sgcr_pack(sgcr_pl, true);
1452 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1455 static int mlxsw_sx_init(struct mlxsw_core *mlxsw_core,
1456 const struct mlxsw_bus_info *mlxsw_bus_info)
1458 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1461 mlxsw_sx->core = mlxsw_core;
1462 mlxsw_sx->bus_info = mlxsw_bus_info;
1464 err = mlxsw_sx_hw_id_get(mlxsw_sx);
1466 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1470 err = mlxsw_sx_ports_create(mlxsw_sx);
1472 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1476 err = mlxsw_sx_event_register(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1478 dev_err(mlxsw_sx->bus_info->dev, "Failed to register for PUDE events\n");
1479 goto err_event_register;
1482 err = mlxsw_sx_traps_init(mlxsw_sx);
1484 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps for RX\n");
1485 goto err_rx_listener_register;
1488 err = mlxsw_sx_flood_init(mlxsw_sx);
1490 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1491 goto err_flood_init;
1497 mlxsw_sx_traps_fini(mlxsw_sx);
1498 err_rx_listener_register:
1499 mlxsw_sx_event_unregister(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1501 mlxsw_sx_ports_remove(mlxsw_sx);
1505 static void mlxsw_sx_fini(struct mlxsw_core *mlxsw_core)
1507 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1509 mlxsw_sx_traps_fini(mlxsw_sx);
1510 mlxsw_sx_event_unregister(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1511 mlxsw_sx_ports_remove(mlxsw_sx);
1514 static struct mlxsw_config_profile mlxsw_sx_config_profile = {
1515 .used_max_vepa_channels = 1,
1516 .max_vepa_channels = 0,
1521 .used_max_system_port = 1,
1522 .max_system_port = 48000,
1523 .used_max_vlan_groups = 1,
1524 .max_vlan_groups = 127,
1525 .used_max_regions = 1,
1527 .used_flood_tables = 1,
1528 .max_flood_tables = 2,
1529 .max_vid_flood_tables = 1,
1530 .used_flood_mode = 1,
1532 .used_max_ib_mc = 1,
1539 .type = MLXSW_PORT_SWID_TYPE_ETH,
1542 .resource_query_enable = 0,
1545 static struct mlxsw_driver mlxsw_sx_driver = {
1546 .kind = MLXSW_DEVICE_KIND_SWITCHX2,
1547 .owner = THIS_MODULE,
1548 .priv_size = sizeof(struct mlxsw_sx),
1549 .init = mlxsw_sx_init,
1550 .fini = mlxsw_sx_fini,
1551 .txhdr_construct = mlxsw_sx_txhdr_construct,
1552 .txhdr_len = MLXSW_TXHDR_LEN,
1553 .profile = &mlxsw_sx_config_profile,
1556 static int __init mlxsw_sx_module_init(void)
1558 return mlxsw_core_driver_register(&mlxsw_sx_driver);
1561 static void __exit mlxsw_sx_module_exit(void)
1563 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1566 module_init(mlxsw_sx_module_init);
1567 module_exit(mlxsw_sx_module_exit);
1569 MODULE_LICENSE("Dual BSD/GPL");
1570 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1571 MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1572 MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SWITCHX2);