2 * Copyright (c) 2017, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <linux/etherdevice.h>
35 #include <linux/mlx5/driver.h>
37 #include "mlx5_core.h"
40 #include "fpga/core.h"
41 #include "fpga/conn.h"
43 static const char *const mlx5_fpga_error_strings[] = {
47 "Internal Link Error",
48 "Watchdog HW Failure",
51 "Temperature Critical",
54 static const char * const mlx5_fpga_qp_error_strings[] = {
56 "Retry Counter Expired",
59 static struct mlx5_fpga_device *mlx5_fpga_device_alloc(void)
61 struct mlx5_fpga_device *fdev = NULL;
63 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
67 spin_lock_init(&fdev->state_lock);
68 fdev->state = MLX5_FPGA_STATUS_NONE;
72 static const char *mlx5_fpga_image_name(enum mlx5_fpga_image image)
75 case MLX5_FPGA_IMAGE_USER:
77 case MLX5_FPGA_IMAGE_FACTORY:
84 static const char *mlx5_fpga_device_name(u32 device)
87 case MLX5_FPGA_DEVICE_KU040:
89 case MLX5_FPGA_DEVICE_KU060:
91 case MLX5_FPGA_DEVICE_KU060_2:
93 case MLX5_FPGA_DEVICE_UNKNOWN:
99 static int mlx5_fpga_device_load_check(struct mlx5_fpga_device *fdev)
101 struct mlx5_fpga_query query;
104 err = mlx5_fpga_query(fdev->mdev, &query);
106 mlx5_fpga_err(fdev, "Failed to query status: %d\n", err);
110 fdev->last_admin_image = query.admin_image;
111 fdev->last_oper_image = query.oper_image;
113 mlx5_fpga_dbg(fdev, "Status %u; Admin image %u; Oper image %u\n",
114 query.status, query.admin_image, query.oper_image);
116 if (query.status != MLX5_FPGA_STATUS_SUCCESS) {
117 mlx5_fpga_err(fdev, "%s image failed to load; status %u\n",
118 mlx5_fpga_image_name(fdev->last_oper_image),
126 static int mlx5_fpga_device_brb(struct mlx5_fpga_device *fdev)
129 struct mlx5_core_dev *mdev = fdev->mdev;
131 err = mlx5_fpga_ctrl_op(mdev, MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON);
133 mlx5_fpga_err(fdev, "Failed to set bypass on: %d\n", err);
136 err = mlx5_fpga_ctrl_op(mdev, MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX);
138 mlx5_fpga_err(fdev, "Failed to reset SBU: %d\n", err);
141 err = mlx5_fpga_ctrl_op(mdev, MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF);
143 mlx5_fpga_err(fdev, "Failed to set bypass off: %d\n", err);
149 static int mlx5_fpga_event(struct mlx5_fpga_device *, unsigned long, void *);
151 static int fpga_err_event(struct notifier_block *nb, unsigned long event, void *eqe)
153 struct mlx5_fpga_device *fdev = mlx5_nb_cof(nb, struct mlx5_fpga_device, fpga_err_nb);
155 return mlx5_fpga_event(fdev, event, eqe);
158 static int fpga_qp_err_event(struct notifier_block *nb, unsigned long event, void *eqe)
160 struct mlx5_fpga_device *fdev = mlx5_nb_cof(nb, struct mlx5_fpga_device, fpga_qp_err_nb);
162 return mlx5_fpga_event(fdev, event, eqe);
165 int mlx5_fpga_device_start(struct mlx5_core_dev *mdev)
167 struct mlx5_fpga_device *fdev = mdev->fpga;
168 unsigned int max_num_qps;
176 err = mlx5_fpga_device_load_check(fdev);
180 err = mlx5_fpga_caps(fdev->mdev);
184 fpga_device_id = MLX5_CAP_FPGA(fdev->mdev, fpga_device);
185 mlx5_fpga_info(fdev, "%s:%u; %s image, version %u; SBU %06x:%04x version %d\n",
186 mlx5_fpga_device_name(fpga_device_id),
188 mlx5_fpga_image_name(fdev->last_oper_image),
189 MLX5_CAP_FPGA(fdev->mdev, image_version),
190 MLX5_CAP_FPGA(fdev->mdev, ieee_vendor_id),
191 MLX5_CAP_FPGA(fdev->mdev, sandbox_product_id),
192 MLX5_CAP_FPGA(fdev->mdev, sandbox_product_version));
194 max_num_qps = MLX5_CAP_FPGA(mdev, shell_caps.max_num_qps);
196 mlx5_fpga_err(fdev, "FPGA reports 0 QPs in SHELL_CAPS\n");
201 err = mlx5_core_reserve_gids(mdev, max_num_qps);
205 MLX5_NB_INIT(&fdev->fpga_err_nb, fpga_err_event, FPGA_ERROR);
206 MLX5_NB_INIT(&fdev->fpga_qp_err_nb, fpga_qp_err_event, FPGA_QP_ERROR);
207 mlx5_eq_notifier_register(fdev->mdev, &fdev->fpga_err_nb);
208 mlx5_eq_notifier_register(fdev->mdev, &fdev->fpga_qp_err_nb);
210 err = mlx5_fpga_conn_device_init(fdev);
214 if (fdev->last_oper_image == MLX5_FPGA_IMAGE_USER) {
215 err = mlx5_fpga_device_brb(fdev);
223 mlx5_fpga_conn_device_cleanup(fdev);
226 mlx5_eq_notifier_unregister(fdev->mdev, &fdev->fpga_err_nb);
227 mlx5_eq_notifier_unregister(fdev->mdev, &fdev->fpga_qp_err_nb);
228 mlx5_core_unreserve_gids(mdev, max_num_qps);
230 spin_lock_irqsave(&fdev->state_lock, flags);
231 fdev->state = err ? MLX5_FPGA_STATUS_FAILURE : MLX5_FPGA_STATUS_SUCCESS;
232 spin_unlock_irqrestore(&fdev->state_lock, flags);
236 int mlx5_fpga_init(struct mlx5_core_dev *mdev)
238 struct mlx5_fpga_device *fdev = NULL;
240 if (!MLX5_CAP_GEN(mdev, fpga)) {
241 mlx5_core_dbg(mdev, "FPGA capability not present\n");
245 mlx5_core_dbg(mdev, "Initializing FPGA\n");
247 fdev = mlx5_fpga_device_alloc();
257 void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev)
259 struct mlx5_fpga_device *fdev = mdev->fpga;
260 unsigned int max_num_qps;
267 spin_lock_irqsave(&fdev->state_lock, flags);
268 if (fdev->state != MLX5_FPGA_STATUS_SUCCESS) {
269 spin_unlock_irqrestore(&fdev->state_lock, flags);
272 fdev->state = MLX5_FPGA_STATUS_NONE;
273 spin_unlock_irqrestore(&fdev->state_lock, flags);
275 if (fdev->last_oper_image == MLX5_FPGA_IMAGE_USER) {
276 err = mlx5_fpga_ctrl_op(mdev, MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON);
278 mlx5_fpga_err(fdev, "Failed to re-set SBU bypass on: %d\n",
282 mlx5_fpga_conn_device_cleanup(fdev);
283 mlx5_eq_notifier_unregister(fdev->mdev, &fdev->fpga_err_nb);
284 mlx5_eq_notifier_unregister(fdev->mdev, &fdev->fpga_qp_err_nb);
286 max_num_qps = MLX5_CAP_FPGA(mdev, shell_caps.max_num_qps);
287 mlx5_core_unreserve_gids(mdev, max_num_qps);
290 void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev)
292 struct mlx5_fpga_device *fdev = mdev->fpga;
294 mlx5_fpga_device_stop(mdev);
299 static const char *mlx5_fpga_syndrome_to_string(u8 syndrome)
301 if (syndrome < ARRAY_SIZE(mlx5_fpga_error_strings))
302 return mlx5_fpga_error_strings[syndrome];
306 static const char *mlx5_fpga_qp_syndrome_to_string(u8 syndrome)
308 if (syndrome < ARRAY_SIZE(mlx5_fpga_qp_error_strings))
309 return mlx5_fpga_qp_error_strings[syndrome];
313 static int mlx5_fpga_event(struct mlx5_fpga_device *fdev,
314 unsigned long event, void *eqe)
316 void *data = ((struct mlx5_eqe *)eqe)->data.raw;
317 const char *event_name;
318 bool teardown = false;
323 case MLX5_EVENT_TYPE_FPGA_ERROR:
324 syndrome = MLX5_GET(fpga_error_event, data, syndrome);
325 event_name = mlx5_fpga_syndrome_to_string(syndrome);
327 case MLX5_EVENT_TYPE_FPGA_QP_ERROR:
328 syndrome = MLX5_GET(fpga_qp_error_event, data, syndrome);
329 event_name = mlx5_fpga_qp_syndrome_to_string(syndrome);
335 spin_lock_irqsave(&fdev->state_lock, flags);
336 switch (fdev->state) {
337 case MLX5_FPGA_STATUS_SUCCESS:
338 mlx5_fpga_warn(fdev, "Error %u: %s\n", syndrome, event_name);
342 mlx5_fpga_warn_ratelimited(fdev, "Unexpected error event %u: %s\n",
343 syndrome, event_name);
345 spin_unlock_irqrestore(&fdev->state_lock, flags);
346 /* We tear-down the card's interfaces and functionality because
347 * the FPGA bump-on-the-wire is misbehaving and we lose ability
348 * to communicate with the network. User may still be able to
349 * recover by re-programming or debugging the FPGA
352 mlx5_trigger_health_work(fdev->mdev);