2 * Copyright (c) 2018, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
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6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/bpf_trace.h>
34 #include <net/xdp_sock.h>
36 #include "en/params.h"
38 int mlx5e_xdp_max_mtu(struct mlx5e_params *params, struct mlx5e_xsk_param *xsk)
40 int hr = mlx5e_get_linear_rq_headroom(params, xsk);
42 /* Let S := SKB_DATA_ALIGN(sizeof(struct skb_shared_info)).
43 * The condition checked in mlx5e_rx_is_linear_skb is:
44 * SKB_DATA_ALIGN(sw_mtu + hard_mtu + hr) + S <= PAGE_SIZE (1)
45 * (Note that hw_mtu == sw_mtu + hard_mtu.)
46 * What is returned from this function is:
47 * max_mtu = PAGE_SIZE - S - hr - hard_mtu (2)
48 * After assigning sw_mtu := max_mtu, the left side of (1) turns to
49 * SKB_DATA_ALIGN(PAGE_SIZE - S) + S, which is equal to PAGE_SIZE,
50 * because both PAGE_SIZE and S are already aligned. Any number greater
51 * than max_mtu would make the left side of (1) greater than PAGE_SIZE,
52 * so max_mtu is the maximum MTU allowed.
55 return MLX5E_HW2SW_MTU(params, SKB_MAX_HEAD(hr));
59 mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq,
60 struct mlx5e_dma_info *di, struct xdp_buff *xdp)
62 struct mlx5e_xdp_xmit_data xdptxd;
63 struct mlx5e_xdp_info xdpi;
64 struct xdp_frame *xdpf;
67 xdpf = convert_to_xdp_frame(xdp);
71 xdptxd.data = xdpf->data;
72 xdptxd.len = xdpf->len;
74 if (xdp->rxq->mem.type == MEM_TYPE_ZERO_COPY) {
75 /* The xdp_buff was in the UMEM and was copied into a newly
76 * allocated page. The UMEM page was returned via the ZCA, and
77 * this new page has to be mapped at this point and has to be
78 * unmapped and returned via xdp_return_frame on completion.
81 /* Prevent double recycling of the UMEM page. Even in case this
82 * function returns false, the xdp_buff shouldn't be recycled,
83 * as it was already done in xdp_convert_zc_to_xdp_frame.
85 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
87 xdpi.mode = MLX5E_XDP_XMIT_MODE_FRAME;
89 dma_addr = dma_map_single(sq->pdev, xdptxd.data, xdptxd.len,
91 if (dma_mapping_error(sq->pdev, dma_addr)) {
92 xdp_return_frame(xdpf);
96 xdptxd.dma_addr = dma_addr;
97 xdpi.frame.xdpf = xdpf;
98 xdpi.frame.dma_addr = dma_addr;
100 /* Driver assumes that convert_to_xdp_frame returns an xdp_frame
101 * that points to the same memory region as the original
102 * xdp_buff. It allows to map the memory only once and to use
103 * the DMA_BIDIRECTIONAL mode.
106 xdpi.mode = MLX5E_XDP_XMIT_MODE_PAGE;
108 dma_addr = di->addr + (xdpf->data - (void *)xdpf);
109 dma_sync_single_for_device(sq->pdev, dma_addr, xdptxd.len,
112 xdptxd.dma_addr = dma_addr;
117 return sq->xmit_xdp_frame(sq, &xdptxd, &xdpi, 0);
120 /* returns true if packet was consumed by xdp */
121 bool mlx5e_xdp_handle(struct mlx5e_rq *rq, struct mlx5e_dma_info *di,
122 void *va, u16 *rx_headroom, u32 *len, bool xsk)
124 struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
132 xdp.data = va + *rx_headroom;
133 xdp_set_data_meta_invalid(&xdp);
134 xdp.data_end = xdp.data + *len;
135 xdp.data_hard_start = va;
137 xdp.handle = di->xsk.handle;
138 xdp.rxq = &rq->xdp_rxq;
140 act = bpf_prog_run_xdp(prog, &xdp);
142 xdp.handle += xdp.data - xdp.data_hard_start;
145 *rx_headroom = xdp.data - xdp.data_hard_start;
146 *len = xdp.data_end - xdp.data;
149 if (unlikely(!mlx5e_xmit_xdp_buff(rq->xdpsq, rq, di, &xdp)))
151 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
154 /* When XDP enabled then page-refcnt==1 here */
155 err = xdp_do_redirect(rq->netdev, &xdp, prog);
158 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags);
159 __set_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags);
161 mlx5e_page_dma_unmap(rq, di);
162 rq->stats->xdp_redirect++;
165 bpf_warn_invalid_xdp_action(act);
169 trace_xdp_exception(rq->netdev, prog, act);
172 rq->stats->xdp_drop++;
177 static void mlx5e_xdp_mpwqe_session_start(struct mlx5e_xdpsq *sq)
179 struct mlx5e_xdp_mpwqe *session = &sq->mpwqe;
180 struct mlx5e_xdpsq_stats *stats = sq->stats;
181 struct mlx5_wq_cyc *wq = &sq->wq;
185 mlx5e_xdpsq_fetch_wqe(sq, &session->wqe);
187 prefetchw(session->wqe->data);
188 session->ds_count = MLX5E_XDP_TX_EMPTY_DS_COUNT;
189 session->pkt_count = 0;
190 session->complete = 0;
192 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
194 /* The mult of MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS
195 * (16 * 4 == 64) does not fit in the 6-bit DS field of Ctrl Segment.
196 * We use a bound lower that MLX5_SEND_WQE_MAX_WQEBBS to let a
197 * full-session WQE be cache-aligned.
199 #if L1_CACHE_BYTES < 128
200 #define MLX5E_XDP_MPW_MAX_WQEBBS (MLX5_SEND_WQE_MAX_WQEBBS - 1)
202 #define MLX5E_XDP_MPW_MAX_WQEBBS (MLX5_SEND_WQE_MAX_WQEBBS - 2)
205 wqebbs = min_t(u16, mlx5_wq_cyc_get_contig_wqebbs(wq, pi),
206 MLX5E_XDP_MPW_MAX_WQEBBS);
208 session->max_ds_count = MLX5_SEND_WQEBB_NUM_DS * wqebbs;
210 mlx5e_xdp_update_inline_state(sq);
215 void mlx5e_xdp_mpwqe_complete(struct mlx5e_xdpsq *sq)
217 struct mlx5_wq_cyc *wq = &sq->wq;
218 struct mlx5e_xdp_mpwqe *session = &sq->mpwqe;
219 struct mlx5_wqe_ctrl_seg *cseg = &session->wqe->ctrl;
220 u16 ds_count = session->ds_count;
221 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
222 struct mlx5e_xdp_wqe_info *wi = &sq->db.wqe_info[pi];
224 cseg->opmod_idx_opcode =
225 cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_ENHANCED_MPSW);
226 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_count);
228 wi->num_wqebbs = DIV_ROUND_UP(ds_count, MLX5_SEND_WQEBB_NUM_DS);
229 wi->num_pkts = session->pkt_count;
231 sq->pc += wi->num_wqebbs;
233 sq->doorbell_cseg = cseg;
235 session->wqe = NULL; /* Close session */
239 MLX5E_XDP_CHECK_OK = 1,
240 MLX5E_XDP_CHECK_START_MPWQE = 2,
243 static int mlx5e_xmit_xdp_frame_check_mpwqe(struct mlx5e_xdpsq *sq)
245 if (unlikely(!sq->mpwqe.wqe)) {
246 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc,
247 MLX5_SEND_WQE_MAX_WQEBBS))) {
248 /* SQ is full, ring doorbell */
249 mlx5e_xmit_xdp_doorbell(sq);
254 return MLX5E_XDP_CHECK_START_MPWQE;
257 return MLX5E_XDP_CHECK_OK;
260 static bool mlx5e_xmit_xdp_frame_mpwqe(struct mlx5e_xdpsq *sq,
261 struct mlx5e_xdp_xmit_data *xdptxd,
262 struct mlx5e_xdp_info *xdpi,
265 struct mlx5e_xdp_mpwqe *session = &sq->mpwqe;
266 struct mlx5e_xdpsq_stats *stats = sq->stats;
268 if (unlikely(xdptxd->len > sq->hw_mtu)) {
274 check_result = mlx5e_xmit_xdp_frame_check_mpwqe(sq);
275 if (unlikely(check_result < 0))
278 if (check_result == MLX5E_XDP_CHECK_START_MPWQE) {
279 /* Start the session when nothing can fail, so it's guaranteed
280 * that if there is an active session, it has at least one dseg,
281 * and it's safe to complete it at any time.
283 mlx5e_xdp_mpwqe_session_start(sq);
286 mlx5e_xdp_mpwqe_add_dseg(sq, xdptxd, stats);
288 if (unlikely(session->complete ||
289 session->ds_count == session->max_ds_count))
290 mlx5e_xdp_mpwqe_complete(sq);
292 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo, xdpi);
297 static int mlx5e_xmit_xdp_frame_check(struct mlx5e_xdpsq *sq)
299 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1))) {
300 /* SQ is full, ring doorbell */
301 mlx5e_xmit_xdp_doorbell(sq);
306 return MLX5E_XDP_CHECK_OK;
309 static bool mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq,
310 struct mlx5e_xdp_xmit_data *xdptxd,
311 struct mlx5e_xdp_info *xdpi,
314 struct mlx5_wq_cyc *wq = &sq->wq;
315 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
316 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
318 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
319 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
320 struct mlx5_wqe_data_seg *dseg = wqe->data;
322 dma_addr_t dma_addr = xdptxd->dma_addr;
323 u32 dma_len = xdptxd->len;
325 struct mlx5e_xdpsq_stats *stats = sq->stats;
329 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || sq->hw_mtu < dma_len)) {
335 check_result = mlx5e_xmit_xdp_frame_check(sq);
336 if (unlikely(check_result < 0))
341 /* copy the inline part if required */
342 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
343 memcpy(eseg->inline_hdr.start, xdptxd->data, MLX5E_XDP_MIN_INLINE);
344 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
345 dma_len -= MLX5E_XDP_MIN_INLINE;
346 dma_addr += MLX5E_XDP_MIN_INLINE;
350 /* write the dma part */
351 dseg->addr = cpu_to_be64(dma_addr);
352 dseg->byte_count = cpu_to_be32(dma_len);
354 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
358 sq->doorbell_cseg = cseg;
360 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo, xdpi);
365 static void mlx5e_free_xdpsq_desc(struct mlx5e_xdpsq *sq,
366 struct mlx5e_xdp_wqe_info *wi,
370 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
373 for (i = 0; i < wi->num_pkts; i++) {
374 struct mlx5e_xdp_info xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
377 case MLX5E_XDP_XMIT_MODE_FRAME:
378 /* XDP_TX from the XSK RQ and XDP_REDIRECT */
379 dma_unmap_single(sq->pdev, xdpi.frame.dma_addr,
380 xdpi.frame.xdpf->len, DMA_TO_DEVICE);
381 xdp_return_frame(xdpi.frame.xdpf);
383 case MLX5E_XDP_XMIT_MODE_PAGE:
384 /* XDP_TX from the regular RQ */
385 mlx5e_page_release_dynamic(xdpi.page.rq, &xdpi.page.di, recycle);
387 case MLX5E_XDP_XMIT_MODE_XSK:
397 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
399 struct mlx5e_xdpsq *sq;
400 struct mlx5_cqe64 *cqe;
405 sq = container_of(cq, struct mlx5e_xdpsq, cq);
407 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
410 cqe = mlx5_cqwq_get_cqe(&cq->wq);
414 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
415 * otherwise a cq overrun may occur
424 mlx5_cqwq_pop(&cq->wq);
426 wqe_counter = be16_to_cpu(cqe->wqe_counter);
428 if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ))
429 netdev_WARN_ONCE(sq->channel->netdev,
430 "Bad OP in XDPSQ CQE: 0x%x\n",
431 get_cqe_opcode(cqe));
434 struct mlx5e_xdp_wqe_info *wi;
437 last_wqe = (sqcc == wqe_counter);
438 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
439 wi = &sq->db.wqe_info[ci];
441 sqcc += wi->num_wqebbs;
443 mlx5e_free_xdpsq_desc(sq, wi, &xsk_frames, true);
445 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
448 xsk_umem_complete_tx(sq->umem, xsk_frames);
450 sq->stats->cqes += i;
452 mlx5_cqwq_update_db_record(&cq->wq);
454 /* ensure cq space is freed before enabling more cqes */
458 return (i == MLX5E_TX_CQ_POLL_BUDGET);
461 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
465 while (sq->cc != sq->pc) {
466 struct mlx5e_xdp_wqe_info *wi;
469 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc);
470 wi = &sq->db.wqe_info[ci];
472 sq->cc += wi->num_wqebbs;
474 mlx5e_free_xdpsq_desc(sq, wi, &xsk_frames, false);
478 xsk_umem_complete_tx(sq->umem, xsk_frames);
481 int mlx5e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
484 struct mlx5e_priv *priv = netdev_priv(dev);
485 struct mlx5e_xdpsq *sq;
490 /* this flag is sufficient, no need to test internal sq state */
491 if (unlikely(!mlx5e_xdp_tx_is_enabled(priv)))
494 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
497 sq_num = smp_processor_id();
499 if (unlikely(sq_num >= priv->channels.num))
502 sq = &priv->channels.c[sq_num]->xdpsq;
504 for (i = 0; i < n; i++) {
505 struct xdp_frame *xdpf = frames[i];
506 struct mlx5e_xdp_xmit_data xdptxd;
507 struct mlx5e_xdp_info xdpi;
509 xdptxd.data = xdpf->data;
510 xdptxd.len = xdpf->len;
511 xdptxd.dma_addr = dma_map_single(sq->pdev, xdptxd.data,
512 xdptxd.len, DMA_TO_DEVICE);
514 if (unlikely(dma_mapping_error(sq->pdev, xdptxd.dma_addr))) {
515 xdp_return_frame_rx_napi(xdpf);
520 xdpi.mode = MLX5E_XDP_XMIT_MODE_FRAME;
521 xdpi.frame.xdpf = xdpf;
522 xdpi.frame.dma_addr = xdptxd.dma_addr;
524 if (unlikely(!sq->xmit_xdp_frame(sq, &xdptxd, &xdpi, 0))) {
525 dma_unmap_single(sq->pdev, xdptxd.dma_addr,
526 xdptxd.len, DMA_TO_DEVICE);
527 xdp_return_frame_rx_napi(xdpf);
532 if (flags & XDP_XMIT_FLUSH) {
534 mlx5e_xdp_mpwqe_complete(sq);
535 mlx5e_xmit_xdp_doorbell(sq);
541 void mlx5e_xdp_rx_poll_complete(struct mlx5e_rq *rq)
543 struct mlx5e_xdpsq *xdpsq = rq->xdpsq;
545 if (xdpsq->mpwqe.wqe)
546 mlx5e_xdp_mpwqe_complete(xdpsq);
548 mlx5e_xmit_xdp_doorbell(xdpsq);
550 if (test_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags)) {
552 __clear_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags);
556 void mlx5e_set_xmit_fp(struct mlx5e_xdpsq *sq, bool is_mpw)
558 sq->xmit_xdp_frame_check = is_mpw ?
559 mlx5e_xmit_xdp_frame_check_mpwqe : mlx5e_xmit_xdp_frame_check;
560 sq->xmit_xdp_frame = is_mpw ?
561 mlx5e_xmit_xdp_frame_mpwqe : mlx5e_xmit_xdp_frame;