drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/mlx5/eq.h>
  44 #include <linux/debugfs.h>
  45
  46 #include "mlx5_core.h"
  47 #include "lib/eq.h"
  48
  49 enum {
  50         CMD_IF_REV = 5,
  51 };
  52
  53 enum {
  54         CMD_MODE_POLLING,
  55         CMD_MODE_EVENTS
  56 };
  57
  58 enum {
  59         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  60         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  61         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  62         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  63         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  64         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  65         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  66         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  67         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  68         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  69         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  70 };
  71
  72 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  73                                            struct mlx5_cmd_msg *in,
  74                                            struct mlx5_cmd_msg *out,
  75                                            void *uout, int uout_size,
  76                                            mlx5_cmd_cbk_t cbk,
  77                                            void *context, int page_queue)
  78 {
  79         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  80         struct mlx5_cmd_work_ent *ent;
  81
  82         ent = kzalloc(sizeof(*ent), alloc_flags);
  83         if (!ent)
  84                 return ERR_PTR(-ENOMEM);
  85
  86         ent->in         = in;
  87         ent->out        = out;
  88         ent->uout       = uout;
  89         ent->uout_size  = uout_size;
  90         ent->callback   = cbk;
  91         ent->context    = context;
  92         ent->cmd        = cmd;
  93         ent->page_queue = page_queue;
  94
  95         return ent;
  96 }
  97
  98 static u8 alloc_token(struct mlx5_cmd *cmd)
  99 {
 100         u8 token;
 101
 102         spin_lock(&cmd->token_lock);
 103         cmd->token++;
 104         if (cmd->token == 0)
 105                 cmd->token++;
 106         token = cmd->token;
 107         spin_unlock(&cmd->token_lock);
 108
 109         return token;
 110 }
 111
 112 static int alloc_ent(struct mlx5_cmd *cmd)
 113 {
 114         unsigned long flags;
 115         int ret;
 116
 117         spin_lock_irqsave(&cmd->alloc_lock, flags);
 118         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 119         if (ret < cmd->max_reg_cmds)
 120                 clear_bit(ret, &cmd->bitmask);
 121         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 122
 123         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 124 }
 125
 126 static void free_ent(struct mlx5_cmd *cmd, int idx)
 127 {
 128         unsigned long flags;
 129
 130         spin_lock_irqsave(&cmd->alloc_lock, flags);
 131         set_bit(idx, &cmd->bitmask);
 132         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 133 }
 134
 135 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 136 {
 137         return cmd->cmd_buf + (idx << cmd->log_stride);
 138 }
 139
 140 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
 141 {
 142         int size = msg->len;
 143         int blen = size - min_t(int, sizeof(msg->first.data), size);
 144
 145         return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
 146 }
 147
 148 static u8 xor8_buf(void *buf, size_t offset, int len)
 149 {
 150         u8 *ptr = buf;
 151         u8 sum = 0;
 152         int i;
 153         int end = len + offset;
 154
 155         for (i = offset; i < end; i++)
 156                 sum ^= ptr[i];
 157
 158         return sum;
 159 }
 160
 161 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 162 {
 163         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 164         int xor_len = sizeof(*block) - sizeof(block->data) - 1;
 165
 166         if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
 167                 return -EINVAL;
 168
 169         if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
 170                 return -EINVAL;
 171
 172         return 0;
 173 }
 174
 175 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
 176 {
 177         int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
 178         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 179
 180         block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
 181         block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
 182 }
 183
 184 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
 185 {
 186         struct mlx5_cmd_mailbox *next = msg->next;
 187         int n = mlx5_calc_cmd_blocks(msg);
 188         int i = 0;
 189
 190         for (i = 0; i < n && next; i++)  {
 191                 calc_block_sig(next->buf);
 192                 next = next->next;
 193         }
 194 }
 195
 196 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 197 {
 198         ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
 199         if (csum) {
 200                 calc_chain_sig(ent->in);
 201                 calc_chain_sig(ent->out);
 202         }
 203 }
 204
 205 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 206 {
 207         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 208         u8 own;
 209
 210         do {
 211                 own = READ_ONCE(ent->lay->status_own);
 212                 if (!(own & CMD_OWNER_HW)) {
 213                         ent->ret = 0;
 214                         return;
 215                 }
 216                 cond_resched();
 217         } while (time_before(jiffies, poll_end));
 218
 219         ent->ret = -ETIMEDOUT;
 220 }
 221
 222 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 223 {
 224         kfree(ent);
 225 }
 226
 227 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 228 {
 229         struct mlx5_cmd_mailbox *next = ent->out->next;
 230         int n = mlx5_calc_cmd_blocks(ent->out);
 231         int err;
 232         u8 sig;
 233         int i = 0;
 234
 235         sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
 236         if (sig != 0xff)
 237                 return -EINVAL;
 238
 239         for (i = 0; i < n && next; i++) {
 240                 err = verify_block_sig(next->buf);
 241                 if (err)
 242                         return err;
 243
 244                 next = next->next;
 245         }
 246
 247         return 0;
 248 }
 249
 250 static void dump_buf(void *buf, int size, int data_only, int offset)
 251 {
 252         __be32 *p = buf;
 253         int i;
 254
 255         for (i = 0; i < size; i += 16) {
 256                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 257                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 258                          be32_to_cpu(p[3]));
 259                 p += 4;
 260                 offset += 16;
 261         }
 262         if (!data_only)
 263                 pr_debug("\n");
 264 }
 265
 266 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 267                                        u32 *synd, u8 *status)
 268 {
 269         *synd = 0;
 270         *status = 0;
 271
 272         switch (op) {
 273         case MLX5_CMD_OP_TEARDOWN_HCA:
 274         case MLX5_CMD_OP_DISABLE_HCA:
 275         case MLX5_CMD_OP_MANAGE_PAGES:
 276         case MLX5_CMD_OP_DESTROY_MKEY:
 277         case MLX5_CMD_OP_DESTROY_EQ:
 278         case MLX5_CMD_OP_DESTROY_CQ:
 279         case MLX5_CMD_OP_DESTROY_QP:
 280         case MLX5_CMD_OP_DESTROY_PSV:
 281         case MLX5_CMD_OP_DESTROY_SRQ:
 282         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 283         case MLX5_CMD_OP_DESTROY_XRQ:
 284         case MLX5_CMD_OP_DESTROY_DCT:
 285         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 286         case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
 287         case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
 288         case MLX5_CMD_OP_DEALLOC_PD:
 289         case MLX5_CMD_OP_DEALLOC_UAR:
 290         case MLX5_CMD_OP_DETACH_FROM_MCG:
 291         case MLX5_CMD_OP_DEALLOC_XRCD:
 292         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 293         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 294         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 295         case MLX5_CMD_OP_DESTROY_LAG:
 296         case MLX5_CMD_OP_DESTROY_VPORT_LAG:
 297         case MLX5_CMD_OP_DESTROY_TIR:
 298         case MLX5_CMD_OP_DESTROY_SQ:
 299         case MLX5_CMD_OP_DESTROY_RQ:
 300         case MLX5_CMD_OP_DESTROY_RMP:
 301         case MLX5_CMD_OP_DESTROY_TIS:
 302         case MLX5_CMD_OP_DESTROY_RQT:
 303         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 304         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 305         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 306         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
 307         case MLX5_CMD_OP_2ERR_QP:
 308         case MLX5_CMD_OP_2RST_QP:
 309         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 310         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
 311         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 312         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
 313         case MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT:
 314         case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
 315         case MLX5_CMD_OP_FPGA_DESTROY_QP:
 316         case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
 317         case MLX5_CMD_OP_DEALLOC_MEMIC:
 318         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 319         case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS:
 320                 return MLX5_CMD_STAT_OK;
 321
 322         case MLX5_CMD_OP_QUERY_HCA_CAP:
 323         case MLX5_CMD_OP_QUERY_ADAPTER:
 324         case MLX5_CMD_OP_INIT_HCA:
 325         case MLX5_CMD_OP_ENABLE_HCA:
 326         case MLX5_CMD_OP_QUERY_PAGES:
 327         case MLX5_CMD_OP_SET_HCA_CAP:
 328         case MLX5_CMD_OP_QUERY_ISSI:
 329         case MLX5_CMD_OP_SET_ISSI:
 330         case MLX5_CMD_OP_CREATE_MKEY:
 331         case MLX5_CMD_OP_QUERY_MKEY:
 332         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 333         case MLX5_CMD_OP_CREATE_EQ:
 334         case MLX5_CMD_OP_QUERY_EQ:
 335         case MLX5_CMD_OP_GEN_EQE:
 336         case MLX5_CMD_OP_CREATE_CQ:
 337         case MLX5_CMD_OP_QUERY_CQ:
 338         case MLX5_CMD_OP_MODIFY_CQ:
 339         case MLX5_CMD_OP_CREATE_QP:
 340         case MLX5_CMD_OP_RST2INIT_QP:
 341         case MLX5_CMD_OP_INIT2RTR_QP:
 342         case MLX5_CMD_OP_RTR2RTS_QP:
 343         case MLX5_CMD_OP_RTS2RTS_QP:
 344         case MLX5_CMD_OP_SQERR2RTS_QP:
 345         case MLX5_CMD_OP_QUERY_QP:
 346         case MLX5_CMD_OP_SQD_RTS_QP:
 347         case MLX5_CMD_OP_INIT2INIT_QP:
 348         case MLX5_CMD_OP_CREATE_PSV:
 349         case MLX5_CMD_OP_CREATE_SRQ:
 350         case MLX5_CMD_OP_QUERY_SRQ:
 351         case MLX5_CMD_OP_ARM_RQ:
 352         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 353         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 354         case MLX5_CMD_OP_ARM_XRC_SRQ:
 355         case MLX5_CMD_OP_CREATE_XRQ:
 356         case MLX5_CMD_OP_QUERY_XRQ:
 357         case MLX5_CMD_OP_ARM_XRQ:
 358         case MLX5_CMD_OP_CREATE_DCT:
 359         case MLX5_CMD_OP_DRAIN_DCT:
 360         case MLX5_CMD_OP_QUERY_DCT:
 361         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 362         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 363         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 364         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 365         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 366         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 367         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 368         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 369         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 370         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 371         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 372         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 373         case MLX5_CMD_OP_QUERY_VNIC_ENV:
 374         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 375         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 376         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 377         case MLX5_CMD_OP_SET_MONITOR_COUNTER:
 378         case MLX5_CMD_OP_ARM_MONITOR_COUNTER:
 379         case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
 380         case MLX5_CMD_OP_QUERY_RATE_LIMIT:
 381         case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
 382         case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
 383         case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
 384         case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
 385         case MLX5_CMD_OP_ALLOC_PD:
 386         case MLX5_CMD_OP_ALLOC_UAR:
 387         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 388         case MLX5_CMD_OP_ACCESS_REG:
 389         case MLX5_CMD_OP_ATTACH_TO_MCG:
 390         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 391         case MLX5_CMD_OP_MAD_IFC:
 392         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 393         case MLX5_CMD_OP_SET_MAD_DEMUX:
 394         case MLX5_CMD_OP_NOP:
 395         case MLX5_CMD_OP_ALLOC_XRCD:
 396         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 397         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 398         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 399         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 400         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 401         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 402         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 403         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 404         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 405         case MLX5_CMD_OP_CREATE_LAG:
 406         case MLX5_CMD_OP_MODIFY_LAG:
 407         case MLX5_CMD_OP_QUERY_LAG:
 408         case MLX5_CMD_OP_CREATE_VPORT_LAG:
 409         case MLX5_CMD_OP_CREATE_TIR:
 410         case MLX5_CMD_OP_MODIFY_TIR:
 411         case MLX5_CMD_OP_QUERY_TIR:
 412         case MLX5_CMD_OP_CREATE_SQ:
 413         case MLX5_CMD_OP_MODIFY_SQ:
 414         case MLX5_CMD_OP_QUERY_SQ:
 415         case MLX5_CMD_OP_CREATE_RQ:
 416         case MLX5_CMD_OP_MODIFY_RQ:
 417         case MLX5_CMD_OP_QUERY_RQ:
 418         case MLX5_CMD_OP_CREATE_RMP:
 419         case MLX5_CMD_OP_MODIFY_RMP:
 420         case MLX5_CMD_OP_QUERY_RMP:
 421         case MLX5_CMD_OP_CREATE_TIS:
 422         case MLX5_CMD_OP_MODIFY_TIS:
 423         case MLX5_CMD_OP_QUERY_TIS:
 424         case MLX5_CMD_OP_CREATE_RQT:
 425         case MLX5_CMD_OP_MODIFY_RQT:
 426         case MLX5_CMD_OP_QUERY_RQT:
 427
 428         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 429         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 430         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 431         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 432         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 433         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
 434         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
 435         case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
 436         case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
 437         case MLX5_CMD_OP_FPGA_CREATE_QP:
 438         case MLX5_CMD_OP_FPGA_MODIFY_QP:
 439         case MLX5_CMD_OP_FPGA_QUERY_QP:
 440         case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
 441         case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
 442         case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
 443         case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
 444         case MLX5_CMD_OP_CREATE_UCTX:
 445         case MLX5_CMD_OP_DESTROY_UCTX:
 446         case MLX5_CMD_OP_CREATE_UMEM:
 447         case MLX5_CMD_OP_DESTROY_UMEM:
 448         case MLX5_CMD_OP_ALLOC_MEMIC:
 449         case MLX5_CMD_OP_MODIFY_XRQ:
 450         case MLX5_CMD_OP_RELEASE_XRQ_ERROR:
 451                 *status = MLX5_DRIVER_STATUS_ABORTED;
 452                 *synd = MLX5_DRIVER_SYND;
 453                 return -EIO;
 454         default:
 455                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 456                 return -EINVAL;
 457         }
 458 }
 459
 460 const char *mlx5_command_str(int command)
 461 {
 462 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
 463
 464         switch (command) {
 465         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
 466         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
 467         MLX5_COMMAND_STR_CASE(INIT_HCA);
 468         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
 469         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
 470         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
 471         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
 472         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
 473         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
 474         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
 475         MLX5_COMMAND_STR_CASE(SET_ISSI);
 476         MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
 477         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
 478         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
 479         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
 480         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
 481         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
 482         MLX5_COMMAND_STR_CASE(CREATE_EQ);
 483         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
 484         MLX5_COMMAND_STR_CASE(QUERY_EQ);
 485         MLX5_COMMAND_STR_CASE(GEN_EQE);
 486         MLX5_COMMAND_STR_CASE(CREATE_CQ);
 487         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
 488         MLX5_COMMAND_STR_CASE(QUERY_CQ);
 489         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
 490         MLX5_COMMAND_STR_CASE(CREATE_QP);
 491         MLX5_COMMAND_STR_CASE(DESTROY_QP);
 492         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
 493         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
 494         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
 495         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
 496         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
 497         MLX5_COMMAND_STR_CASE(2ERR_QP);
 498         MLX5_COMMAND_STR_CASE(2RST_QP);
 499         MLX5_COMMAND_STR_CASE(QUERY_QP);
 500         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
 501         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
 502         MLX5_COMMAND_STR_CASE(CREATE_PSV);
 503         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
 504         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
 505         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
 506         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
 507         MLX5_COMMAND_STR_CASE(ARM_RQ);
 508         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
 509         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
 510         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
 511         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
 512         MLX5_COMMAND_STR_CASE(CREATE_DCT);
 513         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
 514         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
 515         MLX5_COMMAND_STR_CASE(QUERY_DCT);
 516         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
 517         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
 518         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
 519         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
 520         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
 521         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
 522         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
 523         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
 524         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
 525         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
 526         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
 527         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
 528         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
 529         MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
 530         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
 531         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
 532         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
 533         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
 534         MLX5_COMMAND_STR_CASE(SET_MONITOR_COUNTER);
 535         MLX5_COMMAND_STR_CASE(ARM_MONITOR_COUNTER);
 536         MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
 537         MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
 538         MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
 539         MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
 540         MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
 541         MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
 542         MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
 543         MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
 544         MLX5_COMMAND_STR_CASE(ALLOC_PD);
 545         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
 546         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
 547         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
 548         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
 549         MLX5_COMMAND_STR_CASE(ACCESS_REG);
 550         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
 551         MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
 552         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
 553         MLX5_COMMAND_STR_CASE(MAD_IFC);
 554         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
 555         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
 556         MLX5_COMMAND_STR_CASE(NOP);
 557         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
 558         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
 559         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
 560         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
 561         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
 562         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
 563         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
 564         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
 565         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
 566         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
 567         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
 568         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
 569         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
 570         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
 571         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
 572         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
 573         MLX5_COMMAND_STR_CASE(CREATE_LAG);
 574         MLX5_COMMAND_STR_CASE(MODIFY_LAG);
 575         MLX5_COMMAND_STR_CASE(QUERY_LAG);
 576         MLX5_COMMAND_STR_CASE(DESTROY_LAG);
 577         MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
 578         MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
 579         MLX5_COMMAND_STR_CASE(CREATE_TIR);
 580         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
 581         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
 582         MLX5_COMMAND_STR_CASE(QUERY_TIR);
 583         MLX5_COMMAND_STR_CASE(CREATE_SQ);
 584         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
 585         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
 586         MLX5_COMMAND_STR_CASE(QUERY_SQ);
 587         MLX5_COMMAND_STR_CASE(CREATE_RQ);
 588         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
 589         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
 590         MLX5_COMMAND_STR_CASE(QUERY_RQ);
 591         MLX5_COMMAND_STR_CASE(CREATE_RMP);
 592         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
 593         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
 594         MLX5_COMMAND_STR_CASE(QUERY_RMP);
 595         MLX5_COMMAND_STR_CASE(CREATE_TIS);
 596         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
 597         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
 598         MLX5_COMMAND_STR_CASE(QUERY_TIS);
 599         MLX5_COMMAND_STR_CASE(CREATE_RQT);
 600         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
 601         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
 602         MLX5_COMMAND_STR_CASE(QUERY_RQT);
 603         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
 604         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
 605         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
 606         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
 607         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
 608         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
 609         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
 610         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
 611         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
 612         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
 613         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
 614         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
 615         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
 616         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
 617         MLX5_COMMAND_STR_CASE(ALLOC_PACKET_REFORMAT_CONTEXT);
 618         MLX5_COMMAND_STR_CASE(DEALLOC_PACKET_REFORMAT_CONTEXT);
 619         MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
 620         MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
 621         MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
 622         MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
 623         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
 624         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
 625         MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
 626         MLX5_COMMAND_STR_CASE(CREATE_XRQ);
 627         MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
 628         MLX5_COMMAND_STR_CASE(QUERY_XRQ);
 629         MLX5_COMMAND_STR_CASE(ARM_XRQ);
 630         MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
 631         MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
 632         MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
 633         MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
 634         MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
 635         MLX5_COMMAND_STR_CASE(ALLOC_MEMIC);
 636         MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC);
 637         MLX5_COMMAND_STR_CASE(QUERY_ESW_FUNCTIONS);
 638         MLX5_COMMAND_STR_CASE(CREATE_UCTX);
 639         MLX5_COMMAND_STR_CASE(DESTROY_UCTX);
 640         MLX5_COMMAND_STR_CASE(CREATE_UMEM);
 641         MLX5_COMMAND_STR_CASE(DESTROY_UMEM);
 642         MLX5_COMMAND_STR_CASE(RELEASE_XRQ_ERROR);
 643         MLX5_COMMAND_STR_CASE(MODIFY_XRQ);
 644         default: return "unknown command opcode";
 645         }
 646 }
 647
 648 static const char *cmd_status_str(u8 status)
 649 {
 650         switch (status) {
 651         case MLX5_CMD_STAT_OK:
 652                 return "OK";
 653         case MLX5_CMD_STAT_INT_ERR:
 654                 return "internal error";
 655         case MLX5_CMD_STAT_BAD_OP_ERR:
 656                 return "bad operation";
 657         case MLX5_CMD_STAT_BAD_PARAM_ERR:
 658                 return "bad parameter";
 659         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
 660                 return "bad system state";
 661         case MLX5_CMD_STAT_BAD_RES_ERR:
 662                 return "bad resource";
 663         case MLX5_CMD_STAT_RES_BUSY:
 664                 return "resource busy";
 665         case MLX5_CMD_STAT_LIM_ERR:
 666                 return "limits exceeded";
 667         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
 668                 return "bad resource state";
 669         case MLX5_CMD_STAT_IX_ERR:
 670                 return "bad index";
 671         case MLX5_CMD_STAT_NO_RES_ERR:
 672                 return "no resources";
 673         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
 674                 return "bad input length";
 675         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
 676                 return "bad output length";
 677         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
 678                 return "bad QP state";
 679         case MLX5_CMD_STAT_BAD_PKT_ERR:
 680                 return "bad packet (discarded)";
 681         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
 682                 return "bad size too many outstanding CQEs";
 683         default:
 684                 return "unknown status";
 685         }
 686 }
 687
 688 static int cmd_status_to_err(u8 status)
 689 {
 690         switch (status) {
 691         case MLX5_CMD_STAT_OK:                          return 0;
 692         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
 693         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
 694         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
 695         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
 696         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
 697         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
 698         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
 699         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
 700         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
 701         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
 702         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
 703         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
 704         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
 705         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
 706         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
 707         default:                                        return -EIO;
 708         }
 709 }
 710
 711 struct mlx5_ifc_mbox_out_bits {
 712         u8         status[0x8];
 713         u8         reserved_at_8[0x18];
 714
 715         u8         syndrome[0x20];
 716
 717         u8         reserved_at_40[0x40];
 718 };
 719
 720 struct mlx5_ifc_mbox_in_bits {
 721         u8         opcode[0x10];
 722         u8         uid[0x10];
 723
 724         u8         reserved_at_20[0x10];
 725         u8         op_mod[0x10];
 726
 727         u8         reserved_at_40[0x40];
 728 };
 729
 730 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
 731 {
 732         *status = MLX5_GET(mbox_out, out, status);
 733         *syndrome = MLX5_GET(mbox_out, out, syndrome);
 734 }
 735
 736 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
 737 {
 738         u32 syndrome;
 739         u8  status;
 740         u16 opcode;
 741         u16 op_mod;
 742         u16 uid;
 743
 744         mlx5_cmd_mbox_status(out, &status, &syndrome);
 745         if (!status)
 746                 return 0;
 747
 748         opcode = MLX5_GET(mbox_in, in, opcode);
 749         op_mod = MLX5_GET(mbox_in, in, op_mod);
 750         uid    = MLX5_GET(mbox_in, in, uid);
 751
 752         if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
 753                 mlx5_core_err_rl(dev,
 754                         "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
 755                         mlx5_command_str(opcode), opcode, op_mod,
 756                         cmd_status_str(status), status, syndrome);
 757         else
 758                 mlx5_core_dbg(dev,
 759                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
 760                       mlx5_command_str(opcode),
 761                       opcode, op_mod,
 762                       cmd_status_str(status),
 763                       status,
 764                       syndrome);
 765
 766         return cmd_status_to_err(status);
 767 }
 768
 769 static void dump_command(struct mlx5_core_dev *dev,
 770                          struct mlx5_cmd_work_ent *ent, int input)
 771 {
 772         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 773         u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
 774         struct mlx5_cmd_mailbox *next = msg->next;
 775         int n = mlx5_calc_cmd_blocks(msg);
 776         int data_only;
 777         u32 offset = 0;
 778         int dump_len;
 779         int i;
 780
 781         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 782
 783         if (data_only)
 784                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 785                                    "dump command data %s(0x%x) %s\n",
 786                                    mlx5_command_str(op), op,
 787                                    input ? "INPUT" : "OUTPUT");
 788         else
 789                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 790                               mlx5_command_str(op), op,
 791                               input ? "INPUT" : "OUTPUT");
 792
 793         if (data_only) {
 794                 if (input) {
 795                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 796                         offset += sizeof(ent->lay->in);
 797                 } else {
 798                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 799                         offset += sizeof(ent->lay->out);
 800                 }
 801         } else {
 802                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 803                 offset += sizeof(*ent->lay);
 804         }
 805
 806         for (i = 0; i < n && next; i++)  {
 807                 if (data_only) {
 808                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 809                         dump_buf(next->buf, dump_len, 1, offset);
 810                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 811                 } else {
 812                         mlx5_core_dbg(dev, "command block:\n");
 813                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 814                         offset += sizeof(struct mlx5_cmd_prot_block);
 815                 }
 816                 next = next->next;
 817         }
 818
 819         if (data_only)
 820                 pr_debug("\n");
 821 }
 822
 823 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 824 {
 825         return MLX5_GET(mbox_in, in->first.data, opcode);
 826 }
 827
 828 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
 829
 830 static void cb_timeout_handler(struct work_struct *work)
 831 {
 832         struct delayed_work *dwork = container_of(work, struct delayed_work,
 833                                                   work);
 834         struct mlx5_cmd_work_ent *ent = container_of(dwork,
 835                                                      struct mlx5_cmd_work_ent,
 836                                                      cb_timeout_work);
 837         struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
 838                                                  cmd);
 839
 840         ent->ret = -ETIMEDOUT;
 841         mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 842                        mlx5_command_str(msg_to_opcode(ent->in)),
 843                        msg_to_opcode(ent->in));
 844         mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 845 }
 846
 847 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
 848 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
 849                               struct mlx5_cmd_msg *msg);
 850
 851 static void cmd_work_handler(struct work_struct *work)
 852 {
 853         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 854         struct mlx5_cmd *cmd = ent->cmd;
 855         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 856         unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 857         struct mlx5_cmd_layout *lay;
 858         struct semaphore *sem;
 859         unsigned long flags;
 860         bool poll_cmd = ent->polling;
 861         int alloc_ret;
 862         int cmd_mode;
 863
 864         complete(&ent->handling);
 865         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 866         down(sem);
 867         if (!ent->page_queue) {
 868                 alloc_ret = alloc_ent(cmd);
 869                 if (alloc_ret < 0) {
 870                         mlx5_core_err(dev, "failed to allocate command entry\n");
 871                         if (ent->callback) {
 872                                 ent->callback(-EAGAIN, ent->context);
 873                                 mlx5_free_cmd_msg(dev, ent->out);
 874                                 free_msg(dev, ent->in);
 875                                 free_cmd(ent);
 876                         } else {
 877                                 ent->ret = -EAGAIN;
 878                                 complete(&ent->done);
 879                         }
 880                         up(sem);
 881                         return;
 882                 }
 883                 ent->idx = alloc_ret;
 884         } else {
 885                 ent->idx = cmd->max_reg_cmds;
 886                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 887                 clear_bit(ent->idx, &cmd->bitmask);
 888                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 889         }
 890
 891         cmd->ent_arr[ent->idx] = ent;
 892         lay = get_inst(cmd, ent->idx);
 893         ent->lay = lay;
 894         memset(lay, 0, sizeof(*lay));
 895         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 896         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 897         if (ent->in->next)
 898                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 899         lay->inlen = cpu_to_be32(ent->in->len);
 900         if (ent->out->next)
 901                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 902         lay->outlen = cpu_to_be32(ent->out->len);
 903         lay->type = MLX5_PCI_CMD_XPORT;
 904         lay->token = ent->token;
 905         lay->status_own = CMD_OWNER_HW;
 906         set_signature(ent, !cmd->checksum_disabled);
 907         dump_command(dev, ent, 1);
 908         ent->ts1 = ktime_get_ns();
 909         cmd_mode = cmd->mode;
 910
 911         if (ent->callback)
 912                 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
 913         set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
 914
 915         /* Skip sending command to fw if internal error */
 916         if (pci_channel_offline(dev->pdev) ||
 917             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
 918                 u8 status = 0;
 919                 u32 drv_synd;
 920
 921                 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
 922                 MLX5_SET(mbox_out, ent->out, status, status);
 923                 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
 924
 925                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 926                 /* no doorbell, no need to keep the entry */
 927                 free_ent(cmd, ent->idx);
 928                 if (ent->callback)
 929                         free_cmd(ent);
 930                 return;
 931         }
 932
 933         /* ring doorbell after the descriptor is valid */
 934         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 935         wmb();
 936         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 937         /* if not in polling don't use ent after this point */
 938         if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
 939                 poll_timeout(ent);
 940                 /* make sure we read the descriptor after ownership is SW */
 941                 rmb();
 942                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
 943         }
 944 }
 945
 946 static const char *deliv_status_to_str(u8 status)
 947 {
 948         switch (status) {
 949         case MLX5_CMD_DELIVERY_STAT_OK:
 950                 return "no errors";
 951         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 952                 return "signature error";
 953         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 954                 return "token error";
 955         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 956                 return "bad block number";
 957         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 958                 return "output pointer not aligned to block size";
 959         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 960                 return "input pointer not aligned to block size";
 961         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 962                 return "firmware internal error";
 963         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 964                 return "command input length error";
 965         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 966                 return "command output length error";
 967         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 968                 return "reserved fields not cleared";
 969         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 970                 return "bad command descriptor type";
 971         default:
 972                 return "unknown status code";
 973         }
 974 }
 975
 976 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 977 {
 978         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 979         struct mlx5_cmd *cmd = &dev->cmd;
 980         int err;
 981
 982         if (!wait_for_completion_timeout(&ent->handling, timeout) &&
 983             cancel_work_sync(&ent->work)) {
 984                 ent->ret = -ECANCELED;
 985                 goto out_err;
 986         }
 987         if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
 988                 wait_for_completion(&ent->done);
 989         } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
 990                 ent->ret = -ETIMEDOUT;
 991                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 992         }
 993
 994 out_err:
 995         err = ent->ret;
 996
 997         if (err == -ETIMEDOUT) {
 998                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 999                                mlx5_command_str(msg_to_opcode(ent->in)),
1000                                msg_to_opcode(ent->in));
1001         } else if (err == -ECANCELED) {
1002                 mlx5_core_warn(dev, "%s(0x%x) canceled on out of queue timeout.\n",
1003                                mlx5_command_str(msg_to_opcode(ent->in)),
1004                                msg_to_opcode(ent->in));
1005         }
1006         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
1007                       err, deliv_status_to_str(ent->status), ent->status);
1008
1009         return err;
1010 }
1011
1012 /*  Notes:
1013  *    1. Callback functions may not sleep
1014  *    2. page queue commands do not support asynchrous completion
1015  */
1016 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
1017                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
1018                            mlx5_cmd_cbk_t callback,
1019                            void *context, int page_queue, u8 *status,
1020                            u8 token, bool force_polling)
1021 {
1022         struct mlx5_cmd *cmd = &dev->cmd;
1023         struct mlx5_cmd_work_ent *ent;
1024         struct mlx5_cmd_stats *stats;
1025         int err = 0;
1026         s64 ds;
1027         u16 op;
1028
1029         if (callback && page_queue)
1030                 return -EINVAL;
1031
1032         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
1033                         page_queue);
1034         if (IS_ERR(ent))
1035                 return PTR_ERR(ent);
1036
1037         ent->token = token;
1038         ent->polling = force_polling;
1039
1040         init_completion(&ent->handling);
1041         if (!callback)
1042                 init_completion(&ent->done);
1043
1044         INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
1045         INIT_WORK(&ent->work, cmd_work_handler);
1046         if (page_queue) {
1047                 cmd_work_handler(&ent->work);
1048         } else if (!queue_work(cmd->wq, &ent->work)) {
1049                 mlx5_core_warn(dev, "failed to queue work\n");
1050                 err = -ENOMEM;
1051                 goto out_free;
1052         }
1053
1054         if (callback)
1055                 goto out;
1056
1057         err = wait_func(dev, ent);
1058         if (err == -ETIMEDOUT)
1059                 goto out;
1060         if (err == -ECANCELED)
1061                 goto out_free;
1062
1063         ds = ent->ts2 - ent->ts1;
1064         op = MLX5_GET(mbox_in, in->first.data, opcode);
1065         if (op < ARRAY_SIZE(cmd->stats)) {
1066                 stats = &cmd->stats[op];
1067                 spin_lock_irq(&stats->lock);
1068                 stats->sum += ds;
1069                 ++stats->n;
1070                 spin_unlock_irq(&stats->lock);
1071         }
1072         mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1073                            "fw exec time for %s is %lld nsec\n",
1074                            mlx5_command_str(op), ds);
1075         *status = ent->status;
1076
1077 out_free:
1078         free_cmd(ent);
1079 out:
1080         return err;
1081 }
1082
1083 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1084                          size_t count, loff_t *pos)
1085 {
1086         struct mlx5_core_dev *dev = filp->private_data;
1087         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1088         char lbuf[3];
1089         int err;
1090
1091         if (!dbg->in_msg || !dbg->out_msg)
1092                 return -ENOMEM;
1093
1094         if (count < sizeof(lbuf) - 1)
1095                 return -EINVAL;
1096
1097         if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1098                 return -EFAULT;
1099
1100         lbuf[sizeof(lbuf) - 1] = 0;
1101
1102         if (strcmp(lbuf, "go"))
1103                 return -EINVAL;
1104
1105         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1106
1107         return err ? err : count;
1108 }
1109
1110 static const struct file_operations fops = {
1111         .owner  = THIS_MODULE,
1112         .open   = simple_open,
1113         .write  = dbg_write,
1114 };
1115
1116 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1117                             u8 token)
1118 {
1119         struct mlx5_cmd_prot_block *block;
1120         struct mlx5_cmd_mailbox *next;
1121         int copy;
1122
1123         if (!to || !from)
1124                 return -ENOMEM;
1125
1126         copy = min_t(int, size, sizeof(to->first.data));
1127         memcpy(to->first.data, from, copy);
1128         size -= copy;
1129         from += copy;
1130
1131         next = to->next;
1132         while (size) {
1133                 if (!next) {
1134                         /* this is a BUG */
1135                         return -ENOMEM;
1136                 }
1137
1138                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1139                 block = next->buf;
1140                 memcpy(block->data, from, copy);
1141                 from += copy;
1142                 size -= copy;
1143                 block->token = token;
1144                 next = next->next;
1145         }
1146
1147         return 0;
1148 }
1149
1150 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1151 {
1152         struct mlx5_cmd_prot_block *block;
1153         struct mlx5_cmd_mailbox *next;
1154         int copy;
1155
1156         if (!to || !from)
1157                 return -ENOMEM;
1158
1159         copy = min_t(int, size, sizeof(from->first.data));
1160         memcpy(to, from->first.data, copy);
1161         size -= copy;
1162         to += copy;
1163
1164         next = from->next;
1165         while (size) {
1166                 if (!next) {
1167                         /* this is a BUG */
1168                         return -ENOMEM;
1169                 }
1170
1171                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1172                 block = next->buf;
1173
1174                 memcpy(to, block->data, copy);
1175                 to += copy;
1176                 size -= copy;
1177                 next = next->next;
1178         }
1179
1180         return 0;
1181 }
1182
1183 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1184                                               gfp_t flags)
1185 {
1186         struct mlx5_cmd_mailbox *mailbox;
1187
1188         mailbox = kmalloc(sizeof(*mailbox), flags);
1189         if (!mailbox)
1190                 return ERR_PTR(-ENOMEM);
1191
1192         mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1193                                        &mailbox->dma);
1194         if (!mailbox->buf) {
1195                 mlx5_core_dbg(dev, "failed allocation\n");
1196                 kfree(mailbox);
1197                 return ERR_PTR(-ENOMEM);
1198         }
1199         mailbox->next = NULL;
1200
1201         return mailbox;
1202 }
1203
1204 static void free_cmd_box(struct mlx5_core_dev *dev,
1205                          struct mlx5_cmd_mailbox *mailbox)
1206 {
1207         dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1208         kfree(mailbox);
1209 }
1210
1211 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1212                                                gfp_t flags, int size,
1213                                                u8 token)
1214 {
1215         struct mlx5_cmd_mailbox *tmp, *head = NULL;
1216         struct mlx5_cmd_prot_block *block;
1217         struct mlx5_cmd_msg *msg;
1218         int err;
1219         int n;
1220         int i;
1221
1222         msg = kzalloc(sizeof(*msg), flags);
1223         if (!msg)
1224                 return ERR_PTR(-ENOMEM);
1225
1226         msg->len = size;
1227         n = mlx5_calc_cmd_blocks(msg);
1228
1229         for (i = 0; i < n; i++) {
1230                 tmp = alloc_cmd_box(dev, flags);
1231                 if (IS_ERR(tmp)) {
1232                         mlx5_core_warn(dev, "failed allocating block\n");
1233                         err = PTR_ERR(tmp);
1234                         goto err_alloc;
1235                 }
1236
1237                 block = tmp->buf;
1238                 tmp->next = head;
1239                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1240                 block->block_num = cpu_to_be32(n - i - 1);
1241                 block->token = token;
1242                 head = tmp;
1243         }
1244         msg->next = head;
1245         return msg;
1246
1247 err_alloc:
1248         while (head) {
1249                 tmp = head->next;
1250                 free_cmd_box(dev, head);
1251                 head = tmp;
1252         }
1253         kfree(msg);
1254
1255         return ERR_PTR(err);
1256 }
1257
1258 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1259                               struct mlx5_cmd_msg *msg)
1260 {
1261         struct mlx5_cmd_mailbox *head = msg->next;
1262         struct mlx5_cmd_mailbox *next;
1263
1264         while (head) {
1265                 next = head->next;
1266                 free_cmd_box(dev, head);
1267                 head = next;
1268         }
1269         kfree(msg);
1270 }
1271
1272 static ssize_t data_write(struct file *filp, const char __user *buf,
1273                           size_t count, loff_t *pos)
1274 {
1275         struct mlx5_core_dev *dev = filp->private_data;
1276         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1277         void *ptr;
1278
1279         if (*pos != 0)
1280                 return -EINVAL;
1281
1282         kfree(dbg->in_msg);
1283         dbg->in_msg = NULL;
1284         dbg->inlen = 0;
1285         ptr = memdup_user(buf, count);
1286         if (IS_ERR(ptr))
1287                 return PTR_ERR(ptr);
1288         dbg->in_msg = ptr;
1289         dbg->inlen = count;
1290
1291         *pos = count;
1292
1293         return count;
1294 }
1295
1296 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1297                          loff_t *pos)
1298 {
1299         struct mlx5_core_dev *dev = filp->private_data;
1300         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1301
1302         if (!dbg->out_msg)
1303                 return -ENOMEM;
1304
1305         return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1306                                        dbg->outlen);
1307 }
1308
1309 static const struct file_operations dfops = {
1310         .owner  = THIS_MODULE,
1311         .open   = simple_open,
1312         .write  = data_write,
1313         .read   = data_read,
1314 };
1315
1316 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1317                            loff_t *pos)
1318 {
1319         struct mlx5_core_dev *dev = filp->private_data;
1320         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1321         char outlen[8];
1322         int err;
1323
1324         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1325         if (err < 0)
1326                 return err;
1327
1328         return simple_read_from_buffer(buf, count, pos, outlen, err);
1329 }
1330
1331 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1332                             size_t count, loff_t *pos)
1333 {
1334         struct mlx5_core_dev *dev = filp->private_data;
1335         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1336         char outlen_str[8] = {0};
1337         int outlen;
1338         void *ptr;
1339         int err;
1340
1341         if (*pos != 0 || count > 6)
1342                 return -EINVAL;
1343
1344         kfree(dbg->out_msg);
1345         dbg->out_msg = NULL;
1346         dbg->outlen = 0;
1347
1348         if (copy_from_user(outlen_str, buf, count))
1349                 return -EFAULT;
1350
1351         err = sscanf(outlen_str, "%d", &outlen);
1352         if (err < 0)
1353                 return err;
1354
1355         ptr = kzalloc(outlen, GFP_KERNEL);
1356         if (!ptr)
1357                 return -ENOMEM;
1358
1359         dbg->out_msg = ptr;
1360         dbg->outlen = outlen;
1361
1362         *pos = count;
1363
1364         return count;
1365 }
1366
1367 static const struct file_operations olfops = {
1368         .owner  = THIS_MODULE,
1369         .open   = simple_open,
1370         .write  = outlen_write,
1371         .read   = outlen_read,
1372 };
1373
1374 static void set_wqname(struct mlx5_core_dev *dev)
1375 {
1376         struct mlx5_cmd *cmd = &dev->cmd;
1377
1378         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1379                  dev_name(dev->device));
1380 }
1381
1382 static void clean_debug_files(struct mlx5_core_dev *dev)
1383 {
1384         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1385
1386         if (!mlx5_debugfs_root)
1387                 return;
1388
1389         mlx5_cmdif_debugfs_cleanup(dev);
1390         debugfs_remove_recursive(dbg->dbg_root);
1391 }
1392
1393 static void create_debugfs_files(struct mlx5_core_dev *dev)
1394 {
1395         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1396
1397         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1398
1399         debugfs_create_file("in", 0400, dbg->dbg_root, dev, &dfops);
1400         debugfs_create_file("out", 0200, dbg->dbg_root, dev, &dfops);
1401         debugfs_create_file("out_len", 0600, dbg->dbg_root, dev, &olfops);
1402         debugfs_create_u8("status", 0600, dbg->dbg_root, &dbg->status);
1403         debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1404
1405         mlx5_cmdif_debugfs_init(dev);
1406 }
1407
1408 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1409 {
1410         struct mlx5_cmd *cmd = &dev->cmd;
1411         int i;
1412
1413         for (i = 0; i < cmd->max_reg_cmds; i++)
1414                 down(&cmd->sem);
1415         down(&cmd->pages_sem);
1416
1417         cmd->mode = mode;
1418
1419         up(&cmd->pages_sem);
1420         for (i = 0; i < cmd->max_reg_cmds; i++)
1421                 up(&cmd->sem);
1422 }
1423
1424 static int cmd_comp_notifier(struct notifier_block *nb,
1425                              unsigned long type, void *data)
1426 {
1427         struct mlx5_core_dev *dev;
1428         struct mlx5_cmd *cmd;
1429         struct mlx5_eqe *eqe;
1430
1431         cmd = mlx5_nb_cof(nb, struct mlx5_cmd, nb);
1432         dev = container_of(cmd, struct mlx5_core_dev, cmd);
1433         eqe = data;
1434
1435         mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
1436
1437         return NOTIFY_OK;
1438 }
1439 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1440 {
1441         MLX5_NB_INIT(&dev->cmd.nb, cmd_comp_notifier, CMD);
1442         mlx5_eq_notifier_register(dev, &dev->cmd.nb);
1443         mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1444 }
1445
1446 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1447 {
1448         mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1449         mlx5_eq_notifier_unregister(dev, &dev->cmd.nb);
1450 }
1451
1452 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1453 {
1454         unsigned long flags;
1455
1456         if (msg->parent) {
1457                 spin_lock_irqsave(&msg->parent->lock, flags);
1458                 list_add_tail(&msg->list, &msg->parent->head);
1459                 spin_unlock_irqrestore(&msg->parent->lock, flags);
1460         } else {
1461                 mlx5_free_cmd_msg(dev, msg);
1462         }
1463 }
1464
1465 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1466 {
1467         struct mlx5_cmd *cmd = &dev->cmd;
1468         struct mlx5_cmd_work_ent *ent;
1469         mlx5_cmd_cbk_t callback;
1470         void *context;
1471         int err;
1472         int i;
1473         s64 ds;
1474         struct mlx5_cmd_stats *stats;
1475         unsigned long flags;
1476         unsigned long vector;
1477
1478         /* there can be at most 32 command queues */
1479         vector = vec & 0xffffffff;
1480         for (i = 0; i < (1 << cmd->log_sz); i++) {
1481                 if (test_bit(i, &vector)) {
1482                         struct semaphore *sem;
1483
1484                         ent = cmd->ent_arr[i];
1485
1486                         /* if we already completed the command, ignore it */
1487                         if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1488                                                 &ent->state)) {
1489                                 /* only real completion can free the cmd slot */
1490                                 if (!forced) {
1491                                         mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1492                                                       ent->idx);
1493                                         free_ent(cmd, ent->idx);
1494                                         free_cmd(ent);
1495                                 }
1496                                 continue;
1497                         }
1498
1499                         if (ent->callback)
1500                                 cancel_delayed_work(&ent->cb_timeout_work);
1501                         if (ent->page_queue)
1502                                 sem = &cmd->pages_sem;
1503                         else
1504                                 sem = &cmd->sem;
1505                         ent->ts2 = ktime_get_ns();
1506                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1507                         dump_command(dev, ent, 0);
1508                         if (!ent->ret) {
1509                                 if (!cmd->checksum_disabled)
1510                                         ent->ret = verify_signature(ent);
1511                                 else
1512                                         ent->ret = 0;
1513                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1514                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1515                                 else
1516                                         ent->status = ent->lay->status_own >> 1;
1517
1518                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1519                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1520                         }
1521
1522                         /* only real completion will free the entry slot */
1523                         if (!forced)
1524                                 free_ent(cmd, ent->idx);
1525
1526                         if (ent->callback) {
1527                                 ds = ent->ts2 - ent->ts1;
1528                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1529                                         stats = &cmd->stats[ent->op];
1530                                         spin_lock_irqsave(&stats->lock, flags);
1531                                         stats->sum += ds;
1532                                         ++stats->n;
1533                                         spin_unlock_irqrestore(&stats->lock, flags);
1534                                 }
1535
1536                                 callback = ent->callback;
1537                                 context = ent->context;
1538                                 err = ent->ret;
1539                                 if (!err) {
1540                                         err = mlx5_copy_from_msg(ent->uout,
1541                                                                  ent->out,
1542                                                                  ent->uout_size);
1543
1544                                         err = err ? err : mlx5_cmd_check(dev,
1545                                                                         ent->in->first.data,
1546                                                                         ent->uout);
1547                                 }
1548
1549                                 mlx5_free_cmd_msg(dev, ent->out);
1550                                 free_msg(dev, ent->in);
1551
1552                                 err = err ? err : ent->status;
1553                                 if (!forced)
1554                                         free_cmd(ent);
1555                                 callback(err, context);
1556                         } else {
1557                                 complete(&ent->done);
1558                         }
1559                         up(sem);
1560                 }
1561         }
1562 }
1563
1564 void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev)
1565 {
1566         unsigned long flags;
1567         u64 vector;
1568
1569         /* wait for pending handlers to complete */
1570         mlx5_eq_synchronize_cmd_irq(dev);
1571         spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
1572         vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
1573         if (!vector)
1574                 goto no_trig;
1575
1576         vector |= MLX5_TRIGGERED_CMD_COMP;
1577         spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1578
1579         mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
1580         mlx5_cmd_comp_handler(dev, vector, true);
1581         return;
1582
1583 no_trig:
1584         spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1585 }
1586
1587 void mlx5_cmd_flush(struct mlx5_core_dev *dev)
1588 {
1589         struct mlx5_cmd *cmd = &dev->cmd;
1590         int i;
1591
1592         for (i = 0; i < cmd->max_reg_cmds; i++)
1593                 while (down_trylock(&cmd->sem))
1594                         mlx5_cmd_trigger_completions(dev);
1595
1596         while (down_trylock(&cmd->pages_sem))
1597                 mlx5_cmd_trigger_completions(dev);
1598
1599         /* Unlock cmdif */
1600         up(&cmd->pages_sem);
1601         for (i = 0; i < cmd->max_reg_cmds; i++)
1602                 up(&cmd->sem);
1603 }
1604
1605 static int status_to_err(u8 status)
1606 {
1607         switch (status) {
1608         case MLX5_CMD_DELIVERY_STAT_OK:
1609         case MLX5_DRIVER_STATUS_ABORTED:
1610                 return 0;
1611         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
1612         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
1613                 return -EBADR;
1614         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
1615         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1616         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1617                 return -EFAULT; /* Bad address */
1618         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1619         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1620         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1621         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1622                 return -ENOMSG;
1623         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1624                 return -EIO;
1625         default:
1626                 return -EINVAL;
1627         }
1628 }
1629
1630 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1631                                       gfp_t gfp)
1632 {
1633         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1634         struct cmd_msg_cache *ch = NULL;
1635         struct mlx5_cmd *cmd = &dev->cmd;
1636         int i;
1637
1638         if (in_size <= 16)
1639                 goto cache_miss;
1640
1641         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1642                 ch = &cmd->cache[i];
1643                 if (in_size > ch->max_inbox_size)
1644                         continue;
1645                 spin_lock_irq(&ch->lock);
1646                 if (list_empty(&ch->head)) {
1647                         spin_unlock_irq(&ch->lock);
1648                         continue;
1649                 }
1650                 msg = list_entry(ch->head.next, typeof(*msg), list);
1651                 /* For cached lists, we must explicitly state what is
1652                  * the real size
1653                  */
1654                 msg->len = in_size;
1655                 list_del(&msg->list);
1656                 spin_unlock_irq(&ch->lock);
1657                 break;
1658         }
1659
1660         if (!IS_ERR(msg))
1661                 return msg;
1662
1663 cache_miss:
1664         msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1665         return msg;
1666 }
1667
1668 static int is_manage_pages(void *in)
1669 {
1670         return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1671 }
1672
1673 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1674                     int out_size, mlx5_cmd_cbk_t callback, void *context,
1675                     bool force_polling)
1676 {
1677         struct mlx5_cmd_msg *inb;
1678         struct mlx5_cmd_msg *outb;
1679         int pages_queue;
1680         gfp_t gfp;
1681         int err;
1682         u8 status = 0;
1683         u32 drv_synd;
1684         u8 token;
1685
1686         if (pci_channel_offline(dev->pdev) ||
1687             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1688                 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1689
1690                 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1691                 MLX5_SET(mbox_out, out, status, status);
1692                 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1693                 return err;
1694         }
1695
1696         pages_queue = is_manage_pages(in);
1697         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1698
1699         inb = alloc_msg(dev, in_size, gfp);
1700         if (IS_ERR(inb)) {
1701                 err = PTR_ERR(inb);
1702                 return err;
1703         }
1704
1705         token = alloc_token(&dev->cmd);
1706
1707         err = mlx5_copy_to_msg(inb, in, in_size, token);
1708         if (err) {
1709                 mlx5_core_warn(dev, "err %d\n", err);
1710                 goto out_in;
1711         }
1712
1713         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1714         if (IS_ERR(outb)) {
1715                 err = PTR_ERR(outb);
1716                 goto out_in;
1717         }
1718
1719         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1720                               pages_queue, &status, token, force_polling);
1721         if (err)
1722                 goto out_out;
1723
1724         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1725         if (status) {
1726                 err = status_to_err(status);
1727                 goto out_out;
1728         }
1729
1730         if (!callback)
1731                 err = mlx5_copy_from_msg(out, outb, out_size);
1732
1733 out_out:
1734         if (!callback)
1735                 mlx5_free_cmd_msg(dev, outb);
1736
1737 out_in:
1738         if (!callback)
1739                 free_msg(dev, inb);
1740         return err;
1741 }
1742
1743 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1744                   int out_size)
1745 {
1746         int err;
1747
1748         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1749         return err ? : mlx5_cmd_check(dev, in, out);
1750 }
1751 EXPORT_SYMBOL(mlx5_cmd_exec);
1752
1753 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
1754                              struct mlx5_async_ctx *ctx)
1755 {
1756         ctx->dev = dev;
1757         /* Starts at 1 to avoid doing wake_up if we are not cleaning up */
1758         atomic_set(&ctx->num_inflight, 1);
1759         init_waitqueue_head(&ctx->wait);
1760 }
1761 EXPORT_SYMBOL(mlx5_cmd_init_async_ctx);
1762
1763 /**
1764  * mlx5_cmd_cleanup_async_ctx - Clean up an async_ctx
1765  * @ctx: The ctx to clean
1766  *
1767  * Upon return all callbacks given to mlx5_cmd_exec_cb() have been called. The
1768  * caller must ensure that mlx5_cmd_exec_cb() is not called during or after
1769  * the call mlx5_cleanup_async_ctx().
1770  */
1771 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx)
1772 {
1773         atomic_dec(&ctx->num_inflight);
1774         wait_event(ctx->wait, atomic_read(&ctx->num_inflight) == 0);
1775 }
1776 EXPORT_SYMBOL(mlx5_cmd_cleanup_async_ctx);
1777
1778 static void mlx5_cmd_exec_cb_handler(int status, void *_work)
1779 {
1780         struct mlx5_async_work *work = _work;
1781         struct mlx5_async_ctx *ctx = work->ctx;
1782
1783         work->user_callback(status, work);
1784         if (atomic_dec_and_test(&ctx->num_inflight))
1785                 wake_up(&ctx->wait);
1786 }
1787
1788 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
1789                      void *out, int out_size, mlx5_async_cbk_t callback,
1790                      struct mlx5_async_work *work)
1791 {
1792         int ret;
1793
1794         work->ctx = ctx;
1795         work->user_callback = callback;
1796         if (WARN_ON(!atomic_inc_not_zero(&ctx->num_inflight)))
1797                 return -EIO;
1798         ret = cmd_exec(ctx->dev, in, in_size, out, out_size,
1799                        mlx5_cmd_exec_cb_handler, work, false);
1800         if (ret && atomic_dec_and_test(&ctx->num_inflight))
1801                 wake_up(&ctx->wait);
1802
1803         return ret;
1804 }
1805 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1806
1807 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1808                           void *out, int out_size)
1809 {
1810         int err;
1811
1812         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1813
1814         return err ? : mlx5_cmd_check(dev, in, out);
1815 }
1816 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1817
1818 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1819 {
1820         struct cmd_msg_cache *ch;
1821         struct mlx5_cmd_msg *msg;
1822         struct mlx5_cmd_msg *n;
1823         int i;
1824
1825         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1826                 ch = &dev->cmd.cache[i];
1827                 list_for_each_entry_safe(msg, n, &ch->head, list) {
1828                         list_del(&msg->list);
1829                         mlx5_free_cmd_msg(dev, msg);
1830                 }
1831         }
1832 }
1833
1834 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1835         512, 32, 16, 8, 2
1836 };
1837
1838 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1839         16 + MLX5_CMD_DATA_BLOCK_SIZE,
1840         16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1841         16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1842         16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1843         16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1844 };
1845
1846 static void create_msg_cache(struct mlx5_core_dev *dev)
1847 {
1848         struct mlx5_cmd *cmd = &dev->cmd;
1849         struct cmd_msg_cache *ch;
1850         struct mlx5_cmd_msg *msg;
1851         int i;
1852         int k;
1853
1854         /* Initialize and fill the caches with initial entries */
1855         for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1856                 ch = &cmd->cache[k];
1857                 spin_lock_init(&ch->lock);
1858                 INIT_LIST_HEAD(&ch->head);
1859                 ch->num_ent = cmd_cache_num_ent[k];
1860                 ch->max_inbox_size = cmd_cache_ent_size[k];
1861                 for (i = 0; i < ch->num_ent; i++) {
1862                         msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1863                                                  ch->max_inbox_size, 0);
1864                         if (IS_ERR(msg))
1865                                 break;
1866                         msg->parent = ch;
1867                         list_add_tail(&msg->list, &ch->head);
1868                 }
1869         }
1870 }
1871
1872 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1873 {
1874         struct device *ddev = dev->device;
1875
1876         cmd->cmd_alloc_buf = dma_alloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1877                                                 &cmd->alloc_dma, GFP_KERNEL);
1878         if (!cmd->cmd_alloc_buf)
1879                 return -ENOMEM;
1880
1881         /* make sure it is aligned to 4K */
1882         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1883                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1884                 cmd->dma = cmd->alloc_dma;
1885                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1886                 return 0;
1887         }
1888
1889         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1890                           cmd->alloc_dma);
1891         cmd->cmd_alloc_buf = dma_alloc_coherent(ddev,
1892                                                 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1893                                                 &cmd->alloc_dma, GFP_KERNEL);
1894         if (!cmd->cmd_alloc_buf)
1895                 return -ENOMEM;
1896
1897         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1898         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1899         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1900         return 0;
1901 }
1902
1903 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1904 {
1905         struct device *ddev = dev->device;
1906
1907         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1908                           cmd->alloc_dma);
1909 }
1910
1911 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1912 {
1913         int size = sizeof(struct mlx5_cmd_prot_block);
1914         int align = roundup_pow_of_two(size);
1915         struct mlx5_cmd *cmd = &dev->cmd;
1916         u32 cmd_h, cmd_l;
1917         u16 cmd_if_rev;
1918         int err;
1919         int i;
1920
1921         memset(cmd, 0, sizeof(*cmd));
1922         cmd_if_rev = cmdif_rev(dev);
1923         if (cmd_if_rev != CMD_IF_REV) {
1924                 mlx5_core_err(dev,
1925                               "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1926                               CMD_IF_REV, cmd_if_rev);
1927                 return -EINVAL;
1928         }
1929
1930         cmd->pool = dma_pool_create("mlx5_cmd", dev->device, size, align, 0);
1931         if (!cmd->pool)
1932                 return -ENOMEM;
1933
1934         err = alloc_cmd_page(dev, cmd);
1935         if (err)
1936                 goto err_free_pool;
1937
1938         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1939         cmd->log_sz = cmd_l >> 4 & 0xf;
1940         cmd->log_stride = cmd_l & 0xf;
1941         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1942                 mlx5_core_err(dev, "firmware reports too many outstanding commands %d\n",
1943                               1 << cmd->log_sz);
1944                 err = -EINVAL;
1945                 goto err_free_page;
1946         }
1947
1948         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1949                 mlx5_core_err(dev, "command queue size overflow\n");
1950                 err = -EINVAL;
1951                 goto err_free_page;
1952         }
1953
1954         cmd->checksum_disabled = 1;
1955         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1956         cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1957
1958         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1959         if (cmd->cmdif_rev > CMD_IF_REV) {
1960                 mlx5_core_err(dev, "driver does not support command interface version. driver %d, firmware %d\n",
1961                               CMD_IF_REV, cmd->cmdif_rev);
1962                 err = -EOPNOTSUPP;
1963                 goto err_free_page;
1964         }
1965
1966         spin_lock_init(&cmd->alloc_lock);
1967         spin_lock_init(&cmd->token_lock);
1968         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1969                 spin_lock_init(&cmd->stats[i].lock);
1970
1971         sema_init(&cmd->sem, cmd->max_reg_cmds);
1972         sema_init(&cmd->pages_sem, 1);
1973
1974         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1975         cmd_l = (u32)(cmd->dma);
1976         if (cmd_l & 0xfff) {
1977                 mlx5_core_err(dev, "invalid command queue address\n");
1978                 err = -ENOMEM;
1979                 goto err_free_page;
1980         }
1981
1982         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1983         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1984
1985         /* Make sure firmware sees the complete address before we proceed */
1986         wmb();
1987
1988         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1989
1990         cmd->mode = CMD_MODE_POLLING;
1991
1992         create_msg_cache(dev);
1993
1994         set_wqname(dev);
1995         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1996         if (!cmd->wq) {
1997                 mlx5_core_err(dev, "failed to create command workqueue\n");
1998                 err = -ENOMEM;
1999                 goto err_cache;
2000         }
2001
2002         create_debugfs_files(dev);
2003
2004         return 0;
2005
2006 err_cache:
2007         destroy_msg_cache(dev);
2008
2009 err_free_page:
2010         free_cmd_page(dev, cmd);
2011
2012 err_free_pool:
2013         dma_pool_destroy(cmd->pool);
2014
2015         return err;
2016 }
2017 EXPORT_SYMBOL(mlx5_cmd_init);
2018
2019 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
2020 {
2021         struct mlx5_cmd *cmd = &dev->cmd;
2022
2023         clean_debug_files(dev);
2024         destroy_workqueue(cmd->wq);
2025         destroy_msg_cache(dev);
2026         free_cmd_page(dev, cmd);
2027         dma_pool_destroy(cmd->pool);
2028 }
2029 EXPORT_SYMBOL(mlx5_cmd_cleanup);