1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
35 #include <linux/interrupt.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/prefetch.h>
49 #include <scsi/fc/fc_fcoe.h>
52 #include "ixgbe_common.h"
53 #include "ixgbe_dcb_82599.h"
54 #include "ixgbe_sriov.h"
56 char ixgbe_driver_name[] = "ixgbe";
57 static const char ixgbe_driver_string[] =
58 "Intel(R) 10 Gigabit PCI Express Network Driver";
60 char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
63 static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
66 #define DRV_VERSION "3.13.10-k"
67 const char ixgbe_driver_version[] = DRV_VERSION;
68 static const char ixgbe_copyright[] =
69 "Copyright (c) 1999-2013 Intel Corporation.";
71 static const struct ixgbe_info *ixgbe_info_tbl[] = {
72 [board_82598] = &ixgbe_82598_info,
73 [board_82599] = &ixgbe_82599_info,
74 [board_X540] = &ixgbe_X540_info,
77 /* ixgbe_pci_tbl - PCI Device ID Table
79 * Wildcard entries (PCI_ANY_ID) should come last
80 * Last entry must be all 0s
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
85 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
115 /* required last entry */
118 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120 #ifdef CONFIG_IXGBE_DCA
121 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
123 static struct notifier_block dca_notifier = {
124 .notifier_call = ixgbe_notify_dca,
130 #ifdef CONFIG_PCI_IOV
131 static unsigned int max_vfs;
132 module_param(max_vfs, uint, 0);
133 MODULE_PARM_DESC(max_vfs,
134 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
135 #endif /* CONFIG_PCI_IOV */
137 static unsigned int allow_unsupported_sfp;
138 module_param(allow_unsupported_sfp, uint, 0);
139 MODULE_PARM_DESC(allow_unsupported_sfp,
140 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
142 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
143 static int debug = -1;
144 module_param(debug, int, 0);
145 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
147 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
148 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
149 MODULE_LICENSE("GPL");
150 MODULE_VERSION(DRV_VERSION);
152 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
156 struct pci_dev *parent_dev;
157 struct pci_bus *parent_bus;
159 parent_bus = adapter->pdev->bus->parent;
163 parent_dev = parent_bus->self;
167 pos = pci_find_capability(parent_dev, PCI_CAP_ID_EXP);
171 pci_read_config_word(parent_dev, pos + reg, value);
175 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
177 struct ixgbe_hw *hw = &adapter->hw;
181 hw->bus.type = ixgbe_bus_type_pci_express;
183 /* Get the negotiated link width and speed from PCI config space of the
184 * parent, as this device is behind a switch
186 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
188 /* assume caller will handle error case */
192 hw->bus.width = ixgbe_convert_bus_width(link_status);
193 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
198 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
200 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
202 schedule_work(&adapter->service_task);
205 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
209 /* flush memory to make sure state is correct before next watchdog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
214 struct ixgbe_reg_info {
219 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
221 /* General Registers */
222 {IXGBE_CTRL, "CTRL"},
223 {IXGBE_STATUS, "STATUS"},
224 {IXGBE_CTRL_EXT, "CTRL_EXT"},
226 /* Interrupt Registers */
227 {IXGBE_EICR, "EICR"},
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
247 /* List Terminator */
253 * ixgbe_regdump - register printout routine
255 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
261 switch (reginfo->ofs) {
262 case IXGBE_SRRCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
266 case IXGBE_DCA_RXCTRL(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
282 case IXGBE_RXDCTL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
314 case IXGBE_TXDCTL(0):
315 for (i = 0; i < 64; i++)
316 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
319 pr_info("%-15s %08x\n", reginfo->name,
320 IXGBE_READ_REG(hw, reginfo->ofs));
324 for (i = 0; i < 8; i++) {
325 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
326 pr_err("%-15s", rname);
327 for (j = 0; j < 8; j++)
328 pr_cont(" %08x", regs[i*8+j]);
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
337 static void ixgbe_dump(struct ixgbe_adapter *adapter)
339 struct net_device *netdev = adapter->netdev;
340 struct ixgbe_hw *hw = &adapter->hw;
341 struct ixgbe_reg_info *reginfo;
343 struct ixgbe_ring *tx_ring;
344 struct ixgbe_tx_buffer *tx_buffer;
345 union ixgbe_adv_tx_desc *tx_desc;
346 struct my_u0 { u64 a; u64 b; } *u0;
347 struct ixgbe_ring *rx_ring;
348 union ixgbe_adv_rx_desc *rx_desc;
349 struct ixgbe_rx_buffer *rx_buffer_info;
353 if (!netif_msg_hw(adapter))
356 /* Print netdevice Info */
358 dev_info(&adapter->pdev->dev, "Net device Info\n");
359 pr_info("Device Name state "
360 "trans_start last_rx\n");
361 pr_info("%-15s %016lX %016lX %016lX\n",
368 /* Print Registers */
369 dev_info(&adapter->pdev->dev, "Register Dump\n");
370 pr_info(" Register Name Value\n");
371 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
372 reginfo->name; reginfo++) {
373 ixgbe_regdump(hw, reginfo);
376 /* Print TX Ring Summary */
377 if (!netdev || !netif_running(netdev))
380 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
381 pr_info(" %s %s %s %s\n",
382 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
383 "leng", "ntw", "timestamp");
384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
386 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
387 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
388 n, tx_ring->next_to_use, tx_ring->next_to_clean,
389 (u64)dma_unmap_addr(tx_buffer, dma),
390 dma_unmap_len(tx_buffer, len),
391 tx_buffer->next_to_watch,
392 (u64)tx_buffer->time_stamp);
396 if (!netif_msg_tx_done(adapter))
397 goto rx_ring_summary;
399 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
401 /* Transmit Descriptor Formats
403 * 82598 Advanced Transmit Descriptor
404 * +--------------------------------------------------------------+
405 * 0 | Buffer Address [63:0] |
406 * +--------------------------------------------------------------+
407 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
408 * +--------------------------------------------------------------+
409 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
411 * 82598 Advanced Transmit Descriptor (Write-Back Format)
412 * +--------------------------------------------------------------+
414 * +--------------------------------------------------------------+
415 * 8 | RSV | STA | NXTSEQ |
416 * +--------------------------------------------------------------+
419 * 82599+ Advanced Transmit Descriptor
420 * +--------------------------------------------------------------+
421 * 0 | Buffer Address [63:0] |
422 * +--------------------------------------------------------------+
423 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
424 * +--------------------------------------------------------------+
425 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
427 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
428 * +--------------------------------------------------------------+
430 * +--------------------------------------------------------------+
431 * 8 | RSV | STA | RSV |
432 * +--------------------------------------------------------------+
436 for (n = 0; n < adapter->num_tx_queues; n++) {
437 tx_ring = adapter->tx_ring[n];
438 pr_info("------------------------------------\n");
439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("%s%s %s %s %s %s\n",
442 "T [desc] [address 63:0 ] ",
443 "[PlPOIdStDDt Ln] [bi->dma ] ",
444 "leng", "ntw", "timestamp", "bi->skb");
446 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
447 tx_desc = IXGBE_TX_DESC(tx_ring, i);
448 tx_buffer = &tx_ring->tx_buffer_info[i];
449 u0 = (struct my_u0 *)tx_desc;
450 if (dma_unmap_len(tx_buffer, len) > 0) {
451 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
455 (u64)dma_unmap_addr(tx_buffer, dma),
456 dma_unmap_len(tx_buffer, len),
457 tx_buffer->next_to_watch,
458 (u64)tx_buffer->time_stamp,
460 if (i == tx_ring->next_to_use &&
461 i == tx_ring->next_to_clean)
463 else if (i == tx_ring->next_to_use)
465 else if (i == tx_ring->next_to_clean)
470 if (netif_msg_pktdata(adapter) &&
472 print_hex_dump(KERN_INFO, "",
473 DUMP_PREFIX_ADDRESS, 16, 1,
474 tx_buffer->skb->data,
475 dma_unmap_len(tx_buffer, len),
481 /* Print RX Rings Summary */
483 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
484 pr_info("Queue [NTU] [NTC]\n");
485 for (n = 0; n < adapter->num_rx_queues; n++) {
486 rx_ring = adapter->rx_ring[n];
487 pr_info("%5d %5X %5X\n",
488 n, rx_ring->next_to_use, rx_ring->next_to_clean);
492 if (!netif_msg_rx_status(adapter))
495 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
497 /* Receive Descriptor Formats
499 * 82598 Advanced Receive Descriptor (Read) Format
501 * +-----------------------------------------------------+
502 * 0 | Packet Buffer Address [63:1] |A0/NSE|
503 * +----------------------------------------------+------+
504 * 8 | Header Buffer Address [63:1] | DD |
505 * +-----------------------------------------------------+
508 * 82598 Advanced Receive Descriptor (Write-Back) Format
510 * 63 48 47 32 31 30 21 20 16 15 4 3 0
511 * +------------------------------------------------------+
512 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
513 * | Packet | IP | | | | Type | Type |
514 * | Checksum | Ident | | | | | |
515 * +------------------------------------------------------+
516 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
517 * +------------------------------------------------------+
518 * 63 48 47 32 31 20 19 0
520 * 82599+ Advanced Receive Descriptor (Read) Format
522 * +-----------------------------------------------------+
523 * 0 | Packet Buffer Address [63:1] |A0/NSE|
524 * +----------------------------------------------+------+
525 * 8 | Header Buffer Address [63:1] | DD |
526 * +-----------------------------------------------------+
529 * 82599+ Advanced Receive Descriptor (Write-Back) Format
531 * 63 48 47 32 31 30 21 20 17 16 4 3 0
532 * +------------------------------------------------------+
533 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
534 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
535 * |/ Flow Dir Flt ID | | | | | |
536 * +------------------------------------------------------+
537 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
538 * +------------------------------------------------------+
539 * 63 48 47 32 31 20 19 0
542 for (n = 0; n < adapter->num_rx_queues; n++) {
543 rx_ring = adapter->rx_ring[n];
544 pr_info("------------------------------------\n");
545 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
546 pr_info("------------------------------------\n");
548 "R [desc] [ PktBuf A0] ",
549 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
550 "<-- Adv Rx Read format\n");
552 "RWB[desc] [PcsmIpSHl PtRs] ",
553 "[vl er S cks ln] ---------------- [bi->skb ] ",
554 "<-- Adv Rx Write-Back format\n");
556 for (i = 0; i < rx_ring->count; i++) {
557 rx_buffer_info = &rx_ring->rx_buffer_info[i];
558 rx_desc = IXGBE_RX_DESC(rx_ring, i);
559 u0 = (struct my_u0 *)rx_desc;
560 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
561 if (staterr & IXGBE_RXD_STAT_DD) {
562 /* Descriptor Done */
563 pr_info("RWB[0x%03X] %016llX "
564 "%016llX ---------------- %p", i,
567 rx_buffer_info->skb);
569 pr_info("R [0x%03X] %016llX "
570 "%016llX %016llX %p", i,
573 (u64)rx_buffer_info->dma,
574 rx_buffer_info->skb);
576 if (netif_msg_pktdata(adapter) &&
577 rx_buffer_info->dma) {
578 print_hex_dump(KERN_INFO, "",
579 DUMP_PREFIX_ADDRESS, 16, 1,
580 page_address(rx_buffer_info->page) +
581 rx_buffer_info->page_offset,
582 ixgbe_rx_bufsz(rx_ring), true);
586 if (i == rx_ring->next_to_use)
588 else if (i == rx_ring->next_to_clean)
600 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
604 /* Let firmware take over control of h/w */
605 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
606 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
607 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
610 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
614 /* Let firmware know the driver has taken over */
615 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
616 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
617 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
621 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
622 * @adapter: pointer to adapter struct
623 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
624 * @queue: queue to map the corresponding interrupt to
625 * @msix_vector: the vector to map to the corresponding queue
628 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
629 u8 queue, u8 msix_vector)
632 struct ixgbe_hw *hw = &adapter->hw;
633 switch (hw->mac.type) {
634 case ixgbe_mac_82598EB:
635 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
638 index = (((direction * 64) + queue) >> 2) & 0x1F;
639 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
640 ivar &= ~(0xFF << (8 * (queue & 0x3)));
641 ivar |= (msix_vector << (8 * (queue & 0x3)));
642 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
644 case ixgbe_mac_82599EB:
646 if (direction == -1) {
648 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
649 index = ((queue & 1) * 8);
650 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
651 ivar &= ~(0xFF << index);
652 ivar |= (msix_vector << index);
653 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
656 /* tx or rx causes */
657 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
658 index = ((16 * (queue & 1)) + (8 * direction));
659 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
660 ivar &= ~(0xFF << index);
661 ivar |= (msix_vector << index);
662 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
670 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
675 switch (adapter->hw.mac.type) {
676 case ixgbe_mac_82598EB:
677 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
678 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
680 case ixgbe_mac_82599EB:
682 mask = (qmask & 0xFFFFFFFF);
683 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
684 mask = (qmask >> 32);
685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
692 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
693 struct ixgbe_tx_buffer *tx_buffer)
695 if (tx_buffer->skb) {
696 dev_kfree_skb_any(tx_buffer->skb);
697 if (dma_unmap_len(tx_buffer, len))
698 dma_unmap_single(ring->dev,
699 dma_unmap_addr(tx_buffer, dma),
700 dma_unmap_len(tx_buffer, len),
702 } else if (dma_unmap_len(tx_buffer, len)) {
703 dma_unmap_page(ring->dev,
704 dma_unmap_addr(tx_buffer, dma),
705 dma_unmap_len(tx_buffer, len),
708 tx_buffer->next_to_watch = NULL;
709 tx_buffer->skb = NULL;
710 dma_unmap_len_set(tx_buffer, len, 0);
711 /* tx_buffer must be completely set up in the transmit path */
714 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
716 struct ixgbe_hw *hw = &adapter->hw;
717 struct ixgbe_hw_stats *hwstats = &adapter->stats;
721 if ((hw->fc.current_mode != ixgbe_fc_full) &&
722 (hw->fc.current_mode != ixgbe_fc_rx_pause))
725 switch (hw->mac.type) {
726 case ixgbe_mac_82598EB:
727 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
730 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
732 hwstats->lxoffrxc += data;
734 /* refill credits (no tx hang) if we received xoff */
738 for (i = 0; i < adapter->num_tx_queues; i++)
739 clear_bit(__IXGBE_HANG_CHECK_ARMED,
740 &adapter->tx_ring[i]->state);
743 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
745 struct ixgbe_hw *hw = &adapter->hw;
746 struct ixgbe_hw_stats *hwstats = &adapter->stats;
750 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
752 if (adapter->ixgbe_ieee_pfc)
753 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
755 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
756 ixgbe_update_xoff_rx_lfc(adapter);
760 /* update stats for each tc, only valid with PFC enabled */
761 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
764 switch (hw->mac.type) {
765 case ixgbe_mac_82598EB:
766 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
769 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
771 hwstats->pxoffrxc[i] += pxoffrxc;
772 /* Get the TC for given UP */
773 tc = netdev_get_prio_tc_map(adapter->netdev, i);
774 xoff[tc] += pxoffrxc;
777 /* disarm tx queues that have received xoff frames */
778 for (i = 0; i < adapter->num_tx_queues; i++) {
779 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
781 tc = tx_ring->dcb_tc;
783 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
787 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
789 return ring->stats.packets;
792 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
794 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
795 struct ixgbe_hw *hw = &adapter->hw;
797 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
798 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
801 return (head < tail) ?
802 tail - head : (tail + ring->count - head);
807 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
809 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
810 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
811 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
814 clear_check_for_tx_hang(tx_ring);
817 * Check for a hung queue, but be thorough. This verifies
818 * that a transmit has been completed since the previous
819 * check AND there is at least one packet pending. The
820 * ARMED bit is set to indicate a potential hang. The
821 * bit is cleared if a pause frame is received to remove
822 * false hang detection due to PFC or 802.3x frames. By
823 * requiring this to fail twice we avoid races with
824 * pfc clearing the ARMED bit and conditions where we
825 * run the check_tx_hang logic with a transmit completion
826 * pending but without time to complete it yet.
828 if ((tx_done_old == tx_done) && tx_pending) {
829 /* make sure it is true for two checks in a row */
830 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
833 /* update completed stats and continue */
834 tx_ring->tx_stats.tx_done_old = tx_done;
835 /* reset the countdown */
836 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
843 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
844 * @adapter: driver private struct
846 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
849 /* Do the reset outside of interrupt context */
850 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
851 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
852 e_warn(drv, "initiating reset due to tx timeout\n");
853 ixgbe_service_event_schedule(adapter);
858 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
859 * @q_vector: structure containing interrupt and ring information
860 * @tx_ring: tx ring to clean
862 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
863 struct ixgbe_ring *tx_ring)
865 struct ixgbe_adapter *adapter = q_vector->adapter;
866 struct ixgbe_tx_buffer *tx_buffer;
867 union ixgbe_adv_tx_desc *tx_desc;
868 unsigned int total_bytes = 0, total_packets = 0;
869 unsigned int budget = q_vector->tx.work_limit;
870 unsigned int i = tx_ring->next_to_clean;
872 if (test_bit(__IXGBE_DOWN, &adapter->state))
875 tx_buffer = &tx_ring->tx_buffer_info[i];
876 tx_desc = IXGBE_TX_DESC(tx_ring, i);
880 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
882 /* if next_to_watch is not set then there is no work pending */
886 /* prevent any other reads prior to eop_desc */
887 read_barrier_depends();
889 /* if DD is not set pending work has not been completed */
890 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
893 /* clear next_to_watch to prevent false hangs */
894 tx_buffer->next_to_watch = NULL;
896 /* update the statistics for this packet */
897 total_bytes += tx_buffer->bytecount;
898 total_packets += tx_buffer->gso_segs;
901 dev_kfree_skb_any(tx_buffer->skb);
903 /* unmap skb header data */
904 dma_unmap_single(tx_ring->dev,
905 dma_unmap_addr(tx_buffer, dma),
906 dma_unmap_len(tx_buffer, len),
909 /* clear tx_buffer data */
910 tx_buffer->skb = NULL;
911 dma_unmap_len_set(tx_buffer, len, 0);
913 /* unmap remaining buffers */
914 while (tx_desc != eop_desc) {
920 tx_buffer = tx_ring->tx_buffer_info;
921 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
924 /* unmap any remaining paged data */
925 if (dma_unmap_len(tx_buffer, len)) {
926 dma_unmap_page(tx_ring->dev,
927 dma_unmap_addr(tx_buffer, dma),
928 dma_unmap_len(tx_buffer, len),
930 dma_unmap_len_set(tx_buffer, len, 0);
934 /* move us one more past the eop_desc for start of next pkt */
940 tx_buffer = tx_ring->tx_buffer_info;
941 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
944 /* issue prefetch for next Tx descriptor */
947 /* update budget accounting */
949 } while (likely(budget));
952 tx_ring->next_to_clean = i;
953 u64_stats_update_begin(&tx_ring->syncp);
954 tx_ring->stats.bytes += total_bytes;
955 tx_ring->stats.packets += total_packets;
956 u64_stats_update_end(&tx_ring->syncp);
957 q_vector->tx.total_bytes += total_bytes;
958 q_vector->tx.total_packets += total_packets;
960 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
961 /* schedule immediate reset if we believe we hung */
962 struct ixgbe_hw *hw = &adapter->hw;
963 e_err(drv, "Detected Tx Unit Hang\n"
965 " TDH, TDT <%x>, <%x>\n"
966 " next_to_use <%x>\n"
967 " next_to_clean <%x>\n"
968 "tx_buffer_info[next_to_clean]\n"
969 " time_stamp <%lx>\n"
971 tx_ring->queue_index,
972 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
973 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
974 tx_ring->next_to_use, i,
975 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
977 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
980 "tx hang %d detected on queue %d, resetting adapter\n",
981 adapter->tx_timeout_count + 1, tx_ring->queue_index);
983 /* schedule immediate reset if we believe we hung */
984 ixgbe_tx_timeout_reset(adapter);
986 /* the adapter is about to reset, no point in enabling stuff */
990 netdev_tx_completed_queue(txring_txq(tx_ring),
991 total_packets, total_bytes);
993 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
994 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
995 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
996 /* Make sure that anybody stopping the queue after this
997 * sees the new next_to_clean.
1000 if (__netif_subqueue_stopped(tx_ring->netdev,
1001 tx_ring->queue_index)
1002 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1003 netif_wake_subqueue(tx_ring->netdev,
1004 tx_ring->queue_index);
1005 ++tx_ring->tx_stats.restart_queue;
1012 #ifdef CONFIG_IXGBE_DCA
1013 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1014 struct ixgbe_ring *tx_ring,
1017 struct ixgbe_hw *hw = &adapter->hw;
1018 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1021 switch (hw->mac.type) {
1022 case ixgbe_mac_82598EB:
1023 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1025 case ixgbe_mac_82599EB:
1026 case ixgbe_mac_X540:
1027 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1028 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1031 /* for unknown hardware do not write register */
1036 * We can enable relaxed ordering for reads, but not writes when
1037 * DCA is enabled. This is due to a known issue in some chipsets
1038 * which will cause the DCA tag to be cleared.
1040 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1041 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1042 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1044 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1047 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1048 struct ixgbe_ring *rx_ring,
1051 struct ixgbe_hw *hw = &adapter->hw;
1052 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1053 u8 reg_idx = rx_ring->reg_idx;
1056 switch (hw->mac.type) {
1057 case ixgbe_mac_82599EB:
1058 case ixgbe_mac_X540:
1059 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1066 * We can enable relaxed ordering for reads, but not writes when
1067 * DCA is enabled. This is due to a known issue in some chipsets
1068 * which will cause the DCA tag to be cleared.
1070 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1071 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1073 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1076 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1078 struct ixgbe_adapter *adapter = q_vector->adapter;
1079 struct ixgbe_ring *ring;
1080 int cpu = get_cpu();
1082 if (q_vector->cpu == cpu)
1085 ixgbe_for_each_ring(ring, q_vector->tx)
1086 ixgbe_update_tx_dca(adapter, ring, cpu);
1088 ixgbe_for_each_ring(ring, q_vector->rx)
1089 ixgbe_update_rx_dca(adapter, ring, cpu);
1091 q_vector->cpu = cpu;
1096 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1100 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1103 /* always use CB2 mode, difference is masked in the CB driver */
1104 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1106 for (i = 0; i < adapter->num_q_vectors; i++) {
1107 adapter->q_vector[i]->cpu = -1;
1108 ixgbe_update_dca(adapter->q_vector[i]);
1112 static int __ixgbe_notify_dca(struct device *dev, void *data)
1114 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1115 unsigned long event = *(unsigned long *)data;
1117 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1121 case DCA_PROVIDER_ADD:
1122 /* if we're already enabled, don't do it again */
1123 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1125 if (dca_add_requester(dev) == 0) {
1126 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1127 ixgbe_setup_dca(adapter);
1130 /* Fall Through since DCA is disabled. */
1131 case DCA_PROVIDER_REMOVE:
1132 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1133 dca_remove_requester(dev);
1134 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1135 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1143 #endif /* CONFIG_IXGBE_DCA */
1144 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1145 union ixgbe_adv_rx_desc *rx_desc,
1146 struct sk_buff *skb)
1148 if (ring->netdev->features & NETIF_F_RXHASH)
1149 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1154 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1155 * @ring: structure containing ring specific data
1156 * @rx_desc: advanced rx descriptor
1158 * Returns : true if it is FCoE pkt
1160 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1161 union ixgbe_adv_rx_desc *rx_desc)
1163 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1165 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1166 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1167 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1168 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1171 #endif /* IXGBE_FCOE */
1173 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1174 * @ring: structure containing ring specific data
1175 * @rx_desc: current Rx descriptor being processed
1176 * @skb: skb currently being received and modified
1178 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1179 union ixgbe_adv_rx_desc *rx_desc,
1180 struct sk_buff *skb)
1182 skb_checksum_none_assert(skb);
1184 /* Rx csum disabled */
1185 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1188 /* if IP and error */
1189 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1190 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1191 ring->rx_stats.csum_err++;
1195 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1198 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1199 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1202 * 82599 errata, UDP frames with a 0 checksum can be marked as
1205 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1206 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1209 ring->rx_stats.csum_err++;
1213 /* It must be a TCP or UDP packet with a valid checksum */
1214 skb->ip_summed = CHECKSUM_UNNECESSARY;
1217 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1219 rx_ring->next_to_use = val;
1221 /* update next to alloc since we have filled the ring */
1222 rx_ring->next_to_alloc = val;
1224 * Force memory writes to complete before letting h/w
1225 * know there are new descriptors to fetch. (Only
1226 * applicable for weak-ordered memory model archs,
1230 writel(val, rx_ring->tail);
1233 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1234 struct ixgbe_rx_buffer *bi)
1236 struct page *page = bi->page;
1237 dma_addr_t dma = bi->dma;
1239 /* since we are recycling buffers we should seldom need to alloc */
1243 /* alloc new page for storage */
1244 if (likely(!page)) {
1245 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1246 bi->skb, ixgbe_rx_pg_order(rx_ring));
1247 if (unlikely(!page)) {
1248 rx_ring->rx_stats.alloc_rx_page_failed++;
1254 /* map page for use */
1255 dma = dma_map_page(rx_ring->dev, page, 0,
1256 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1259 * if mapping failed free memory back to system since
1260 * there isn't much point in holding memory we can't use
1262 if (dma_mapping_error(rx_ring->dev, dma)) {
1263 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1266 rx_ring->rx_stats.alloc_rx_page_failed++;
1271 bi->page_offset = 0;
1277 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1278 * @rx_ring: ring to place buffers on
1279 * @cleaned_count: number of buffers to replace
1281 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1283 union ixgbe_adv_rx_desc *rx_desc;
1284 struct ixgbe_rx_buffer *bi;
1285 u16 i = rx_ring->next_to_use;
1291 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1292 bi = &rx_ring->rx_buffer_info[i];
1293 i -= rx_ring->count;
1296 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1300 * Refresh the desc even if buffer_addrs didn't change
1301 * because each write-back erases this info.
1303 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1309 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1310 bi = rx_ring->rx_buffer_info;
1311 i -= rx_ring->count;
1314 /* clear the hdr_addr for the next_to_use descriptor */
1315 rx_desc->read.hdr_addr = 0;
1318 } while (cleaned_count);
1320 i += rx_ring->count;
1322 if (rx_ring->next_to_use != i)
1323 ixgbe_release_rx_desc(rx_ring, i);
1327 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1328 * @data: pointer to the start of the headers
1329 * @max_len: total length of section to find headers in
1331 * This function is meant to determine the length of headers that will
1332 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1333 * motivation of doing this is to only perform one pull for IPv4 TCP
1334 * packets so that we can do basic things like calculating the gso_size
1335 * based on the average data per packet.
1337 static unsigned int ixgbe_get_headlen(unsigned char *data,
1338 unsigned int max_len)
1341 unsigned char *network;
1344 struct vlan_hdr *vlan;
1347 struct ipv6hdr *ipv6;
1350 u8 nexthdr = 0; /* default to not TCP */
1353 /* this should never happen, but better safe than sorry */
1354 if (max_len < ETH_HLEN)
1357 /* initialize network frame pointer */
1360 /* set first protocol and move network header forward */
1361 protocol = hdr.eth->h_proto;
1362 hdr.network += ETH_HLEN;
1364 /* handle any vlan tag if present */
1365 if (protocol == __constant_htons(ETH_P_8021Q)) {
1366 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1369 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1370 hdr.network += VLAN_HLEN;
1373 /* handle L3 protocols */
1374 if (protocol == __constant_htons(ETH_P_IP)) {
1375 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1378 /* access ihl as a u8 to avoid unaligned access on ia64 */
1379 hlen = (hdr.network[0] & 0x0F) << 2;
1381 /* verify hlen meets minimum size requirements */
1382 if (hlen < sizeof(struct iphdr))
1383 return hdr.network - data;
1385 /* record next protocol if header is present */
1386 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
1387 nexthdr = hdr.ipv4->protocol;
1388 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1389 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1392 /* record next protocol */
1393 nexthdr = hdr.ipv6->nexthdr;
1394 hlen = sizeof(struct ipv6hdr);
1396 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1397 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1399 hlen = FCOE_HEADER_LEN;
1402 return hdr.network - data;
1405 /* relocate pointer to start of L4 header */
1406 hdr.network += hlen;
1408 /* finally sort out TCP/UDP */
1409 if (nexthdr == IPPROTO_TCP) {
1410 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1413 /* access doff as a u8 to avoid unaligned access on ia64 */
1414 hlen = (hdr.network[12] & 0xF0) >> 2;
1416 /* verify hlen meets minimum size requirements */
1417 if (hlen < sizeof(struct tcphdr))
1418 return hdr.network - data;
1420 hdr.network += hlen;
1421 } else if (nexthdr == IPPROTO_UDP) {
1422 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1425 hdr.network += sizeof(struct udphdr);
1429 * If everything has gone correctly hdr.network should be the
1430 * data section of the packet and will be the end of the header.
1431 * If not then it probably represents the end of the last recognized
1434 if ((hdr.network - data) < max_len)
1435 return hdr.network - data;
1440 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1441 struct sk_buff *skb)
1443 u16 hdr_len = skb_headlen(skb);
1445 /* set gso_size to avoid messing up TCP MSS */
1446 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1447 IXGBE_CB(skb)->append_cnt);
1448 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1451 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1452 struct sk_buff *skb)
1454 /* if append_cnt is 0 then frame is not RSC */
1455 if (!IXGBE_CB(skb)->append_cnt)
1458 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1459 rx_ring->rx_stats.rsc_flush++;
1461 ixgbe_set_rsc_gso_size(rx_ring, skb);
1463 /* gso_size is computed using append_cnt so always clear it last */
1464 IXGBE_CB(skb)->append_cnt = 0;
1468 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1469 * @rx_ring: rx descriptor ring packet is being transacted on
1470 * @rx_desc: pointer to the EOP Rx descriptor
1471 * @skb: pointer to current skb being populated
1473 * This function checks the ring, descriptor, and packet information in
1474 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1475 * other fields within the skb.
1477 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1478 union ixgbe_adv_rx_desc *rx_desc,
1479 struct sk_buff *skb)
1481 struct net_device *dev = rx_ring->netdev;
1483 ixgbe_update_rsc_stats(rx_ring, skb);
1485 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1487 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1489 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1491 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1492 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1493 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1494 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1497 skb_record_rx_queue(skb, rx_ring->queue_index);
1499 skb->protocol = eth_type_trans(skb, dev);
1502 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1503 struct sk_buff *skb)
1505 struct ixgbe_adapter *adapter = q_vector->adapter;
1507 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1508 napi_gro_receive(&q_vector->napi, skb);
1514 * ixgbe_is_non_eop - process handling of non-EOP buffers
1515 * @rx_ring: Rx ring being processed
1516 * @rx_desc: Rx descriptor for current buffer
1517 * @skb: Current socket buffer containing buffer in progress
1519 * This function updates next to clean. If the buffer is an EOP buffer
1520 * this function exits returning false, otherwise it will place the
1521 * sk_buff in the next buffer to be chained and return true indicating
1522 * that this is in fact a non-EOP buffer.
1524 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1525 union ixgbe_adv_rx_desc *rx_desc,
1526 struct sk_buff *skb)
1528 u32 ntc = rx_ring->next_to_clean + 1;
1530 /* fetch, update, and store next to clean */
1531 ntc = (ntc < rx_ring->count) ? ntc : 0;
1532 rx_ring->next_to_clean = ntc;
1534 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1536 /* update RSC append count if present */
1537 if (ring_is_rsc_enabled(rx_ring)) {
1538 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1539 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1541 if (unlikely(rsc_enabled)) {
1542 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1544 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1545 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1547 /* update ntc based on RSC value */
1548 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1549 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1550 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1554 /* if we are the last buffer then there is nothing else to do */
1555 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1558 /* place skb in next buffer to be received */
1559 rx_ring->rx_buffer_info[ntc].skb = skb;
1560 rx_ring->rx_stats.non_eop_descs++;
1566 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1567 * @rx_ring: rx descriptor ring packet is being transacted on
1568 * @skb: pointer to current skb being adjusted
1570 * This function is an ixgbe specific version of __pskb_pull_tail. The
1571 * main difference between this version and the original function is that
1572 * this function can make several assumptions about the state of things
1573 * that allow for significant optimizations versus the standard function.
1574 * As a result we can do things like drop a frag and maintain an accurate
1575 * truesize for the skb.
1577 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1578 struct sk_buff *skb)
1580 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1582 unsigned int pull_len;
1585 * it is valid to use page_address instead of kmap since we are
1586 * working with pages allocated out of the lomem pool per
1587 * alloc_page(GFP_ATOMIC)
1589 va = skb_frag_address(frag);
1592 * we need the header to contain the greater of either ETH_HLEN or
1593 * 60 bytes if the skb->len is less than 60 for skb_pad.
1595 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1597 /* align pull length to size of long to optimize memcpy performance */
1598 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1600 /* update all of the pointers */
1601 skb_frag_size_sub(frag, pull_len);
1602 frag->page_offset += pull_len;
1603 skb->data_len -= pull_len;
1604 skb->tail += pull_len;
1608 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1609 * @rx_ring: rx descriptor ring packet is being transacted on
1610 * @skb: pointer to current skb being updated
1612 * This function provides a basic DMA sync up for the first fragment of an
1613 * skb. The reason for doing this is that the first fragment cannot be
1614 * unmapped until we have reached the end of packet descriptor for a buffer
1617 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1618 struct sk_buff *skb)
1620 /* if the page was released unmap it, else just sync our portion */
1621 if (unlikely(IXGBE_CB(skb)->page_released)) {
1622 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1623 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1624 IXGBE_CB(skb)->page_released = false;
1626 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1628 dma_sync_single_range_for_cpu(rx_ring->dev,
1631 ixgbe_rx_bufsz(rx_ring),
1634 IXGBE_CB(skb)->dma = 0;
1638 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1639 * @rx_ring: rx descriptor ring packet is being transacted on
1640 * @rx_desc: pointer to the EOP Rx descriptor
1641 * @skb: pointer to current skb being fixed
1643 * Check for corrupted packet headers caused by senders on the local L2
1644 * embedded NIC switch not setting up their Tx Descriptors right. These
1645 * should be very rare.
1647 * Also address the case where we are pulling data in on pages only
1648 * and as such no data is present in the skb header.
1650 * In addition if skb is not at least 60 bytes we need to pad it so that
1651 * it is large enough to qualify as a valid Ethernet frame.
1653 * Returns true if an error was encountered and skb was freed.
1655 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1656 union ixgbe_adv_rx_desc *rx_desc,
1657 struct sk_buff *skb)
1659 struct net_device *netdev = rx_ring->netdev;
1661 /* verify that the packet does not have any known errors */
1662 if (unlikely(ixgbe_test_staterr(rx_desc,
1663 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1664 !(netdev->features & NETIF_F_RXALL))) {
1665 dev_kfree_skb_any(skb);
1669 /* place header in linear portion of buffer */
1670 if (skb_is_nonlinear(skb))
1671 ixgbe_pull_tail(rx_ring, skb);
1674 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1675 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1679 /* if skb_pad returns an error the skb was freed */
1680 if (unlikely(skb->len < 60)) {
1681 int pad_len = 60 - skb->len;
1683 if (skb_pad(skb, pad_len))
1685 __skb_put(skb, pad_len);
1692 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1693 * @rx_ring: rx descriptor ring to store buffers on
1694 * @old_buff: donor buffer to have page reused
1696 * Synchronizes page for reuse by the adapter
1698 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1699 struct ixgbe_rx_buffer *old_buff)
1701 struct ixgbe_rx_buffer *new_buff;
1702 u16 nta = rx_ring->next_to_alloc;
1704 new_buff = &rx_ring->rx_buffer_info[nta];
1706 /* update, and store next to alloc */
1708 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1710 /* transfer page from old buffer to new buffer */
1711 new_buff->page = old_buff->page;
1712 new_buff->dma = old_buff->dma;
1713 new_buff->page_offset = old_buff->page_offset;
1715 /* sync the buffer for use by the device */
1716 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1717 new_buff->page_offset,
1718 ixgbe_rx_bufsz(rx_ring),
1723 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1724 * @rx_ring: rx descriptor ring to transact packets on
1725 * @rx_buffer: buffer containing page to add
1726 * @rx_desc: descriptor containing length of buffer written by hardware
1727 * @skb: sk_buff to place the data into
1729 * This function will add the data contained in rx_buffer->page to the skb.
1730 * This is done either through a direct copy if the data in the buffer is
1731 * less than the skb header size, otherwise it will just attach the page as
1732 * a frag to the skb.
1734 * The function will then update the page offset if necessary and return
1735 * true if the buffer can be reused by the adapter.
1737 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1738 struct ixgbe_rx_buffer *rx_buffer,
1739 union ixgbe_adv_rx_desc *rx_desc,
1740 struct sk_buff *skb)
1742 struct page *page = rx_buffer->page;
1743 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1744 #if (PAGE_SIZE < 8192)
1745 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1747 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1748 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1749 ixgbe_rx_bufsz(rx_ring);
1752 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1753 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1755 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1757 /* we can reuse buffer as-is, just make sure it is local */
1758 if (likely(page_to_nid(page) == numa_node_id()))
1761 /* this page cannot be reused so discard it */
1766 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1767 rx_buffer->page_offset, size, truesize);
1769 /* avoid re-using remote pages */
1770 if (unlikely(page_to_nid(page) != numa_node_id()))
1773 #if (PAGE_SIZE < 8192)
1774 /* if we are only owner of page we can reuse it */
1775 if (unlikely(page_count(page) != 1))
1778 /* flip page offset to other buffer */
1779 rx_buffer->page_offset ^= truesize;
1782 * since we are the only owner of the page and we need to
1783 * increment it, just set the value to 2 in order to avoid
1784 * an unecessary locked operation
1786 atomic_set(&page->_count, 2);
1788 /* move offset up to the next cache line */
1789 rx_buffer->page_offset += truesize;
1791 if (rx_buffer->page_offset > last_offset)
1794 /* bump ref count on page before it is given to the stack */
1801 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1802 union ixgbe_adv_rx_desc *rx_desc)
1804 struct ixgbe_rx_buffer *rx_buffer;
1805 struct sk_buff *skb;
1808 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1809 page = rx_buffer->page;
1812 skb = rx_buffer->skb;
1815 void *page_addr = page_address(page) +
1816 rx_buffer->page_offset;
1818 /* prefetch first cache line of first page */
1819 prefetch(page_addr);
1820 #if L1_CACHE_BYTES < 128
1821 prefetch(page_addr + L1_CACHE_BYTES);
1824 /* allocate a skb to store the frags */
1825 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1827 if (unlikely(!skb)) {
1828 rx_ring->rx_stats.alloc_rx_buff_failed++;
1833 * we will be copying header into skb->data in
1834 * pskb_may_pull so it is in our interest to prefetch
1835 * it now to avoid a possible cache miss
1837 prefetchw(skb->data);
1840 * Delay unmapping of the first packet. It carries the
1841 * header information, HW may still access the header
1842 * after the writeback. Only unmap it when EOP is
1845 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1848 IXGBE_CB(skb)->dma = rx_buffer->dma;
1850 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1851 ixgbe_dma_sync_frag(rx_ring, skb);
1854 /* we are reusing so sync this buffer for CPU use */
1855 dma_sync_single_range_for_cpu(rx_ring->dev,
1857 rx_buffer->page_offset,
1858 ixgbe_rx_bufsz(rx_ring),
1862 /* pull page into skb */
1863 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1864 /* hand second half of page back to the ring */
1865 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1866 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1867 /* the page has been released from the ring */
1868 IXGBE_CB(skb)->page_released = true;
1870 /* we are not reusing the buffer so unmap it */
1871 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1872 ixgbe_rx_pg_size(rx_ring),
1876 /* clear contents of buffer_info */
1877 rx_buffer->skb = NULL;
1879 rx_buffer->page = NULL;
1885 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1886 * @q_vector: structure containing interrupt and ring information
1887 * @rx_ring: rx descriptor ring to transact packets on
1888 * @budget: Total limit on number of packets to process
1890 * This function provides a "bounce buffer" approach to Rx interrupt
1891 * processing. The advantage to this is that on systems that have
1892 * expensive overhead for IOMMU access this provides a means of avoiding
1893 * it by maintaining the mapping of the page to the syste.
1895 * Returns true if all work is completed without reaching budget
1897 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1898 struct ixgbe_ring *rx_ring,
1901 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1903 struct ixgbe_adapter *adapter = q_vector->adapter;
1905 unsigned int mss = 0;
1906 #endif /* IXGBE_FCOE */
1907 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1910 union ixgbe_adv_rx_desc *rx_desc;
1911 struct sk_buff *skb;
1913 /* return some buffers to hardware, one at a time is too slow */
1914 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1915 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1919 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
1921 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1925 * This memory barrier is needed to keep us from reading
1926 * any other fields out of the rx_desc until we know the
1927 * RXD_STAT_DD bit is set
1931 /* retrieve a buffer from the ring */
1932 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
1934 /* exit if we failed to retrieve a buffer */
1940 /* place incomplete frames back on ring for completion */
1941 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1944 /* verify the packet layout is correct */
1945 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1948 /* probably a little skewed due to removing CRC */
1949 total_rx_bytes += skb->len;
1951 /* populate checksum, timestamp, VLAN, and protocol */
1952 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1955 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1956 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
1957 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1958 /* include DDPed FCoE data */
1959 if (ddp_bytes > 0) {
1961 mss = rx_ring->netdev->mtu -
1962 sizeof(struct fcoe_hdr) -
1963 sizeof(struct fc_frame_header) -
1964 sizeof(struct fcoe_crc_eof);
1968 total_rx_bytes += ddp_bytes;
1969 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1973 dev_kfree_skb_any(skb);
1978 #endif /* IXGBE_FCOE */
1979 ixgbe_rx_skb(q_vector, skb);
1981 /* update budget accounting */
1983 } while (likely(total_rx_packets < budget));
1985 u64_stats_update_begin(&rx_ring->syncp);
1986 rx_ring->stats.packets += total_rx_packets;
1987 rx_ring->stats.bytes += total_rx_bytes;
1988 u64_stats_update_end(&rx_ring->syncp);
1989 q_vector->rx.total_packets += total_rx_packets;
1990 q_vector->rx.total_bytes += total_rx_bytes;
1993 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1995 return (total_rx_packets < budget);
1999 * ixgbe_configure_msix - Configure MSI-X hardware
2000 * @adapter: board private structure
2002 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2005 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2007 struct ixgbe_q_vector *q_vector;
2011 /* Populate MSIX to EITR Select */
2012 if (adapter->num_vfs > 32) {
2013 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2014 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2018 * Populate the IVAR table and set the ITR values to the
2019 * corresponding register.
2021 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2022 struct ixgbe_ring *ring;
2023 q_vector = adapter->q_vector[v_idx];
2025 ixgbe_for_each_ring(ring, q_vector->rx)
2026 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2028 ixgbe_for_each_ring(ring, q_vector->tx)
2029 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2031 ixgbe_write_eitr(q_vector);
2034 switch (adapter->hw.mac.type) {
2035 case ixgbe_mac_82598EB:
2036 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2039 case ixgbe_mac_82599EB:
2040 case ixgbe_mac_X540:
2041 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2046 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2048 /* set up to autoclear timer, and the vectors */
2049 mask = IXGBE_EIMS_ENABLE_MASK;
2050 mask &= ~(IXGBE_EIMS_OTHER |
2051 IXGBE_EIMS_MAILBOX |
2054 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2057 enum latency_range {
2061 latency_invalid = 255
2065 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2066 * @q_vector: structure containing interrupt and ring information
2067 * @ring_container: structure containing ring performance data
2069 * Stores a new ITR value based on packets and byte
2070 * counts during the last interrupt. The advantage of per interrupt
2071 * computation is faster updates and more accurate ITR for the current
2072 * traffic pattern. Constants in this function were computed
2073 * based on theoretical maximum wire speed and thresholds were set based
2074 * on testing data as well as attempting to minimize response time
2075 * while increasing bulk throughput.
2076 * this functionality is controlled by the InterruptThrottleRate module
2077 * parameter (see ixgbe_param.c)
2079 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2080 struct ixgbe_ring_container *ring_container)
2082 int bytes = ring_container->total_bytes;
2083 int packets = ring_container->total_packets;
2086 u8 itr_setting = ring_container->itr;
2091 /* simple throttlerate management
2092 * 0-10MB/s lowest (100000 ints/s)
2093 * 10-20MB/s low (20000 ints/s)
2094 * 20-1249MB/s bulk (8000 ints/s)
2096 /* what was last interrupt timeslice? */
2097 timepassed_us = q_vector->itr >> 2;
2098 if (timepassed_us == 0)
2101 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2103 switch (itr_setting) {
2104 case lowest_latency:
2105 if (bytes_perint > 10)
2106 itr_setting = low_latency;
2109 if (bytes_perint > 20)
2110 itr_setting = bulk_latency;
2111 else if (bytes_perint <= 10)
2112 itr_setting = lowest_latency;
2115 if (bytes_perint <= 20)
2116 itr_setting = low_latency;
2120 /* clear work counters since we have the values we need */
2121 ring_container->total_bytes = 0;
2122 ring_container->total_packets = 0;
2124 /* write updated itr to ring container */
2125 ring_container->itr = itr_setting;
2129 * ixgbe_write_eitr - write EITR register in hardware specific way
2130 * @q_vector: structure containing interrupt and ring information
2132 * This function is made to be called by ethtool and by the driver
2133 * when it needs to update EITR registers at runtime. Hardware
2134 * specific quirks/differences are taken care of here.
2136 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2138 struct ixgbe_adapter *adapter = q_vector->adapter;
2139 struct ixgbe_hw *hw = &adapter->hw;
2140 int v_idx = q_vector->v_idx;
2141 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2143 switch (adapter->hw.mac.type) {
2144 case ixgbe_mac_82598EB:
2145 /* must write high and low 16 bits to reset counter */
2146 itr_reg |= (itr_reg << 16);
2148 case ixgbe_mac_82599EB:
2149 case ixgbe_mac_X540:
2151 * set the WDIS bit to not clear the timer bits and cause an
2152 * immediate assertion of the interrupt
2154 itr_reg |= IXGBE_EITR_CNT_WDIS;
2159 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2162 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2164 u32 new_itr = q_vector->itr;
2167 ixgbe_update_itr(q_vector, &q_vector->tx);
2168 ixgbe_update_itr(q_vector, &q_vector->rx);
2170 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2172 switch (current_itr) {
2173 /* counts and packets in update_itr are dependent on these numbers */
2174 case lowest_latency:
2175 new_itr = IXGBE_100K_ITR;
2178 new_itr = IXGBE_20K_ITR;
2181 new_itr = IXGBE_8K_ITR;
2187 if (new_itr != q_vector->itr) {
2188 /* do an exponential smoothing */
2189 new_itr = (10 * new_itr * q_vector->itr) /
2190 ((9 * new_itr) + q_vector->itr);
2192 /* save the algorithm value here */
2193 q_vector->itr = new_itr;
2195 ixgbe_write_eitr(q_vector);
2200 * ixgbe_check_overtemp_subtask - check for over temperature
2201 * @adapter: pointer to adapter
2203 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2205 struct ixgbe_hw *hw = &adapter->hw;
2206 u32 eicr = adapter->interrupt_event;
2208 if (test_bit(__IXGBE_DOWN, &adapter->state))
2211 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2212 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2215 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2217 switch (hw->device_id) {
2218 case IXGBE_DEV_ID_82599_T3_LOM:
2220 * Since the warning interrupt is for both ports
2221 * we don't have to check if:
2222 * - This interrupt wasn't for our port.
2223 * - We may have missed the interrupt so always have to
2224 * check if we got a LSC
2226 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2227 !(eicr & IXGBE_EICR_LSC))
2230 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2232 bool link_up = false;
2234 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2240 /* Check if this is not due to overtemp */
2241 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2246 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2251 "Network adapter has been stopped because it has over heated. "
2252 "Restart the computer. If the problem persists, "
2253 "power off the system and replace the adapter\n");
2255 adapter->interrupt_event = 0;
2258 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2260 struct ixgbe_hw *hw = &adapter->hw;
2262 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2263 (eicr & IXGBE_EICR_GPI_SDP1)) {
2264 e_crit(probe, "Fan has stopped, replace the adapter\n");
2265 /* write to clear the interrupt */
2266 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2270 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2272 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2275 switch (adapter->hw.mac.type) {
2276 case ixgbe_mac_82599EB:
2278 * Need to check link state so complete overtemp check
2281 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2282 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2283 adapter->interrupt_event = eicr;
2284 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2285 ixgbe_service_event_schedule(adapter);
2289 case ixgbe_mac_X540:
2290 if (!(eicr & IXGBE_EICR_TS))
2298 "Network adapter has been stopped because it has over heated. "
2299 "Restart the computer. If the problem persists, "
2300 "power off the system and replace the adapter\n");
2303 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2305 struct ixgbe_hw *hw = &adapter->hw;
2307 if (eicr & IXGBE_EICR_GPI_SDP2) {
2308 /* Clear the interrupt */
2309 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2310 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2311 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2312 ixgbe_service_event_schedule(adapter);
2316 if (eicr & IXGBE_EICR_GPI_SDP1) {
2317 /* Clear the interrupt */
2318 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2319 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2320 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2321 ixgbe_service_event_schedule(adapter);
2326 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2328 struct ixgbe_hw *hw = &adapter->hw;
2331 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2332 adapter->link_check_timeout = jiffies;
2333 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2334 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2335 IXGBE_WRITE_FLUSH(hw);
2336 ixgbe_service_event_schedule(adapter);
2340 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2344 struct ixgbe_hw *hw = &adapter->hw;
2346 switch (hw->mac.type) {
2347 case ixgbe_mac_82598EB:
2348 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2349 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2351 case ixgbe_mac_82599EB:
2352 case ixgbe_mac_X540:
2353 mask = (qmask & 0xFFFFFFFF);
2355 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2356 mask = (qmask >> 32);
2358 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2363 /* skip the flush */
2366 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2370 struct ixgbe_hw *hw = &adapter->hw;
2372 switch (hw->mac.type) {
2373 case ixgbe_mac_82598EB:
2374 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2375 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2377 case ixgbe_mac_82599EB:
2378 case ixgbe_mac_X540:
2379 mask = (qmask & 0xFFFFFFFF);
2381 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2382 mask = (qmask >> 32);
2384 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2389 /* skip the flush */
2393 * ixgbe_irq_enable - Enable default interrupt generation settings
2394 * @adapter: board private structure
2396 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2399 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2401 /* don't reenable LSC while waiting for link */
2402 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2403 mask &= ~IXGBE_EIMS_LSC;
2405 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2406 switch (adapter->hw.mac.type) {
2407 case ixgbe_mac_82599EB:
2408 mask |= IXGBE_EIMS_GPI_SDP0;
2410 case ixgbe_mac_X540:
2411 mask |= IXGBE_EIMS_TS;
2416 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2417 mask |= IXGBE_EIMS_GPI_SDP1;
2418 switch (adapter->hw.mac.type) {
2419 case ixgbe_mac_82599EB:
2420 mask |= IXGBE_EIMS_GPI_SDP1;
2421 mask |= IXGBE_EIMS_GPI_SDP2;
2422 case ixgbe_mac_X540:
2423 mask |= IXGBE_EIMS_ECC;
2424 mask |= IXGBE_EIMS_MAILBOX;
2430 if (adapter->hw.mac.type == ixgbe_mac_X540)
2431 mask |= IXGBE_EIMS_TIMESYNC;
2433 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2434 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2435 mask |= IXGBE_EIMS_FLOW_DIR;
2437 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2439 ixgbe_irq_enable_queues(adapter, ~0);
2441 IXGBE_WRITE_FLUSH(&adapter->hw);
2444 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2446 struct ixgbe_adapter *adapter = data;
2447 struct ixgbe_hw *hw = &adapter->hw;
2451 * Workaround for Silicon errata. Use clear-by-write instead
2452 * of clear-by-read. Reading with EICS will return the
2453 * interrupt causes without clearing, which later be done
2454 * with the write to EICR.
2456 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2458 /* The lower 16bits of the EICR register are for the queue interrupts
2459 * which should be masked here in order to not accidently clear them if
2460 * the bits are high when ixgbe_msix_other is called. There is a race
2461 * condition otherwise which results in possible performance loss
2462 * especially if the ixgbe_msix_other interrupt is triggering
2463 * consistently (as it would when PPS is turned on for the X540 device)
2467 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2469 if (eicr & IXGBE_EICR_LSC)
2470 ixgbe_check_lsc(adapter);
2472 if (eicr & IXGBE_EICR_MAILBOX)
2473 ixgbe_msg_task(adapter);
2475 switch (hw->mac.type) {
2476 case ixgbe_mac_82599EB:
2477 case ixgbe_mac_X540:
2478 if (eicr & IXGBE_EICR_ECC)
2479 e_info(link, "Received unrecoverable ECC Err, please "
2481 /* Handle Flow Director Full threshold interrupt */
2482 if (eicr & IXGBE_EICR_FLOW_DIR) {
2483 int reinit_count = 0;
2485 for (i = 0; i < adapter->num_tx_queues; i++) {
2486 struct ixgbe_ring *ring = adapter->tx_ring[i];
2487 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2492 /* no more flow director interrupts until after init */
2493 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2494 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2495 ixgbe_service_event_schedule(adapter);
2498 ixgbe_check_sfp_event(adapter, eicr);
2499 ixgbe_check_overtemp_event(adapter, eicr);
2505 ixgbe_check_fan_failure(adapter, eicr);
2507 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2508 ixgbe_ptp_check_pps_event(adapter, eicr);
2510 /* re-enable the original interrupt state, no lsc, no queues */
2511 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2512 ixgbe_irq_enable(adapter, false, false);
2517 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2519 struct ixgbe_q_vector *q_vector = data;
2521 /* EIAM disabled interrupts (on this vector) for us */
2523 if (q_vector->rx.ring || q_vector->tx.ring)
2524 napi_schedule(&q_vector->napi);
2530 * ixgbe_poll - NAPI Rx polling callback
2531 * @napi: structure for representing this polling device
2532 * @budget: how many packets driver is allowed to clean
2534 * This function is used for legacy and MSI, NAPI mode
2536 int ixgbe_poll(struct napi_struct *napi, int budget)
2538 struct ixgbe_q_vector *q_vector =
2539 container_of(napi, struct ixgbe_q_vector, napi);
2540 struct ixgbe_adapter *adapter = q_vector->adapter;
2541 struct ixgbe_ring *ring;
2542 int per_ring_budget;
2543 bool clean_complete = true;
2545 #ifdef CONFIG_IXGBE_DCA
2546 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2547 ixgbe_update_dca(q_vector);
2550 ixgbe_for_each_ring(ring, q_vector->tx)
2551 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2553 /* attempt to distribute budget to each queue fairly, but don't allow
2554 * the budget to go below 1 because we'll exit polling */
2555 if (q_vector->rx.count > 1)
2556 per_ring_budget = max(budget/q_vector->rx.count, 1);
2558 per_ring_budget = budget;
2560 ixgbe_for_each_ring(ring, q_vector->rx)
2561 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2564 /* If all work not completed, return budget and keep polling */
2565 if (!clean_complete)
2568 /* all work done, exit the polling mode */
2569 napi_complete(napi);
2570 if (adapter->rx_itr_setting & 1)
2571 ixgbe_set_itr(q_vector);
2572 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2573 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2579 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2580 * @adapter: board private structure
2582 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2583 * interrupts from the kernel.
2585 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2587 struct net_device *netdev = adapter->netdev;
2591 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2592 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2593 struct msix_entry *entry = &adapter->msix_entries[vector];
2595 if (q_vector->tx.ring && q_vector->rx.ring) {
2596 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2597 "%s-%s-%d", netdev->name, "TxRx", ri++);
2599 } else if (q_vector->rx.ring) {
2600 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2601 "%s-%s-%d", netdev->name, "rx", ri++);
2602 } else if (q_vector->tx.ring) {
2603 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2604 "%s-%s-%d", netdev->name, "tx", ti++);
2606 /* skip this unused q_vector */
2609 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2610 q_vector->name, q_vector);
2612 e_err(probe, "request_irq failed for MSIX interrupt "
2613 "Error: %d\n", err);
2614 goto free_queue_irqs;
2616 /* If Flow Director is enabled, set interrupt affinity */
2617 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2618 /* assign the mask for this irq */
2619 irq_set_affinity_hint(entry->vector,
2620 &q_vector->affinity_mask);
2624 err = request_irq(adapter->msix_entries[vector].vector,
2625 ixgbe_msix_other, 0, netdev->name, adapter);
2627 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2628 goto free_queue_irqs;
2636 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2638 free_irq(adapter->msix_entries[vector].vector,
2639 adapter->q_vector[vector]);
2641 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2642 pci_disable_msix(adapter->pdev);
2643 kfree(adapter->msix_entries);
2644 adapter->msix_entries = NULL;
2649 * ixgbe_intr - legacy mode Interrupt Handler
2650 * @irq: interrupt number
2651 * @data: pointer to a network interface device structure
2653 static irqreturn_t ixgbe_intr(int irq, void *data)
2655 struct ixgbe_adapter *adapter = data;
2656 struct ixgbe_hw *hw = &adapter->hw;
2657 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2661 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2662 * before the read of EICR.
2664 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2666 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2667 * therefore no explicit interrupt disable is necessary */
2668 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2671 * shared interrupt alert!
2672 * make sure interrupts are enabled because the read will
2673 * have disabled interrupts due to EIAM
2674 * finish the workaround of silicon errata on 82598. Unmask
2675 * the interrupt that we masked before the EICR read.
2677 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2678 ixgbe_irq_enable(adapter, true, true);
2679 return IRQ_NONE; /* Not our interrupt */
2682 if (eicr & IXGBE_EICR_LSC)
2683 ixgbe_check_lsc(adapter);
2685 switch (hw->mac.type) {
2686 case ixgbe_mac_82599EB:
2687 ixgbe_check_sfp_event(adapter, eicr);
2689 case ixgbe_mac_X540:
2690 if (eicr & IXGBE_EICR_ECC)
2691 e_info(link, "Received unrecoverable ECC err, please "
2693 ixgbe_check_overtemp_event(adapter, eicr);
2699 ixgbe_check_fan_failure(adapter, eicr);
2700 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2701 ixgbe_ptp_check_pps_event(adapter, eicr);
2703 /* would disable interrupts here but EIAM disabled it */
2704 napi_schedule(&q_vector->napi);
2707 * re-enable link(maybe) and non-queue interrupts, no flush.
2708 * ixgbe_poll will re-enable the queue interrupts
2710 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2711 ixgbe_irq_enable(adapter, false, false);
2717 * ixgbe_request_irq - initialize interrupts
2718 * @adapter: board private structure
2720 * Attempts to configure interrupts using the best available
2721 * capabilities of the hardware and kernel.
2723 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2725 struct net_device *netdev = adapter->netdev;
2728 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2729 err = ixgbe_request_msix_irqs(adapter);
2730 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2731 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2732 netdev->name, adapter);
2734 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2735 netdev->name, adapter);
2738 e_err(probe, "request_irq failed, Error %d\n", err);
2743 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2747 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2748 free_irq(adapter->pdev->irq, adapter);
2752 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2753 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2754 struct msix_entry *entry = &adapter->msix_entries[vector];
2756 /* free only the irqs that were actually requested */
2757 if (!q_vector->rx.ring && !q_vector->tx.ring)
2760 /* clear the affinity_mask in the IRQ descriptor */
2761 irq_set_affinity_hint(entry->vector, NULL);
2763 free_irq(entry->vector, q_vector);
2766 free_irq(adapter->msix_entries[vector++].vector, adapter);
2770 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2771 * @adapter: board private structure
2773 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2775 switch (adapter->hw.mac.type) {
2776 case ixgbe_mac_82598EB:
2777 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2779 case ixgbe_mac_82599EB:
2780 case ixgbe_mac_X540:
2781 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2782 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2783 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2788 IXGBE_WRITE_FLUSH(&adapter->hw);
2789 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2792 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2793 synchronize_irq(adapter->msix_entries[vector].vector);
2795 synchronize_irq(adapter->msix_entries[vector++].vector);
2797 synchronize_irq(adapter->pdev->irq);
2802 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2805 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2807 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2809 ixgbe_write_eitr(q_vector);
2811 ixgbe_set_ivar(adapter, 0, 0, 0);
2812 ixgbe_set_ivar(adapter, 1, 0, 0);
2814 e_info(hw, "Legacy interrupt IVAR setup done\n");
2818 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2819 * @adapter: board private structure
2820 * @ring: structure containing ring specific data
2822 * Configure the Tx descriptor ring after a reset.
2824 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2825 struct ixgbe_ring *ring)
2827 struct ixgbe_hw *hw = &adapter->hw;
2828 u64 tdba = ring->dma;
2830 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2831 u8 reg_idx = ring->reg_idx;
2833 /* disable queue to avoid issues while updating state */
2834 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2835 IXGBE_WRITE_FLUSH(hw);
2837 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2838 (tdba & DMA_BIT_MASK(32)));
2839 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2840 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2841 ring->count * sizeof(union ixgbe_adv_tx_desc));
2842 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2843 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2844 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2847 * set WTHRESH to encourage burst writeback, it should not be set
2848 * higher than 1 when:
2849 * - ITR is 0 as it could cause false TX hangs
2850 * - ITR is set to > 100k int/sec and BQL is enabled
2852 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2853 * to or less than the number of on chip descriptors, which is
2856 #if IS_ENABLED(CONFIG_BQL)
2857 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2859 if (!ring->q_vector || (ring->q_vector->itr < 8))
2861 txdctl |= (1 << 16); /* WTHRESH = 1 */
2863 txdctl |= (8 << 16); /* WTHRESH = 8 */
2866 * Setting PTHRESH to 32 both improves performance
2867 * and avoids a TX hang with DFP enabled
2869 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2870 32; /* PTHRESH = 32 */
2872 /* reinitialize flowdirector state */
2873 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2874 ring->atr_sample_rate = adapter->atr_sample_rate;
2875 ring->atr_count = 0;
2876 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2878 ring->atr_sample_rate = 0;
2881 /* initialize XPS */
2882 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
2883 struct ixgbe_q_vector *q_vector = ring->q_vector;
2886 netif_set_xps_queue(adapter->netdev,
2887 &q_vector->affinity_mask,
2891 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2894 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2896 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2897 if (hw->mac.type == ixgbe_mac_82598EB &&
2898 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2901 /* poll to verify queue is enabled */
2903 usleep_range(1000, 2000);
2904 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2905 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2907 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2910 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2912 struct ixgbe_hw *hw = &adapter->hw;
2914 u8 tcs = netdev_get_num_tc(adapter->netdev);
2916 if (hw->mac.type == ixgbe_mac_82598EB)
2919 /* disable the arbiter while setting MTQC */
2920 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2921 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2922 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2924 /* set transmit pool layout */
2925 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2926 mtqc = IXGBE_MTQC_VT_ENA;
2928 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2930 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2931 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2932 mtqc |= IXGBE_MTQC_32VF;
2934 mtqc |= IXGBE_MTQC_64VF;
2937 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2939 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2941 mtqc = IXGBE_MTQC_64Q_1PB;
2944 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
2946 /* Enable Security TX Buffer IFG for multiple pb */
2948 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2949 sectx |= IXGBE_SECTX_DCB;
2950 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
2953 /* re-enable the arbiter */
2954 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2955 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2959 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2960 * @adapter: board private structure
2962 * Configure the Tx unit of the MAC after a reset.
2964 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2966 struct ixgbe_hw *hw = &adapter->hw;
2970 ixgbe_setup_mtqc(adapter);
2972 if (hw->mac.type != ixgbe_mac_82598EB) {
2973 /* DMATXCTL.EN must be before Tx queues are enabled */
2974 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2975 dmatxctl |= IXGBE_DMATXCTL_TE;
2976 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2979 /* Setup the HW Tx Head and Tail descriptor pointers */
2980 for (i = 0; i < adapter->num_tx_queues; i++)
2981 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2984 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2985 struct ixgbe_ring *ring)
2987 struct ixgbe_hw *hw = &adapter->hw;
2988 u8 reg_idx = ring->reg_idx;
2989 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2991 srrctl |= IXGBE_SRRCTL_DROP_EN;
2993 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2996 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2997 struct ixgbe_ring *ring)
2999 struct ixgbe_hw *hw = &adapter->hw;
3000 u8 reg_idx = ring->reg_idx;
3001 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3003 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3005 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3008 #ifdef CONFIG_IXGBE_DCB
3009 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3011 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3015 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3017 if (adapter->ixgbe_ieee_pfc)
3018 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3021 * We should set the drop enable bit if:
3024 * Number of Rx queues > 1 and flow control is disabled
3026 * This allows us to avoid head of line blocking for security
3027 * and performance reasons.
3029 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3030 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3031 for (i = 0; i < adapter->num_rx_queues; i++)
3032 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3034 for (i = 0; i < adapter->num_rx_queues; i++)
3035 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3039 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3041 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3042 struct ixgbe_ring *rx_ring)
3044 struct ixgbe_hw *hw = &adapter->hw;
3046 u8 reg_idx = rx_ring->reg_idx;
3048 if (hw->mac.type == ixgbe_mac_82598EB) {
3049 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3052 * if VMDq is not active we must program one srrctl register
3053 * per RSS queue since we have enabled RDRXCTL.MVMEN
3058 /* configure header buffer length, needed for RSC */
3059 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3061 /* configure the packet buffer length */
3062 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3064 /* configure descriptor type */
3065 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3067 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3070 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3072 struct ixgbe_hw *hw = &adapter->hw;
3073 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3074 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3075 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3076 u32 mrqc = 0, reta = 0;
3079 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3082 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3083 * make full use of any rings they may have. We will use the
3084 * PSRTYPE register to control how many rings we use within the PF.
3086 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3089 /* Fill out hash function seeds */
3090 for (i = 0; i < 10; i++)
3091 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3093 /* Fill out redirection table */
3094 for (i = 0, j = 0; i < 128; i++, j++) {
3097 /* reta = 4-byte sliding window of
3098 * 0x00..(indices-1)(indices-1)00..etc. */
3099 reta = (reta << 8) | (j * 0x11);
3101 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3104 /* Disable indicating checksum in descriptor, enables RSS hash */
3105 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3106 rxcsum |= IXGBE_RXCSUM_PCSD;
3107 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3109 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3110 if (adapter->ring_feature[RING_F_RSS].mask)
3111 mrqc = IXGBE_MRQC_RSSEN;
3113 u8 tcs = netdev_get_num_tc(adapter->netdev);
3115 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3117 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3119 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3120 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3121 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3123 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3126 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3128 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3130 mrqc = IXGBE_MRQC_RSSEN;
3134 /* Perform hash on these packet types */
3135 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3136 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3137 IXGBE_MRQC_RSS_FIELD_IPV6 |
3138 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3140 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3141 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3142 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3143 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3145 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3149 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3150 * @adapter: address of board private structure
3151 * @index: index of ring to set
3153 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3154 struct ixgbe_ring *ring)
3156 struct ixgbe_hw *hw = &adapter->hw;
3158 u8 reg_idx = ring->reg_idx;
3160 if (!ring_is_rsc_enabled(ring))
3163 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3164 rscctrl |= IXGBE_RSCCTL_RSCEN;
3166 * we must limit the number of descriptors so that the
3167 * total size of max desc * buf_len is not greater
3170 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3171 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3174 #define IXGBE_MAX_RX_DESC_POLL 10
3175 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3176 struct ixgbe_ring *ring)
3178 struct ixgbe_hw *hw = &adapter->hw;
3179 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3181 u8 reg_idx = ring->reg_idx;
3183 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3184 if (hw->mac.type == ixgbe_mac_82598EB &&
3185 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3189 usleep_range(1000, 2000);
3190 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3191 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3194 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3195 "the polling period\n", reg_idx);
3199 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3200 struct ixgbe_ring *ring)
3202 struct ixgbe_hw *hw = &adapter->hw;
3203 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3205 u8 reg_idx = ring->reg_idx;
3207 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3208 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3210 /* write value back with RXDCTL.ENABLE bit cleared */
3211 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3213 if (hw->mac.type == ixgbe_mac_82598EB &&
3214 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3217 /* the hardware may take up to 100us to really disable the rx queue */
3220 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3221 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3224 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3225 "the polling period\n", reg_idx);
3229 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3230 struct ixgbe_ring *ring)
3232 struct ixgbe_hw *hw = &adapter->hw;
3233 u64 rdba = ring->dma;
3235 u8 reg_idx = ring->reg_idx;
3237 /* disable queue to avoid issues while updating state */
3238 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3239 ixgbe_disable_rx_queue(adapter, ring);
3241 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3242 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3243 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3244 ring->count * sizeof(union ixgbe_adv_rx_desc));
3245 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3246 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3247 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3249 ixgbe_configure_srrctl(adapter, ring);
3250 ixgbe_configure_rscctl(adapter, ring);
3252 if (hw->mac.type == ixgbe_mac_82598EB) {
3254 * enable cache line friendly hardware writes:
3255 * PTHRESH=32 descriptors (half the internal cache),
3256 * this also removes ugly rx_no_buffer_count increment
3257 * HTHRESH=4 descriptors (to minimize latency on fetch)
3258 * WTHRESH=8 burst writeback up to two cache lines
3260 rxdctl &= ~0x3FFFFF;
3264 /* enable receive descriptor ring */
3265 rxdctl |= IXGBE_RXDCTL_ENABLE;
3266 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3268 ixgbe_rx_desc_queue_enable(adapter, ring);
3269 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3272 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3274 struct ixgbe_hw *hw = &adapter->hw;
3275 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3278 /* PSRTYPE must be initialized in non 82598 adapters */
3279 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3280 IXGBE_PSRTYPE_UDPHDR |
3281 IXGBE_PSRTYPE_IPV4HDR |
3282 IXGBE_PSRTYPE_L2HDR |
3283 IXGBE_PSRTYPE_IPV6HDR;
3285 if (hw->mac.type == ixgbe_mac_82598EB)
3293 for (p = 0; p < adapter->num_rx_pools; p++)
3294 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
3298 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3300 struct ixgbe_hw *hw = &adapter->hw;
3301 u32 reg_offset, vf_shift;
3302 u32 gcr_ext, vmdctl;
3305 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3308 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3309 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3310 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3311 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3312 vmdctl |= IXGBE_VT_CTL_REPLEN;
3313 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3315 vf_shift = VMDQ_P(0) % 32;
3316 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3318 /* Enable only the PF's pool for Tx/Rx */
3319 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3320 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3321 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3322 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3323 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3324 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3326 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3327 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3330 * Set up VF register offsets for selected VT Mode,
3331 * i.e. 32 or 64 VFs for SR-IOV
3333 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3334 case IXGBE_82599_VMDQ_8Q_MASK:
3335 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3337 case IXGBE_82599_VMDQ_4Q_MASK:
3338 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3341 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3345 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3348 /* Enable MAC Anti-Spoofing */
3349 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3351 /* For VFs that have spoof checking turned off */
3352 for (i = 0; i < adapter->num_vfs; i++) {
3353 if (!adapter->vfinfo[i].spoofchk_enabled)
3354 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3358 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3360 struct ixgbe_hw *hw = &adapter->hw;
3361 struct net_device *netdev = adapter->netdev;
3362 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3363 struct ixgbe_ring *rx_ring;
3368 /* adjust max frame to be able to do baby jumbo for FCoE */
3369 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3370 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3371 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3373 #endif /* IXGBE_FCOE */
3375 /* adjust max frame to be at least the size of a standard frame */
3376 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3377 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3379 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3380 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3381 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3382 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3384 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3387 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3388 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3389 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3390 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3393 * Setup the HW Rx Head and Tail Descriptor Pointers and
3394 * the Base and Length of the Rx Descriptor Ring
3396 for (i = 0; i < adapter->num_rx_queues; i++) {
3397 rx_ring = adapter->rx_ring[i];
3398 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3399 set_ring_rsc_enabled(rx_ring);
3401 clear_ring_rsc_enabled(rx_ring);
3405 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3407 struct ixgbe_hw *hw = &adapter->hw;
3408 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3410 switch (hw->mac.type) {
3411 case ixgbe_mac_82598EB:
3413 * For VMDq support of different descriptor types or
3414 * buffer sizes through the use of multiple SRRCTL
3415 * registers, RDRXCTL.MVMEN must be set to 1
3417 * also, the manual doesn't mention it clearly but DCA hints
3418 * will only use queue 0's tags unless this bit is set. Side
3419 * effects of setting this bit are only that SRRCTL must be
3420 * fully programmed [0..15]
3422 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3424 case ixgbe_mac_82599EB:
3425 case ixgbe_mac_X540:
3426 /* Disable RSC for ACK packets */
3427 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3428 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3429 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3430 /* hardware requires some bits to be set by default */
3431 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3432 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3435 /* We should do nothing since we don't know this hardware */
3439 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3443 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3444 * @adapter: board private structure
3446 * Configure the Rx unit of the MAC after a reset.
3448 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3450 struct ixgbe_hw *hw = &adapter->hw;
3454 /* disable receives while setting up the descriptors */
3455 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3456 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3458 ixgbe_setup_psrtype(adapter);
3459 ixgbe_setup_rdrxctl(adapter);
3461 /* Program registers for the distribution of queues */
3462 ixgbe_setup_mrqc(adapter);
3464 /* set_rx_buffer_len must be called before ring initialization */
3465 ixgbe_set_rx_buffer_len(adapter);
3468 * Setup the HW Rx Head and Tail Descriptor Pointers and
3469 * the Base and Length of the Rx Descriptor Ring
3471 for (i = 0; i < adapter->num_rx_queues; i++)
3472 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3474 /* disable drop enable for 82598 parts */
3475 if (hw->mac.type == ixgbe_mac_82598EB)
3476 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3478 /* enable all receives */
3479 rxctrl |= IXGBE_RXCTRL_RXEN;
3480 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3483 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3484 __be16 proto, u16 vid)
3486 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3487 struct ixgbe_hw *hw = &adapter->hw;
3489 /* add VID to filter table */
3490 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3491 set_bit(vid, adapter->active_vlans);
3496 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3497 __be16 proto, u16 vid)
3499 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3500 struct ixgbe_hw *hw = &adapter->hw;
3502 /* remove VID from filter table */
3503 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3504 clear_bit(vid, adapter->active_vlans);
3510 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3511 * @adapter: driver data
3513 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3515 struct ixgbe_hw *hw = &adapter->hw;
3518 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3519 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3520 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3524 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3525 * @adapter: driver data
3527 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3529 struct ixgbe_hw *hw = &adapter->hw;
3532 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3533 vlnctrl |= IXGBE_VLNCTRL_VFE;
3534 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3535 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3539 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3540 * @adapter: driver data
3542 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3544 struct ixgbe_hw *hw = &adapter->hw;
3548 switch (hw->mac.type) {
3549 case ixgbe_mac_82598EB:
3550 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3551 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3552 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3554 case ixgbe_mac_82599EB:
3555 case ixgbe_mac_X540:
3556 for (i = 0; i < adapter->num_rx_queues; i++) {
3557 j = adapter->rx_ring[i]->reg_idx;
3558 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3559 vlnctrl &= ~IXGBE_RXDCTL_VME;
3560 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3569 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3570 * @adapter: driver data
3572 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3574 struct ixgbe_hw *hw = &adapter->hw;
3578 switch (hw->mac.type) {
3579 case ixgbe_mac_82598EB:
3580 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3581 vlnctrl |= IXGBE_VLNCTRL_VME;
3582 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3584 case ixgbe_mac_82599EB:
3585 case ixgbe_mac_X540:
3586 for (i = 0; i < adapter->num_rx_queues; i++) {
3587 j = adapter->rx_ring[i]->reg_idx;
3588 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3589 vlnctrl |= IXGBE_RXDCTL_VME;
3590 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3598 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3602 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3604 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3605 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
3609 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3610 * @netdev: network interface device structure
3612 * Writes unicast address list to the RAR table.
3613 * Returns: -ENOMEM on failure/insufficient address space
3614 * 0 on no addresses written
3615 * X on writing X addresses to the RAR table
3617 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3619 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3620 struct ixgbe_hw *hw = &adapter->hw;
3621 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3624 /* In SR-IOV mode significantly less RAR entries are available */
3625 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3626 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3628 /* return ENOMEM indicating insufficient memory for addresses */
3629 if (netdev_uc_count(netdev) > rar_entries)
3632 if (!netdev_uc_empty(netdev)) {
3633 struct netdev_hw_addr *ha;
3634 /* return error if we do not support writing to RAR table */
3635 if (!hw->mac.ops.set_rar)
3638 netdev_for_each_uc_addr(ha, netdev) {
3641 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3642 VMDQ_P(0), IXGBE_RAH_AV);
3646 /* write the addresses in reverse order to avoid write combining */
3647 for (; rar_entries > 0 ; rar_entries--)
3648 hw->mac.ops.clear_rar(hw, rar_entries);
3654 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3655 * @netdev: network interface device structure
3657 * The set_rx_method entry point is called whenever the unicast/multicast
3658 * address list or the network interface flags are updated. This routine is
3659 * responsible for configuring the hardware for proper unicast, multicast and
3662 void ixgbe_set_rx_mode(struct net_device *netdev)
3664 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3665 struct ixgbe_hw *hw = &adapter->hw;
3666 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3669 /* Check for Promiscuous and All Multicast modes */
3671 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3673 /* set all bits that we expect to always be set */
3674 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3675 fctrl |= IXGBE_FCTRL_BAM;
3676 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3677 fctrl |= IXGBE_FCTRL_PMCF;
3679 /* clear the bits we are changing the status of */
3680 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3682 if (netdev->flags & IFF_PROMISC) {
3683 hw->addr_ctrl.user_set_promisc = true;
3684 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3685 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3686 /* don't hardware filter vlans in promisc mode */
3687 ixgbe_vlan_filter_disable(adapter);
3689 if (netdev->flags & IFF_ALLMULTI) {
3690 fctrl |= IXGBE_FCTRL_MPE;
3691 vmolr |= IXGBE_VMOLR_MPE;
3694 * Write addresses to the MTA, if the attempt fails
3695 * then we should just turn on promiscuous mode so
3696 * that we can at least receive multicast traffic
3698 hw->mac.ops.update_mc_addr_list(hw, netdev);
3699 vmolr |= IXGBE_VMOLR_ROMPE;
3701 ixgbe_vlan_filter_enable(adapter);
3702 hw->addr_ctrl.user_set_promisc = false;
3706 * Write addresses to available RAR registers, if there is not
3707 * sufficient space to store all the addresses then enable
3708 * unicast promiscuous mode
3710 count = ixgbe_write_uc_addr_list(netdev);
3712 fctrl |= IXGBE_FCTRL_UPE;
3713 vmolr |= IXGBE_VMOLR_ROPE;
3716 if (adapter->num_vfs)
3717 ixgbe_restore_vf_multicasts(adapter);
3719 if (hw->mac.type != ixgbe_mac_82598EB) {
3720 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3721 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3723 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3726 /* This is useful for sniffing bad packets. */
3727 if (adapter->netdev->features & NETIF_F_RXALL) {
3728 /* UPE and MPE will be handled by normal PROMISC logic
3729 * in e1000e_set_rx_mode */
3730 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3731 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3732 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3734 fctrl &= ~(IXGBE_FCTRL_DPF);
3735 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3738 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3740 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3741 ixgbe_vlan_strip_enable(adapter);
3743 ixgbe_vlan_strip_disable(adapter);
3746 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3750 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3751 napi_enable(&adapter->q_vector[q_idx]->napi);
3754 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3758 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3759 napi_disable(&adapter->q_vector[q_idx]->napi);
3762 #ifdef CONFIG_IXGBE_DCB
3764 * ixgbe_configure_dcb - Configure DCB hardware
3765 * @adapter: ixgbe adapter struct
3767 * This is called by the driver on open to configure the DCB hardware.
3768 * This is also called by the gennetlink interface when reconfiguring
3771 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3773 struct ixgbe_hw *hw = &adapter->hw;
3774 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3776 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3777 if (hw->mac.type == ixgbe_mac_82598EB)
3778 netif_set_gso_max_size(adapter->netdev, 65536);
3782 if (hw->mac.type == ixgbe_mac_82598EB)
3783 netif_set_gso_max_size(adapter->netdev, 32768);
3786 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3787 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3790 /* reconfigure the hardware */
3791 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3792 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3794 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3796 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3797 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3798 ixgbe_dcb_hw_ets(&adapter->hw,
3799 adapter->ixgbe_ieee_ets,
3801 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3802 adapter->ixgbe_ieee_pfc->pfc_en,
3803 adapter->ixgbe_ieee_ets->prio_tc);
3806 /* Enable RSS Hash per TC */
3807 if (hw->mac.type != ixgbe_mac_82598EB) {
3809 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3816 /* write msb to all 8 TCs in one write */
3817 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3822 /* Additional bittime to account for IXGBE framing */
3823 #define IXGBE_ETH_FRAMING 20
3826 * ixgbe_hpbthresh - calculate high water mark for flow control
3828 * @adapter: board private structure to calculate for
3829 * @pb: packet buffer to calculate
3831 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3833 struct ixgbe_hw *hw = &adapter->hw;
3834 struct net_device *dev = adapter->netdev;
3835 int link, tc, kb, marker;
3838 /* Calculate max LAN frame size */
3839 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3842 /* FCoE traffic class uses FCOE jumbo frames */
3843 if ((dev->features & NETIF_F_FCOE_MTU) &&
3844 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3845 (pb == ixgbe_fcoe_get_tc(adapter)))
3846 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3849 /* Calculate delay value for device */
3850 switch (hw->mac.type) {
3851 case ixgbe_mac_X540:
3852 dv_id = IXGBE_DV_X540(link, tc);
3855 dv_id = IXGBE_DV(link, tc);
3859 /* Loopback switch introduces additional latency */
3860 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3861 dv_id += IXGBE_B2BT(tc);
3863 /* Delay value is calculated in bit times convert to KB */
3864 kb = IXGBE_BT2KB(dv_id);
3865 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3867 marker = rx_pba - kb;
3869 /* It is possible that the packet buffer is not large enough
3870 * to provide required headroom. In this case throw an error
3871 * to user and a do the best we can.
3874 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3875 "headroom to support flow control."
3876 "Decrease MTU or number of traffic classes\n", pb);
3884 * ixgbe_lpbthresh - calculate low water mark for for flow control
3886 * @adapter: board private structure to calculate for
3887 * @pb: packet buffer to calculate
3889 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3891 struct ixgbe_hw *hw = &adapter->hw;
3892 struct net_device *dev = adapter->netdev;
3896 /* Calculate max LAN frame size */
3897 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3899 /* Calculate delay value for device */
3900 switch (hw->mac.type) {
3901 case ixgbe_mac_X540:
3902 dv_id = IXGBE_LOW_DV_X540(tc);
3905 dv_id = IXGBE_LOW_DV(tc);
3909 /* Delay value is calculated in bit times convert to KB */
3910 return IXGBE_BT2KB(dv_id);
3914 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3916 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3918 struct ixgbe_hw *hw = &adapter->hw;
3919 int num_tc = netdev_get_num_tc(adapter->netdev);
3925 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3927 for (i = 0; i < num_tc; i++) {
3928 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3930 /* Low water marks must not be larger than high water marks */
3931 if (hw->fc.low_water > hw->fc.high_water[i])
3932 hw->fc.low_water = 0;
3936 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3938 struct ixgbe_hw *hw = &adapter->hw;
3940 u8 tc = netdev_get_num_tc(adapter->netdev);
3942 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3943 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3944 hdrm = 32 << adapter->fdir_pballoc;
3948 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3949 ixgbe_pbthresh_setup(adapter);
3952 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3954 struct ixgbe_hw *hw = &adapter->hw;
3955 struct hlist_node *node2;
3956 struct ixgbe_fdir_filter *filter;
3958 spin_lock(&adapter->fdir_perfect_lock);
3960 if (!hlist_empty(&adapter->fdir_filter_list))
3961 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3963 hlist_for_each_entry_safe(filter, node2,
3964 &adapter->fdir_filter_list, fdir_node) {
3965 ixgbe_fdir_write_perfect_filter_82599(hw,
3968 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3969 IXGBE_FDIR_DROP_QUEUE :
3970 adapter->rx_ring[filter->action]->reg_idx);
3973 spin_unlock(&adapter->fdir_perfect_lock);
3976 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3978 struct ixgbe_hw *hw = &adapter->hw;
3980 ixgbe_configure_pb(adapter);
3981 #ifdef CONFIG_IXGBE_DCB
3982 ixgbe_configure_dcb(adapter);
3985 * We must restore virtualization before VLANs or else
3986 * the VLVF registers will not be populated
3988 ixgbe_configure_virtualization(adapter);
3990 ixgbe_set_rx_mode(adapter->netdev);
3991 ixgbe_restore_vlan(adapter);
3993 switch (hw->mac.type) {
3994 case ixgbe_mac_82599EB:
3995 case ixgbe_mac_X540:
3996 hw->mac.ops.disable_rx_buff(hw);
4002 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4003 ixgbe_init_fdir_signature_82599(&adapter->hw,
4004 adapter->fdir_pballoc);
4005 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4006 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4007 adapter->fdir_pballoc);
4008 ixgbe_fdir_filter_restore(adapter);
4011 switch (hw->mac.type) {
4012 case ixgbe_mac_82599EB:
4013 case ixgbe_mac_X540:
4014 hw->mac.ops.enable_rx_buff(hw);
4021 /* configure FCoE L2 filters, redirection table, and Rx control */
4022 ixgbe_configure_fcoe(adapter);
4024 #endif /* IXGBE_FCOE */
4025 ixgbe_configure_tx(adapter);
4026 ixgbe_configure_rx(adapter);
4029 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4031 switch (hw->phy.type) {
4032 case ixgbe_phy_sfp_avago:
4033 case ixgbe_phy_sfp_ftl:
4034 case ixgbe_phy_sfp_intel:
4035 case ixgbe_phy_sfp_unknown:
4036 case ixgbe_phy_sfp_passive_tyco:
4037 case ixgbe_phy_sfp_passive_unknown:
4038 case ixgbe_phy_sfp_active_unknown:
4039 case ixgbe_phy_sfp_ftl_active:
4042 if (hw->mac.type == ixgbe_mac_82598EB)
4050 * ixgbe_sfp_link_config - set up SFP+ link
4051 * @adapter: pointer to private adapter struct
4053 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4056 * We are assuming the worst case scenario here, and that
4057 * is that an SFP was inserted/removed after the reset
4058 * but before SFP detection was enabled. As such the best
4059 * solution is to just start searching as soon as we start
4061 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4062 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4064 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4068 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4069 * @hw: pointer to private hardware struct
4071 * Returns 0 on success, negative on failure
4073 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4076 bool autoneg, link_up = false;
4077 u32 ret = IXGBE_ERR_LINK_SETUP;
4079 if (hw->mac.ops.check_link)
4080 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4085 speed = hw->phy.autoneg_advertised;
4086 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4087 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4092 if (hw->mac.ops.setup_link)
4093 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4098 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4100 struct ixgbe_hw *hw = &adapter->hw;
4103 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4104 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4106 gpie |= IXGBE_GPIE_EIAME;
4108 * use EIAM to auto-mask when MSI-X interrupt is asserted
4109 * this saves a register write for every interrupt
4111 switch (hw->mac.type) {
4112 case ixgbe_mac_82598EB:
4113 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4115 case ixgbe_mac_82599EB:
4116 case ixgbe_mac_X540:
4118 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4119 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4123 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4124 * specifically only auto mask tx and rx interrupts */
4125 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4128 /* XXX: to interrupt immediately for EICS writes, enable this */
4129 /* gpie |= IXGBE_GPIE_EIMEN; */
4131 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4132 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4134 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4135 case IXGBE_82599_VMDQ_8Q_MASK:
4136 gpie |= IXGBE_GPIE_VTMODE_16;
4138 case IXGBE_82599_VMDQ_4Q_MASK:
4139 gpie |= IXGBE_GPIE_VTMODE_32;
4142 gpie |= IXGBE_GPIE_VTMODE_64;
4147 /* Enable Thermal over heat sensor interrupt */
4148 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4149 switch (adapter->hw.mac.type) {
4150 case ixgbe_mac_82599EB:
4151 gpie |= IXGBE_SDP0_GPIEN;
4153 case ixgbe_mac_X540:
4154 gpie |= IXGBE_EIMS_TS;
4161 /* Enable fan failure interrupt */
4162 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4163 gpie |= IXGBE_SDP1_GPIEN;
4165 if (hw->mac.type == ixgbe_mac_82599EB) {
4166 gpie |= IXGBE_SDP1_GPIEN;
4167 gpie |= IXGBE_SDP2_GPIEN;
4170 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4173 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4175 struct ixgbe_hw *hw = &adapter->hw;
4179 ixgbe_get_hw_control(adapter);
4180 ixgbe_setup_gpie(adapter);
4182 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4183 ixgbe_configure_msix(adapter);
4185 ixgbe_configure_msi_and_legacy(adapter);
4187 /* enable the optics for 82599 SFP+ fiber */
4188 if (hw->mac.ops.enable_tx_laser)
4189 hw->mac.ops.enable_tx_laser(hw);
4191 clear_bit(__IXGBE_DOWN, &adapter->state);
4192 ixgbe_napi_enable_all(adapter);
4194 if (ixgbe_is_sfp(hw)) {
4195 ixgbe_sfp_link_config(adapter);
4197 err = ixgbe_non_sfp_link_config(hw);
4199 e_err(probe, "link_config FAILED %d\n", err);
4202 /* clear any pending interrupts, may auto mask */
4203 IXGBE_READ_REG(hw, IXGBE_EICR);
4204 ixgbe_irq_enable(adapter, true, true);
4207 * If this adapter has a fan, check to see if we had a failure
4208 * before we enabled the interrupt.
4210 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4211 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4212 if (esdp & IXGBE_ESDP_SDP1)
4213 e_crit(drv, "Fan has stopped, replace the adapter\n");
4216 /* enable transmits */
4217 netif_tx_start_all_queues(adapter->netdev);
4219 /* bring the link up in the watchdog, this could race with our first
4220 * link up interrupt but shouldn't be a problem */
4221 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4222 adapter->link_check_timeout = jiffies;
4223 mod_timer(&adapter->service_timer, jiffies);
4225 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4226 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4227 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4228 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4231 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4233 WARN_ON(in_interrupt());
4234 /* put off any impending NetWatchDogTimeout */
4235 adapter->netdev->trans_start = jiffies;
4237 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4238 usleep_range(1000, 2000);
4239 ixgbe_down(adapter);
4241 * If SR-IOV enabled then wait a bit before bringing the adapter
4242 * back up to give the VFs time to respond to the reset. The
4243 * two second wait is based upon the watchdog timer cycle in
4246 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4249 clear_bit(__IXGBE_RESETTING, &adapter->state);
4252 void ixgbe_up(struct ixgbe_adapter *adapter)
4254 /* hardware has been reset, we need to reload some things */
4255 ixgbe_configure(adapter);
4257 ixgbe_up_complete(adapter);
4260 void ixgbe_reset(struct ixgbe_adapter *adapter)
4262 struct ixgbe_hw *hw = &adapter->hw;
4265 /* lock SFP init bit to prevent race conditions with the watchdog */
4266 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4267 usleep_range(1000, 2000);
4269 /* clear all SFP and link config related flags while holding SFP_INIT */
4270 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4271 IXGBE_FLAG2_SFP_NEEDS_RESET);
4272 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4274 err = hw->mac.ops.init_hw(hw);
4277 case IXGBE_ERR_SFP_NOT_PRESENT:
4278 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4280 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4281 e_dev_err("master disable timed out\n");
4283 case IXGBE_ERR_EEPROM_VERSION:
4284 /* We are running on a pre-production device, log a warning */
4285 e_dev_warn("This device is a pre-production adapter/LOM. "
4286 "Please be aware there may be issues associated with "
4287 "your hardware. If you are experiencing problems "
4288 "please contact your Intel or hardware "
4289 "representative who provided you with this "
4293 e_dev_err("Hardware Error: %d\n", err);
4296 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4298 /* reprogram the RAR[0] in case user changed it. */
4299 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4301 /* update SAN MAC vmdq pool selection */
4302 if (hw->mac.san_mac_rar_index)
4303 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4305 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4306 ixgbe_ptp_reset(adapter);
4310 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4311 * @rx_ring: ring to free buffers from
4313 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4315 struct device *dev = rx_ring->dev;
4319 /* ring already cleared, nothing to do */
4320 if (!rx_ring->rx_buffer_info)
4323 /* Free all the Rx ring sk_buffs */
4324 for (i = 0; i < rx_ring->count; i++) {
4325 struct ixgbe_rx_buffer *rx_buffer;
4327 rx_buffer = &rx_ring->rx_buffer_info[i];
4328 if (rx_buffer->skb) {
4329 struct sk_buff *skb = rx_buffer->skb;
4330 if (IXGBE_CB(skb)->page_released) {
4333 ixgbe_rx_bufsz(rx_ring),
4335 IXGBE_CB(skb)->page_released = false;
4339 rx_buffer->skb = NULL;
4341 dma_unmap_page(dev, rx_buffer->dma,
4342 ixgbe_rx_pg_size(rx_ring),
4345 if (rx_buffer->page)
4346 __free_pages(rx_buffer->page,
4347 ixgbe_rx_pg_order(rx_ring));
4348 rx_buffer->page = NULL;
4351 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4352 memset(rx_ring->rx_buffer_info, 0, size);
4354 /* Zero out the descriptor ring */
4355 memset(rx_ring->desc, 0, rx_ring->size);
4357 rx_ring->next_to_alloc = 0;
4358 rx_ring->next_to_clean = 0;
4359 rx_ring->next_to_use = 0;
4363 * ixgbe_clean_tx_ring - Free Tx Buffers
4364 * @tx_ring: ring to be cleaned
4366 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4368 struct ixgbe_tx_buffer *tx_buffer_info;
4372 /* ring already cleared, nothing to do */
4373 if (!tx_ring->tx_buffer_info)
4376 /* Free all the Tx ring sk_buffs */
4377 for (i = 0; i < tx_ring->count; i++) {
4378 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4379 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4382 netdev_tx_reset_queue(txring_txq(tx_ring));
4384 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4385 memset(tx_ring->tx_buffer_info, 0, size);
4387 /* Zero out the descriptor ring */
4388 memset(tx_ring->desc, 0, tx_ring->size);
4390 tx_ring->next_to_use = 0;
4391 tx_ring->next_to_clean = 0;
4395 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4396 * @adapter: board private structure
4398 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4402 for (i = 0; i < adapter->num_rx_queues; i++)
4403 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4407 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4408 * @adapter: board private structure
4410 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4414 for (i = 0; i < adapter->num_tx_queues; i++)
4415 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4418 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4420 struct hlist_node *node2;
4421 struct ixgbe_fdir_filter *filter;
4423 spin_lock(&adapter->fdir_perfect_lock);
4425 hlist_for_each_entry_safe(filter, node2,
4426 &adapter->fdir_filter_list, fdir_node) {
4427 hlist_del(&filter->fdir_node);
4430 adapter->fdir_filter_count = 0;
4432 spin_unlock(&adapter->fdir_perfect_lock);
4435 void ixgbe_down(struct ixgbe_adapter *adapter)
4437 struct net_device *netdev = adapter->netdev;
4438 struct ixgbe_hw *hw = &adapter->hw;
4442 /* signal that we are down to the interrupt handler */
4443 set_bit(__IXGBE_DOWN, &adapter->state);
4445 /* disable receives */
4446 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4447 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4449 /* disable all enabled rx queues */
4450 for (i = 0; i < adapter->num_rx_queues; i++)
4451 /* this call also flushes the previous write */
4452 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4454 usleep_range(10000, 20000);
4456 netif_tx_stop_all_queues(netdev);
4458 /* call carrier off first to avoid false dev_watchdog timeouts */
4459 netif_carrier_off(netdev);
4460 netif_tx_disable(netdev);
4462 ixgbe_irq_disable(adapter);
4464 ixgbe_napi_disable_all(adapter);
4466 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4467 IXGBE_FLAG2_RESET_REQUESTED);
4468 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4470 del_timer_sync(&adapter->service_timer);
4472 if (adapter->num_vfs) {
4473 /* Clear EITR Select mapping */
4474 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4476 /* Mark all the VFs as inactive */
4477 for (i = 0 ; i < adapter->num_vfs; i++)
4478 adapter->vfinfo[i].clear_to_send = false;
4480 /* ping all the active vfs to let them know we are going down */
4481 ixgbe_ping_all_vfs(adapter);
4483 /* Disable all VFTE/VFRE TX/RX */
4484 ixgbe_disable_tx_rx(adapter);
4487 /* disable transmits in the hardware now that interrupts are off */
4488 for (i = 0; i < adapter->num_tx_queues; i++) {
4489 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4490 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4493 /* Disable the Tx DMA engine on 82599 and X540 */
4494 switch (hw->mac.type) {
4495 case ixgbe_mac_82599EB:
4496 case ixgbe_mac_X540:
4497 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4498 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4499 ~IXGBE_DMATXCTL_TE));
4505 if (!pci_channel_offline(adapter->pdev))
4506 ixgbe_reset(adapter);
4508 /* power down the optics for 82599 SFP+ fiber */
4509 if (hw->mac.ops.disable_tx_laser)
4510 hw->mac.ops.disable_tx_laser(hw);
4512 ixgbe_clean_all_tx_rings(adapter);
4513 ixgbe_clean_all_rx_rings(adapter);
4515 #ifdef CONFIG_IXGBE_DCA
4516 /* since we reset the hardware DCA settings were cleared */
4517 ixgbe_setup_dca(adapter);
4522 * ixgbe_tx_timeout - Respond to a Tx Hang
4523 * @netdev: network interface device structure
4525 static void ixgbe_tx_timeout(struct net_device *netdev)
4527 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4529 /* Do the reset outside of interrupt context */
4530 ixgbe_tx_timeout_reset(adapter);
4534 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4535 * @adapter: board private structure to initialize
4537 * ixgbe_sw_init initializes the Adapter private data structure.
4538 * Fields are initialized based on PCI device information and
4539 * OS network device settings (MTU size).
4541 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
4543 struct ixgbe_hw *hw = &adapter->hw;
4544 struct pci_dev *pdev = adapter->pdev;
4545 unsigned int rss, fdir;
4547 #ifdef CONFIG_IXGBE_DCB
4549 struct tc_configuration *tc;
4552 /* PCI config space info */
4554 hw->vendor_id = pdev->vendor;
4555 hw->device_id = pdev->device;
4556 hw->revision_id = pdev->revision;
4557 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4558 hw->subsystem_device_id = pdev->subsystem_device;
4560 /* Set common capability flags and settings */
4561 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4562 adapter->ring_feature[RING_F_RSS].limit = rss;
4563 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4564 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4565 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4566 adapter->atr_sample_rate = 20;
4567 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4568 adapter->ring_feature[RING_F_FDIR].limit = fdir;
4569 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4570 #ifdef CONFIG_IXGBE_DCA
4571 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4574 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4575 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4576 #ifdef CONFIG_IXGBE_DCB
4577 /* Default traffic class to use for FCoE */
4578 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4579 #endif /* CONFIG_IXGBE_DCB */
4580 #endif /* IXGBE_FCOE */
4582 /* Set MAC specific capability flags and exceptions */
4583 switch (hw->mac.type) {
4584 case ixgbe_mac_82598EB:
4585 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4586 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4588 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4589 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4591 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4592 adapter->ring_feature[RING_F_FDIR].limit = 0;
4593 adapter->atr_sample_rate = 0;
4594 adapter->fdir_pballoc = 0;
4596 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4597 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4598 #ifdef CONFIG_IXGBE_DCB
4599 adapter->fcoe.up = 0;
4600 #endif /* IXGBE_DCB */
4601 #endif /* IXGBE_FCOE */
4603 case ixgbe_mac_82599EB:
4604 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4605 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4607 case ixgbe_mac_X540:
4608 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4609 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4610 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4617 /* FCoE support exists, always init the FCoE lock */
4618 spin_lock_init(&adapter->fcoe.lock);
4621 /* n-tuple support exists, always init our spinlock */
4622 spin_lock_init(&adapter->fdir_perfect_lock);
4624 #ifdef CONFIG_IXGBE_DCB
4625 switch (hw->mac.type) {
4626 case ixgbe_mac_X540:
4627 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4628 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4631 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4632 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4636 /* Configure DCB traffic classes */
4637 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4638 tc = &adapter->dcb_cfg.tc_config[j];
4639 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4640 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4641 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4642 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4643 tc->dcb_pfc = pfc_disabled;
4646 /* Initialize default user to priority mapping, UPx->TC0 */
4647 tc = &adapter->dcb_cfg.tc_config[0];
4648 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4649 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4651 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4652 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4653 adapter->dcb_cfg.pfc_mode_enable = false;
4654 adapter->dcb_set_bitmap = 0x00;
4655 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4656 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4657 sizeof(adapter->temp_dcb_cfg));
4661 /* default flow control settings */
4662 hw->fc.requested_mode = ixgbe_fc_full;
4663 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4664 ixgbe_pbthresh_setup(adapter);
4665 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4666 hw->fc.send_xon = true;
4667 hw->fc.disable_fc_autoneg =
4668 (ixgbe_device_supports_autoneg_fc(hw) == 0) ? false : true;
4670 #ifdef CONFIG_PCI_IOV
4671 /* assign number of SR-IOV VFs */
4672 if (hw->mac.type != ixgbe_mac_82598EB)
4673 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4676 /* enable itr by default in dynamic mode */
4677 adapter->rx_itr_setting = 1;
4678 adapter->tx_itr_setting = 1;
4680 /* set default ring sizes */
4681 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4682 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4684 /* set default work limits */
4685 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4687 /* initialize eeprom parameters */
4688 if (ixgbe_init_eeprom_params_generic(hw)) {
4689 e_dev_err("EEPROM initialization failed\n");
4693 set_bit(__IXGBE_DOWN, &adapter->state);
4699 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4700 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4702 * Return 0 on success, negative on failure
4704 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4706 struct device *dev = tx_ring->dev;
4707 int orig_node = dev_to_node(dev);
4711 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4713 if (tx_ring->q_vector)
4714 numa_node = tx_ring->q_vector->numa_node;
4716 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4717 if (!tx_ring->tx_buffer_info)
4718 tx_ring->tx_buffer_info = vzalloc(size);
4719 if (!tx_ring->tx_buffer_info)
4722 /* round up to nearest 4K */
4723 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4724 tx_ring->size = ALIGN(tx_ring->size, 4096);
4726 set_dev_node(dev, numa_node);
4727 tx_ring->desc = dma_alloc_coherent(dev,
4731 set_dev_node(dev, orig_node);
4733 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4734 &tx_ring->dma, GFP_KERNEL);
4738 tx_ring->next_to_use = 0;
4739 tx_ring->next_to_clean = 0;
4743 vfree(tx_ring->tx_buffer_info);
4744 tx_ring->tx_buffer_info = NULL;
4745 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4750 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4751 * @adapter: board private structure
4753 * If this function returns with an error, then it's possible one or
4754 * more of the rings is populated (while the rest are not). It is the
4755 * callers duty to clean those orphaned rings.
4757 * Return 0 on success, negative on failure
4759 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4763 for (i = 0; i < adapter->num_tx_queues; i++) {
4764 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4768 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4774 /* rewind the index freeing the rings as we go */
4776 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4781 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4782 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4784 * Returns 0 on success, negative on failure
4786 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4788 struct device *dev = rx_ring->dev;
4789 int orig_node = dev_to_node(dev);
4793 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4795 if (rx_ring->q_vector)
4796 numa_node = rx_ring->q_vector->numa_node;
4798 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4799 if (!rx_ring->rx_buffer_info)
4800 rx_ring->rx_buffer_info = vzalloc(size);
4801 if (!rx_ring->rx_buffer_info)
4804 /* Round up to nearest 4K */
4805 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4806 rx_ring->size = ALIGN(rx_ring->size, 4096);
4808 set_dev_node(dev, numa_node);
4809 rx_ring->desc = dma_alloc_coherent(dev,
4813 set_dev_node(dev, orig_node);
4815 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4816 &rx_ring->dma, GFP_KERNEL);
4820 rx_ring->next_to_clean = 0;
4821 rx_ring->next_to_use = 0;
4825 vfree(rx_ring->rx_buffer_info);
4826 rx_ring->rx_buffer_info = NULL;
4827 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4832 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4833 * @adapter: board private structure
4835 * If this function returns with an error, then it's possible one or
4836 * more of the rings is populated (while the rest are not). It is the
4837 * callers duty to clean those orphaned rings.
4839 * Return 0 on success, negative on failure
4841 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4845 for (i = 0; i < adapter->num_rx_queues; i++) {
4846 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4850 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4855 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4860 /* rewind the index freeing the rings as we go */
4862 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4867 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4868 * @tx_ring: Tx descriptor ring for a specific queue
4870 * Free all transmit software resources
4872 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4874 ixgbe_clean_tx_ring(tx_ring);
4876 vfree(tx_ring->tx_buffer_info);
4877 tx_ring->tx_buffer_info = NULL;
4879 /* if not set, then don't free */
4883 dma_free_coherent(tx_ring->dev, tx_ring->size,
4884 tx_ring->desc, tx_ring->dma);
4886 tx_ring->desc = NULL;
4890 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4891 * @adapter: board private structure
4893 * Free all transmit software resources
4895 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4899 for (i = 0; i < adapter->num_tx_queues; i++)
4900 if (adapter->tx_ring[i]->desc)
4901 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4905 * ixgbe_free_rx_resources - Free Rx Resources
4906 * @rx_ring: ring to clean the resources from
4908 * Free all receive software resources
4910 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4912 ixgbe_clean_rx_ring(rx_ring);
4914 vfree(rx_ring->rx_buffer_info);
4915 rx_ring->rx_buffer_info = NULL;
4917 /* if not set, then don't free */
4921 dma_free_coherent(rx_ring->dev, rx_ring->size,
4922 rx_ring->desc, rx_ring->dma);
4924 rx_ring->desc = NULL;
4928 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4929 * @adapter: board private structure
4931 * Free all receive software resources
4933 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4938 ixgbe_free_fcoe_ddp_resources(adapter);
4941 for (i = 0; i < adapter->num_rx_queues; i++)
4942 if (adapter->rx_ring[i]->desc)
4943 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4947 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4948 * @netdev: network interface device structure
4949 * @new_mtu: new value for maximum frame size
4951 * Returns 0 on success, negative on failure
4953 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4955 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4956 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4958 /* MTU < 68 is an error and causes problems on some kernels */
4959 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4963 * For 82599EB we cannot allow legacy VFs to enable their receive
4964 * paths when MTU greater than 1500 is configured. So display a
4965 * warning that legacy VFs will be disabled.
4967 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4968 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4969 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
4970 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
4972 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4974 /* must set new MTU before calling down or up */
4975 netdev->mtu = new_mtu;
4977 if (netif_running(netdev))
4978 ixgbe_reinit_locked(adapter);
4984 * ixgbe_open - Called when a network interface is made active
4985 * @netdev: network interface device structure
4987 * Returns 0 on success, negative value on failure
4989 * The open entry point is called when a network interface is made
4990 * active by the system (IFF_UP). At this point all resources needed
4991 * for transmit and receive operations are allocated, the interrupt
4992 * handler is registered with the OS, the watchdog timer is started,
4993 * and the stack is notified that the interface is ready.
4995 static int ixgbe_open(struct net_device *netdev)
4997 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5000 /* disallow open during test */
5001 if (test_bit(__IXGBE_TESTING, &adapter->state))
5004 netif_carrier_off(netdev);
5006 /* allocate transmit descriptors */
5007 err = ixgbe_setup_all_tx_resources(adapter);
5011 /* allocate receive descriptors */
5012 err = ixgbe_setup_all_rx_resources(adapter);
5016 ixgbe_configure(adapter);
5018 err = ixgbe_request_irq(adapter);
5022 /* Notify the stack of the actual queue counts. */
5023 err = netif_set_real_num_tx_queues(netdev,
5024 adapter->num_rx_pools > 1 ? 1 :
5025 adapter->num_tx_queues);
5027 goto err_set_queues;
5030 err = netif_set_real_num_rx_queues(netdev,
5031 adapter->num_rx_pools > 1 ? 1 :
5032 adapter->num_rx_queues);
5034 goto err_set_queues;
5036 ixgbe_ptp_init(adapter);
5038 ixgbe_up_complete(adapter);
5043 ixgbe_free_irq(adapter);
5045 ixgbe_free_all_rx_resources(adapter);
5047 ixgbe_free_all_tx_resources(adapter);
5049 ixgbe_reset(adapter);
5055 * ixgbe_close - Disables a network interface
5056 * @netdev: network interface device structure
5058 * Returns 0, this is not allowed to fail
5060 * The close entry point is called when an interface is de-activated
5061 * by the OS. The hardware is still under the drivers control, but
5062 * needs to be disabled. A global MAC reset is issued to stop the
5063 * hardware, and all transmit and receive resources are freed.
5065 static int ixgbe_close(struct net_device *netdev)
5067 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5069 ixgbe_ptp_stop(adapter);
5071 ixgbe_down(adapter);
5072 ixgbe_free_irq(adapter);
5074 ixgbe_fdir_filter_exit(adapter);
5076 ixgbe_free_all_tx_resources(adapter);
5077 ixgbe_free_all_rx_resources(adapter);
5079 ixgbe_release_hw_control(adapter);
5085 static int ixgbe_resume(struct pci_dev *pdev)
5087 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5088 struct net_device *netdev = adapter->netdev;
5091 pci_set_power_state(pdev, PCI_D0);
5092 pci_restore_state(pdev);
5094 * pci_restore_state clears dev->state_saved so call
5095 * pci_save_state to restore it.
5097 pci_save_state(pdev);
5099 err = pci_enable_device_mem(pdev);
5101 e_dev_err("Cannot enable PCI device from suspend\n");
5104 pci_set_master(pdev);
5106 pci_wake_from_d3(pdev, false);
5108 ixgbe_reset(adapter);
5110 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5113 err = ixgbe_init_interrupt_scheme(adapter);
5114 if (!err && netif_running(netdev))
5115 err = ixgbe_open(netdev);
5122 netif_device_attach(netdev);
5126 #endif /* CONFIG_PM */
5128 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5130 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5131 struct net_device *netdev = adapter->netdev;
5132 struct ixgbe_hw *hw = &adapter->hw;
5134 u32 wufc = adapter->wol;
5139 netif_device_detach(netdev);
5142 if (netif_running(netdev)) {
5143 ixgbe_down(adapter);
5144 ixgbe_free_irq(adapter);
5145 ixgbe_free_all_tx_resources(adapter);
5146 ixgbe_free_all_rx_resources(adapter);
5150 ixgbe_clear_interrupt_scheme(adapter);
5153 retval = pci_save_state(pdev);
5159 ixgbe_set_rx_mode(netdev);
5161 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5162 if (hw->mac.ops.enable_tx_laser)
5163 hw->mac.ops.enable_tx_laser(hw);
5165 /* turn on all-multi mode if wake on multicast is enabled */
5166 if (wufc & IXGBE_WUFC_MC) {
5167 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5168 fctrl |= IXGBE_FCTRL_MPE;
5169 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5172 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5173 ctrl |= IXGBE_CTRL_GIO_DIS;
5174 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5176 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5178 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5179 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5182 switch (hw->mac.type) {
5183 case ixgbe_mac_82598EB:
5184 pci_wake_from_d3(pdev, false);
5186 case ixgbe_mac_82599EB:
5187 case ixgbe_mac_X540:
5188 pci_wake_from_d3(pdev, !!wufc);
5194 *enable_wake = !!wufc;
5196 ixgbe_release_hw_control(adapter);
5198 pci_disable_device(pdev);
5204 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5209 retval = __ixgbe_shutdown(pdev, &wake);
5214 pci_prepare_to_sleep(pdev);
5216 pci_wake_from_d3(pdev, false);
5217 pci_set_power_state(pdev, PCI_D3hot);
5222 #endif /* CONFIG_PM */
5224 static void ixgbe_shutdown(struct pci_dev *pdev)
5228 __ixgbe_shutdown(pdev, &wake);
5230 if (system_state == SYSTEM_POWER_OFF) {
5231 pci_wake_from_d3(pdev, wake);
5232 pci_set_power_state(pdev, PCI_D3hot);
5237 * ixgbe_update_stats - Update the board statistics counters.
5238 * @adapter: board private structure
5240 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5242 struct net_device *netdev = adapter->netdev;
5243 struct ixgbe_hw *hw = &adapter->hw;
5244 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5246 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5247 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5248 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5249 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5251 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5252 test_bit(__IXGBE_RESETTING, &adapter->state))
5255 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5258 for (i = 0; i < adapter->num_rx_queues; i++) {
5259 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5260 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5262 adapter->rsc_total_count = rsc_count;
5263 adapter->rsc_total_flush = rsc_flush;
5266 for (i = 0; i < adapter->num_rx_queues; i++) {
5267 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5268 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5269 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5270 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5271 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5272 bytes += rx_ring->stats.bytes;
5273 packets += rx_ring->stats.packets;
5275 adapter->non_eop_descs = non_eop_descs;
5276 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5277 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5278 adapter->hw_csum_rx_error = hw_csum_rx_error;
5279 netdev->stats.rx_bytes = bytes;
5280 netdev->stats.rx_packets = packets;
5284 /* gather some stats to the adapter struct that are per queue */
5285 for (i = 0; i < adapter->num_tx_queues; i++) {
5286 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5287 restart_queue += tx_ring->tx_stats.restart_queue;
5288 tx_busy += tx_ring->tx_stats.tx_busy;
5289 bytes += tx_ring->stats.bytes;
5290 packets += tx_ring->stats.packets;
5292 adapter->restart_queue = restart_queue;
5293 adapter->tx_busy = tx_busy;
5294 netdev->stats.tx_bytes = bytes;
5295 netdev->stats.tx_packets = packets;
5297 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5299 /* 8 register reads */
5300 for (i = 0; i < 8; i++) {
5301 /* for packet buffers not used, the register should read 0 */
5302 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5304 hwstats->mpc[i] += mpc;
5305 total_mpc += hwstats->mpc[i];
5306 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5307 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5308 switch (hw->mac.type) {
5309 case ixgbe_mac_82598EB:
5310 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5311 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5312 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5313 hwstats->pxonrxc[i] +=
5314 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5316 case ixgbe_mac_82599EB:
5317 case ixgbe_mac_X540:
5318 hwstats->pxonrxc[i] +=
5319 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5326 /*16 register reads */
5327 for (i = 0; i < 16; i++) {
5328 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5329 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5330 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5331 (hw->mac.type == ixgbe_mac_X540)) {
5332 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5333 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5334 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5335 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5339 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5340 /* work around hardware counting issue */
5341 hwstats->gprc -= missed_rx;
5343 ixgbe_update_xoff_received(adapter);
5345 /* 82598 hardware only has a 32 bit counter in the high register */
5346 switch (hw->mac.type) {
5347 case ixgbe_mac_82598EB:
5348 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5349 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5350 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5351 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5353 case ixgbe_mac_X540:
5354 /* OS2BMC stats are X540 only*/
5355 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5356 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5357 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5358 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5359 case ixgbe_mac_82599EB:
5360 for (i = 0; i < 16; i++)
5361 adapter->hw_rx_no_dma_resources +=
5362 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5363 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5364 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5365 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5366 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5367 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5368 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5369 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5370 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5371 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5373 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5374 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5375 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5376 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5377 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5378 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5379 /* Add up per cpu counters for total ddp aloc fail */
5380 if (adapter->fcoe.ddp_pool) {
5381 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5382 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5384 u64 noddp = 0, noddp_ext_buff = 0;
5385 for_each_possible_cpu(cpu) {
5386 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5387 noddp += ddp_pool->noddp;
5388 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5390 hwstats->fcoe_noddp = noddp;
5391 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5393 #endif /* IXGBE_FCOE */
5398 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5399 hwstats->bprc += bprc;
5400 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5401 if (hw->mac.type == ixgbe_mac_82598EB)
5402 hwstats->mprc -= bprc;
5403 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5404 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5405 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5406 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5407 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5408 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5409 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5410 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5411 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5412 hwstats->lxontxc += lxon;
5413 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5414 hwstats->lxofftxc += lxoff;
5415 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5416 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5418 * 82598 errata - tx of flow control packets is included in tx counters
5420 xon_off_tot = lxon + lxoff;
5421 hwstats->gptc -= xon_off_tot;
5422 hwstats->mptc -= xon_off_tot;
5423 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5424 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5425 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5426 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5427 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5428 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5429 hwstats->ptc64 -= xon_off_tot;
5430 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5431 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5432 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5433 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5434 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5435 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5437 /* Fill out the OS statistics structure */
5438 netdev->stats.multicast = hwstats->mprc;
5441 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5442 netdev->stats.rx_dropped = 0;
5443 netdev->stats.rx_length_errors = hwstats->rlec;
5444 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5445 netdev->stats.rx_missed_errors = total_mpc;
5449 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5450 * @adapter: pointer to the device adapter structure
5452 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5454 struct ixgbe_hw *hw = &adapter->hw;
5457 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5460 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5462 /* if interface is down do nothing */
5463 if (test_bit(__IXGBE_DOWN, &adapter->state))
5466 /* do nothing if we are not using signature filters */
5467 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5470 adapter->fdir_overflow++;
5472 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5473 for (i = 0; i < adapter->num_tx_queues; i++)
5474 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5475 &(adapter->tx_ring[i]->state));
5476 /* re-enable flow director interrupts */
5477 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5479 e_err(probe, "failed to finish FDIR re-initialization, "
5480 "ignored adding FDIR ATR filters\n");
5485 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5486 * @adapter: pointer to the device adapter structure
5488 * This function serves two purposes. First it strobes the interrupt lines
5489 * in order to make certain interrupts are occurring. Secondly it sets the
5490 * bits needed to check for TX hangs. As a result we should immediately
5491 * determine if a hang has occurred.
5493 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5495 struct ixgbe_hw *hw = &adapter->hw;
5499 /* If we're down or resetting, just bail */
5500 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5501 test_bit(__IXGBE_RESETTING, &adapter->state))
5504 /* Force detection of hung controller */
5505 if (netif_carrier_ok(adapter->netdev)) {
5506 for (i = 0; i < adapter->num_tx_queues; i++)
5507 set_check_for_tx_hang(adapter->tx_ring[i]);
5510 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5512 * for legacy and MSI interrupts don't set any bits
5513 * that are enabled for EIAM, because this operation
5514 * would set *both* EIMS and EICS for any bit in EIAM
5516 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5517 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5519 /* get one bit for every active tx/rx interrupt vector */
5520 for (i = 0; i < adapter->num_q_vectors; i++) {
5521 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5522 if (qv->rx.ring || qv->tx.ring)
5523 eics |= ((u64)1 << i);
5527 /* Cause software interrupt to ensure rings are cleaned */
5528 ixgbe_irq_rearm_queues(adapter, eics);
5533 * ixgbe_watchdog_update_link - update the link status
5534 * @adapter: pointer to the device adapter structure
5535 * @link_speed: pointer to a u32 to store the link_speed
5537 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5539 struct ixgbe_hw *hw = &adapter->hw;
5540 u32 link_speed = adapter->link_speed;
5541 bool link_up = adapter->link_up;
5542 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5544 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5547 if (hw->mac.ops.check_link) {
5548 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5550 /* always assume link is up, if no check link function */
5551 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5555 if (adapter->ixgbe_ieee_pfc)
5556 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5558 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5559 hw->mac.ops.fc_enable(hw);
5560 ixgbe_set_rx_drop_en(adapter);
5564 time_after(jiffies, (adapter->link_check_timeout +
5565 IXGBE_TRY_LINK_TIMEOUT))) {
5566 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5567 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5568 IXGBE_WRITE_FLUSH(hw);
5571 adapter->link_up = link_up;
5572 adapter->link_speed = link_speed;
5575 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5577 #ifdef CONFIG_IXGBE_DCB
5578 struct net_device *netdev = adapter->netdev;
5579 struct dcb_app app = {
5580 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5585 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5586 up = dcb_ieee_getapp_mask(netdev, &app);
5588 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5593 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5594 * print link up message
5595 * @adapter: pointer to the device adapter structure
5597 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5599 struct net_device *netdev = adapter->netdev;
5600 struct ixgbe_hw *hw = &adapter->hw;
5601 u32 link_speed = adapter->link_speed;
5602 bool flow_rx, flow_tx;
5604 /* only continue if link was previously down */
5605 if (netif_carrier_ok(netdev))
5608 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5610 switch (hw->mac.type) {
5611 case ixgbe_mac_82598EB: {
5612 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5613 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5614 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5615 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5618 case ixgbe_mac_X540:
5619 case ixgbe_mac_82599EB: {
5620 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5621 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5622 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5623 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5632 adapter->last_rx_ptp_check = jiffies;
5634 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5635 ixgbe_ptp_start_cyclecounter(adapter);
5637 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5638 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5640 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5642 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5645 ((flow_rx && flow_tx) ? "RX/TX" :
5647 (flow_tx ? "TX" : "None"))));
5649 netif_carrier_on(netdev);
5650 ixgbe_check_vf_rate_limit(adapter);
5652 /* update the default user priority for VFs */
5653 ixgbe_update_default_up(adapter);
5655 /* ping all the active vfs to let them know link has changed */
5656 ixgbe_ping_all_vfs(adapter);
5660 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5661 * print link down message
5662 * @adapter: pointer to the adapter structure
5664 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5666 struct net_device *netdev = adapter->netdev;
5667 struct ixgbe_hw *hw = &adapter->hw;
5669 adapter->link_up = false;
5670 adapter->link_speed = 0;
5672 /* only continue if link was up previously */
5673 if (!netif_carrier_ok(netdev))
5676 /* poll for SFP+ cable when link is down */
5677 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5678 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5680 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5681 ixgbe_ptp_start_cyclecounter(adapter);
5683 e_info(drv, "NIC Link is Down\n");
5684 netif_carrier_off(netdev);
5686 /* ping all the active vfs to let them know link has changed */
5687 ixgbe_ping_all_vfs(adapter);
5691 * ixgbe_watchdog_flush_tx - flush queues on link down
5692 * @adapter: pointer to the device adapter structure
5694 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5697 int some_tx_pending = 0;
5699 if (!netif_carrier_ok(adapter->netdev)) {
5700 for (i = 0; i < adapter->num_tx_queues; i++) {
5701 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5702 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5703 some_tx_pending = 1;
5708 if (some_tx_pending) {
5709 /* We've lost link, so the controller stops DMA,
5710 * but we've got queued Tx work that's never going
5711 * to get done, so reset controller to flush Tx.
5712 * (Do the reset outside of interrupt context).
5714 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
5715 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5720 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5724 /* Do not perform spoof check for 82598 or if not in IOV mode */
5725 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5726 adapter->num_vfs == 0)
5729 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5732 * ssvpc register is cleared on read, if zero then no
5733 * spoofed packets in the last interval.
5738 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
5742 * ixgbe_watchdog_subtask - check and bring link up
5743 * @adapter: pointer to the device adapter structure
5745 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5747 /* if interface is down do nothing */
5748 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5749 test_bit(__IXGBE_RESETTING, &adapter->state))
5752 ixgbe_watchdog_update_link(adapter);
5754 if (adapter->link_up)
5755 ixgbe_watchdog_link_is_up(adapter);
5757 ixgbe_watchdog_link_is_down(adapter);
5759 ixgbe_spoof_check(adapter);
5760 ixgbe_update_stats(adapter);
5762 ixgbe_watchdog_flush_tx(adapter);
5766 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5767 * @adapter: the ixgbe adapter structure
5769 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5771 struct ixgbe_hw *hw = &adapter->hw;
5774 /* not searching for SFP so there is nothing to do here */
5775 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5776 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5779 /* concurent i2c reads are not supported */
5780 if (test_bit(__IXGBE_READ_I2C, &adapter->state))
5783 /* someone else is in init, wait until next service event */
5784 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5787 err = hw->phy.ops.identify_sfp(hw);
5788 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5791 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5792 /* If no cable is present, then we need to reset
5793 * the next time we find a good cable. */
5794 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5801 /* exit if reset not needed */
5802 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5805 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5808 * A module may be identified correctly, but the EEPROM may not have
5809 * support for that module. setup_sfp() will fail in that case, so
5810 * we should not allow that module to load.
5812 if (hw->mac.type == ixgbe_mac_82598EB)
5813 err = hw->phy.ops.reset(hw);
5815 err = hw->mac.ops.setup_sfp(hw);
5817 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5820 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5821 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5824 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5826 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5827 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5828 e_dev_err("failed to initialize because an unsupported "
5829 "SFP+ module type was detected.\n");
5830 e_dev_err("Reload the driver after installing a "
5831 "supported module.\n");
5832 unregister_netdev(adapter->netdev);
5837 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5838 * @adapter: the ixgbe adapter structure
5840 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5842 struct ixgbe_hw *hw = &adapter->hw;
5844 bool autoneg = false;
5846 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5849 /* someone else is in init, wait until next service event */
5850 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5853 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5855 speed = hw->phy.autoneg_advertised;
5856 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5857 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
5858 if (hw->mac.ops.setup_link)
5859 hw->mac.ops.setup_link(hw, speed, true);
5861 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5862 adapter->link_check_timeout = jiffies;
5863 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5866 #ifdef CONFIG_PCI_IOV
5867 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5870 struct ixgbe_hw *hw = &adapter->hw;
5871 struct net_device *netdev = adapter->netdev;
5875 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5876 if (gpc) /* If incrementing then no need for the check below */
5879 * Check to see if a bad DMA write target from an errant or
5880 * malicious VF has caused a PCIe error. If so then we can
5881 * issue a VFLR to the offending VF(s) and then resume without
5882 * requesting a full slot reset.
5885 for (vf = 0; vf < adapter->num_vfs; vf++) {
5886 ciaa = (vf << 16) | 0x80000000;
5887 /* 32 bit read so align, we really want status at offset 6 */
5888 ciaa |= PCI_COMMAND;
5889 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5890 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5892 /* disable debug mode asap after reading data */
5893 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5894 /* Get the upper 16 bits which will be the PCI status reg */
5896 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5897 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5899 ciaa = (vf << 16) | 0x80000000;
5901 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5902 ciad = 0x00008000; /* VFLR */
5903 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5905 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5912 * ixgbe_service_timer - Timer Call-back
5913 * @data: pointer to adapter cast into an unsigned long
5915 static void ixgbe_service_timer(unsigned long data)
5917 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5918 unsigned long next_event_offset;
5921 /* poll faster when waiting for link */
5922 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5923 next_event_offset = HZ / 10;
5925 next_event_offset = HZ * 2;
5927 #ifdef CONFIG_PCI_IOV
5929 * don't bother with SR-IOV VF DMA hang check if there are
5930 * no VFs or the link is down
5932 if (!adapter->num_vfs ||
5933 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5934 goto normal_timer_service;
5936 /* If we have VFs allocated then we must check for DMA hangs */
5937 ixgbe_check_for_bad_vf(adapter);
5938 next_event_offset = HZ / 50;
5939 adapter->timer_event_accumulator++;
5941 if (adapter->timer_event_accumulator >= 100)
5942 adapter->timer_event_accumulator = 0;
5946 normal_timer_service:
5948 /* Reset the timer */
5949 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5952 ixgbe_service_event_schedule(adapter);
5955 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5957 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5960 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5962 /* If we're already down or resetting, just bail */
5963 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5964 test_bit(__IXGBE_RESETTING, &adapter->state))
5967 ixgbe_dump(adapter);
5968 netdev_err(adapter->netdev, "Reset adapter\n");
5969 adapter->tx_timeout_count++;
5971 ixgbe_reinit_locked(adapter);
5975 * ixgbe_service_task - manages and runs subtasks
5976 * @work: pointer to work_struct containing our data
5978 static void ixgbe_service_task(struct work_struct *work)
5980 struct ixgbe_adapter *adapter = container_of(work,
5981 struct ixgbe_adapter,
5983 ixgbe_reset_subtask(adapter);
5984 ixgbe_sfp_detection_subtask(adapter);
5985 ixgbe_sfp_link_config_subtask(adapter);
5986 ixgbe_check_overtemp_subtask(adapter);
5987 ixgbe_watchdog_subtask(adapter);
5988 ixgbe_fdir_reinit_subtask(adapter);
5989 ixgbe_check_hang_subtask(adapter);
5991 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) {
5992 ixgbe_ptp_overflow_check(adapter);
5993 ixgbe_ptp_rx_hang(adapter);
5996 ixgbe_service_event_complete(adapter);
5999 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6000 struct ixgbe_tx_buffer *first,
6003 struct sk_buff *skb = first->skb;
6004 u32 vlan_macip_lens, type_tucmd;
6005 u32 mss_l4len_idx, l4len;
6007 if (skb->ip_summed != CHECKSUM_PARTIAL)
6010 if (!skb_is_gso(skb))
6013 if (skb_header_cloned(skb)) {
6014 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6019 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6020 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6022 if (first->protocol == __constant_htons(ETH_P_IP)) {
6023 struct iphdr *iph = ip_hdr(skb);
6026 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6030 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6031 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6032 IXGBE_TX_FLAGS_CSUM |
6033 IXGBE_TX_FLAGS_IPV4;
6034 } else if (skb_is_gso_v6(skb)) {
6035 ipv6_hdr(skb)->payload_len = 0;
6036 tcp_hdr(skb)->check =
6037 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6038 &ipv6_hdr(skb)->daddr,
6040 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6041 IXGBE_TX_FLAGS_CSUM;
6044 /* compute header lengths */
6045 l4len = tcp_hdrlen(skb);
6046 *hdr_len = skb_transport_offset(skb) + l4len;
6048 /* update gso size and bytecount with header size */
6049 first->gso_segs = skb_shinfo(skb)->gso_segs;
6050 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6052 /* mss_l4len_id: use 0 as index for TSO */
6053 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6054 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6056 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6057 vlan_macip_lens = skb_network_header_len(skb);
6058 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6059 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6061 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6067 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6068 struct ixgbe_tx_buffer *first)
6070 struct sk_buff *skb = first->skb;
6071 u32 vlan_macip_lens = 0;
6072 u32 mss_l4len_idx = 0;
6075 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6076 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6077 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6081 switch (first->protocol) {
6082 case __constant_htons(ETH_P_IP):
6083 vlan_macip_lens |= skb_network_header_len(skb);
6084 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6085 l4_hdr = ip_hdr(skb)->protocol;
6087 case __constant_htons(ETH_P_IPV6):
6088 vlan_macip_lens |= skb_network_header_len(skb);
6089 l4_hdr = ipv6_hdr(skb)->nexthdr;
6092 if (unlikely(net_ratelimit())) {
6093 dev_warn(tx_ring->dev,
6094 "partial checksum but proto=%x!\n",
6102 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6103 mss_l4len_idx = tcp_hdrlen(skb) <<
6104 IXGBE_ADVTXD_L4LEN_SHIFT;
6107 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6108 mss_l4len_idx = sizeof(struct sctphdr) <<
6109 IXGBE_ADVTXD_L4LEN_SHIFT;
6112 mss_l4len_idx = sizeof(struct udphdr) <<
6113 IXGBE_ADVTXD_L4LEN_SHIFT;
6116 if (unlikely(net_ratelimit())) {
6117 dev_warn(tx_ring->dev,
6118 "partial checksum but l4 proto=%x!\n",
6124 /* update TX checksum flag */
6125 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6128 /* vlan_macip_lens: MACLEN, VLAN tag */
6129 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6130 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6132 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6133 type_tucmd, mss_l4len_idx);
6136 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6137 ((_flag <= _result) ? \
6138 ((u32)(_input & _flag) * (_result / _flag)) : \
6139 ((u32)(_input & _flag) / (_flag / _result)))
6141 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6143 /* set type for advanced descriptor with frame checksum insertion */
6144 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6145 IXGBE_ADVTXD_DCMD_DEXT |
6146 IXGBE_ADVTXD_DCMD_IFCS;
6148 /* set HW vlan bit if vlan is present */
6149 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6150 IXGBE_ADVTXD_DCMD_VLE);
6152 /* set segmentation enable bits for TSO/FSO */
6153 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6154 IXGBE_ADVTXD_DCMD_TSE);
6156 /* set timestamp bit if present */
6157 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6158 IXGBE_ADVTXD_MAC_TSTAMP);
6160 /* insert frame checksum */
6161 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6166 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6167 u32 tx_flags, unsigned int paylen)
6169 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6171 /* enable L4 checksum for TSO and TX checksum offload */
6172 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6173 IXGBE_TX_FLAGS_CSUM,
6174 IXGBE_ADVTXD_POPTS_TXSM);
6176 /* enble IPv4 checksum for TSO */
6177 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6178 IXGBE_TX_FLAGS_IPV4,
6179 IXGBE_ADVTXD_POPTS_IXSM);
6182 * Check Context must be set if Tx switch is enabled, which it
6183 * always is for case where virtual functions are running
6185 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6189 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6192 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6195 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6196 struct ixgbe_tx_buffer *first,
6199 struct sk_buff *skb = first->skb;
6200 struct ixgbe_tx_buffer *tx_buffer;
6201 union ixgbe_adv_tx_desc *tx_desc;
6202 struct skb_frag_struct *frag;
6204 unsigned int data_len, size;
6205 u32 tx_flags = first->tx_flags;
6206 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6207 u16 i = tx_ring->next_to_use;
6209 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6211 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6213 size = skb_headlen(skb);
6214 data_len = skb->data_len;
6217 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6218 if (data_len < sizeof(struct fcoe_crc_eof)) {
6219 size -= sizeof(struct fcoe_crc_eof) - data_len;
6222 data_len -= sizeof(struct fcoe_crc_eof);
6227 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6231 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6232 if (dma_mapping_error(tx_ring->dev, dma))
6235 /* record length, and DMA address */
6236 dma_unmap_len_set(tx_buffer, len, size);
6237 dma_unmap_addr_set(tx_buffer, dma, dma);
6239 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6241 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6242 tx_desc->read.cmd_type_len =
6243 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6247 if (i == tx_ring->count) {
6248 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6251 tx_desc->read.olinfo_status = 0;
6253 dma += IXGBE_MAX_DATA_PER_TXD;
6254 size -= IXGBE_MAX_DATA_PER_TXD;
6256 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6259 if (likely(!data_len))
6262 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6266 if (i == tx_ring->count) {
6267 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6270 tx_desc->read.olinfo_status = 0;
6273 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6275 size = skb_frag_size(frag);
6279 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6282 tx_buffer = &tx_ring->tx_buffer_info[i];
6285 /* write last descriptor with RS and EOP bits */
6286 cmd_type |= size | IXGBE_TXD_CMD;
6287 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6289 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6291 /* set the timestamp */
6292 first->time_stamp = jiffies;
6295 * Force memory writes to complete before letting h/w know there
6296 * are new descriptors to fetch. (Only applicable for weak-ordered
6297 * memory model archs, such as IA-64).
6299 * We also need this memory barrier to make certain all of the
6300 * status bits have been updated before next_to_watch is written.
6304 /* set next_to_watch value indicating a packet is present */
6305 first->next_to_watch = tx_desc;
6308 if (i == tx_ring->count)
6311 tx_ring->next_to_use = i;
6313 /* notify HW of packet */
6314 writel(i, tx_ring->tail);
6318 dev_err(tx_ring->dev, "TX DMA map failed\n");
6320 /* clear dma mappings for failed tx_buffer_info map */
6322 tx_buffer = &tx_ring->tx_buffer_info[i];
6323 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6324 if (tx_buffer == first)
6331 tx_ring->next_to_use = i;
6334 static void ixgbe_atr(struct ixgbe_ring *ring,
6335 struct ixgbe_tx_buffer *first)
6337 struct ixgbe_q_vector *q_vector = ring->q_vector;
6338 union ixgbe_atr_hash_dword input = { .dword = 0 };
6339 union ixgbe_atr_hash_dword common = { .dword = 0 };
6341 unsigned char *network;
6343 struct ipv6hdr *ipv6;
6348 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6352 /* do nothing if sampling is disabled */
6353 if (!ring->atr_sample_rate)
6358 /* snag network header to get L4 type and address */
6359 hdr.network = skb_network_header(first->skb);
6361 /* Currently only IPv4/IPv6 with TCP is supported */
6362 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6363 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6364 (first->protocol != __constant_htons(ETH_P_IP) ||
6365 hdr.ipv4->protocol != IPPROTO_TCP))
6368 th = tcp_hdr(first->skb);
6370 /* skip this packet since it is invalid or the socket is closing */
6374 /* sample on all syn packets or once every atr sample count */
6375 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6378 /* reset sample count */
6379 ring->atr_count = 0;
6381 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6384 * src and dst are inverted, think how the receiver sees them
6386 * The input is broken into two sections, a non-compressed section
6387 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6388 * is XORed together and stored in the compressed dword.
6390 input.formatted.vlan_id = vlan_id;
6393 * since src port and flex bytes occupy the same word XOR them together
6394 * and write the value to source port portion of compressed dword
6396 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6397 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6399 common.port.src ^= th->dest ^ first->protocol;
6400 common.port.dst ^= th->source;
6402 if (first->protocol == __constant_htons(ETH_P_IP)) {
6403 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6404 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6406 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6407 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6408 hdr.ipv6->saddr.s6_addr32[1] ^
6409 hdr.ipv6->saddr.s6_addr32[2] ^
6410 hdr.ipv6->saddr.s6_addr32[3] ^
6411 hdr.ipv6->daddr.s6_addr32[0] ^
6412 hdr.ipv6->daddr.s6_addr32[1] ^
6413 hdr.ipv6->daddr.s6_addr32[2] ^
6414 hdr.ipv6->daddr.s6_addr32[3];
6417 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6418 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6419 input, common, ring->queue_index);
6422 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6424 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6425 /* Herbert's original patch had:
6426 * smp_mb__after_netif_stop_queue();
6427 * but since that doesn't exist yet, just open code it. */
6430 /* We need to check again in a case another CPU has just
6431 * made room available. */
6432 if (likely(ixgbe_desc_unused(tx_ring) < size))
6435 /* A reprieve! - use start_queue because it doesn't call schedule */
6436 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6437 ++tx_ring->tx_stats.restart_queue;
6441 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6443 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6445 return __ixgbe_maybe_stop_tx(tx_ring, size);
6449 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6451 struct ixgbe_adapter *adapter;
6452 struct ixgbe_ring_feature *f;
6456 * only execute the code below if protocol is FCoE
6457 * or FIP and we have FCoE enabled on the adapter
6459 switch (vlan_get_protocol(skb)) {
6460 case __constant_htons(ETH_P_FCOE):
6461 case __constant_htons(ETH_P_FIP):
6462 adapter = netdev_priv(dev);
6464 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6467 return __netdev_pick_tx(dev, skb);
6470 f = &adapter->ring_feature[RING_F_FCOE];
6472 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6475 while (txq >= f->indices)
6478 return txq + f->offset;
6482 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6483 struct ixgbe_adapter *adapter,
6484 struct ixgbe_ring *tx_ring)
6486 struct ixgbe_tx_buffer *first;
6490 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6491 __be16 protocol = skb->protocol;
6495 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6496 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6497 * + 2 desc gap to keep tail from touching head,
6498 * + 1 desc for context descriptor,
6499 * otherwise try next time
6501 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6502 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6504 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6505 tx_ring->tx_stats.tx_busy++;
6506 return NETDEV_TX_BUSY;
6509 /* record the location of the first descriptor for this packet */
6510 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6512 first->bytecount = skb->len;
6513 first->gso_segs = 1;
6515 /* if we have a HW VLAN tag being added default to the HW one */
6516 if (vlan_tx_tag_present(skb)) {
6517 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6518 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6519 /* else if it is a SW VLAN check the next protocol and store the tag */
6520 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6521 struct vlan_hdr *vhdr, _vhdr;
6522 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6526 protocol = vhdr->h_vlan_encapsulated_proto;
6527 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6528 IXGBE_TX_FLAGS_VLAN_SHIFT;
6529 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6532 skb_tx_timestamp(skb);
6534 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6535 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6536 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6538 /* schedule check for Tx timestamp */
6539 adapter->ptp_tx_skb = skb_get(skb);
6540 adapter->ptp_tx_start = jiffies;
6541 schedule_work(&adapter->ptp_tx_work);
6544 #ifdef CONFIG_PCI_IOV
6546 * Use the l2switch_enable flag - would be false if the DMA
6547 * Tx switch had been disabled.
6549 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6550 tx_flags |= IXGBE_TX_FLAGS_CC;
6553 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6554 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6555 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6556 (skb->priority != TC_PRIO_CONTROL))) {
6557 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6558 tx_flags |= (skb->priority & 0x7) <<
6559 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6560 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6561 struct vlan_ethhdr *vhdr;
6562 if (skb_header_cloned(skb) &&
6563 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6565 vhdr = (struct vlan_ethhdr *)skb->data;
6566 vhdr->h_vlan_TCI = htons(tx_flags >>
6567 IXGBE_TX_FLAGS_VLAN_SHIFT);
6569 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6573 /* record initial flags and protocol */
6574 first->tx_flags = tx_flags;
6575 first->protocol = protocol;
6578 /* setup tx offload for FCoE */
6579 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6580 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6581 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6588 #endif /* IXGBE_FCOE */
6589 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6593 ixgbe_tx_csum(tx_ring, first);
6595 /* add the ATR filter if ATR is on */
6596 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6597 ixgbe_atr(tx_ring, first);
6601 #endif /* IXGBE_FCOE */
6602 ixgbe_tx_map(tx_ring, first, hdr_len);
6604 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6606 return NETDEV_TX_OK;
6609 dev_kfree_skb_any(first->skb);
6612 return NETDEV_TX_OK;
6615 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6616 struct net_device *netdev)
6618 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6619 struct ixgbe_ring *tx_ring;
6622 * The minimum packet size for olinfo paylen is 17 so pad the skb
6623 * in order to meet this minimum size requirement.
6625 if (unlikely(skb->len < 17)) {
6626 if (skb_pad(skb, 17 - skb->len))
6627 return NETDEV_TX_OK;
6629 skb_set_tail_pointer(skb, 17);
6632 tx_ring = adapter->tx_ring[skb->queue_mapping];
6633 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6637 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6638 * @netdev: network interface device structure
6639 * @p: pointer to an address structure
6641 * Returns 0 on success, negative on failure
6643 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6645 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6646 struct ixgbe_hw *hw = &adapter->hw;
6647 struct sockaddr *addr = p;
6649 if (!is_valid_ether_addr(addr->sa_data))
6650 return -EADDRNOTAVAIL;
6652 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6653 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6655 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
6661 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6663 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6664 struct ixgbe_hw *hw = &adapter->hw;
6668 if (prtad != hw->phy.mdio.prtad)
6670 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6676 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6677 u16 addr, u16 value)
6679 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6680 struct ixgbe_hw *hw = &adapter->hw;
6682 if (prtad != hw->phy.mdio.prtad)
6684 return hw->phy.ops.write_reg(hw, addr, devad, value);
6687 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6689 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6693 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6695 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6700 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6702 * @netdev: network interface device structure
6704 * Returns non-zero on failure
6706 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6709 struct ixgbe_adapter *adapter = netdev_priv(dev);
6710 struct ixgbe_hw *hw = &adapter->hw;
6712 if (is_valid_ether_addr(hw->mac.san_addr)) {
6714 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
6717 /* update SAN MAC vmdq pool selection */
6718 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6724 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6726 * @netdev: network interface device structure
6728 * Returns non-zero on failure
6730 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6733 struct ixgbe_adapter *adapter = netdev_priv(dev);
6734 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6736 if (is_valid_ether_addr(mac->san_addr)) {
6738 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6744 #ifdef CONFIG_NET_POLL_CONTROLLER
6746 * Polling 'interrupt' - used by things like netconsole to send skbs
6747 * without having to re-enable interrupts. It's not called while
6748 * the interrupt routine is executing.
6750 static void ixgbe_netpoll(struct net_device *netdev)
6752 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6755 /* if interface is down do nothing */
6756 if (test_bit(__IXGBE_DOWN, &adapter->state))
6759 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6760 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6761 for (i = 0; i < adapter->num_q_vectors; i++)
6762 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
6764 ixgbe_intr(adapter->pdev->irq, netdev);
6766 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6770 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6771 struct rtnl_link_stats64 *stats)
6773 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6777 for (i = 0; i < adapter->num_rx_queues; i++) {
6778 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6784 start = u64_stats_fetch_begin_bh(&ring->syncp);
6785 packets = ring->stats.packets;
6786 bytes = ring->stats.bytes;
6787 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6788 stats->rx_packets += packets;
6789 stats->rx_bytes += bytes;
6793 for (i = 0; i < adapter->num_tx_queues; i++) {
6794 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6800 start = u64_stats_fetch_begin_bh(&ring->syncp);
6801 packets = ring->stats.packets;
6802 bytes = ring->stats.bytes;
6803 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6804 stats->tx_packets += packets;
6805 stats->tx_bytes += bytes;
6809 /* following stats updated by ixgbe_watchdog_task() */
6810 stats->multicast = netdev->stats.multicast;
6811 stats->rx_errors = netdev->stats.rx_errors;
6812 stats->rx_length_errors = netdev->stats.rx_length_errors;
6813 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6814 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6818 #ifdef CONFIG_IXGBE_DCB
6820 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6821 * @adapter: pointer to ixgbe_adapter
6822 * @tc: number of traffic classes currently enabled
6824 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6825 * 802.1Q priority maps to a packet buffer that exists.
6827 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6829 struct ixgbe_hw *hw = &adapter->hw;
6833 /* 82598 have a static priority to TC mapping that can not
6834 * be changed so no validation is needed.
6836 if (hw->mac.type == ixgbe_mac_82598EB)
6839 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6842 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6843 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6845 /* If up2tc is out of bounds default to zero */
6847 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6851 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6857 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6858 * @adapter: Pointer to adapter struct
6860 * Populate the netdev user priority to tc map
6862 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6864 struct net_device *dev = adapter->netdev;
6865 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6866 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6869 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6872 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6873 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6875 tc = ets->prio_tc[prio];
6877 netdev_set_prio_tc_map(dev, prio, tc);
6881 #endif /* CONFIG_IXGBE_DCB */
6883 * ixgbe_setup_tc - configure net_device for multiple traffic classes
6885 * @netdev: net device to configure
6886 * @tc: number of traffic classes to enable
6888 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6890 struct ixgbe_adapter *adapter = netdev_priv(dev);
6891 struct ixgbe_hw *hw = &adapter->hw;
6893 /* Hardware supports up to 8 traffic classes */
6894 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6895 (hw->mac.type == ixgbe_mac_82598EB &&
6896 tc < MAX_TRAFFIC_CLASS))
6899 /* Hardware has to reinitialize queues and interrupts to
6900 * match packet buffer alignment. Unfortunately, the
6901 * hardware is not flexible enough to do this dynamically.
6903 if (netif_running(dev))
6905 ixgbe_clear_interrupt_scheme(adapter);
6907 #ifdef CONFIG_IXGBE_DCB
6909 netdev_set_num_tc(dev, tc);
6910 ixgbe_set_prio_tc_map(adapter);
6912 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6914 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6915 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
6916 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6919 netdev_reset_tc(dev);
6921 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6922 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6924 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6926 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6927 adapter->dcb_cfg.pfc_mode_enable = false;
6930 ixgbe_validate_rtr(adapter, tc);
6932 #endif /* CONFIG_IXGBE_DCB */
6933 ixgbe_init_interrupt_scheme(adapter);
6935 if (netif_running(dev))
6936 return ixgbe_open(dev);
6941 #ifdef CONFIG_PCI_IOV
6942 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
6944 struct net_device *netdev = adapter->netdev;
6947 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
6952 void ixgbe_do_reset(struct net_device *netdev)
6954 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6956 if (netif_running(netdev))
6957 ixgbe_reinit_locked(adapter);
6959 ixgbe_reset(adapter);
6962 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6963 netdev_features_t features)
6965 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6967 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6968 if (!(features & NETIF_F_RXCSUM))
6969 features &= ~NETIF_F_LRO;
6971 /* Turn off LRO if not RSC capable */
6972 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6973 features &= ~NETIF_F_LRO;
6978 static int ixgbe_set_features(struct net_device *netdev,
6979 netdev_features_t features)
6981 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6982 netdev_features_t changed = netdev->features ^ features;
6983 bool need_reset = false;
6985 /* Make sure RSC matches LRO, reset if change */
6986 if (!(features & NETIF_F_LRO)) {
6987 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6989 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6990 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6991 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6992 if (adapter->rx_itr_setting == 1 ||
6993 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6994 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6996 } else if ((changed ^ features) & NETIF_F_LRO) {
6997 e_info(probe, "rx-usecs set too low, "
7003 * Check if Flow Director n-tuple support was enabled or disabled. If
7004 * the state changed, we need to reset.
7006 switch (features & NETIF_F_NTUPLE) {
7007 case NETIF_F_NTUPLE:
7008 /* turn off ATR, enable perfect filters and reset */
7009 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7012 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7013 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7016 /* turn off perfect filters, enable ATR and reset */
7017 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7020 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7022 /* We cannot enable ATR if SR-IOV is enabled */
7023 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7026 /* We cannot enable ATR if we have 2 or more traffic classes */
7027 if (netdev_get_num_tc(netdev) > 1)
7030 /* We cannot enable ATR if RSS is disabled */
7031 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7034 /* A sample rate of 0 indicates ATR disabled */
7035 if (!adapter->atr_sample_rate)
7038 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7042 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7043 ixgbe_vlan_strip_enable(adapter);
7045 ixgbe_vlan_strip_disable(adapter);
7047 if (changed & NETIF_F_RXALL)
7050 netdev->features = features;
7052 ixgbe_do_reset(netdev);
7057 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7058 struct net_device *dev,
7059 const unsigned char *addr,
7062 struct ixgbe_adapter *adapter = netdev_priv(dev);
7065 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7066 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
7068 /* Hardware does not support aging addresses so if a
7069 * ndm_state is given only allow permanent addresses
7071 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7072 pr_info("%s: FDB only supports static addresses\n",
7077 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7078 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7080 if (netdev_uc_count(dev) < rar_uc_entries)
7081 err = dev_uc_add_excl(dev, addr);
7084 } else if (is_multicast_ether_addr(addr)) {
7085 err = dev_mc_add_excl(dev, addr);
7090 /* Only return duplicate errors if NLM_F_EXCL is set */
7091 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7097 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7098 struct nlmsghdr *nlh)
7100 struct ixgbe_adapter *adapter = netdev_priv(dev);
7101 struct nlattr *attr, *br_spec;
7104 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7107 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7109 nla_for_each_nested(attr, br_spec, rem) {
7113 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7116 mode = nla_get_u16(attr);
7117 if (mode == BRIDGE_MODE_VEPA) {
7119 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7120 } else if (mode == BRIDGE_MODE_VEB) {
7121 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7122 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7126 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7128 e_info(drv, "enabling bridge mode: %s\n",
7129 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7135 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7136 struct net_device *dev,
7139 struct ixgbe_adapter *adapter = netdev_priv(dev);
7142 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7145 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7146 mode = BRIDGE_MODE_VEB;
7148 mode = BRIDGE_MODE_VEPA;
7150 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7153 static const struct net_device_ops ixgbe_netdev_ops = {
7154 .ndo_open = ixgbe_open,
7155 .ndo_stop = ixgbe_close,
7156 .ndo_start_xmit = ixgbe_xmit_frame,
7158 .ndo_select_queue = ixgbe_select_queue,
7160 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7161 .ndo_validate_addr = eth_validate_addr,
7162 .ndo_set_mac_address = ixgbe_set_mac,
7163 .ndo_change_mtu = ixgbe_change_mtu,
7164 .ndo_tx_timeout = ixgbe_tx_timeout,
7165 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7166 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7167 .ndo_do_ioctl = ixgbe_ioctl,
7168 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7169 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7170 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7171 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7172 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7173 .ndo_get_stats64 = ixgbe_get_stats64,
7174 #ifdef CONFIG_IXGBE_DCB
7175 .ndo_setup_tc = ixgbe_setup_tc,
7177 #ifdef CONFIG_NET_POLL_CONTROLLER
7178 .ndo_poll_controller = ixgbe_netpoll,
7181 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7182 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7183 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7184 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7185 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7186 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7187 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7188 #endif /* IXGBE_FCOE */
7189 .ndo_set_features = ixgbe_set_features,
7190 .ndo_fix_features = ixgbe_fix_features,
7191 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7192 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7193 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7197 * ixgbe_wol_supported - Check whether device supports WoL
7198 * @hw: hw specific details
7199 * @device_id: the device ID
7200 * @subdev_id: the subsystem device ID
7202 * This function is used by probe and ethtool to determine
7203 * which devices have WoL support
7206 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7209 struct ixgbe_hw *hw = &adapter->hw;
7210 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7211 int is_wol_supported = 0;
7213 switch (device_id) {
7214 case IXGBE_DEV_ID_82599_SFP:
7215 /* Only these subdevices could supports WOL */
7216 switch (subdevice_id) {
7217 case IXGBE_SUBDEV_ID_82599_560FLR:
7218 /* only support first port */
7219 if (hw->bus.func != 0)
7221 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
7222 case IXGBE_SUBDEV_ID_82599_SFP:
7223 case IXGBE_SUBDEV_ID_82599_RNDC:
7224 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7225 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
7226 is_wol_supported = 1;
7230 case IXGBE_DEV_ID_82599EN_SFP:
7231 /* Only this subdevice supports WOL */
7232 switch (subdevice_id) {
7233 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7234 is_wol_supported = 1;
7238 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7239 /* All except this subdevice support WOL */
7240 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7241 is_wol_supported = 1;
7243 case IXGBE_DEV_ID_82599_KX4:
7244 is_wol_supported = 1;
7246 case IXGBE_DEV_ID_X540T:
7247 case IXGBE_DEV_ID_X540T1:
7248 /* check eeprom to see if enabled wol */
7249 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7250 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7251 (hw->bus.func == 0))) {
7252 is_wol_supported = 1;
7257 return is_wol_supported;
7261 * ixgbe_probe - Device Initialization Routine
7262 * @pdev: PCI device information struct
7263 * @ent: entry in ixgbe_pci_tbl
7265 * Returns 0 on success, negative on failure
7267 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7268 * The OS initialization, configuring of the adapter private structure,
7269 * and a hardware reset occur.
7271 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7273 struct net_device *netdev;
7274 struct ixgbe_adapter *adapter = NULL;
7275 struct ixgbe_hw *hw;
7276 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7277 static int cards_found;
7278 int i, err, pci_using_dac;
7279 unsigned int indices = MAX_TX_QUEUES;
7280 u8 part_str[IXGBE_PBANUM_LENGTH];
7286 /* Catch broken hardware that put the wrong VF device ID in
7287 * the PCIe SR-IOV capability.
7289 if (pdev->is_virtfn) {
7290 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7291 pci_name(pdev), pdev->vendor, pdev->device);
7295 err = pci_enable_device_mem(pdev);
7299 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7300 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7303 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7305 err = dma_set_coherent_mask(&pdev->dev,
7309 "No usable DMA configuration, aborting\n");
7316 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7317 IORESOURCE_MEM), ixgbe_driver_name);
7320 "pci_request_selected_regions failed 0x%x\n", err);
7324 pci_enable_pcie_error_reporting(pdev);
7326 pci_set_master(pdev);
7327 pci_save_state(pdev);
7329 if (ii->mac == ixgbe_mac_82598EB) {
7330 #ifdef CONFIG_IXGBE_DCB
7331 /* 8 TC w/ 4 queues per TC */
7332 indices = 4 * MAX_TRAFFIC_CLASS;
7334 indices = IXGBE_MAX_RSS_INDICES;
7338 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7341 goto err_alloc_etherdev;
7344 SET_NETDEV_DEV(netdev, &pdev->dev);
7346 adapter = netdev_priv(netdev);
7347 pci_set_drvdata(pdev, adapter);
7349 adapter->netdev = netdev;
7350 adapter->pdev = pdev;
7353 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7355 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7356 pci_resource_len(pdev, 0));
7362 netdev->netdev_ops = &ixgbe_netdev_ops;
7363 ixgbe_set_ethtool_ops(netdev);
7364 netdev->watchdog_timeo = 5 * HZ;
7365 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7367 adapter->bd_number = cards_found;
7370 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7371 hw->mac.type = ii->mac;
7374 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7375 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7376 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7377 if (!(eec & (1 << 8)))
7378 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7381 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7382 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7383 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7384 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7385 hw->phy.mdio.mmds = 0;
7386 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7387 hw->phy.mdio.dev = netdev;
7388 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7389 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7391 ii->get_invariants(hw);
7393 /* setup the private structure */
7394 err = ixgbe_sw_init(adapter);
7398 /* Cache if MNG FW is up so we don't have to read the REG later */
7399 if (hw->mac.ops.mng_fw_enabled)
7400 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
7402 /* Make it possible the adapter to be woken up via WOL */
7403 switch (adapter->hw.mac.type) {
7404 case ixgbe_mac_82599EB:
7405 case ixgbe_mac_X540:
7406 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7413 * If there is a fan on this device and it has failed log the
7416 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7417 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7418 if (esdp & IXGBE_ESDP_SDP1)
7419 e_crit(probe, "Fan has stopped, replace the adapter\n");
7422 if (allow_unsupported_sfp)
7423 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7425 /* reset_hw fills in the perm_addr as well */
7426 hw->phy.reset_if_overtemp = true;
7427 err = hw->mac.ops.reset_hw(hw);
7428 hw->phy.reset_if_overtemp = false;
7429 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7430 hw->mac.type == ixgbe_mac_82598EB) {
7432 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7433 e_dev_err("failed to load because an unsupported SFP+ "
7434 "module type was detected.\n");
7435 e_dev_err("Reload the driver after installing a supported "
7439 e_dev_err("HW Init failed: %d\n", err);
7443 #ifdef CONFIG_PCI_IOV
7444 /* SR-IOV not supported on the 82598 */
7445 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7448 ixgbe_init_mbx_params_pf(hw);
7449 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7450 ixgbe_enable_sriov(adapter);
7451 pci_sriov_set_totalvfs(pdev, 63);
7455 netdev->features = NETIF_F_SG |
7458 NETIF_F_HW_VLAN_CTAG_TX |
7459 NETIF_F_HW_VLAN_CTAG_RX |
7460 NETIF_F_HW_VLAN_CTAG_FILTER |
7466 netdev->hw_features = netdev->features;
7468 switch (adapter->hw.mac.type) {
7469 case ixgbe_mac_82599EB:
7470 case ixgbe_mac_X540:
7471 netdev->features |= NETIF_F_SCTP_CSUM;
7472 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7479 netdev->hw_features |= NETIF_F_RXALL;
7481 netdev->vlan_features |= NETIF_F_TSO;
7482 netdev->vlan_features |= NETIF_F_TSO6;
7483 netdev->vlan_features |= NETIF_F_IP_CSUM;
7484 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7485 netdev->vlan_features |= NETIF_F_SG;
7487 netdev->priv_flags |= IFF_UNICAST_FLT;
7488 netdev->priv_flags |= IFF_SUPP_NOFCS;
7490 #ifdef CONFIG_IXGBE_DCB
7491 netdev->dcbnl_ops = &dcbnl_ops;
7495 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7496 unsigned int fcoe_l;
7498 if (hw->mac.ops.get_device_caps) {
7499 hw->mac.ops.get_device_caps(hw, &device_caps);
7500 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7501 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7505 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
7506 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7508 netdev->features |= NETIF_F_FSO |
7511 netdev->vlan_features |= NETIF_F_FSO |
7515 #endif /* IXGBE_FCOE */
7516 if (pci_using_dac) {
7517 netdev->features |= NETIF_F_HIGHDMA;
7518 netdev->vlan_features |= NETIF_F_HIGHDMA;
7521 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7522 netdev->hw_features |= NETIF_F_LRO;
7523 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7524 netdev->features |= NETIF_F_LRO;
7526 /* make sure the EEPROM is good */
7527 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7528 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7533 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7535 if (!is_valid_ether_addr(netdev->dev_addr)) {
7536 e_dev_err("invalid MAC address\n");
7541 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7542 (unsigned long) adapter);
7544 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7545 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7547 err = ixgbe_init_interrupt_scheme(adapter);
7551 /* WOL not supported for all devices */
7553 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7554 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
7555 pdev->subsystem_device);
7556 if (hw->wol_enabled)
7557 adapter->wol = IXGBE_WUFC_MAG;
7559 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7561 /* save off EEPROM version number */
7562 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7563 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7565 /* pick up the PCI bus settings for reporting later */
7566 hw->mac.ops.get_bus_info(hw);
7567 if (hw->device_id == IXGBE_DEV_ID_82599_SFP_SF_QP)
7568 ixgbe_get_parent_bus_info(adapter);
7570 /* print bus type/speed/width info */
7571 e_dev_info("(PCI Express:%s:%s) %pM\n",
7572 (hw->bus.speed == ixgbe_bus_speed_8000 ? "8.0GT/s" :
7573 hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7574 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7576 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7577 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7578 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7582 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7584 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7585 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7586 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7587 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7590 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7591 hw->mac.type, hw->phy.type, part_str);
7593 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7594 e_dev_warn("PCI-Express bandwidth available for this card is "
7595 "not sufficient for optimal performance.\n");
7596 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7600 /* reset the hardware with the new settings */
7601 err = hw->mac.ops.start_hw(hw);
7602 if (err == IXGBE_ERR_EEPROM_VERSION) {
7603 /* We are running on a pre-production device, log a warning */
7604 e_dev_warn("This device is a pre-production adapter/LOM. "
7605 "Please be aware there may be issues associated "
7606 "with your hardware. If you are experiencing "
7607 "problems please contact your Intel or hardware "
7608 "representative who provided you with this "
7611 strcpy(netdev->name, "eth%d");
7612 err = register_netdev(netdev);
7616 /* power down the optics for 82599 SFP+ fiber */
7617 if (hw->mac.ops.disable_tx_laser)
7618 hw->mac.ops.disable_tx_laser(hw);
7620 /* carrier off reporting is important to ethtool even BEFORE open */
7621 netif_carrier_off(netdev);
7623 #ifdef CONFIG_IXGBE_DCA
7624 if (dca_add_requester(&pdev->dev) == 0) {
7625 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7626 ixgbe_setup_dca(adapter);
7629 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7630 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7631 for (i = 0; i < adapter->num_vfs; i++)
7632 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7635 /* firmware requires driver version to be 0xFFFFFFFF
7636 * since os does not support feature
7638 if (hw->mac.ops.set_fw_drv_ver)
7639 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7642 /* add san mac addr to netdev */
7643 ixgbe_add_sanmac_netdev(netdev);
7645 e_dev_info("%s\n", ixgbe_default_device_descr);
7648 #ifdef CONFIG_IXGBE_HWMON
7649 if (ixgbe_sysfs_init(adapter))
7650 e_err(probe, "failed to allocate sysfs resources\n");
7651 #endif /* CONFIG_IXGBE_HWMON */
7653 ixgbe_dbg_adapter_init(adapter);
7655 /* Need link setup for MNG FW, else wait for IXGBE_UP */
7656 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
7657 hw->mac.ops.setup_link(hw,
7658 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
7664 ixgbe_release_hw_control(adapter);
7665 ixgbe_clear_interrupt_scheme(adapter);
7667 ixgbe_disable_sriov(adapter);
7668 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7669 iounmap(hw->hw_addr);
7671 free_netdev(netdev);
7673 pci_release_selected_regions(pdev,
7674 pci_select_bars(pdev, IORESOURCE_MEM));
7677 pci_disable_device(pdev);
7682 * ixgbe_remove - Device Removal Routine
7683 * @pdev: PCI device information struct
7685 * ixgbe_remove is called by the PCI subsystem to alert the driver
7686 * that it should release a PCI device. The could be caused by a
7687 * Hot-Plug event, or because the driver is going to be removed from
7690 static void ixgbe_remove(struct pci_dev *pdev)
7692 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7693 struct net_device *netdev = adapter->netdev;
7695 ixgbe_dbg_adapter_exit(adapter);
7697 set_bit(__IXGBE_DOWN, &adapter->state);
7698 cancel_work_sync(&adapter->service_task);
7701 #ifdef CONFIG_IXGBE_DCA
7702 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7703 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7704 dca_remove_requester(&pdev->dev);
7705 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7709 #ifdef CONFIG_IXGBE_HWMON
7710 ixgbe_sysfs_exit(adapter);
7711 #endif /* CONFIG_IXGBE_HWMON */
7713 /* remove the added san mac */
7714 ixgbe_del_sanmac_netdev(netdev);
7716 if (netdev->reg_state == NETREG_REGISTERED)
7717 unregister_netdev(netdev);
7719 #ifdef CONFIG_PCI_IOV
7721 * Only disable SR-IOV on unload if the user specified the now
7722 * deprecated max_vfs module parameter.
7725 ixgbe_disable_sriov(adapter);
7727 ixgbe_clear_interrupt_scheme(adapter);
7729 ixgbe_release_hw_control(adapter);
7732 kfree(adapter->ixgbe_ieee_pfc);
7733 kfree(adapter->ixgbe_ieee_ets);
7736 iounmap(adapter->hw.hw_addr);
7737 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7740 e_dev_info("complete\n");
7742 free_netdev(netdev);
7744 pci_disable_pcie_error_reporting(pdev);
7746 pci_disable_device(pdev);
7750 * ixgbe_io_error_detected - called when PCI error is detected
7751 * @pdev: Pointer to PCI device
7752 * @state: The current pci connection state
7754 * This function is called after a PCI bus error affecting
7755 * this device has been detected.
7757 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7758 pci_channel_state_t state)
7760 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7761 struct net_device *netdev = adapter->netdev;
7763 #ifdef CONFIG_PCI_IOV
7764 struct pci_dev *bdev, *vfdev;
7765 u32 dw0, dw1, dw2, dw3;
7767 u16 req_id, pf_func;
7769 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7770 adapter->num_vfs == 0)
7771 goto skip_bad_vf_detection;
7773 bdev = pdev->bus->self;
7774 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
7775 bdev = bdev->bus->self;
7778 goto skip_bad_vf_detection;
7780 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7782 goto skip_bad_vf_detection;
7784 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7785 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7786 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7787 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7790 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7791 if (!(req_id & 0x0080))
7792 goto skip_bad_vf_detection;
7794 pf_func = req_id & 0x01;
7795 if ((pf_func & 1) == (pdev->devfn & 1)) {
7796 unsigned int device_id;
7798 vf = (req_id & 0x7F) >> 1;
7799 e_dev_err("VF %d has caused a PCIe error\n", vf);
7800 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7801 "%8.8x\tdw3: %8.8x\n",
7802 dw0, dw1, dw2, dw3);
7803 switch (adapter->hw.mac.type) {
7804 case ixgbe_mac_82599EB:
7805 device_id = IXGBE_82599_VF_DEVICE_ID;
7807 case ixgbe_mac_X540:
7808 device_id = IXGBE_X540_VF_DEVICE_ID;
7815 /* Find the pci device of the offending VF */
7816 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
7818 if (vfdev->devfn == (req_id & 0xFF))
7820 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
7824 * There's a slim chance the VF could have been hot plugged,
7825 * so if it is no longer present we don't need to issue the
7826 * VFLR. Just clean up the AER in that case.
7829 e_dev_err("Issuing VFLR to VF %d\n", vf);
7830 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7831 /* Free device reference count */
7835 pci_cleanup_aer_uncorrect_error_status(pdev);
7839 * Even though the error may have occurred on the other port
7840 * we still need to increment the vf error reference count for
7841 * both ports because the I/O resume function will be called
7844 adapter->vferr_refcount++;
7846 return PCI_ERS_RESULT_RECOVERED;
7848 skip_bad_vf_detection:
7849 #endif /* CONFIG_PCI_IOV */
7850 netif_device_detach(netdev);
7852 if (state == pci_channel_io_perm_failure)
7853 return PCI_ERS_RESULT_DISCONNECT;
7855 if (netif_running(netdev))
7856 ixgbe_down(adapter);
7857 pci_disable_device(pdev);
7859 /* Request a slot reset. */
7860 return PCI_ERS_RESULT_NEED_RESET;
7864 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7865 * @pdev: Pointer to PCI device
7867 * Restart the card from scratch, as if from a cold-boot.
7869 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7871 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7872 pci_ers_result_t result;
7875 if (pci_enable_device_mem(pdev)) {
7876 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7877 result = PCI_ERS_RESULT_DISCONNECT;
7879 pci_set_master(pdev);
7880 pci_restore_state(pdev);
7881 pci_save_state(pdev);
7883 pci_wake_from_d3(pdev, false);
7885 ixgbe_reset(adapter);
7886 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7887 result = PCI_ERS_RESULT_RECOVERED;
7890 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7892 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7893 "failed 0x%0x\n", err);
7894 /* non-fatal, continue */
7901 * ixgbe_io_resume - called when traffic can start flowing again.
7902 * @pdev: Pointer to PCI device
7904 * This callback is called when the error recovery driver tells us that
7905 * its OK to resume normal operation.
7907 static void ixgbe_io_resume(struct pci_dev *pdev)
7909 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7910 struct net_device *netdev = adapter->netdev;
7912 #ifdef CONFIG_PCI_IOV
7913 if (adapter->vferr_refcount) {
7914 e_info(drv, "Resuming after VF err\n");
7915 adapter->vferr_refcount--;
7920 if (netif_running(netdev))
7923 netif_device_attach(netdev);
7926 static const struct pci_error_handlers ixgbe_err_handler = {
7927 .error_detected = ixgbe_io_error_detected,
7928 .slot_reset = ixgbe_io_slot_reset,
7929 .resume = ixgbe_io_resume,
7932 static struct pci_driver ixgbe_driver = {
7933 .name = ixgbe_driver_name,
7934 .id_table = ixgbe_pci_tbl,
7935 .probe = ixgbe_probe,
7936 .remove = ixgbe_remove,
7938 .suspend = ixgbe_suspend,
7939 .resume = ixgbe_resume,
7941 .shutdown = ixgbe_shutdown,
7942 .sriov_configure = ixgbe_pci_sriov_configure,
7943 .err_handler = &ixgbe_err_handler
7947 * ixgbe_init_module - Driver Registration Routine
7949 * ixgbe_init_module is the first routine called when the driver is
7950 * loaded. All it does is register with the PCI subsystem.
7952 static int __init ixgbe_init_module(void)
7955 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7956 pr_info("%s\n", ixgbe_copyright);
7960 ret = pci_register_driver(&ixgbe_driver);
7966 #ifdef CONFIG_IXGBE_DCA
7967 dca_register_notify(&dca_notifier);
7973 module_init(ixgbe_init_module);
7976 * ixgbe_exit_module - Driver Exit Cleanup Routine
7978 * ixgbe_exit_module is called just before the driver is removed
7981 static void __exit ixgbe_exit_module(void)
7983 #ifdef CONFIG_IXGBE_DCA
7984 dca_unregister_notify(&dca_notifier);
7986 pci_unregister_driver(&ixgbe_driver);
7990 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7993 #ifdef CONFIG_IXGBE_DCA
7994 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7999 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8000 __ixgbe_notify_dca);
8002 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8005 #endif /* CONFIG_IXGBE_DCA */
8007 module_exit(ixgbe_exit_module);