1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018 Intel Corporation */
5 #include <linux/delay.h>
10 /* forward declaration */
11 static s32 igc_set_fc_watermarks(struct igc_hw *hw);
14 * igc_disable_pcie_master - Disables PCI-express master access
15 * @hw: pointer to the HW structure
17 * Returns 0 (0) if successful, else returns -10
18 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
19 * the master requests to be disabled.
21 * Disables PCI-Express master access and verifies there are no pending
24 s32 igc_disable_pcie_master(struct igc_hw *hw)
26 s32 timeout = MASTER_DISABLE_TIMEOUT;
30 ctrl = rd32(IGC_CTRL);
31 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;
35 if (!(rd32(IGC_STATUS) &
36 IGC_STATUS_GIO_MASTER_ENABLE))
38 usleep_range(2000, 3000);
43 hw_dbg("Master requests are pending.\n");
44 ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING;
53 * igc_init_rx_addrs - Initialize receive addresses
54 * @hw: pointer to the HW structure
55 * @rar_count: receive address registers
57 * Setup the receive address registers by setting the base receive address
58 * register to the devices MAC address and clearing all the other receive
59 * address registers to 0.
61 void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count)
63 u8 mac_addr[ETH_ALEN] = {0};
66 /* Setup the receive address */
67 hw_dbg("Programming MAC Address into RAR[0]\n");
69 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
71 /* Zero out the other (rar_entry_count - 1) receive addresses */
72 hw_dbg("Clearing RAR[1-%u]\n", rar_count - 1);
73 for (i = 1; i < rar_count; i++)
74 hw->mac.ops.rar_set(hw, mac_addr, i);
78 * igc_setup_link - Setup flow control and link settings
79 * @hw: pointer to the HW structure
81 * Determines which flow control settings to use, then configures flow
82 * control. Calls the appropriate media-specific link configuration
83 * function. Assuming the adapter has a valid link partner, a valid link
84 * should be established. Assumes the hardware has previously been reset
85 * and the transmitter and receiver are not enabled.
87 s32 igc_setup_link(struct igc_hw *hw)
91 /* In the case of the phy reset being blocked, we already have a link.
92 * We do not need to set it up again.
94 if (igc_check_reset_block(hw))
97 /* If requested flow control is set to default, set flow control
98 * to the both 'rx' and 'tx' pause frames.
100 if (hw->fc.requested_mode == igc_fc_default)
101 hw->fc.requested_mode = igc_fc_full;
103 /* We want to save off the original Flow Control configuration just
104 * in case we get disconnected and then reconnected into a different
105 * hub or switch with different Flow Control capabilities.
107 hw->fc.current_mode = hw->fc.requested_mode;
109 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
111 /* Call the necessary media_type subroutine to configure the link. */
112 ret_val = hw->mac.ops.setup_physical_interface(hw);
116 /* Initialize the flow control address, type, and PAUSE timer
117 * registers to their default values. This is done even if flow
118 * control is disabled, because it does not hurt anything to
119 * initialize these registers.
121 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
122 wr32(IGC_FCT, FLOW_CONTROL_TYPE);
123 wr32(IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
124 wr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);
126 wr32(IGC_FCTTV, hw->fc.pause_time);
128 ret_val = igc_set_fc_watermarks(hw);
135 * igc_force_mac_fc - Force the MAC's flow control settings
136 * @hw: pointer to the HW structure
138 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
139 * device control register to reflect the adapter settings. TFCE and RFCE
140 * need to be explicitly set by software when a copper PHY is used because
141 * autonegotiation is managed by the PHY rather than the MAC. Software must
142 * also configure these bits when link is forced on a fiber connection.
144 s32 igc_force_mac_fc(struct igc_hw *hw)
149 ctrl = rd32(IGC_CTRL);
151 /* Because we didn't get link via the internal auto-negotiation
152 * mechanism (we either forced link or we got link via PHY
153 * auto-neg), we have to manually enable/disable transmit an
154 * receive flow control.
156 * The "Case" statement below enables/disable flow control
157 * according to the "hw->fc.current_mode" parameter.
159 * The possible values of the "fc" parameter are:
160 * 0: Flow control is completely disabled
161 * 1: Rx flow control is enabled (we can receive pause
162 * frames but not send pause frames).
163 * 2: Tx flow control is enabled (we can send pause frames
164 * frames but we do not receive pause frames).
165 * 3: Both Rx and TX flow control (symmetric) is enabled.
166 * other: No other values should be possible at this point.
168 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
170 switch (hw->fc.current_mode) {
172 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));
174 case igc_fc_rx_pause:
175 ctrl &= (~IGC_CTRL_TFCE);
176 ctrl |= IGC_CTRL_RFCE;
178 case igc_fc_tx_pause:
179 ctrl &= (~IGC_CTRL_RFCE);
180 ctrl |= IGC_CTRL_TFCE;
183 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);
186 hw_dbg("Flow control param set incorrectly\n");
187 ret_val = -IGC_ERR_CONFIG;
191 wr32(IGC_CTRL, ctrl);
198 * igc_set_fc_watermarks - Set flow control high/low watermarks
199 * @hw: pointer to the HW structure
201 * Sets the flow control high/low threshold (watermark) registers. If
202 * flow control XON frame transmission is enabled, then set XON frame
203 * transmission as well.
205 static s32 igc_set_fc_watermarks(struct igc_hw *hw)
207 u32 fcrtl = 0, fcrth = 0;
209 /* Set the flow control receive threshold registers. Normally,
210 * these registers will be set to a default threshold that may be
211 * adjusted later by the driver's runtime code. However, if the
212 * ability to transmit pause frames is not enabled, then these
213 * registers will be set to 0.
215 if (hw->fc.current_mode & igc_fc_tx_pause) {
216 /* We need to set up the Receive Threshold high and low water
217 * marks as well as (optionally) enabling the transmission of
220 fcrtl = hw->fc.low_water;
222 fcrtl |= IGC_FCRTL_XONE;
224 fcrth = hw->fc.high_water;
226 wr32(IGC_FCRTL, fcrtl);
227 wr32(IGC_FCRTH, fcrth);
233 * igc_clear_hw_cntrs_base - Clear base hardware counters
234 * @hw: pointer to the HW structure
236 * Clears the base hardware counters by reading the counter registers.
238 void igc_clear_hw_cntrs_base(struct igc_hw *hw)
327 * igc_rar_set - Set receive address register
328 * @hw: pointer to the HW structure
329 * @addr: pointer to the receive address
330 * @index: receive address array register
332 * Sets the receive address array register at index to the address passed
335 void igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index)
337 u32 rar_low, rar_high;
339 /* HW expects these in little endian so we reverse the byte order
340 * from network order (big endian) to little endian
342 rar_low = ((u32)addr[0] |
343 ((u32)addr[1] << 8) |
344 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
346 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
348 /* If MAC address zero, no need to set the AV bit */
349 if (rar_low || rar_high)
350 rar_high |= IGC_RAH_AV;
352 /* Some bridges will combine consecutive 32-bit writes into
353 * a single burst write, which will malfunction on some parts.
354 * The flushes avoid this.
356 wr32(IGC_RAL(index), rar_low);
358 wr32(IGC_RAH(index), rar_high);
363 * igc_check_for_copper_link - Check for link (Copper)
364 * @hw: pointer to the HW structure
366 * Checks to see of the link status of the hardware has changed. If a
367 * change in link status has been detected, then we read the PHY registers
368 * to get the current speed/duplex if link exists.
370 s32 igc_check_for_copper_link(struct igc_hw *hw)
372 struct igc_mac_info *mac = &hw->mac;
376 /* We only want to go out to the PHY registers to see if Auto-Neg
377 * has completed and/or if our link status has changed. The
378 * get_link_status flag is set upon receiving a Link Status
379 * Change or Rx Sequence Error interrupt.
381 if (!mac->get_link_status) {
386 /* First we want to see if the MII Status Register reports
387 * link. If so, then we want to get the current speed/duplex
390 ret_val = igc_phy_has_link(hw, 1, 0, &link);
395 goto out; /* No link detected */
397 mac->get_link_status = false;
399 /* Check if there was DownShift, must be checked
400 * immediately after link-up
402 igc_check_downshift(hw);
404 /* If we are forcing speed/duplex, then we simply return since
405 * we have already determined whether we have link or not.
408 ret_val = -IGC_ERR_CONFIG;
412 /* Auto-Neg is enabled. Auto Speed Detection takes care
413 * of MAC speed/duplex configuration. So we only need to
414 * configure Collision Distance in the MAC.
416 igc_config_collision_dist(hw);
418 /* Configure Flow Control now that Auto-Neg has completed.
419 * First, we need to restore the desired flow control
420 * settings because we may have had to re-autoneg with a
421 * different link partner.
423 ret_val = igc_config_fc_after_link_up(hw);
425 hw_dbg("Error configuring flow control\n");
432 * igc_config_collision_dist - Configure collision distance
433 * @hw: pointer to the HW structure
435 * Configures the collision distance to the default value and is used
436 * during link setup. Currently no func pointer exists and all
437 * implementations are handled in the generic version of this function.
439 void igc_config_collision_dist(struct igc_hw *hw)
443 tctl = rd32(IGC_TCTL);
445 tctl &= ~IGC_TCTL_COLD;
446 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT;
448 wr32(IGC_TCTL, tctl);
453 * igc_config_fc_after_link_up - Configures flow control after link
454 * @hw: pointer to the HW structure
456 * Checks the status of auto-negotiation after link up to ensure that the
457 * speed and duplex were not forced. If the link needed to be forced, then
458 * flow control needs to be forced also. If auto-negotiation is enabled
459 * and did not fail, then we configure flow control based on our link
462 s32 igc_config_fc_after_link_up(struct igc_hw *hw)
464 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
465 struct igc_mac_info *mac = &hw->mac;
469 /* Check for the case where we have fiber media and auto-neg failed
470 * so we had to force link. In this case, we need to force the
471 * configuration of the MAC to match the "fc" parameter.
473 if (mac->autoneg_failed) {
474 if (hw->phy.media_type == igc_media_type_copper)
475 ret_val = igc_force_mac_fc(hw);
479 hw_dbg("Error forcing flow control settings\n");
483 /* Check for the case where we have copper media and auto-neg is
484 * enabled. In this case, we need to check and see if Auto-Neg
485 * has completed, and if so, how the PHY and link partner has
486 * flow control configured.
488 if (hw->phy.media_type == igc_media_type_copper && mac->autoneg) {
489 /* Read the MII Status Register and check to see if AutoNeg
490 * has completed. We read this twice because this reg has
491 * some "sticky" (latched) bits.
493 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
497 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
502 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
503 hw_dbg("Copper PHY and Auto Neg has not completed.\n");
507 /* The AutoNeg process has completed, so we now need to
508 * read both the Auto Negotiation Advertisement
509 * Register (Address 4) and the Auto_Negotiation Base
510 * Page Ability Register (Address 5) to determine how
511 * flow control was negotiated.
513 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
517 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
518 &mii_nway_lp_ability_reg);
521 /* Two bits in the Auto Negotiation Advertisement Register
522 * (Address 4) and two bits in the Auto Negotiation Base
523 * Page Ability Register (Address 5) determine flow control
524 * for both the PHY and the link partner. The following
525 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
526 * 1999, describes these PAUSE resolution bits and how flow
527 * control is determined based upon these settings.
528 * NOTE: DC = Don't Care
530 * LOCAL DEVICE | LINK PARTNER
531 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
532 *-------|---------|-------|---------|--------------------
533 * 0 | 0 | DC | DC | igc_fc_none
534 * 0 | 1 | 0 | DC | igc_fc_none
535 * 0 | 1 | 1 | 0 | igc_fc_none
536 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
537 * 1 | 0 | 0 | DC | igc_fc_none
538 * 1 | DC | 1 | DC | igc_fc_full
539 * 1 | 1 | 0 | 0 | igc_fc_none
540 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
542 * Are both PAUSE bits set to 1? If so, this implies
543 * Symmetric Flow Control is enabled at both ends. The
544 * ASM_DIR bits are irrelevant per the spec.
546 * For Symmetric Flow Control:
548 * LOCAL DEVICE | LINK PARTNER
549 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
550 *-------|---------|-------|---------|--------------------
551 * 1 | DC | 1 | DC | IGC_fc_full
554 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
555 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
556 /* Now we need to check if the user selected RX ONLY
557 * of pause frames. In this case, we had to advertise
558 * FULL flow control because we could not advertise RX
559 * ONLY. Hence, we must now check to see if we need to
560 * turn OFF the TRANSMISSION of PAUSE frames.
562 if (hw->fc.requested_mode == igc_fc_full) {
563 hw->fc.current_mode = igc_fc_full;
564 hw_dbg("Flow Control = FULL.\n");
566 hw->fc.current_mode = igc_fc_rx_pause;
567 hw_dbg("Flow Control = RX PAUSE frames only.\n");
571 /* For receiving PAUSE frames ONLY.
573 * LOCAL DEVICE | LINK PARTNER
574 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
575 *-------|---------|-------|---------|--------------------
576 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
578 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
579 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
580 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
581 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
582 hw->fc.current_mode = igc_fc_tx_pause;
583 hw_dbg("Flow Control = TX PAUSE frames only.\n");
585 /* For transmitting PAUSE frames ONLY.
587 * LOCAL DEVICE | LINK PARTNER
588 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
589 *-------|---------|-------|---------|--------------------
590 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
592 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
593 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
594 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
595 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
596 hw->fc.current_mode = igc_fc_rx_pause;
597 hw_dbg("Flow Control = RX PAUSE frames only.\n");
599 /* Per the IEEE spec, at this point flow control should be
600 * disabled. However, we want to consider that we could
601 * be connected to a legacy switch that doesn't advertise
602 * desired flow control, but can be forced on the link
603 * partner. So if we advertised no flow control, that is
604 * what we will resolve to. If we advertised some kind of
605 * receive capability (Rx Pause Only or Full Flow Control)
606 * and the link partner advertised none, we will configure
607 * ourselves to enable Rx Flow Control only. We can do
608 * this safely for two reasons: If the link partner really
609 * didn't want flow control enabled, and we enable Rx, no
610 * harm done since we won't be receiving any PAUSE frames
611 * anyway. If the intent on the link partner was to have
612 * flow control enabled, then by us enabling RX only, we
613 * can at least receive pause frames and process them.
614 * This is a good idea because in most cases, since we are
615 * predominantly a server NIC, more times than not we will
616 * be asked to delay transmission of packets than asking
617 * our link partner to pause transmission of frames.
619 else if ((hw->fc.requested_mode == igc_fc_none) ||
620 (hw->fc.requested_mode == igc_fc_tx_pause) ||
621 (hw->fc.strict_ieee)) {
622 hw->fc.current_mode = igc_fc_none;
623 hw_dbg("Flow Control = NONE.\n");
625 hw->fc.current_mode = igc_fc_rx_pause;
626 hw_dbg("Flow Control = RX PAUSE frames only.\n");
629 /* Now we need to do one last check... If we auto-
630 * negotiated to HALF DUPLEX, flow control should not be
631 * enabled per IEEE 802.3 spec.
633 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
635 hw_dbg("Error getting link speed and duplex\n");
639 if (duplex == HALF_DUPLEX)
640 hw->fc.current_mode = igc_fc_none;
642 /* Now we call a subroutine to actually force the MAC
643 * controller to use the correct flow control settings.
645 ret_val = igc_force_mac_fc(hw);
647 hw_dbg("Error forcing flow control settings\n");
657 * igc_get_auto_rd_done - Check for auto read completion
658 * @hw: pointer to the HW structure
660 * Check EEPROM for Auto Read done bit.
662 s32 igc_get_auto_rd_done(struct igc_hw *hw)
667 while (i < AUTO_READ_DONE_TIMEOUT) {
668 if (rd32(IGC_EECD) & IGC_EECD_AUTO_RD)
670 usleep_range(1000, 2000);
674 if (i == AUTO_READ_DONE_TIMEOUT) {
675 hw_dbg("Auto read by HW from NVM has not completed.\n");
676 ret_val = -IGC_ERR_RESET;
685 * igc_get_speed_and_duplex_copper - Retrieve current speed/duplex
686 * @hw: pointer to the HW structure
687 * @speed: stores the current speed
688 * @duplex: stores the current duplex
690 * Read the status register for the current speed/duplex and store the current
691 * speed and duplex for copper connections.
693 s32 igc_get_speed_and_duplex_copper(struct igc_hw *hw, u16 *speed,
698 status = rd32(IGC_STATUS);
699 if (status & IGC_STATUS_SPEED_1000) {
700 /* For I225, STATUS will indicate 1G speed in both 1 Gbps
701 * and 2.5 Gbps link modes. An additional bit is used
702 * to differentiate between 1 Gbps and 2.5 Gbps.
704 if (hw->mac.type == igc_i225 &&
705 (status & IGC_STATUS_SPEED_2500)) {
707 hw_dbg("2500 Mbs, ");
710 hw_dbg("1000 Mbs, ");
712 } else if (status & IGC_STATUS_SPEED_100) {
720 if (status & IGC_STATUS_FD) {
721 *duplex = FULL_DUPLEX;
722 hw_dbg("Full Duplex\n");
724 *duplex = HALF_DUPLEX;
725 hw_dbg("Half Duplex\n");
732 * igc_put_hw_semaphore - Release hardware semaphore
733 * @hw: pointer to the HW structure
735 * Release hardware semaphore used to access the PHY or NVM
737 void igc_put_hw_semaphore(struct igc_hw *hw)
741 swsm = rd32(IGC_SWSM);
743 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);
745 wr32(IGC_SWSM, swsm);
749 * igc_enable_mng_pass_thru - Enable processing of ARP's
750 * @hw: pointer to the HW structure
752 * Verifies the hardware needs to leave interface enabled so that frames can
753 * be directed to and from the management interface.
755 bool igc_enable_mng_pass_thru(struct igc_hw *hw)
757 bool ret_val = false;
761 if (!hw->mac.asf_firmware_present)
764 manc = rd32(IGC_MANC);
766 if (!(manc & IGC_MANC_RCV_TCO_EN))
769 if (hw->mac.arc_subsystem_valid) {
770 fwsm = rd32(IGC_FWSM);
771 factps = rd32(IGC_FACTPS);
773 if (!(factps & IGC_FACTPS_MNGCG) &&
774 ((fwsm & IGC_FWSM_MODE_MASK) ==
775 (igc_mng_mode_pt << IGC_FWSM_MODE_SHIFT))) {
780 if ((manc & IGC_MANC_SMBUS_EN) &&
781 !(manc & IGC_MANC_ASF_EN)) {