1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 #include <linux/if_ether.h>
25 #include <linux/delay.h>
27 #include "e1000_mac.h"
28 #include "e1000_phy.h"
30 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
31 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
33 static s32 igb_wait_autoneg(struct e1000_hw *hw);
34 static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
36 /* Cable length tables */
37 static const u16 e1000_m88_cable_length_table[] = {
38 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
39 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
40 (sizeof(e1000_m88_cable_length_table) / \
41 sizeof(e1000_m88_cable_length_table[0]))
43 static const u16 e1000_igp_2_cable_length_table[] = {
44 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
45 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
46 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
47 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
48 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
49 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
50 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
51 104, 109, 114, 118, 121, 124};
52 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
53 (sizeof(e1000_igp_2_cable_length_table) / \
54 sizeof(e1000_igp_2_cable_length_table[0]))
57 * igb_check_reset_block - Check if PHY reset is blocked
58 * @hw: pointer to the HW structure
60 * Read the PHY management control register and check whether a PHY reset
61 * is blocked. If a reset is not blocked return 0, otherwise
62 * return E1000_BLK_PHY_RESET (12).
64 s32 igb_check_reset_block(struct e1000_hw *hw)
68 manc = rd32(E1000_MANC);
70 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
74 * igb_get_phy_id - Retrieve the PHY ID and revision
75 * @hw: pointer to the HW structure
77 * Reads the PHY registers and stores the PHY ID and possibly the PHY
78 * revision in the hardware structure.
80 s32 igb_get_phy_id(struct e1000_hw *hw)
82 struct e1000_phy_info *phy = &hw->phy;
86 /* ensure PHY page selection to fix misconfigured i210 */
87 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
88 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0);
90 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
94 phy->id = (u32)(phy_id << 16);
96 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
100 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
101 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
108 * igb_phy_reset_dsp - Reset PHY DSP
109 * @hw: pointer to the HW structure
111 * Reset the digital signal processor.
113 static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
117 if (!(hw->phy.ops.write_reg))
120 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
124 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
131 * igb_read_phy_reg_mdic - Read MDI control register
132 * @hw: pointer to the HW structure
133 * @offset: register offset to be read
134 * @data: pointer to the read data
136 * Reads the MDI control regsiter in the PHY at offset and stores the
137 * information read to data.
139 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
141 struct e1000_phy_info *phy = &hw->phy;
145 if (offset > MAX_PHY_REG_ADDRESS) {
146 hw_dbg("PHY Address %d is out of range\n", offset);
147 ret_val = -E1000_ERR_PARAM;
151 /* Set up Op-code, Phy Address, and register offset in the MDI
152 * Control register. The MAC will take care of interfacing with the
153 * PHY to retrieve the desired data.
155 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
156 (phy->addr << E1000_MDIC_PHY_SHIFT) |
157 (E1000_MDIC_OP_READ));
159 wr32(E1000_MDIC, mdic);
161 /* Poll the ready bit to see if the MDI read completed
162 * Increasing the time out as testing showed failures with
165 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
167 mdic = rd32(E1000_MDIC);
168 if (mdic & E1000_MDIC_READY)
171 if (!(mdic & E1000_MDIC_READY)) {
172 hw_dbg("MDI Read did not complete\n");
173 ret_val = -E1000_ERR_PHY;
176 if (mdic & E1000_MDIC_ERROR) {
177 hw_dbg("MDI Error\n");
178 ret_val = -E1000_ERR_PHY;
188 * igb_write_phy_reg_mdic - Write MDI control register
189 * @hw: pointer to the HW structure
190 * @offset: register offset to write to
191 * @data: data to write to register at offset
193 * Writes data to MDI control register in the PHY at offset.
195 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
197 struct e1000_phy_info *phy = &hw->phy;
201 if (offset > MAX_PHY_REG_ADDRESS) {
202 hw_dbg("PHY Address %d is out of range\n", offset);
203 ret_val = -E1000_ERR_PARAM;
207 /* Set up Op-code, Phy Address, and register offset in the MDI
208 * Control register. The MAC will take care of interfacing with the
209 * PHY to retrieve the desired data.
211 mdic = (((u32)data) |
212 (offset << E1000_MDIC_REG_SHIFT) |
213 (phy->addr << E1000_MDIC_PHY_SHIFT) |
214 (E1000_MDIC_OP_WRITE));
216 wr32(E1000_MDIC, mdic);
218 /* Poll the ready bit to see if the MDI read completed
219 * Increasing the time out as testing showed failures with
222 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
224 mdic = rd32(E1000_MDIC);
225 if (mdic & E1000_MDIC_READY)
228 if (!(mdic & E1000_MDIC_READY)) {
229 hw_dbg("MDI Write did not complete\n");
230 ret_val = -E1000_ERR_PHY;
233 if (mdic & E1000_MDIC_ERROR) {
234 hw_dbg("MDI Error\n");
235 ret_val = -E1000_ERR_PHY;
244 * igb_read_phy_reg_i2c - Read PHY register using i2c
245 * @hw: pointer to the HW structure
246 * @offset: register offset to be read
247 * @data: pointer to the read data
249 * Reads the PHY register at offset using the i2c interface and stores the
250 * retrieved information in data.
252 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
254 struct e1000_phy_info *phy = &hw->phy;
257 /* Set up Op-code, Phy Address, and register address in the I2CCMD
258 * register. The MAC will take care of interfacing with the
259 * PHY to retrieve the desired data.
261 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
262 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
263 (E1000_I2CCMD_OPCODE_READ));
265 wr32(E1000_I2CCMD, i2ccmd);
267 /* Poll the ready bit to see if the I2C read completed */
268 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
270 i2ccmd = rd32(E1000_I2CCMD);
271 if (i2ccmd & E1000_I2CCMD_READY)
274 if (!(i2ccmd & E1000_I2CCMD_READY)) {
275 hw_dbg("I2CCMD Read did not complete\n");
276 return -E1000_ERR_PHY;
278 if (i2ccmd & E1000_I2CCMD_ERROR) {
279 hw_dbg("I2CCMD Error bit set\n");
280 return -E1000_ERR_PHY;
283 /* Need to byte-swap the 16-bit value. */
284 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
290 * igb_write_phy_reg_i2c - Write PHY register using i2c
291 * @hw: pointer to the HW structure
292 * @offset: register offset to write to
293 * @data: data to write at register offset
295 * Writes the data to PHY register at the offset using the i2c interface.
297 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
299 struct e1000_phy_info *phy = &hw->phy;
301 u16 phy_data_swapped;
303 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
304 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
305 hw_dbg("PHY I2C Address %d is out of range.\n",
307 return -E1000_ERR_CONFIG;
310 /* Swap the data bytes for the I2C interface */
311 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
313 /* Set up Op-code, Phy Address, and register address in the I2CCMD
314 * register. The MAC will take care of interfacing with the
315 * PHY to retrieve the desired data.
317 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
318 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
319 E1000_I2CCMD_OPCODE_WRITE |
322 wr32(E1000_I2CCMD, i2ccmd);
324 /* Poll the ready bit to see if the I2C read completed */
325 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
327 i2ccmd = rd32(E1000_I2CCMD);
328 if (i2ccmd & E1000_I2CCMD_READY)
331 if (!(i2ccmd & E1000_I2CCMD_READY)) {
332 hw_dbg("I2CCMD Write did not complete\n");
333 return -E1000_ERR_PHY;
335 if (i2ccmd & E1000_I2CCMD_ERROR) {
336 hw_dbg("I2CCMD Error bit set\n");
337 return -E1000_ERR_PHY;
344 * igb_read_sfp_data_byte - Reads SFP module data.
345 * @hw: pointer to the HW structure
346 * @offset: byte location offset to be read
347 * @data: read data buffer pointer
349 * Reads one byte from SFP module data stored
350 * in SFP resided EEPROM memory or SFP diagnostic area.
351 * Function should be called with
352 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
353 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
356 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
362 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
363 hw_dbg("I2CCMD command address exceeds upper limit\n");
364 return -E1000_ERR_PHY;
367 /* Set up Op-code, EEPROM Address,in the I2CCMD
368 * register. The MAC will take care of interfacing with the
369 * EEPROM to retrieve the desired data.
371 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
372 E1000_I2CCMD_OPCODE_READ);
374 wr32(E1000_I2CCMD, i2ccmd);
376 /* Poll the ready bit to see if the I2C read completed */
377 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
379 data_local = rd32(E1000_I2CCMD);
380 if (data_local & E1000_I2CCMD_READY)
383 if (!(data_local & E1000_I2CCMD_READY)) {
384 hw_dbg("I2CCMD Read did not complete\n");
385 return -E1000_ERR_PHY;
387 if (data_local & E1000_I2CCMD_ERROR) {
388 hw_dbg("I2CCMD Error bit set\n");
389 return -E1000_ERR_PHY;
391 *data = (u8) data_local & 0xFF;
397 * igb_read_phy_reg_igp - Read igp PHY register
398 * @hw: pointer to the HW structure
399 * @offset: register offset to be read
400 * @data: pointer to the read data
402 * Acquires semaphore, if necessary, then reads the PHY register at offset
403 * and storing the retrieved information in data. Release any acquired
404 * semaphores before exiting.
406 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
410 if (!(hw->phy.ops.acquire))
413 ret_val = hw->phy.ops.acquire(hw);
417 if (offset > MAX_PHY_MULTI_PAGE_REG) {
418 ret_val = igb_write_phy_reg_mdic(hw,
419 IGP01E1000_PHY_PAGE_SELECT,
422 hw->phy.ops.release(hw);
427 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
430 hw->phy.ops.release(hw);
437 * igb_write_phy_reg_igp - Write igp PHY register
438 * @hw: pointer to the HW structure
439 * @offset: register offset to write to
440 * @data: data to write at register offset
442 * Acquires semaphore, if necessary, then writes the data to PHY register
443 * at the offset. Release any acquired semaphores before exiting.
445 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
449 if (!(hw->phy.ops.acquire))
452 ret_val = hw->phy.ops.acquire(hw);
456 if (offset > MAX_PHY_MULTI_PAGE_REG) {
457 ret_val = igb_write_phy_reg_mdic(hw,
458 IGP01E1000_PHY_PAGE_SELECT,
461 hw->phy.ops.release(hw);
466 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
469 hw->phy.ops.release(hw);
476 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
477 * @hw: pointer to the HW structure
479 * Sets up Carrier-sense on Transmit and downshift values.
481 s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
483 struct e1000_phy_info *phy = &hw->phy;
487 if (phy->reset_disable) {
492 if (phy->type == e1000_phy_82580) {
493 ret_val = hw->phy.ops.reset(hw);
495 hw_dbg("Error resetting the PHY.\n");
500 /* Enable CRS on TX. This must be set for half-duplex operation. */
501 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
505 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
507 /* Enable downshift */
508 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
510 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
514 /* Set MDI/MDIX mode */
515 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
518 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
524 switch (hw->phy.mdix) {
528 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
532 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
535 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
542 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
543 * @hw: pointer to the HW structure
545 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
546 * and downshift values are set also.
548 s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
550 struct e1000_phy_info *phy = &hw->phy;
554 if (phy->reset_disable) {
559 /* Enable CRS on TX. This must be set for half-duplex operation. */
560 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
564 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
567 * MDI/MDI-X = 0 (default)
568 * 0 - Auto for all speeds
571 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
573 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
577 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
580 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
583 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
587 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
592 * disable_polarity_correction = 0 (default)
593 * Automatic Correction for Reversed Cable Polarity
597 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
598 if (phy->disable_polarity_correction == 1)
599 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
601 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
605 if (phy->revision < E1000_REVISION_4) {
606 /* Force TX_CLK in the Extended PHY Specific Control Register
609 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
614 phy_data |= M88E1000_EPSCR_TX_CLK_25;
616 if ((phy->revision == E1000_REVISION_2) &&
617 (phy->id == M88E1111_I_PHY_ID)) {
618 /* 82573L PHY - set the downshift counter to 5x. */
619 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
620 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
622 /* Configure Master and Slave downshift values */
623 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
624 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
625 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
626 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
628 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
634 /* Commit the changes. */
635 ret_val = igb_phy_sw_reset(hw);
637 hw_dbg("Error committing the PHY changes\n");
646 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
647 * @hw: pointer to the HW structure
649 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
650 * Also enables and sets the downshift parameters.
652 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
654 struct e1000_phy_info *phy = &hw->phy;
658 if (phy->reset_disable)
661 /* Enable CRS on Tx. This must be set for half-duplex operation. */
662 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
667 * MDI/MDI-X = 0 (default)
668 * 0 - Auto for all speeds
671 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
673 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
677 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
680 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
683 /* M88E1112 does not support this mode) */
684 if (phy->id != M88E1112_E_PHY_ID) {
685 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
690 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
695 * disable_polarity_correction = 0 (default)
696 * Automatic Correction for Reversed Cable Polarity
700 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
701 if (phy->disable_polarity_correction == 1)
702 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
704 /* Enable downshift and setting it to X6 */
705 if (phy->id == M88E1543_E_PHY_ID) {
706 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
708 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
712 ret_val = igb_phy_sw_reset(hw);
714 hw_dbg("Error committing the PHY changes\n");
719 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
720 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
721 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
723 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
727 /* Commit the changes. */
728 ret_val = igb_phy_sw_reset(hw);
730 hw_dbg("Error committing the PHY changes\n");
733 ret_val = igb_set_master_slave_mode(hw);
741 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
742 * @hw: pointer to the HW structure
744 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
747 s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
749 struct e1000_phy_info *phy = &hw->phy;
753 if (phy->reset_disable) {
758 ret_val = phy->ops.reset(hw);
760 hw_dbg("Error resetting the PHY.\n");
764 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
765 * timeout issues when LFS is enabled.
769 /* The NVM settings will configure LPLU in D3 for
772 if (phy->type == e1000_phy_igp) {
773 /* disable lplu d3 during driver init */
774 if (phy->ops.set_d3_lplu_state)
775 ret_val = phy->ops.set_d3_lplu_state(hw, false);
777 hw_dbg("Error Disabling LPLU D3\n");
782 /* disable lplu d0 during driver init */
783 ret_val = phy->ops.set_d0_lplu_state(hw, false);
785 hw_dbg("Error Disabling LPLU D0\n");
788 /* Configure mdi-mdix settings */
789 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
793 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
797 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
800 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
804 data |= IGP01E1000_PSCR_AUTO_MDIX;
807 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
811 /* set auto-master slave resolution settings */
812 if (hw->mac.autoneg) {
813 /* when autonegotiation advertisement is only 1000Mbps then we
814 * should disable SmartSpeed and enable Auto MasterSlave
815 * resolution as hardware default.
817 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
818 /* Disable SmartSpeed */
819 ret_val = phy->ops.read_reg(hw,
820 IGP01E1000_PHY_PORT_CONFIG,
825 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
826 ret_val = phy->ops.write_reg(hw,
827 IGP01E1000_PHY_PORT_CONFIG,
832 /* Set auto Master/Slave resolution process */
833 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
837 data &= ~CR_1000T_MS_ENABLE;
838 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
843 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
847 /* load defaults for future use */
848 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
849 ((data & CR_1000T_MS_VALUE) ?
850 e1000_ms_force_master :
851 e1000_ms_force_slave) :
854 switch (phy->ms_type) {
855 case e1000_ms_force_master:
856 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
858 case e1000_ms_force_slave:
859 data |= CR_1000T_MS_ENABLE;
860 data &= ~(CR_1000T_MS_VALUE);
863 data &= ~CR_1000T_MS_ENABLE;
867 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
877 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
878 * @hw: pointer to the HW structure
880 * Performs initial bounds checking on autoneg advertisement parameter, then
881 * configure to advertise the full capability. Setup the PHY to autoneg
882 * and restart the negotiation process between the link partner. If
883 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
885 static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
887 struct e1000_phy_info *phy = &hw->phy;
891 /* Perform some bounds checking on the autoneg advertisement
894 phy->autoneg_advertised &= phy->autoneg_mask;
896 /* If autoneg_advertised is zero, we assume it was not defaulted
897 * by the calling code so we set to advertise full capability.
899 if (phy->autoneg_advertised == 0)
900 phy->autoneg_advertised = phy->autoneg_mask;
902 hw_dbg("Reconfiguring auto-neg advertisement params\n");
903 ret_val = igb_phy_setup_autoneg(hw);
905 hw_dbg("Error Setting up Auto-Negotiation\n");
908 hw_dbg("Restarting Auto-Neg\n");
910 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
911 * the Auto Neg Restart bit in the PHY control register.
913 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
917 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
918 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
922 /* Does the user want to wait for Auto-Neg to complete here, or
923 * check at a later time (for example, callback routine).
925 if (phy->autoneg_wait_to_complete) {
926 ret_val = igb_wait_autoneg(hw);
928 hw_dbg("Error while waiting for autoneg to complete\n");
933 hw->mac.get_link_status = true;
940 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
941 * @hw: pointer to the HW structure
943 * Reads the MII auto-neg advertisement register and/or the 1000T control
944 * register and if the PHY is already setup for auto-negotiation, then
945 * return successful. Otherwise, setup advertisement and flow control to
946 * the appropriate values for the wanted auto-negotiation.
948 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
950 struct e1000_phy_info *phy = &hw->phy;
952 u16 mii_autoneg_adv_reg;
953 u16 mii_1000t_ctrl_reg = 0;
955 phy->autoneg_advertised &= phy->autoneg_mask;
957 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
958 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
962 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
963 /* Read the MII 1000Base-T Control Register (Address 9). */
964 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
965 &mii_1000t_ctrl_reg);
970 /* Need to parse both autoneg_advertised and fc and set up
971 * the appropriate PHY registers. First we will parse for
972 * autoneg_advertised software override. Since we can advertise
973 * a plethora of combinations, we need to check each bit
977 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
978 * Advertisement Register (Address 4) and the 1000 mb speed bits in
979 * the 1000Base-T Control Register (Address 9).
981 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
982 NWAY_AR_100TX_HD_CAPS |
983 NWAY_AR_10T_FD_CAPS |
984 NWAY_AR_10T_HD_CAPS);
985 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
987 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
989 /* Do we want to advertise 10 Mb Half Duplex? */
990 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
991 hw_dbg("Advertise 10mb Half duplex\n");
992 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
995 /* Do we want to advertise 10 Mb Full Duplex? */
996 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
997 hw_dbg("Advertise 10mb Full duplex\n");
998 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1001 /* Do we want to advertise 100 Mb Half Duplex? */
1002 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1003 hw_dbg("Advertise 100mb Half duplex\n");
1004 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1007 /* Do we want to advertise 100 Mb Full Duplex? */
1008 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1009 hw_dbg("Advertise 100mb Full duplex\n");
1010 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1013 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1014 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1015 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
1017 /* Do we want to advertise 1000 Mb Full Duplex? */
1018 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1019 hw_dbg("Advertise 1000mb Full duplex\n");
1020 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1023 /* Check for a software override of the flow control settings, and
1024 * setup the PHY advertisement registers accordingly. If
1025 * auto-negotiation is enabled, then software will have to set the
1026 * "PAUSE" bits to the correct value in the Auto-Negotiation
1027 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1030 * The possible values of the "fc" parameter are:
1031 * 0: Flow control is completely disabled
1032 * 1: Rx flow control is enabled (we can receive pause frames
1033 * but not send pause frames).
1034 * 2: Tx flow control is enabled (we can send pause frames
1035 * but we do not support receiving pause frames).
1036 * 3: Both Rx and TX flow control (symmetric) are enabled.
1037 * other: No software override. The flow control configuration
1038 * in the EEPROM is used.
1040 switch (hw->fc.current_mode) {
1042 /* Flow control (RX & TX) is completely disabled by a
1043 * software over-ride.
1045 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1047 case e1000_fc_rx_pause:
1048 /* RX Flow control is enabled, and TX Flow control is
1049 * disabled, by a software over-ride.
1051 * Since there really isn't a way to advertise that we are
1052 * capable of RX Pause ONLY, we will advertise that we
1053 * support both symmetric and asymmetric RX PAUSE. Later
1054 * (in e1000_config_fc_after_link_up) we will disable the
1055 * hw's ability to send PAUSE frames.
1057 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1059 case e1000_fc_tx_pause:
1060 /* TX Flow control is enabled, and RX Flow control is
1061 * disabled, by a software over-ride.
1063 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1064 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1067 /* Flow control (both RX and TX) is enabled by a software
1070 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1073 hw_dbg("Flow control param set incorrectly\n");
1074 ret_val = -E1000_ERR_CONFIG;
1078 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1082 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1084 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1085 ret_val = phy->ops.write_reg(hw,
1087 mii_1000t_ctrl_reg);
1097 * igb_setup_copper_link - Configure copper link settings
1098 * @hw: pointer to the HW structure
1100 * Calls the appropriate function to configure the link for auto-neg or forced
1101 * speed and duplex. Then we check for link, once link is established calls
1102 * to configure collision distance and flow control are called. If link is
1103 * not established, we return -E1000_ERR_PHY (-2).
1105 s32 igb_setup_copper_link(struct e1000_hw *hw)
1110 if (hw->mac.autoneg) {
1111 /* Setup autoneg and flow control advertisement and perform
1114 ret_val = igb_copper_link_autoneg(hw);
1118 /* PHY will be set to 10H, 10F, 100H or 100F
1119 * depending on user settings.
1121 hw_dbg("Forcing Speed and Duplex\n");
1122 ret_val = hw->phy.ops.force_speed_duplex(hw);
1124 hw_dbg("Error Forcing Speed and Duplex\n");
1129 /* Check link status. Wait up to 100 microseconds for link to become
1132 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
1137 hw_dbg("Valid link established!!!\n");
1138 igb_config_collision_dist(hw);
1139 ret_val = igb_config_fc_after_link_up(hw);
1141 hw_dbg("Unable to establish link!!!\n");
1149 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1150 * @hw: pointer to the HW structure
1152 * Calls the PHY setup function to force speed and duplex. Clears the
1153 * auto-crossover to force MDI manually. Waits for link and returns
1154 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1156 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1158 struct e1000_phy_info *phy = &hw->phy;
1163 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1167 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1169 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1173 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1174 * forced whenever speed and duplex are forced.
1176 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1180 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1181 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1183 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1187 hw_dbg("IGP PSCR: %X\n", phy_data);
1191 if (phy->autoneg_wait_to_complete) {
1192 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1194 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1199 hw_dbg("Link taking longer than expected.\n");
1202 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1212 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1213 * @hw: pointer to the HW structure
1215 * Calls the PHY setup function to force speed and duplex. Clears the
1216 * auto-crossover to force MDI manually. Resets the PHY to commit the
1217 * changes. If time expires while waiting for link up, we reset the DSP.
1218 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1219 * successful completion, else return corresponding error code.
1221 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1223 struct e1000_phy_info *phy = &hw->phy;
1228 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1229 if (phy->type != e1000_phy_i210) {
1230 /* Clear Auto-Crossover to force MDI manually. M88E1000
1231 * requires MDI forced whenever speed and duplex are forced.
1233 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1238 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1239 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1244 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
1247 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1251 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1253 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1257 /* Reset the phy to commit changes. */
1258 ret_val = igb_phy_sw_reset(hw);
1262 if (phy->autoneg_wait_to_complete) {
1263 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1265 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1270 bool reset_dsp = true;
1272 switch (hw->phy.id) {
1273 case I347AT4_E_PHY_ID:
1274 case M88E1112_E_PHY_ID:
1279 if (hw->phy.type != e1000_phy_m88)
1284 hw_dbg("Link taking longer than expected.\n");
1286 /* We didn't get link.
1287 * Reset the DSP and cross our fingers.
1289 ret_val = phy->ops.write_reg(hw,
1290 M88E1000_PHY_PAGE_SELECT,
1294 ret_val = igb_phy_reset_dsp(hw);
1301 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
1307 if (hw->phy.type != e1000_phy_m88 ||
1308 hw->phy.id == I347AT4_E_PHY_ID ||
1309 hw->phy.id == M88E1112_E_PHY_ID ||
1310 hw->phy.id == I210_I_PHY_ID)
1313 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1317 /* Resetting the phy means we need to re-force TX_CLK in the
1318 * Extended PHY Specific Control Register to 25MHz clock from
1319 * the reset value of 2.5MHz.
1321 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1322 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1326 /* In addition, we must re-enable CRS on Tx for both half and full
1329 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1333 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1334 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1341 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1342 * @hw: pointer to the HW structure
1343 * @phy_ctrl: pointer to current value of PHY_CONTROL
1345 * Forces speed and duplex on the PHY by doing the following: disable flow
1346 * control, force speed/duplex on the MAC, disable auto speed detection,
1347 * disable auto-negotiation, configure duplex, configure speed, configure
1348 * the collision distance, write configuration to CTRL register. The
1349 * caller must write to the PHY_CONTROL register for these settings to
1352 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1355 struct e1000_mac_info *mac = &hw->mac;
1358 /* Turn off flow control when forcing speed/duplex */
1359 hw->fc.current_mode = e1000_fc_none;
1361 /* Force speed/duplex on the mac */
1362 ctrl = rd32(E1000_CTRL);
1363 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1364 ctrl &= ~E1000_CTRL_SPD_SEL;
1366 /* Disable Auto Speed Detection */
1367 ctrl &= ~E1000_CTRL_ASDE;
1369 /* Disable autoneg on the phy */
1370 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1372 /* Forcing Full or Half Duplex? */
1373 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1374 ctrl &= ~E1000_CTRL_FD;
1375 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1376 hw_dbg("Half Duplex\n");
1378 ctrl |= E1000_CTRL_FD;
1379 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1380 hw_dbg("Full Duplex\n");
1383 /* Forcing 10mb or 100mb? */
1384 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1385 ctrl |= E1000_CTRL_SPD_100;
1386 *phy_ctrl |= MII_CR_SPEED_100;
1387 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1388 hw_dbg("Forcing 100mb\n");
1390 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1391 *phy_ctrl |= MII_CR_SPEED_10;
1392 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1393 hw_dbg("Forcing 10mb\n");
1396 igb_config_collision_dist(hw);
1398 wr32(E1000_CTRL, ctrl);
1402 * igb_set_d3_lplu_state - Sets low power link up state for D3
1403 * @hw: pointer to the HW structure
1404 * @active: boolean used to enable/disable lplu
1406 * Success returns 0, Failure returns 1
1408 * The low power link up (lplu) state is set to the power management level D3
1409 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1410 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1411 * is used during Dx states where the power conservation is most important.
1412 * During driver activity, SmartSpeed should be enabled so performance is
1415 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1417 struct e1000_phy_info *phy = &hw->phy;
1421 if (!(hw->phy.ops.read_reg))
1424 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1429 data &= ~IGP02E1000_PM_D3_LPLU;
1430 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1434 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1435 * during Dx states where the power conservation is most
1436 * important. During driver activity we should enable
1437 * SmartSpeed, so performance is maintained.
1439 if (phy->smart_speed == e1000_smart_speed_on) {
1440 ret_val = phy->ops.read_reg(hw,
1441 IGP01E1000_PHY_PORT_CONFIG,
1446 data |= IGP01E1000_PSCFR_SMART_SPEED;
1447 ret_val = phy->ops.write_reg(hw,
1448 IGP01E1000_PHY_PORT_CONFIG,
1452 } else if (phy->smart_speed == e1000_smart_speed_off) {
1453 ret_val = phy->ops.read_reg(hw,
1454 IGP01E1000_PHY_PORT_CONFIG,
1459 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1460 ret_val = phy->ops.write_reg(hw,
1461 IGP01E1000_PHY_PORT_CONFIG,
1466 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1467 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1468 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1469 data |= IGP02E1000_PM_D3_LPLU;
1470 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1475 /* When LPLU is enabled, we should disable SmartSpeed */
1476 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1481 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1482 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1491 * igb_check_downshift - Checks whether a downshift in speed occurred
1492 * @hw: pointer to the HW structure
1494 * Success returns 0, Failure returns 1
1496 * A downshift is detected by querying the PHY link health.
1498 s32 igb_check_downshift(struct e1000_hw *hw)
1500 struct e1000_phy_info *phy = &hw->phy;
1502 u16 phy_data, offset, mask;
1504 switch (phy->type) {
1505 case e1000_phy_i210:
1507 case e1000_phy_gg82563:
1508 offset = M88E1000_PHY_SPEC_STATUS;
1509 mask = M88E1000_PSSR_DOWNSHIFT;
1511 case e1000_phy_igp_2:
1513 case e1000_phy_igp_3:
1514 offset = IGP01E1000_PHY_LINK_HEALTH;
1515 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1518 /* speed downshift not supported */
1519 phy->speed_downgraded = false;
1524 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1527 phy->speed_downgraded = (phy_data & mask) ? true : false;
1534 * igb_check_polarity_m88 - Checks the polarity.
1535 * @hw: pointer to the HW structure
1537 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1539 * Polarity is determined based on the PHY specific status register.
1541 s32 igb_check_polarity_m88(struct e1000_hw *hw)
1543 struct e1000_phy_info *phy = &hw->phy;
1547 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1550 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1551 ? e1000_rev_polarity_reversed
1552 : e1000_rev_polarity_normal;
1558 * igb_check_polarity_igp - Checks the polarity.
1559 * @hw: pointer to the HW structure
1561 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1563 * Polarity is determined based on the PHY port status register, and the
1564 * current speed (since there is no polarity at 100Mbps).
1566 static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1568 struct e1000_phy_info *phy = &hw->phy;
1570 u16 data, offset, mask;
1572 /* Polarity is determined based on the speed of
1575 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1579 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1580 IGP01E1000_PSSR_SPEED_1000MBPS) {
1581 offset = IGP01E1000_PHY_PCS_INIT_REG;
1582 mask = IGP01E1000_PHY_POLARITY_MASK;
1584 /* This really only applies to 10Mbps since
1585 * there is no polarity for 100Mbps (always 0).
1587 offset = IGP01E1000_PHY_PORT_STATUS;
1588 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1591 ret_val = phy->ops.read_reg(hw, offset, &data);
1594 phy->cable_polarity = (data & mask)
1595 ? e1000_rev_polarity_reversed
1596 : e1000_rev_polarity_normal;
1603 * igb_wait_autoneg - Wait for auto-neg completion
1604 * @hw: pointer to the HW structure
1606 * Waits for auto-negotiation to complete or for the auto-negotiation time
1607 * limit to expire, which ever happens first.
1609 static s32 igb_wait_autoneg(struct e1000_hw *hw)
1614 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1615 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1616 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1619 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1622 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1627 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1634 * igb_phy_has_link - Polls PHY for link
1635 * @hw: pointer to the HW structure
1636 * @iterations: number of times to poll for link
1637 * @usec_interval: delay between polling attempts
1638 * @success: pointer to whether polling was successful or not
1640 * Polls the PHY status register for link, 'iterations' number of times.
1642 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1643 u32 usec_interval, bool *success)
1648 for (i = 0; i < iterations; i++) {
1649 /* Some PHYs require the PHY_STATUS register to be read
1650 * twice due to the link bit being sticky. No harm doing
1651 * it across the board.
1653 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1654 if (ret_val && usec_interval > 0) {
1655 /* If the first read fails, another entity may have
1656 * ownership of the resources, wait and try again to
1657 * see if they have relinquished the resources yet.
1659 if (usec_interval >= 1000)
1660 mdelay(usec_interval/1000);
1662 udelay(usec_interval);
1664 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1667 if (phy_status & MII_SR_LINK_STATUS)
1669 if (usec_interval >= 1000)
1670 mdelay(usec_interval/1000);
1672 udelay(usec_interval);
1675 *success = (i < iterations) ? true : false;
1681 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1682 * @hw: pointer to the HW structure
1684 * Reads the PHY specific status register to retrieve the cable length
1685 * information. The cable length is determined by averaging the minimum and
1686 * maximum values to get the "average" cable length. The m88 PHY has four
1687 * possible cable length values, which are:
1688 * Register Value Cable Length
1692 * 3 110 - 140 meters
1695 s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1697 struct e1000_phy_info *phy = &hw->phy;
1699 u16 phy_data, index;
1701 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1705 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1706 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1707 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1708 ret_val = -E1000_ERR_PHY;
1712 phy->min_cable_length = e1000_m88_cable_length_table[index];
1713 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1715 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1721 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
1723 struct e1000_phy_info *phy = &hw->phy;
1725 u16 phy_data, phy_data2, index, default_page, is_cm;
1727 switch (hw->phy.id) {
1729 /* Get cable length from PHY Cable Diagnostics Control Reg */
1730 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1731 (I347AT4_PCDL + phy->addr),
1736 /* Check if the unit of cable length is meters or cm */
1737 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1738 I347AT4_PCDC, &phy_data2);
1742 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1744 /* Populate the phy structure with cable length in meters */
1745 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1746 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1747 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1749 case M88E1543_E_PHY_ID:
1750 case I347AT4_E_PHY_ID:
1751 /* Remember the original page select and set it to 7 */
1752 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1757 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
1761 /* Get cable length from PHY Cable Diagnostics Control Reg */
1762 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
1767 /* Check if the unit of cable length is meters or cm */
1768 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
1772 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1774 /* Populate the phy structure with cable length in meters */
1775 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1776 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1777 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1779 /* Reset the page selec to its original value */
1780 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1785 case M88E1112_E_PHY_ID:
1786 /* Remember the original page select and set it to 5 */
1787 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1792 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
1796 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
1801 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1802 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1803 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1804 ret_val = -E1000_ERR_PHY;
1808 phy->min_cable_length = e1000_m88_cable_length_table[index];
1809 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1811 phy->cable_length = (phy->min_cable_length +
1812 phy->max_cable_length) / 2;
1814 /* Reset the page select to its original value */
1815 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1822 ret_val = -E1000_ERR_PHY;
1831 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1832 * @hw: pointer to the HW structure
1834 * The automatic gain control (agc) normalizes the amplitude of the
1835 * received signal, adjusting for the attenuation produced by the
1836 * cable. By reading the AGC registers, which represent the
1837 * combination of coarse and fine gain value, the value can be put
1838 * into a lookup table to obtain the approximate cable length
1841 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1843 struct e1000_phy_info *phy = &hw->phy;
1845 u16 phy_data, i, agc_value = 0;
1846 u16 cur_agc_index, max_agc_index = 0;
1847 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1848 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1849 IGP02E1000_PHY_AGC_A,
1850 IGP02E1000_PHY_AGC_B,
1851 IGP02E1000_PHY_AGC_C,
1852 IGP02E1000_PHY_AGC_D
1855 /* Read the AGC registers for all channels */
1856 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1857 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1861 /* Getting bits 15:9, which represent the combination of
1862 * coarse and fine gain values. The result is a number
1863 * that can be put into the lookup table to obtain the
1864 * approximate cable length.
1866 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1867 IGP02E1000_AGC_LENGTH_MASK;
1869 /* Array index bound check. */
1870 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1871 (cur_agc_index == 0)) {
1872 ret_val = -E1000_ERR_PHY;
1876 /* Remove min & max AGC values from calculation. */
1877 if (e1000_igp_2_cable_length_table[min_agc_index] >
1878 e1000_igp_2_cable_length_table[cur_agc_index])
1879 min_agc_index = cur_agc_index;
1880 if (e1000_igp_2_cable_length_table[max_agc_index] <
1881 e1000_igp_2_cable_length_table[cur_agc_index])
1882 max_agc_index = cur_agc_index;
1884 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1887 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1888 e1000_igp_2_cable_length_table[max_agc_index]);
1889 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1891 /* Calculate cable length with the error range of +/- 10 meters. */
1892 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1893 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1894 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1896 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1903 * igb_get_phy_info_m88 - Retrieve PHY information
1904 * @hw: pointer to the HW structure
1906 * Valid for only copper links. Read the PHY status register (sticky read)
1907 * to verify that link is up. Read the PHY special control register to
1908 * determine the polarity and 10base-T extended distance. Read the PHY
1909 * special status register to determine MDI/MDIx and current speed. If
1910 * speed is 1000, then determine cable length, local and remote receiver.
1912 s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1914 struct e1000_phy_info *phy = &hw->phy;
1919 if (phy->media_type != e1000_media_type_copper) {
1920 hw_dbg("Phy info is only valid for copper media\n");
1921 ret_val = -E1000_ERR_CONFIG;
1925 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1930 hw_dbg("Phy info is only valid if link is up\n");
1931 ret_val = -E1000_ERR_CONFIG;
1935 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1939 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1942 ret_val = igb_check_polarity_m88(hw);
1946 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1950 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1952 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1953 ret_val = phy->ops.get_cable_length(hw);
1957 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1961 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1962 ? e1000_1000t_rx_status_ok
1963 : e1000_1000t_rx_status_not_ok;
1965 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1966 ? e1000_1000t_rx_status_ok
1967 : e1000_1000t_rx_status_not_ok;
1969 /* Set values to "undefined" */
1970 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1971 phy->local_rx = e1000_1000t_rx_status_undefined;
1972 phy->remote_rx = e1000_1000t_rx_status_undefined;
1980 * igb_get_phy_info_igp - Retrieve igp PHY information
1981 * @hw: pointer to the HW structure
1983 * Read PHY status to determine if link is up. If link is up, then
1984 * set/determine 10base-T extended distance and polarity correction. Read
1985 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1986 * determine on the cable length, local and remote receiver.
1988 s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1990 struct e1000_phy_info *phy = &hw->phy;
1995 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2000 hw_dbg("Phy info is only valid if link is up\n");
2001 ret_val = -E1000_ERR_CONFIG;
2005 phy->polarity_correction = true;
2007 ret_val = igb_check_polarity_igp(hw);
2011 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2015 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2017 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2018 IGP01E1000_PSSR_SPEED_1000MBPS) {
2019 ret_val = phy->ops.get_cable_length(hw);
2023 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2027 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2028 ? e1000_1000t_rx_status_ok
2029 : e1000_1000t_rx_status_not_ok;
2031 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2032 ? e1000_1000t_rx_status_ok
2033 : e1000_1000t_rx_status_not_ok;
2035 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2036 phy->local_rx = e1000_1000t_rx_status_undefined;
2037 phy->remote_rx = e1000_1000t_rx_status_undefined;
2045 * igb_phy_sw_reset - PHY software reset
2046 * @hw: pointer to the HW structure
2048 * Does a software reset of the PHY by reading the PHY control register and
2049 * setting/write the control register reset bit to the PHY.
2051 s32 igb_phy_sw_reset(struct e1000_hw *hw)
2056 if (!(hw->phy.ops.read_reg))
2059 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2063 phy_ctrl |= MII_CR_RESET;
2064 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2075 * igb_phy_hw_reset - PHY hardware reset
2076 * @hw: pointer to the HW structure
2078 * Verify the reset block is not blocking us from resetting. Acquire
2079 * semaphore (if necessary) and read/set/write the device control reset
2080 * bit in the PHY. Wait the appropriate delay time for the device to
2081 * reset and release the semaphore (if necessary).
2083 s32 igb_phy_hw_reset(struct e1000_hw *hw)
2085 struct e1000_phy_info *phy = &hw->phy;
2089 ret_val = igb_check_reset_block(hw);
2095 ret_val = phy->ops.acquire(hw);
2099 ctrl = rd32(E1000_CTRL);
2100 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2103 udelay(phy->reset_delay_us);
2105 wr32(E1000_CTRL, ctrl);
2110 phy->ops.release(hw);
2112 ret_val = phy->ops.get_cfg_done(hw);
2119 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
2120 * @hw: pointer to the HW structure
2122 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2124 s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2126 hw_dbg("Running IGP 3 PHY init script\n");
2128 /* PHY init IGP 3 */
2129 /* Enable rise/fall, 10-mode work in class-A */
2130 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2131 /* Remove all caps from Replica path filter */
2132 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2133 /* Bias trimming for ADC, AFE and Driver (Default) */
2134 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2135 /* Increase Hybrid poly bias */
2136 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2137 /* Add 4% to TX amplitude in Giga mode */
2138 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2139 /* Disable trimming (TTT) */
2140 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2141 /* Poly DC correction to 94.6% + 2% for all channels */
2142 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2143 /* ABS DC correction to 95.9% */
2144 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2145 /* BG temp curve trim */
2146 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2147 /* Increasing ADC OPAMP stage 1 currents to max */
2148 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2149 /* Force 1000 ( required for enabling PHY regs configuration) */
2150 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2151 /* Set upd_freq to 6 */
2152 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2154 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2155 /* Disable adaptive fixed FFE (Default) */
2156 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2157 /* Enable FFE hysteresis */
2158 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2159 /* Fixed FFE for short cable lengths */
2160 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2161 /* Fixed FFE for medium cable lengths */
2162 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2163 /* Fixed FFE for long cable lengths */
2164 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2165 /* Enable Adaptive Clip Threshold */
2166 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2167 /* AHT reset limit to 1 */
2168 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2169 /* Set AHT master delay to 127 msec */
2170 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2171 /* Set scan bits for AHT */
2172 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2173 /* Set AHT Preset bits */
2174 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2175 /* Change integ_factor of channel A to 3 */
2176 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2177 /* Change prop_factor of channels BCD to 8 */
2178 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2179 /* Change cg_icount + enable integbp for channels BCD */
2180 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2181 /* Change cg_icount + enable integbp + change prop_factor_master
2182 * to 8 for channel A
2184 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2185 /* Disable AHT in Slave mode on channel A */
2186 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2187 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2190 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2191 /* Enable restart AN on an1000_dis change */
2192 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2193 /* Enable wh_fifo read clock in 10/100 modes */
2194 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2195 /* Restart AN, Speed selection is 1000 */
2196 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2202 * igb_power_up_phy_copper - Restore copper link in case of PHY power down
2203 * @hw: pointer to the HW structure
2205 * In the case of a PHY power down to save power, or to turn off link during a
2206 * driver unload, restore the link to previous settings.
2208 void igb_power_up_phy_copper(struct e1000_hw *hw)
2212 /* The PHY will retain its settings across a power down/up cycle */
2213 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2214 mii_reg &= ~MII_CR_POWER_DOWN;
2215 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2219 * igb_power_down_phy_copper - Power down copper PHY
2220 * @hw: pointer to the HW structure
2222 * Power down PHY to save power when interface is down and wake on lan
2225 void igb_power_down_phy_copper(struct e1000_hw *hw)
2229 /* The PHY will retain its settings across a power down/up cycle */
2230 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2231 mii_reg |= MII_CR_POWER_DOWN;
2232 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2233 usleep_range(1000, 2000);
2237 * igb_check_polarity_82580 - Checks the polarity.
2238 * @hw: pointer to the HW structure
2240 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2242 * Polarity is determined based on the PHY specific status register.
2244 static s32 igb_check_polarity_82580(struct e1000_hw *hw)
2246 struct e1000_phy_info *phy = &hw->phy;
2251 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2254 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
2255 ? e1000_rev_polarity_reversed
2256 : e1000_rev_polarity_normal;
2262 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
2263 * @hw: pointer to the HW structure
2265 * Calls the PHY setup function to force speed and duplex. Clears the
2266 * auto-crossover to force MDI manually. Waits for link and returns
2267 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2269 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
2271 struct e1000_phy_info *phy = &hw->phy;
2276 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2280 igb_phy_force_speed_duplex_setup(hw, &phy_data);
2282 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2286 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI
2287 * forced whenever speed and duplex are forced.
2289 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
2293 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
2295 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
2299 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
2303 if (phy->autoneg_wait_to_complete) {
2304 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
2306 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2311 hw_dbg("Link taking longer than expected.\n");
2314 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2324 * igb_get_phy_info_82580 - Retrieve I82580 PHY information
2325 * @hw: pointer to the HW structure
2327 * Read PHY status to determine if link is up. If link is up, then
2328 * set/determine 10base-T extended distance and polarity correction. Read
2329 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2330 * determine on the cable length, local and remote receiver.
2332 s32 igb_get_phy_info_82580(struct e1000_hw *hw)
2334 struct e1000_phy_info *phy = &hw->phy;
2339 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2344 hw_dbg("Phy info is only valid if link is up\n");
2345 ret_val = -E1000_ERR_CONFIG;
2349 phy->polarity_correction = true;
2351 ret_val = igb_check_polarity_82580(hw);
2355 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2359 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
2361 if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
2362 I82580_PHY_STATUS2_SPEED_1000MBPS) {
2363 ret_val = hw->phy.ops.get_cable_length(hw);
2367 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2371 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2372 ? e1000_1000t_rx_status_ok
2373 : e1000_1000t_rx_status_not_ok;
2375 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2376 ? e1000_1000t_rx_status_ok
2377 : e1000_1000t_rx_status_not_ok;
2379 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2380 phy->local_rx = e1000_1000t_rx_status_undefined;
2381 phy->remote_rx = e1000_1000t_rx_status_undefined;
2389 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY
2390 * @hw: pointer to the HW structure
2392 * Reads the diagnostic status register and verifies result is valid before
2393 * placing it in the phy_cable_length field.
2395 s32 igb_get_cable_length_82580(struct e1000_hw *hw)
2397 struct e1000_phy_info *phy = &hw->phy;
2399 u16 phy_data, length;
2401 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
2405 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >>
2406 I82580_DSTATUS_CABLE_LENGTH_SHIFT;
2408 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2409 ret_val = -E1000_ERR_PHY;
2411 phy->cable_length = length;
2418 * igb_write_phy_reg_gs40g - Write GS40G PHY register
2419 * @hw: pointer to the HW structure
2420 * @offset: lower half is register offset to write to
2421 * upper half is page to use.
2422 * @data: data to write at register offset
2424 * Acquires semaphore, if necessary, then writes the data to PHY register
2425 * at the offset. Release any acquired semaphores before exiting.
2427 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
2430 u16 page = offset >> GS40G_PAGE_SHIFT;
2432 offset = offset & GS40G_OFFSET_MASK;
2433 ret_val = hw->phy.ops.acquire(hw);
2437 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2440 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2443 hw->phy.ops.release(hw);
2448 * igb_read_phy_reg_gs40g - Read GS40G PHY register
2449 * @hw: pointer to the HW structure
2450 * @offset: lower half is register offset to read to
2451 * upper half is page to use.
2452 * @data: data to read at register offset
2454 * Acquires semaphore, if necessary, then reads the data in the PHY register
2455 * at the offset. Release any acquired semaphores before exiting.
2457 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
2460 u16 page = offset >> GS40G_PAGE_SHIFT;
2462 offset = offset & GS40G_OFFSET_MASK;
2463 ret_val = hw->phy.ops.acquire(hw);
2467 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2470 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2473 hw->phy.ops.release(hw);
2478 * igb_set_master_slave_mode - Setup PHY for Master/slave mode
2479 * @hw: pointer to the HW structure
2481 * Sets up Master/slave mode
2483 static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
2488 /* Resolve Master/Slave mode */
2489 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2493 /* load defaults for future use */
2494 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2495 ((phy_data & CR_1000T_MS_VALUE) ?
2496 e1000_ms_force_master :
2497 e1000_ms_force_slave) : e1000_ms_auto;
2499 switch (hw->phy.ms_type) {
2500 case e1000_ms_force_master:
2501 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2503 case e1000_ms_force_slave:
2504 phy_data |= CR_1000T_MS_ENABLE;
2505 phy_data &= ~(CR_1000T_MS_VALUE);
2508 phy_data &= ~CR_1000T_MS_ENABLE;
2514 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);