drivers/net/ethernet/intel/i40e/i40e_type.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
   3
   4 #ifndef _I40E_TYPE_H_
   5 #define _I40E_TYPE_H_
   6
   7 #include "i40e_status.h"
   8 #include "i40e_osdep.h"
   9 #include "i40e_register.h"
  10 #include "i40e_adminq.h"
  11 #include "i40e_hmc.h"
  12 #include "i40e_lan_hmc.h"
  13 #include "i40e_devids.h"
  14
  15 /* I40E_MASK is a macro used on 32 bit registers */
  16 #define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
  17
  18 #define I40E_MAX_VSI_QP                 16
  19 #define I40E_MAX_VF_VSI                 4
  20 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  21 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  22
  23 /* Max default timeout in ms, */
  24 #define I40E_MAX_NVM_TIMEOUT            18000
  25
  26 /* Max timeout in ms for the phy to respond */
  27 #define I40E_MAX_PHY_TIMEOUT            500
  28
  29 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  30 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  31
  32 /* forward declaration */
  33 struct i40e_hw;
  34 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  35
  36 /* Data type manipulation macros. */
  37
  38 #define I40E_DESC_UNUSED(R)     \
  39         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  40         (R)->next_to_clean - (R)->next_to_use - 1)
  41
  42 /* bitfields for Tx queue mapping in QTX_CTL */
  43 #define I40E_QTX_CTL_VF_QUEUE   0x0
  44 #define I40E_QTX_CTL_VM_QUEUE   0x1
  45 #define I40E_QTX_CTL_PF_QUEUE   0x2
  46
  47 /* debug masks - set these bits in hw->debug_mask to control output */
  48 enum i40e_debug_mask {
  49         I40E_DEBUG_INIT                 = 0x00000001,
  50         I40E_DEBUG_RELEASE              = 0x00000002,
  51
  52         I40E_DEBUG_LINK                 = 0x00000010,
  53         I40E_DEBUG_PHY                  = 0x00000020,
  54         I40E_DEBUG_HMC                  = 0x00000040,
  55         I40E_DEBUG_NVM                  = 0x00000080,
  56         I40E_DEBUG_LAN                  = 0x00000100,
  57         I40E_DEBUG_FLOW                 = 0x00000200,
  58         I40E_DEBUG_DCB                  = 0x00000400,
  59         I40E_DEBUG_DIAG                 = 0x00000800,
  60         I40E_DEBUG_FD                   = 0x00001000,
  61         I40E_DEBUG_PACKAGE              = 0x00002000,
  62         I40E_DEBUG_IWARP                = 0x00F00000,
  63         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
  64         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
  65         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
  66         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
  67         I40E_DEBUG_AQ                   = 0x0F000000,
  68
  69         I40E_DEBUG_USER                 = 0xF0000000,
  70
  71         I40E_DEBUG_ALL                  = 0xFFFFFFFF
  72 };
  73
  74 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
  75                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
  76 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
  77                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
  78 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
  79                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
  80
  81 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
  82                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
  83 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
  84                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
  85 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
  86                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
  87 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
  88                                                 I40E_GLGEN_MSCA_OPCODE_SHIFT)
  89 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
  90                                                 I40E_GLGEN_MSCA_OPCODE_SHIFT)
  91
  92 #define I40E_PHY_COM_REG_PAGE                   0x1E
  93 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
  94 #define I40E_PHY_LED_MANUAL_ON                  0x100
  95 #define I40E_PHY_LED_PROV_REG_1                 0xC430
  96 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
  97 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
  98
  99 /* These are structs for managing the hardware information and the operations.
 100  * The structures of function pointers are filled out at init time when we
 101  * know for sure exactly which hardware we're working with.  This gives us the
 102  * flexibility of using the same main driver code but adapting to slightly
 103  * different hardware needs as new parts are developed.  For this architecture,
 104  * the Firmware and AdminQ are intended to insulate the driver from most of the
 105  * future changes, but these structures will also do part of the job.
 106  */
 107 enum i40e_mac_type {
 108         I40E_MAC_UNKNOWN = 0,
 109         I40E_MAC_XL710,
 110         I40E_MAC_VF,
 111         I40E_MAC_X722,
 112         I40E_MAC_X722_VF,
 113         I40E_MAC_GENERIC,
 114 };
 115
 116 enum i40e_media_type {
 117         I40E_MEDIA_TYPE_UNKNOWN = 0,
 118         I40E_MEDIA_TYPE_FIBER,
 119         I40E_MEDIA_TYPE_BASET,
 120         I40E_MEDIA_TYPE_BACKPLANE,
 121         I40E_MEDIA_TYPE_CX4,
 122         I40E_MEDIA_TYPE_DA,
 123         I40E_MEDIA_TYPE_VIRTUAL
 124 };
 125
 126 enum i40e_fc_mode {
 127         I40E_FC_NONE = 0,
 128         I40E_FC_RX_PAUSE,
 129         I40E_FC_TX_PAUSE,
 130         I40E_FC_FULL,
 131         I40E_FC_PFC,
 132         I40E_FC_DEFAULT
 133 };
 134
 135 enum i40e_set_fc_aq_failures {
 136         I40E_SET_FC_AQ_FAIL_NONE = 0,
 137         I40E_SET_FC_AQ_FAIL_GET = 1,
 138         I40E_SET_FC_AQ_FAIL_SET = 2,
 139         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 140         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 141 };
 142
 143 enum i40e_vsi_type {
 144         I40E_VSI_MAIN   = 0,
 145         I40E_VSI_VMDQ1  = 1,
 146         I40E_VSI_VMDQ2  = 2,
 147         I40E_VSI_CTRL   = 3,
 148         I40E_VSI_FCOE   = 4,
 149         I40E_VSI_MIRROR = 5,
 150         I40E_VSI_SRIOV  = 6,
 151         I40E_VSI_FDIR   = 7,
 152         I40E_VSI_IWARP  = 8,
 153         I40E_VSI_TYPE_UNKNOWN
 154 };
 155
 156 enum i40e_queue_type {
 157         I40E_QUEUE_TYPE_RX = 0,
 158         I40E_QUEUE_TYPE_TX,
 159         I40E_QUEUE_TYPE_PE_CEQ,
 160         I40E_QUEUE_TYPE_UNKNOWN
 161 };
 162
 163 struct i40e_link_status {
 164         enum i40e_aq_phy_type phy_type;
 165         enum i40e_aq_link_speed link_speed;
 166         u8 link_info;
 167         u8 an_info;
 168         u8 req_fec_info;
 169         u8 fec_info;
 170         u8 ext_info;
 171         u8 loopback;
 172         /* is Link Status Event notification to SW enabled */
 173         bool lse_enable;
 174         u16 max_frame_size;
 175         bool crc_enable;
 176         u8 pacing;
 177         u8 requested_speeds;
 178         u8 module_type[3];
 179         /* 1st byte: module identifier */
 180 #define I40E_MODULE_TYPE_SFP            0x03
 181 #define I40E_MODULE_TYPE_QSFP           0x0D
 182         /* 2nd byte: ethernet compliance codes for 10/40G */
 183 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 184 #define I40E_MODULE_TYPE_40G_LR4        0x02
 185 #define I40E_MODULE_TYPE_40G_SR4        0x04
 186 #define I40E_MODULE_TYPE_40G_CR4        0x08
 187 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 188 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 189 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 190 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 191         /* 3rd byte: ethernet compliance codes for 1G */
 192 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 193 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 194 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 195 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 196 };
 197
 198 struct i40e_phy_info {
 199         struct i40e_link_status link_info;
 200         struct i40e_link_status link_info_old;
 201         bool get_link_info;
 202         enum i40e_media_type media_type;
 203         /* all the phy types the NVM is capable of */
 204         u64 phy_types;
 205 };
 206
 207 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 208 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 209 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 210 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 211 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 212 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 213 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 214 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 215 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 216 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 217 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 218 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 219 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 220 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 221 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 222 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 223 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 224 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 225 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 226 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 227 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 228 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 229 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 230 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 231 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 232 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 233 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 234                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 235 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 236 /* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 237  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 238  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 239  * a shift is needed to adjust for this with values larger than 31. The
 240  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 241  */
 242 #define I40E_PHY_TYPE_OFFSET 1
 243 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 244                                              I40E_PHY_TYPE_OFFSET)
 245 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 246                                              I40E_PHY_TYPE_OFFSET)
 247 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 248                                              I40E_PHY_TYPE_OFFSET)
 249 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 250                                              I40E_PHY_TYPE_OFFSET)
 251 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
 252                                              I40E_PHY_TYPE_OFFSET)
 253 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
 254                                              I40E_PHY_TYPE_OFFSET)
 255 /* Offset for 2.5G/5G PHY Types value to bit number conversion */
 256 #define I40E_PHY_TYPE_OFFSET2 (-10)
 257 #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \
 258                                              I40E_PHY_TYPE_OFFSET2)
 259 #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \
 260                                              I40E_PHY_TYPE_OFFSET2)
 261 #define I40E_HW_CAP_MAX_GPIO                    30
 262 /* Capabilities of a PF or a VF or the whole device */
 263 struct i40e_hw_capabilities {
 264         u32  switch_mode;
 265 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 266 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 267 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 268
 269         /* Cloud filter modes:
 270          * Mode1: Filter on L4 port only
 271          * Mode2: Filter for non-tunneled traffic
 272          * Mode3: Filter for tunnel traffic
 273          */
 274 #define I40E_CLOUD_FILTER_MODE1 0x6
 275 #define I40E_CLOUD_FILTER_MODE2 0x7
 276 #define I40E_CLOUD_FILTER_MODE3 0x8
 277 #define I40E_SWITCH_MODE_MASK   0xF
 278
 279         u32  management_mode;
 280         u32  mng_protocols_over_mctp;
 281 #define I40E_MNG_PROTOCOL_PLDM          0x2
 282 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 283 #define I40E_MNG_PROTOCOL_NCSI          0x8
 284         u32  npar_enable;
 285         u32  os2bmc;
 286         u32  valid_functions;
 287         bool sr_iov_1_1;
 288         bool vmdq;
 289         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 290         bool evb_802_1_qbh; /* Bridge Port Extension */
 291         bool dcb;
 292         bool fcoe;
 293         bool iscsi; /* Indicates iSCSI enabled */
 294         bool flex10_enable;
 295         bool flex10_capable;
 296         u32  flex10_mode;
 297 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 298 #define I40E_FLEX10_MODE_DCC            0x1
 299 #define I40E_FLEX10_MODE_DCI            0x2
 300
 301         u32 flex10_status;
 302 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 303 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 304
 305         bool sec_rev_disabled;
 306         bool update_disabled;
 307 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 308 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 309
 310         bool mgmt_cem;
 311         bool ieee_1588;
 312         bool iwarp;
 313         bool fd;
 314         u32 fd_filters_guaranteed;
 315         u32 fd_filters_best_effort;
 316         bool rss;
 317         u32 rss_table_size;
 318         u32 rss_table_entry_width;
 319         bool led[I40E_HW_CAP_MAX_GPIO];
 320         bool sdp[I40E_HW_CAP_MAX_GPIO];
 321         u32 nvm_image_type;
 322         u32 num_flow_director_filters;
 323         u32 num_vfs;
 324         u32 vf_base_id;
 325         u32 num_vsis;
 326         u32 num_rx_qp;
 327         u32 num_tx_qp;
 328         u32 base_queue;
 329         u32 num_msix_vectors;
 330         u32 num_msix_vectors_vf;
 331         u32 led_pin_num;
 332         u32 sdp_pin_num;
 333         u32 mdio_port_num;
 334         u32 mdio_port_mode;
 335         u8 rx_buf_chain_len;
 336         u32 enabled_tcmap;
 337         u32 maxtc;
 338         u64 wr_csr_prot;
 339 };
 340
 341 struct i40e_mac_info {
 342         enum i40e_mac_type type;
 343         u8 addr[ETH_ALEN];
 344         u8 perm_addr[ETH_ALEN];
 345         u8 san_addr[ETH_ALEN];
 346         u8 port_addr[ETH_ALEN];
 347         u16 max_fcoeq;
 348 };
 349
 350 enum i40e_aq_resources_ids {
 351         I40E_NVM_RESOURCE_ID = 1
 352 };
 353
 354 enum i40e_aq_resource_access_type {
 355         I40E_RESOURCE_READ = 1,
 356         I40E_RESOURCE_WRITE
 357 };
 358
 359 struct i40e_nvm_info {
 360         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 361         u32 timeout;              /* [ms] */
 362         u16 sr_size;              /* Shadow RAM size in words */
 363         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 364         u16 version;              /* NVM package version */
 365         u32 eetrack;              /* NVM data version */
 366         u32 oem_ver;              /* OEM version info */
 367 };
 368
 369 /* definitions used in NVM update support */
 370
 371 enum i40e_nvmupd_cmd {
 372         I40E_NVMUPD_INVALID,
 373         I40E_NVMUPD_READ_CON,
 374         I40E_NVMUPD_READ_SNT,
 375         I40E_NVMUPD_READ_LCB,
 376         I40E_NVMUPD_READ_SA,
 377         I40E_NVMUPD_WRITE_ERA,
 378         I40E_NVMUPD_WRITE_CON,
 379         I40E_NVMUPD_WRITE_SNT,
 380         I40E_NVMUPD_WRITE_LCB,
 381         I40E_NVMUPD_WRITE_SA,
 382         I40E_NVMUPD_CSUM_CON,
 383         I40E_NVMUPD_CSUM_SA,
 384         I40E_NVMUPD_CSUM_LCB,
 385         I40E_NVMUPD_STATUS,
 386         I40E_NVMUPD_EXEC_AQ,
 387         I40E_NVMUPD_GET_AQ_RESULT,
 388         I40E_NVMUPD_GET_AQ_EVENT,
 389 };
 390
 391 enum i40e_nvmupd_state {
 392         I40E_NVMUPD_STATE_INIT,
 393         I40E_NVMUPD_STATE_READING,
 394         I40E_NVMUPD_STATE_WRITING,
 395         I40E_NVMUPD_STATE_INIT_WAIT,
 396         I40E_NVMUPD_STATE_WRITE_WAIT,
 397         I40E_NVMUPD_STATE_ERROR
 398 };
 399
 400 /* nvm_access definition and its masks/shifts need to be accessible to
 401  * application, core driver, and shared code.  Where is the right file?
 402  */
 403 #define I40E_NVM_READ   0xB
 404 #define I40E_NVM_WRITE  0xC
 405
 406 #define I40E_NVM_MOD_PNT_MASK 0xFF
 407
 408 #define I40E_NVM_TRANS_SHIFT                    8
 409 #define I40E_NVM_TRANS_MASK                     (0xf << I40E_NVM_TRANS_SHIFT)
 410 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT       12
 411 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
 412                                 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
 413 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED    0x01
 414 #define I40E_NVM_PRESERVATION_FLAGS_ALL         0x02
 415 #define I40E_NVM_CON                            0x0
 416 #define I40E_NVM_SNT                            0x1
 417 #define I40E_NVM_LCB                            0x2
 418 #define I40E_NVM_SA                             (I40E_NVM_SNT | I40E_NVM_LCB)
 419 #define I40E_NVM_ERA                            0x4
 420 #define I40E_NVM_CSUM                           0x8
 421 #define I40E_NVM_AQE                            0xe
 422 #define I40E_NVM_EXEC                           0xf
 423
 424 #define I40E_NVM_ADAPT_SHIFT    16
 425 #define I40E_NVM_ADAPT_MASK     (0xffff << I40E_NVM_ADAPT_SHIFT)
 426
 427 #define I40E_NVMUPD_MAX_DATA    4096
 428 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 429
 430 struct i40e_nvm_access {
 431         u32 command;
 432         u32 config;
 433         u32 offset;     /* in bytes */
 434         u32 data_size;  /* in bytes */
 435         u8 data[1];
 436 };
 437
 438 /* (Q)SFP module access definitions */
 439 #define I40E_I2C_EEPROM_DEV_ADDR        0xA0
 440 #define I40E_I2C_EEPROM_DEV_ADDR2       0xA2
 441 #define I40E_MODULE_TYPE_ADDR           0x00
 442 #define I40E_MODULE_REVISION_ADDR       0x01
 443 #define I40E_MODULE_SFF_8472_COMP       0x5E
 444 #define I40E_MODULE_SFF_8472_SWAP       0x5C
 445 #define I40E_MODULE_SFF_ADDR_MODE       0x04
 446 #define I40E_MODULE_TYPE_QSFP_PLUS      0x0D
 447 #define I40E_MODULE_TYPE_QSFP28         0x11
 448 #define I40E_MODULE_QSFP_MAX_LEN        640
 449
 450 /* PCI bus types */
 451 enum i40e_bus_type {
 452         i40e_bus_type_unknown = 0,
 453         i40e_bus_type_pci,
 454         i40e_bus_type_pcix,
 455         i40e_bus_type_pci_express,
 456         i40e_bus_type_reserved
 457 };
 458
 459 /* PCI bus speeds */
 460 enum i40e_bus_speed {
 461         i40e_bus_speed_unknown  = 0,
 462         i40e_bus_speed_33       = 33,
 463         i40e_bus_speed_66       = 66,
 464         i40e_bus_speed_100      = 100,
 465         i40e_bus_speed_120      = 120,
 466         i40e_bus_speed_133      = 133,
 467         i40e_bus_speed_2500     = 2500,
 468         i40e_bus_speed_5000     = 5000,
 469         i40e_bus_speed_8000     = 8000,
 470         i40e_bus_speed_reserved
 471 };
 472
 473 /* PCI bus widths */
 474 enum i40e_bus_width {
 475         i40e_bus_width_unknown  = 0,
 476         i40e_bus_width_pcie_x1  = 1,
 477         i40e_bus_width_pcie_x2  = 2,
 478         i40e_bus_width_pcie_x4  = 4,
 479         i40e_bus_width_pcie_x8  = 8,
 480         i40e_bus_width_32       = 32,
 481         i40e_bus_width_64       = 64,
 482         i40e_bus_width_reserved
 483 };
 484
 485 /* Bus parameters */
 486 struct i40e_bus_info {
 487         enum i40e_bus_speed speed;
 488         enum i40e_bus_width width;
 489         enum i40e_bus_type type;
 490
 491         u16 func;
 492         u16 device;
 493         u16 lan_id;
 494         u16 bus_id;
 495 };
 496
 497 /* Flow control (FC) parameters */
 498 struct i40e_fc_info {
 499         enum i40e_fc_mode current_mode; /* FC mode in effect */
 500         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 501 };
 502
 503 #define I40E_MAX_TRAFFIC_CLASS          8
 504 #define I40E_MAX_USER_PRIORITY          8
 505 #define I40E_DCBX_MAX_APPS              32
 506 #define I40E_LLDPDU_SIZE                1500
 507 #define I40E_TLV_STATUS_OPER            0x1
 508 #define I40E_TLV_STATUS_SYNC            0x2
 509 #define I40E_TLV_STATUS_ERR             0x4
 510 #define I40E_CEE_OPER_MAX_APPS          3
 511 #define I40E_APP_PROTOID_FCOE           0x8906
 512 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 513 #define I40E_APP_PROTOID_FIP            0x8914
 514 #define I40E_APP_SEL_ETHTYPE            0x1
 515 #define I40E_APP_SEL_TCPIP              0x2
 516 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 517 #define I40E_CEE_APP_SEL_TCPIP          0x1
 518
 519 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 520 struct i40e_dcb_ets_config {
 521         u8 willing;
 522         u8 cbs;
 523         u8 maxtcs;
 524         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 525         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 526         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 527 };
 528
 529 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 530 struct i40e_dcb_pfc_config {
 531         u8 willing;
 532         u8 mbc;
 533         u8 pfccap;
 534         u8 pfcenable;
 535 };
 536
 537 /* CEE or IEEE 802.1Qaz Application Priority data */
 538 struct i40e_dcb_app_priority_table {
 539         u8  priority;
 540         u8  selector;
 541         u16 protocolid;
 542 };
 543
 544 struct i40e_dcbx_config {
 545         u8  dcbx_mode;
 546 #define I40E_DCBX_MODE_CEE      0x1
 547 #define I40E_DCBX_MODE_IEEE     0x2
 548         u8  app_mode;
 549 #define I40E_DCBX_APPS_NON_WILLING      0x1
 550         u32 numapps;
 551         u32 tlv_status; /* CEE mode TLV status */
 552         struct i40e_dcb_ets_config etscfg;
 553         struct i40e_dcb_ets_config etsrec;
 554         struct i40e_dcb_pfc_config pfc;
 555         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 556 };
 557
 558 /* Port hardware description */
 559 struct i40e_hw {
 560         u8 __iomem *hw_addr;
 561         void *back;
 562
 563         /* subsystem structs */
 564         struct i40e_phy_info phy;
 565         struct i40e_mac_info mac;
 566         struct i40e_bus_info bus;
 567         struct i40e_nvm_info nvm;
 568         struct i40e_fc_info fc;
 569
 570         /* pci info */
 571         u16 device_id;
 572         u16 vendor_id;
 573         u16 subsystem_device_id;
 574         u16 subsystem_vendor_id;
 575         u8 revision_id;
 576         u8 port;
 577         bool adapter_stopped;
 578
 579         /* capabilities for entire device and PCI func */
 580         struct i40e_hw_capabilities dev_caps;
 581         struct i40e_hw_capabilities func_caps;
 582
 583         /* Flow Director shared filter space */
 584         u16 fdir_shared_filter_count;
 585
 586         /* device profile info */
 587         u8  pf_id;
 588         u16 main_vsi_seid;
 589
 590         /* for multi-function MACs */
 591         u16 partition_id;
 592         u16 num_partitions;
 593         u16 num_ports;
 594
 595         /* Closest numa node to the device */
 596         u16 numa_node;
 597
 598         /* Admin Queue info */
 599         struct i40e_adminq_info aq;
 600
 601         /* state of nvm update process */
 602         enum i40e_nvmupd_state nvmupd_state;
 603         struct i40e_aq_desc nvm_wb_desc;
 604         struct i40e_aq_desc nvm_aq_event_desc;
 605         struct i40e_virt_mem nvm_buff;
 606         bool nvm_release_on_done;
 607         u16 nvm_wait_opcode;
 608
 609         /* HMC info */
 610         struct i40e_hmc_info hmc; /* HMC info struct */
 611
 612         /* LLDP/DCBX Status */
 613         u16 dcbx_status;
 614
 615         /* DCBX info */
 616         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 617         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 618         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 619
 620 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 621 #define I40E_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 622 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 623 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
 624 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE      BIT_ULL(4)
 625 #define I40E_HW_FLAG_FW_LLDP_PERSISTENT     BIT_ULL(5)
 626         u64 flags;
 627
 628         /* Used in set switch config AQ command */
 629         u16 switch_tag;
 630         u16 first_tag;
 631         u16 second_tag;
 632
 633         /* debug mask */
 634         u32 debug_mask;
 635         char err_str[16];
 636 };
 637
 638 static inline bool i40e_is_vf(struct i40e_hw *hw)
 639 {
 640         return (hw->mac.type == I40E_MAC_VF ||
 641                 hw->mac.type == I40E_MAC_X722_VF);
 642 }
 643
 644 struct i40e_driver_version {
 645         u8 major_version;
 646         u8 minor_version;
 647         u8 build_version;
 648         u8 subbuild_version;
 649         u8 driver_string[32];
 650 };
 651
 652 /* RX Descriptors */
 653 union i40e_16byte_rx_desc {
 654         struct {
 655                 __le64 pkt_addr; /* Packet buffer address */
 656                 __le64 hdr_addr; /* Header buffer address */
 657         } read;
 658         struct {
 659                 struct {
 660                         struct {
 661                                 union {
 662                                         __le16 mirroring_status;
 663                                         __le16 fcoe_ctx_id;
 664                                 } mirr_fcoe;
 665                                 __le16 l2tag1;
 666                         } lo_dword;
 667                         union {
 668                                 __le32 rss; /* RSS Hash */
 669                                 __le32 fd_id; /* Flow director filter id */
 670                                 __le32 fcoe_param; /* FCoE DDP Context id */
 671                         } hi_dword;
 672                 } qword0;
 673                 struct {
 674                         /* ext status/error/pktype/length */
 675                         __le64 status_error_len;
 676                 } qword1;
 677         } wb;  /* writeback */
 678 };
 679
 680 union i40e_32byte_rx_desc {
 681         struct {
 682                 __le64  pkt_addr; /* Packet buffer address */
 683                 __le64  hdr_addr; /* Header buffer address */
 684                         /* bit 0 of hdr_buffer_addr is DD bit */
 685                 __le64  rsvd1;
 686                 __le64  rsvd2;
 687         } read;
 688         struct {
 689                 struct {
 690                         struct {
 691                                 union {
 692                                         __le16 mirroring_status;
 693                                         __le16 fcoe_ctx_id;
 694                                 } mirr_fcoe;
 695                                 __le16 l2tag1;
 696                         } lo_dword;
 697                         union {
 698                                 __le32 rss; /* RSS Hash */
 699                                 __le32 fcoe_param; /* FCoE DDP Context id */
 700                                 /* Flow director filter id in case of
 701                                  * Programming status desc WB
 702                                  */
 703                                 __le32 fd_id;
 704                         } hi_dword;
 705                 } qword0;
 706                 struct {
 707                         /* status/error/pktype/length */
 708                         __le64 status_error_len;
 709                 } qword1;
 710                 struct {
 711                         __le16 ext_status; /* extended status */
 712                         __le16 rsvd;
 713                         __le16 l2tag2_1;
 714                         __le16 l2tag2_2;
 715                 } qword2;
 716                 struct {
 717                         union {
 718                                 __le32 flex_bytes_lo;
 719                                 __le32 pe_status;
 720                         } lo_dword;
 721                         union {
 722                                 __le32 flex_bytes_hi;
 723                                 __le32 fd_id;
 724                         } hi_dword;
 725                 } qword3;
 726         } wb;  /* writeback */
 727 };
 728
 729 enum i40e_rx_desc_status_bits {
 730         /* Note: These are predefined bit offsets */
 731         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 732         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 733         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 734         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 735         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 736         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 737         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 738         /* Note: Bit 8 is reserved in X710 and XL710 */
 739         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 740         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 741         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 742         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 743         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 744         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 745         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 746         /* Note: For non-tunnel packets INT_UDP_0 is the right status for
 747          * UDP header
 748          */
 749         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 750         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 751 };
 752
 753 #define I40E_RXD_QW1_STATUS_SHIFT       0
 754 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
 755                                          << I40E_RXD_QW1_STATUS_SHIFT)
 756
 757 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 758 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 759                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 760
 761 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 762 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
 763                                     BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 764
 765 enum i40e_rx_desc_fltstat_values {
 766         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 767         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 768         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 769         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 770 };
 771
 772 #define I40E_RXD_QW1_ERROR_SHIFT        19
 773 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 774
 775 enum i40e_rx_desc_error_bits {
 776         /* Note: These are predefined bit offsets */
 777         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 778         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 779         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 780         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 781         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 782         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 783         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 784         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 785         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 786 };
 787
 788 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 789         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 790         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 791         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 792         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 793         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 794 };
 795
 796 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 797 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 798
 799 /* Packet type non-ip values */
 800 enum i40e_rx_l2_ptype {
 801         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 802         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 803         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 804         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 805         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 806         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 807         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 808         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 809         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 810         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 811         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 812         I40E_RX_PTYPE_L2_ARP                            = 11,
 813         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 814         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 815         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 816         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 817         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 818         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 819         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 820         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 821         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 822         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 823         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 824         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 825         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 826         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 827 };
 828
 829 struct i40e_rx_ptype_decoded {
 830         u32 ptype:8;
 831         u32 known:1;
 832         u32 outer_ip:1;
 833         u32 outer_ip_ver:1;
 834         u32 outer_frag:1;
 835         u32 tunnel_type:3;
 836         u32 tunnel_end_prot:2;
 837         u32 tunnel_end_frag:1;
 838         u32 inner_prot:4;
 839         u32 payload_layer:3;
 840 };
 841
 842 enum i40e_rx_ptype_outer_ip {
 843         I40E_RX_PTYPE_OUTER_L2  = 0,
 844         I40E_RX_PTYPE_OUTER_IP  = 1
 845 };
 846
 847 enum i40e_rx_ptype_outer_ip_ver {
 848         I40E_RX_PTYPE_OUTER_NONE        = 0,
 849         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 850         I40E_RX_PTYPE_OUTER_IPV6        = 1
 851 };
 852
 853 enum i40e_rx_ptype_outer_fragmented {
 854         I40E_RX_PTYPE_NOT_FRAG  = 0,
 855         I40E_RX_PTYPE_FRAG      = 1
 856 };
 857
 858 enum i40e_rx_ptype_tunnel_type {
 859         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 860         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 861         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 862         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 863         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 864 };
 865
 866 enum i40e_rx_ptype_tunnel_end_prot {
 867         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 868         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 869         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 870 };
 871
 872 enum i40e_rx_ptype_inner_prot {
 873         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 874         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 875         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 876         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 877         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 878         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 879 };
 880
 881 enum i40e_rx_ptype_payload_layer {
 882         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 883         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 884         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 885         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 886 };
 887
 888 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 889 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 890                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 891
 892 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 893 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 894                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 895
 896 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 897 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 898
 899 enum i40e_rx_desc_ext_status_bits {
 900         /* Note: These are predefined bit offsets */
 901         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 902         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 903         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 904         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 905         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 906         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 907         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 908 };
 909
 910 enum i40e_rx_desc_pe_status_bits {
 911         /* Note: These are predefined bit offsets */
 912         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 913         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 914         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 915         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 916         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 917         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 918         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 919         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 920         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 921 };
 922
 923 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 924 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 925
 926 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 927 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 928                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 929
 930 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 931 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 932                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 933
 934 enum i40e_rx_prog_status_desc_status_bits {
 935         /* Note: These are predefined bit offsets */
 936         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 937         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 938 };
 939
 940 enum i40e_rx_prog_status_desc_prog_id_masks {
 941         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 942         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 943         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 944 };
 945
 946 enum i40e_rx_prog_status_desc_error_bits {
 947         /* Note: These are predefined bit offsets */
 948         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 949         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 950         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 951         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 952 };
 953
 954 /* TX Descriptor */
 955 struct i40e_tx_desc {
 956         __le64 buffer_addr; /* Address of descriptor's data buf */
 957         __le64 cmd_type_offset_bsz;
 958 };
 959
 960 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 961 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 962
 963 enum i40e_tx_desc_dtype_value {
 964         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 965         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 966         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 967         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 968         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 969         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 970         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 971         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 972         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 973         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 974 };
 975
 976 #define I40E_TXD_QW1_CMD_SHIFT  4
 977 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 978
 979 enum i40e_tx_desc_cmd_bits {
 980         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 981         I40E_TX_DESC_CMD_RS                     = 0x0002,
 982         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 983         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 984         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 985         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 986         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 987         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 988         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 989         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 990         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 991         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 992         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 993         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 994         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 995         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 996         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 997         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 998 };
 999
1000 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1001 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1002                                          I40E_TXD_QW1_OFFSET_SHIFT)
1003
1004 enum i40e_tx_desc_length_fields {
1005         /* Note: These are predefined bit offsets */
1006         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1007         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1008         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1009 };
1010
1011 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1012 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1013                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1014
1015 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1016 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1017
1018 /* Context descriptors */
1019 struct i40e_tx_context_desc {
1020         __le32 tunneling_params;
1021         __le16 l2tag2;
1022         __le16 rsvd;
1023         __le64 type_cmd_tso_mss;
1024 };
1025
1026 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1027 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1028
1029 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1030 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1031
1032 enum i40e_tx_ctx_desc_cmd_bits {
1033         I40E_TX_CTX_DESC_TSO            = 0x01,
1034         I40E_TX_CTX_DESC_TSYN           = 0x02,
1035         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1036         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1037         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1038         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1039         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1040         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1041         I40E_TX_CTX_DESC_SWPE           = 0x40
1042 };
1043
1044 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1045 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1046                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1047
1048 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1049 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1050                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1051
1052 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1053 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1054
1055 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1056 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1057                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1058
1059 enum i40e_tx_ctx_desc_eipt_offload {
1060         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1061         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1062         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1063         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1064 };
1065
1066 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1067 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1068                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1069
1070 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1071 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1072
1073 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1074 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1075
1076 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1077 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
1078                                        BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1079
1080 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1081
1082 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1083 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1084                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1085
1086 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1087 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1088                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1089
1090 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1091 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1092 struct i40e_filter_program_desc {
1093         __le32 qindex_flex_ptype_vsi;
1094         __le32 rsvd;
1095         __le32 dtype_cmd_cntindex;
1096         __le32 fd_id;
1097 };
1098 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1099 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1100                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1101 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1102 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1103                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1104 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1105 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1106                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1107
1108 /* Packet Classifier Types for filters */
1109 enum i40e_filter_pctype {
1110         /* Note: Values 0-28 are reserved for future use.
1111          * Value 29, 30, 32 are not supported on XL710 and X710.
1112          */
1113         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1114         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1115         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1116         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1117         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1118         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1119         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1120         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1121         /* Note: Values 37-38 are reserved for future use.
1122          * Value 39, 40, 42 are not supported on XL710 and X710.
1123          */
1124         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1125         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1126         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1127         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1128         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1129         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1130         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1131         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1132         /* Note: Value 47 is reserved for future use */
1133         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1134         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1135         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1136         /* Note: Values 51-62 are reserved for future use */
1137         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1138 };
1139
1140 enum i40e_filter_program_desc_dest {
1141         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1142         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1143         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1144 };
1145
1146 enum i40e_filter_program_desc_fd_status {
1147         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1148         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1149         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1150         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1151 };
1152
1153 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1154 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1155                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1156
1157 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1158 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1159                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1160
1161 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1162 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1163
1164 enum i40e_filter_program_desc_pcmd {
1165         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1166         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1167 };
1168
1169 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1170 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1171
1172 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1173 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1174
1175 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1176                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1177 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1178                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1179
1180 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1181                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1182 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1183
1184 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1185                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1186 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1187
1188 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1189 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1190                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1191
1192 enum i40e_filter_type {
1193         I40E_FLOW_DIRECTOR_FLTR = 0,
1194         I40E_PE_QUAD_HASH_FLTR = 1,
1195         I40E_ETHERTYPE_FLTR,
1196         I40E_FCOE_CTX_FLTR,
1197         I40E_MAC_VLAN_FLTR,
1198         I40E_HASH_FLTR
1199 };
1200
1201 struct i40e_vsi_context {
1202         u16 seid;
1203         u16 uplink_seid;
1204         u16 vsi_number;
1205         u16 vsis_allocated;
1206         u16 vsis_unallocated;
1207         u16 flags;
1208         u8 pf_num;
1209         u8 vf_num;
1210         u8 connection_type;
1211         struct i40e_aqc_vsi_properties_data info;
1212 };
1213
1214 struct i40e_veb_context {
1215         u16 seid;
1216         u16 uplink_seid;
1217         u16 veb_number;
1218         u16 vebs_allocated;
1219         u16 vebs_unallocated;
1220         u16 flags;
1221         struct i40e_aqc_get_veb_parameters_completion info;
1222 };
1223
1224 /* Statistics collected by each port, VSI, VEB, and S-channel */
1225 struct i40e_eth_stats {
1226         u64 rx_bytes;                   /* gorc */
1227         u64 rx_unicast;                 /* uprc */
1228         u64 rx_multicast;               /* mprc */
1229         u64 rx_broadcast;               /* bprc */
1230         u64 rx_discards;                /* rdpc */
1231         u64 rx_unknown_protocol;        /* rupp */
1232         u64 tx_bytes;                   /* gotc */
1233         u64 tx_unicast;                 /* uptc */
1234         u64 tx_multicast;               /* mptc */
1235         u64 tx_broadcast;               /* bptc */
1236         u64 tx_discards;                /* tdpc */
1237         u64 tx_errors;                  /* tepc */
1238 };
1239
1240 /* Statistics collected per VEB per TC */
1241 struct i40e_veb_tc_stats {
1242         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1243         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1244         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1245         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1246 };
1247
1248 /* Statistics collected by the MAC */
1249 struct i40e_hw_port_stats {
1250         /* eth stats collected by the port */
1251         struct i40e_eth_stats eth;
1252
1253         /* additional port specific stats */
1254         u64 tx_dropped_link_down;       /* tdold */
1255         u64 crc_errors;                 /* crcerrs */
1256         u64 illegal_bytes;              /* illerrc */
1257         u64 error_bytes;                /* errbc */
1258         u64 mac_local_faults;           /* mlfc */
1259         u64 mac_remote_faults;          /* mrfc */
1260         u64 rx_length_errors;           /* rlec */
1261         u64 link_xon_rx;                /* lxonrxc */
1262         u64 link_xoff_rx;               /* lxoffrxc */
1263         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1264         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1265         u64 link_xon_tx;                /* lxontxc */
1266         u64 link_xoff_tx;               /* lxofftxc */
1267         u64 priority_xon_tx[8];         /* pxontxc[8] */
1268         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1269         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1270         u64 rx_size_64;                 /* prc64 */
1271         u64 rx_size_127;                /* prc127 */
1272         u64 rx_size_255;                /* prc255 */
1273         u64 rx_size_511;                /* prc511 */
1274         u64 rx_size_1023;               /* prc1023 */
1275         u64 rx_size_1522;               /* prc1522 */
1276         u64 rx_size_big;                /* prc9522 */
1277         u64 rx_undersize;               /* ruc */
1278         u64 rx_fragments;               /* rfc */
1279         u64 rx_oversize;                /* roc */
1280         u64 rx_jabber;                  /* rjc */
1281         u64 tx_size_64;                 /* ptc64 */
1282         u64 tx_size_127;                /* ptc127 */
1283         u64 tx_size_255;                /* ptc255 */
1284         u64 tx_size_511;                /* ptc511 */
1285         u64 tx_size_1023;               /* ptc1023 */
1286         u64 tx_size_1522;               /* ptc1522 */
1287         u64 tx_size_big;                /* ptc9522 */
1288         u64 mac_short_packet_dropped;   /* mspdc */
1289         u64 checksum_error;             /* xec */
1290         /* flow director stats */
1291         u64 fd_atr_match;
1292         u64 fd_sb_match;
1293         u64 fd_atr_tunnel_match;
1294         u32 fd_atr_status;
1295         u32 fd_sb_status;
1296         /* EEE LPI */
1297         u32 tx_lpi_status;
1298         u32 rx_lpi_status;
1299         u64 tx_lpi_count;               /* etlpic */
1300         u64 rx_lpi_count;               /* erlpic */
1301 };
1302
1303 /* Checksum and Shadow RAM pointers */
1304 #define I40E_SR_NVM_CONTROL_WORD                0x00
1305 #define I40E_EMP_MODULE_PTR                     0x0F
1306 #define I40E_SR_EMP_MODULE_PTR                  0x48
1307 #define I40E_SR_PBA_FLAGS                       0x15
1308 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1309 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1310 #define I40E_NVM_OEM_VER_OFF                    0x83
1311 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1312 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1313 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1314 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1315 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1316 #define I40E_SR_VPD_PTR                         0x2F
1317 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1318 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1319
1320 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1321 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1322 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1323 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1324 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1325 #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID   BIT(5)
1326 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE          BIT(12)
1327 #define I40E_PTR_TYPE                           BIT(15)
1328 #define I40E_SR_OCP_CFG_WORD0                   0x2B
1329 #define I40E_SR_OCP_ENABLED                     BIT(15)
1330
1331 /* Shadow RAM related */
1332 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1333 #define I40E_SR_WORDS_IN_1KB            512
1334 /* Checksum should be calculated such that after adding all the words,
1335  * including the checksum word itself, the sum should be 0xBABA.
1336  */
1337 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1338
1339 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1340
1341 enum i40e_switch_element_types {
1342         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1343         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1344         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1345         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1346         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1347         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1348         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1349         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1350         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1351 };
1352
1353 /* Supported EtherType filters */
1354 enum i40e_ether_type_index {
1355         I40E_ETHER_TYPE_1588            = 0,
1356         I40E_ETHER_TYPE_FIP             = 1,
1357         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1358         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1359         I40E_ETHER_TYPE_LLDP            = 4,
1360         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1361         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1362         I40E_ETHER_TYPE_QCN_CNM         = 7,
1363         I40E_ETHER_TYPE_8021X           = 8,
1364         I40E_ETHER_TYPE_ARP             = 9,
1365         I40E_ETHER_TYPE_RSV1            = 10,
1366         I40E_ETHER_TYPE_RSV2            = 11,
1367 };
1368
1369 /* Filter context base size is 1K */
1370 #define I40E_HASH_FILTER_BASE_SIZE      1024
1371 /* Supported Hash filter values */
1372 enum i40e_hash_filter_size {
1373         I40E_HASH_FILTER_SIZE_1K        = 0,
1374         I40E_HASH_FILTER_SIZE_2K        = 1,
1375         I40E_HASH_FILTER_SIZE_4K        = 2,
1376         I40E_HASH_FILTER_SIZE_8K        = 3,
1377         I40E_HASH_FILTER_SIZE_16K       = 4,
1378         I40E_HASH_FILTER_SIZE_32K       = 5,
1379         I40E_HASH_FILTER_SIZE_64K       = 6,
1380         I40E_HASH_FILTER_SIZE_128K      = 7,
1381         I40E_HASH_FILTER_SIZE_256K      = 8,
1382         I40E_HASH_FILTER_SIZE_512K      = 9,
1383         I40E_HASH_FILTER_SIZE_1M        = 10,
1384 };
1385
1386 /* DMA context base size is 0.5K */
1387 #define I40E_DMA_CNTX_BASE_SIZE         512
1388 /* Supported DMA context values */
1389 enum i40e_dma_cntx_size {
1390         I40E_DMA_CNTX_SIZE_512          = 0,
1391         I40E_DMA_CNTX_SIZE_1K           = 1,
1392         I40E_DMA_CNTX_SIZE_2K           = 2,
1393         I40E_DMA_CNTX_SIZE_4K           = 3,
1394         I40E_DMA_CNTX_SIZE_8K           = 4,
1395         I40E_DMA_CNTX_SIZE_16K          = 5,
1396         I40E_DMA_CNTX_SIZE_32K          = 6,
1397         I40E_DMA_CNTX_SIZE_64K          = 7,
1398         I40E_DMA_CNTX_SIZE_128K         = 8,
1399         I40E_DMA_CNTX_SIZE_256K         = 9,
1400 };
1401
1402 /* Supported Hash look up table (LUT) sizes */
1403 enum i40e_hash_lut_size {
1404         I40E_HASH_LUT_SIZE_128          = 0,
1405         I40E_HASH_LUT_SIZE_512          = 1,
1406 };
1407
1408 /* Structure to hold a per PF filter control settings */
1409 struct i40e_filter_control_settings {
1410         /* number of PE Quad Hash filter buckets */
1411         enum i40e_hash_filter_size pe_filt_num;
1412         /* number of PE Quad Hash contexts */
1413         enum i40e_dma_cntx_size pe_cntx_num;
1414         /* number of FCoE filter buckets */
1415         enum i40e_hash_filter_size fcoe_filt_num;
1416         /* number of FCoE DDP contexts */
1417         enum i40e_dma_cntx_size fcoe_cntx_num;
1418         /* size of the Hash LUT */
1419         enum i40e_hash_lut_size hash_lut_size;
1420         /* enable FDIR filters for PF and its VFs */
1421         bool enable_fdir;
1422         /* enable Ethertype filters for PF and its VFs */
1423         bool enable_ethtype;
1424         /* enable MAC/VLAN filters for PF and its VFs */
1425         bool enable_macvlan;
1426 };
1427
1428 /* Structure to hold device level control filter counts */
1429 struct i40e_control_filter_stats {
1430         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1431         u16 etype_used;       /* Used perfect EtherType filters */
1432         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1433         u16 etype_free;       /* Un-used perfect EtherType filters */
1434 };
1435
1436 enum i40e_reset_type {
1437         I40E_RESET_POR          = 0,
1438         I40E_RESET_CORER        = 1,
1439         I40E_RESET_GLOBR        = 2,
1440         I40E_RESET_EMPR         = 3,
1441 };
1442
1443 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1444 #define I40E_NVM_LLDP_CFG_PTR   0x06
1445 #define I40E_SR_LLDP_CFG_PTR    0x31
1446 struct i40e_lldp_variables {
1447         u16 length;
1448         u16 adminstatus;
1449         u16 msgfasttx;
1450         u16 msgtxinterval;
1451         u16 txparams;
1452         u16 timers;
1453         u16 crc8;
1454 };
1455
1456 /* Offsets into Alternate Ram */
1457 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1458 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1459 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1460 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1461 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1462 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1463
1464 /* Alternate Ram Bandwidth Masks */
1465 #define I40E_ALT_BW_VALUE_MASK          0xFF
1466 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1467 #define I40E_ALT_BW_VALID_MASK          0x80000000
1468
1469 /* RSS Hash Table Size */
1470 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1471
1472 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1473 #define I40E_L3_SRC_SHIFT               47
1474 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1475 #define I40E_L3_V6_SRC_SHIFT            43
1476 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1477 #define I40E_L3_DST_SHIFT               35
1478 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1479 #define I40E_L3_V6_DST_SHIFT            35
1480 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1481 #define I40E_L4_SRC_SHIFT               34
1482 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1483 #define I40E_L4_DST_SHIFT               33
1484 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1485 #define I40E_VERIFY_TAG_SHIFT           31
1486 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1487
1488 #define I40E_FLEX_50_SHIFT              13
1489 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1490 #define I40E_FLEX_51_SHIFT              12
1491 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1492 #define I40E_FLEX_52_SHIFT              11
1493 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1494 #define I40E_FLEX_53_SHIFT              10
1495 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1496 #define I40E_FLEX_54_SHIFT              9
1497 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1498 #define I40E_FLEX_55_SHIFT              8
1499 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1500 #define I40E_FLEX_56_SHIFT              7
1501 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1502 #define I40E_FLEX_57_SHIFT              6
1503 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1504
1505 /* Version format for Dynamic Device Personalization(DDP) */
1506 struct i40e_ddp_version {
1507         u8 major;
1508         u8 minor;
1509         u8 update;
1510         u8 draft;
1511 };
1512
1513 #define I40E_DDP_NAME_SIZE      32
1514
1515 /* Package header */
1516 struct i40e_package_header {
1517         struct i40e_ddp_version version;
1518         u32 segment_count;
1519         u32 segment_offset[1];
1520 };
1521
1522 /* Generic segment header */
1523 struct i40e_generic_seg_header {
1524 #define SEGMENT_TYPE_METADATA   0x00000001
1525 #define SEGMENT_TYPE_NOTES      0x00000002
1526 #define SEGMENT_TYPE_I40E       0x00000011
1527 #define SEGMENT_TYPE_X722       0x00000012
1528         u32 type;
1529         struct i40e_ddp_version version;
1530         u32 size;
1531         char name[I40E_DDP_NAME_SIZE];
1532 };
1533
1534 struct i40e_metadata_segment {
1535         struct i40e_generic_seg_header header;
1536         struct i40e_ddp_version version;
1537 #define I40E_DDP_TRACKID_RDONLY         0
1538 #define I40E_DDP_TRACKID_INVALID        0xFFFFFFFF
1539         u32 track_id;
1540         char name[I40E_DDP_NAME_SIZE];
1541 };
1542
1543 struct i40e_device_id_entry {
1544         u32 vendor_dev_id;
1545         u32 sub_vendor_dev_id;
1546 };
1547
1548 struct i40e_profile_segment {
1549         struct i40e_generic_seg_header header;
1550         struct i40e_ddp_version version;
1551         char name[I40E_DDP_NAME_SIZE];
1552         u32 device_table_count;
1553         struct i40e_device_id_entry device_table[1];
1554 };
1555
1556 struct i40e_section_table {
1557         u32 section_count;
1558         u32 section_offset[1];
1559 };
1560
1561 struct i40e_profile_section_header {
1562         u16 tbl_size;
1563         u16 data_end;
1564         struct {
1565 #define SECTION_TYPE_INFO       0x00000010
1566 #define SECTION_TYPE_MMIO       0x00000800
1567 #define SECTION_TYPE_RB_MMIO    0x00001800
1568 #define SECTION_TYPE_AQ         0x00000801
1569 #define SECTION_TYPE_RB_AQ      0x00001801
1570 #define SECTION_TYPE_NOTE       0x80000000
1571 #define SECTION_TYPE_NAME       0x80000001
1572 #define SECTION_TYPE_PROTO      0x80000002
1573 #define SECTION_TYPE_PCTYPE     0x80000003
1574 #define SECTION_TYPE_PTYPE      0x80000004
1575                 u32 type;
1576                 u32 offset;
1577                 u32 size;
1578         } section;
1579 };
1580
1581 struct i40e_profile_tlv_section_record {
1582         u8 rtype;
1583         u8 type;
1584         u16 len;
1585         u8 data[12];
1586 };
1587
1588 /* Generic AQ section in proflie */
1589 struct i40e_profile_aq_section {
1590         u16 opcode;
1591         u16 flags;
1592         u8  param[16];
1593         u16 datalen;
1594         u8  data[1];
1595 };
1596
1597 struct i40e_profile_info {
1598         u32 track_id;
1599         struct i40e_ddp_version version;
1600         u8 op;
1601 #define I40E_DDP_ADD_TRACKID            0x01
1602 #define I40E_DDP_REMOVE_TRACKID 0x02
1603         u8 reserved[7];
1604         u8 name[I40E_DDP_NAME_SIZE];
1605 };
1606 #endif /* _I40E_TYPE_H_ */