drivers/net/ethernet/intel/e1000e/manage.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4 #ifndef _E1000E_MANAGE_H_
   5 #define _E1000E_MANAGE_H_
   6
   7 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
   8 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
   9 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
  10 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
  11
  12 enum e1000_mng_mode {
  13         e1000_mng_mode_none = 0,
  14         e1000_mng_mode_asf,
  15         e1000_mng_mode_pt,
  16         e1000_mng_mode_ipmi,
  17         e1000_mng_mode_host_if_only
  18 };
  19
  20 #define E1000_FACTPS_MNGCG                      0x20000000
  21
  22 #define E1000_FWSM_MODE_MASK                    0xE
  23 #define E1000_FWSM_MODE_SHIFT                   1
  24
  25 #define E1000_MNG_IAMT_MODE                     0x3
  26 #define E1000_MNG_DHCP_COOKIE_LENGTH            0x10
  27 #define E1000_MNG_DHCP_COOKIE_OFFSET            0x6F0
  28 #define E1000_MNG_DHCP_COMMAND_TIMEOUT          10
  29 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD           64
  30 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING    0x1
  31 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN       0x2
  32
  33 #define E1000_VFTA_ENTRY_SHIFT                  5
  34 #define E1000_VFTA_ENTRY_MASK                   0x7F
  35 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK         0x1F
  36
  37 #define E1000_HICR_EN                   0x01    /* Enable bit - RO */
  38 /* Driver sets this bit when done to put command in RAM */
  39 #define E1000_HICR_C                    0x02
  40 #define E1000_HICR_SV                   0x04    /* Status Validity */
  41 #define E1000_HICR_FW_RESET_ENABLE      0x40
  42 #define E1000_HICR_FW_RESET             0x80
  43
  44 /* Intel(R) Active Management Technology signature */
  45 #define E1000_IAMT_SIGNATURE            0x544D4149
  46
  47 #endif