1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/net/ethernet/ibm/emac/core.c
5 * Driver for PowerPC 4xx on-chip ethernet controller.
7 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
8 * <benh@kernel.crashing.org>
10 * Based on the arch/ppc version of the driver:
12 * Copyright (c) 2004, 2005 Zultys Technologies.
13 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
15 * Based on original work by
16 * Matt Porter <mporter@kernel.crashing.org>
17 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
18 * Armin Kuster <akuster@mvista.com>
19 * Johnnie Peters <jpeters@mvista.com>
22 #include <linux/module.h>
23 #include <linux/sched.h>
24 #include <linux/string.h>
25 #include <linux/errno.h>
26 #include <linux/delay.h>
27 #include <linux/types.h>
28 #include <linux/pci.h>
29 #include <linux/etherdevice.h>
30 #include <linux/skbuff.h>
31 #include <linux/crc32.h>
32 #include <linux/ethtool.h>
33 #include <linux/mii.h>
34 #include <linux/bitops.h>
35 #include <linux/workqueue.h>
37 #include <linux/of_address.h>
38 #include <linux/of_irq.h>
39 #include <linux/of_net.h>
40 #include <linux/of_mdio.h>
41 #include <linux/slab.h>
43 #include <asm/processor.h>
46 #include <linux/uaccess.h>
48 #include <asm/dcr-regs.h>
53 * Lack of dma_unmap_???? calls is intentional.
55 * API-correct usage requires additional support state information to be
56 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
57 * EMAC design (e.g. TX buffer passed from network stack can be split into
58 * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
59 * maintaining such information will add additional overhead.
60 * Current DMA API implementation for 4xx processors only ensures cache coherency
61 * and dma_unmap_???? routines are empty and are likely to stay this way.
62 * I decided to omit dma_unmap_??? calls because I don't want to add additional
63 * complexity just for the sake of following some abstract API, when it doesn't
64 * add any real benefit to the driver. I understand that this decision maybe
65 * controversial, but I really tried to make code API-correct and efficient
66 * at the same time and didn't come up with code I liked :(. --ebs
69 #define DRV_NAME "emac"
70 #define DRV_VERSION "3.54"
71 #define DRV_DESC "PPC 4xx OCP EMAC driver"
73 MODULE_DESCRIPTION(DRV_DESC);
75 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
76 MODULE_LICENSE("GPL");
78 /* minimum number of free TX descriptors required to wake up TX process */
79 #define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4)
81 /* If packet size is less than this number, we allocate small skb and copy packet
82 * contents into it instead of just sending original big skb up
84 #define EMAC_RX_COPY_THRESH CONFIG_IBM_EMAC_RX_COPY_THRESHOLD
86 /* Since multiple EMACs share MDIO lines in various ways, we need
87 * to avoid re-using the same PHY ID in cases where the arch didn't
88 * setup precise phy_map entries
90 * XXX This is something that needs to be reworked as we can have multiple
91 * EMAC "sets" (multiple ASICs containing several EMACs) though we can
92 * probably require in that case to have explicit PHY IDs in the device-tree
94 static u32 busy_phy_map;
95 static DEFINE_MUTEX(emac_phy_map_lock);
97 /* This is the wait queue used to wait on any event related to probe, that
98 * is discovery of MALs, other EMACs, ZMII/RGMIIs, etc...
100 static DECLARE_WAIT_QUEUE_HEAD(emac_probe_wait);
102 /* Having stable interface names is a doomed idea. However, it would be nice
103 * if we didn't have completely random interface names at boot too :-) It's
104 * just a matter of making everybody's life easier. Since we are doing
105 * threaded probing, it's a bit harder though. The base idea here is that
106 * we make up a list of all emacs in the device-tree before we register the
107 * driver. Every emac will then wait for the previous one in the list to
108 * initialize before itself. We should also keep that list ordered by
110 * That list is only 4 entries long, meaning that additional EMACs don't
111 * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased.
114 #define EMAC_BOOT_LIST_SIZE 4
115 static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE];
117 /* How long should I wait for dependent devices ? */
118 #define EMAC_PROBE_DEP_TIMEOUT (HZ * 5)
120 /* I don't want to litter system log with timeout errors
121 * when we have brain-damaged PHY.
123 static inline void emac_report_timeout_error(struct emac_instance *dev,
126 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
127 EMAC_FTR_460EX_PHY_CLK_FIX |
128 EMAC_FTR_440EP_PHY_CLK_FIX))
129 DBG(dev, "%s" NL, error);
130 else if (net_ratelimit())
131 printk(KERN_ERR "%pOF: %s\n", dev->ofdev->dev.of_node, error);
134 /* EMAC PHY clock workaround:
135 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX,
136 * which allows controlling each EMAC clock
138 static inline void emac_rx_clk_tx(struct emac_instance *dev)
140 #ifdef CONFIG_PPC_DCR_NATIVE
141 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
142 dcri_clrset(SDR0, SDR0_MFR,
143 0, SDR0_MFR_ECS >> dev->cell_index);
147 static inline void emac_rx_clk_default(struct emac_instance *dev)
149 #ifdef CONFIG_PPC_DCR_NATIVE
150 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
151 dcri_clrset(SDR0, SDR0_MFR,
152 SDR0_MFR_ECS >> dev->cell_index, 0);
156 /* PHY polling intervals */
157 #define PHY_POLL_LINK_ON HZ
158 #define PHY_POLL_LINK_OFF (HZ / 5)
160 /* Graceful stop timeouts in us.
161 * We should allow up to 1 frame time (full-duplex, ignoring collisions)
163 #define STOP_TIMEOUT_10 1230
164 #define STOP_TIMEOUT_100 124
165 #define STOP_TIMEOUT_1000 13
166 #define STOP_TIMEOUT_1000_JUMBO 73
168 static unsigned char default_mcast_addr[] = {
169 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01
172 /* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
173 static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
174 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
175 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
176 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
177 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
178 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
179 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
180 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
181 "rx_bad_packet", "rx_runt_packet", "rx_short_event",
182 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
183 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
184 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
185 "tx_bd_excessive_collisions", "tx_bd_late_collision",
186 "tx_bd_multple_collisions", "tx_bd_single_collision",
187 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
191 static irqreturn_t emac_irq(int irq, void *dev_instance);
192 static void emac_clean_tx_ring(struct emac_instance *dev);
193 static void __emac_set_multicast_list(struct emac_instance *dev);
195 static inline int emac_phy_supports_gige(int phy_mode)
197 return phy_interface_mode_is_rgmii(phy_mode) ||
198 phy_mode == PHY_INTERFACE_MODE_GMII ||
199 phy_mode == PHY_INTERFACE_MODE_SGMII ||
200 phy_mode == PHY_INTERFACE_MODE_TBI ||
201 phy_mode == PHY_INTERFACE_MODE_RTBI;
204 static inline int emac_phy_gpcs(int phy_mode)
206 return phy_mode == PHY_INTERFACE_MODE_SGMII ||
207 phy_mode == PHY_INTERFACE_MODE_TBI ||
208 phy_mode == PHY_INTERFACE_MODE_RTBI;
211 static inline void emac_tx_enable(struct emac_instance *dev)
213 struct emac_regs __iomem *p = dev->emacp;
216 DBG(dev, "tx_enable" NL);
218 r = in_be32(&p->mr0);
219 if (!(r & EMAC_MR0_TXE))
220 out_be32(&p->mr0, r | EMAC_MR0_TXE);
223 static void emac_tx_disable(struct emac_instance *dev)
225 struct emac_regs __iomem *p = dev->emacp;
228 DBG(dev, "tx_disable" NL);
230 r = in_be32(&p->mr0);
231 if (r & EMAC_MR0_TXE) {
232 int n = dev->stop_timeout;
233 out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
234 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
239 emac_report_timeout_error(dev, "TX disable timeout");
243 static void emac_rx_enable(struct emac_instance *dev)
245 struct emac_regs __iomem *p = dev->emacp;
248 if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags)))
251 DBG(dev, "rx_enable" NL);
253 r = in_be32(&p->mr0);
254 if (!(r & EMAC_MR0_RXE)) {
255 if (unlikely(!(r & EMAC_MR0_RXI))) {
256 /* Wait if previous async disable is still in progress */
257 int n = dev->stop_timeout;
258 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
263 emac_report_timeout_error(dev,
264 "RX disable timeout");
266 out_be32(&p->mr0, r | EMAC_MR0_RXE);
272 static void emac_rx_disable(struct emac_instance *dev)
274 struct emac_regs __iomem *p = dev->emacp;
277 DBG(dev, "rx_disable" NL);
279 r = in_be32(&p->mr0);
280 if (r & EMAC_MR0_RXE) {
281 int n = dev->stop_timeout;
282 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
283 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
288 emac_report_timeout_error(dev, "RX disable timeout");
292 static inline void emac_netif_stop(struct emac_instance *dev)
294 netif_tx_lock_bh(dev->ndev);
295 netif_addr_lock(dev->ndev);
297 netif_addr_unlock(dev->ndev);
298 netif_tx_unlock_bh(dev->ndev);
299 netif_trans_update(dev->ndev); /* prevent tx timeout */
300 mal_poll_disable(dev->mal, &dev->commac);
301 netif_tx_disable(dev->ndev);
304 static inline void emac_netif_start(struct emac_instance *dev)
306 netif_tx_lock_bh(dev->ndev);
307 netif_addr_lock(dev->ndev);
309 if (dev->mcast_pending && netif_running(dev->ndev))
310 __emac_set_multicast_list(dev);
311 netif_addr_unlock(dev->ndev);
312 netif_tx_unlock_bh(dev->ndev);
314 netif_wake_queue(dev->ndev);
316 /* NOTE: unconditional netif_wake_queue is only appropriate
317 * so long as all callers are assured to have free tx slots
318 * (taken from tg3... though the case where that is wrong is
319 * not terribly harmful)
321 mal_poll_enable(dev->mal, &dev->commac);
324 static inline void emac_rx_disable_async(struct emac_instance *dev)
326 struct emac_regs __iomem *p = dev->emacp;
329 DBG(dev, "rx_disable_async" NL);
331 r = in_be32(&p->mr0);
332 if (r & EMAC_MR0_RXE)
333 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
336 static int emac_reset(struct emac_instance *dev)
338 struct emac_regs __iomem *p = dev->emacp;
340 bool __maybe_unused try_internal_clock = false;
342 DBG(dev, "reset" NL);
344 if (!dev->reset_failed) {
345 /* 40x erratum suggests stopping RX channel before reset,
348 emac_rx_disable(dev);
349 emac_tx_disable(dev);
352 #ifdef CONFIG_PPC_DCR_NATIVE
355 * PPC460EX/GT Embedded Processor Advanced User's Manual
356 * section 28.10.1 Mode Register 0 (EMACx_MR0) states:
357 * Note: The PHY must provide a TX Clk in order to perform a soft reset
358 * of the EMAC. If none is present, select the internal clock
359 * (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1).
360 * After a soft reset, select the external clock.
362 * The AR8035-A PHY Meraki MR24 does not provide a TX Clk if the
363 * ethernet cable is not attached. This causes the reset to timeout
364 * and the PHY detection code in emac_init_phy() is unable to
365 * communicate and detect the AR8035-A PHY. As a result, the emac
366 * driver bails out early and the user has no ethernet.
367 * In order to stay compatible with existing configurations, the
368 * driver will temporarily switch to the internal clock, after
369 * the first reset fails.
371 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
372 if (try_internal_clock || (dev->phy_address == 0xffffffff &&
373 dev->phy_map == 0xffffffff)) {
374 /* No PHY: select internal loop clock before reset */
375 dcri_clrset(SDR0, SDR0_ETH_CFG,
376 0, SDR0_ETH_CFG_ECS << dev->cell_index);
378 /* PHY present: select external clock before reset */
379 dcri_clrset(SDR0, SDR0_ETH_CFG,
380 SDR0_ETH_CFG_ECS << dev->cell_index, 0);
385 out_be32(&p->mr0, EMAC_MR0_SRST);
386 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
389 #ifdef CONFIG_PPC_DCR_NATIVE
390 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
391 if (!n && !try_internal_clock) {
392 /* first attempt has timed out. */
394 try_internal_clock = true;
398 if (try_internal_clock || (dev->phy_address == 0xffffffff &&
399 dev->phy_map == 0xffffffff)) {
400 /* No PHY: restore external clock source after reset */
401 dcri_clrset(SDR0, SDR0_ETH_CFG,
402 SDR0_ETH_CFG_ECS << dev->cell_index, 0);
408 dev->reset_failed = 0;
411 emac_report_timeout_error(dev, "reset timeout");
412 dev->reset_failed = 1;
417 static void emac_hash_mc(struct emac_instance *dev)
419 const int regs = EMAC_XAHT_REGS(dev);
420 u32 *gaht_base = emac_gaht_base(dev);
421 u32 gaht_temp[EMAC_XAHT_MAX_REGS];
422 struct netdev_hw_addr *ha;
425 DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev));
427 memset(gaht_temp, 0, sizeof (gaht_temp));
429 netdev_for_each_mc_addr(ha, dev->ndev) {
431 DBG2(dev, "mc %pM" NL, ha->addr);
433 slot = EMAC_XAHT_CRC_TO_SLOT(dev,
434 ether_crc(ETH_ALEN, ha->addr));
435 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot);
436 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot);
438 gaht_temp[reg] |= mask;
441 for (i = 0; i < regs; i++)
442 out_be32(gaht_base + i, gaht_temp[i]);
445 static inline u32 emac_iff2rmr(struct net_device *ndev)
447 struct emac_instance *dev = netdev_priv(ndev);
450 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE;
452 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
457 if (ndev->flags & IFF_PROMISC)
459 else if (ndev->flags & IFF_ALLMULTI ||
460 (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev)))
462 else if (!netdev_mc_empty(ndev))
465 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
466 r &= ~EMAC4_RMR_MJS_MASK;
467 r |= EMAC4_RMR_MJS(ndev->mtu);
473 static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
475 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT;
477 DBG2(dev, "__emac_calc_base_mr1" NL);
481 ret |= EMAC_MR1_TFS_2K;
484 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
485 dev->ndev->name, tx_size);
490 ret |= EMAC_MR1_RFS_16K;
493 ret |= EMAC_MR1_RFS_4K;
496 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
497 dev->ndev->name, rx_size);
503 static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
505 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR |
506 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000);
508 DBG2(dev, "__emac4_calc_base_mr1" NL);
512 ret |= EMAC4_MR1_TFS_16K;
515 ret |= EMAC4_MR1_TFS_8K;
518 ret |= EMAC4_MR1_TFS_4K;
521 ret |= EMAC4_MR1_TFS_2K;
524 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
525 dev->ndev->name, tx_size);
530 ret |= EMAC4_MR1_RFS_16K;
533 ret |= EMAC4_MR1_RFS_8K;
536 ret |= EMAC4_MR1_RFS_4K;
539 ret |= EMAC4_MR1_RFS_2K;
542 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
543 dev->ndev->name, rx_size);
549 static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
551 return emac_has_feature(dev, EMAC_FTR_EMAC4) ?
552 __emac4_calc_base_mr1(dev, tx_size, rx_size) :
553 __emac_calc_base_mr1(dev, tx_size, rx_size);
556 static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size)
558 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
559 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4;
561 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT;
564 static inline u32 emac_calc_rwmr(struct emac_instance *dev,
565 unsigned int low, unsigned int high)
567 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
568 return (low << 22) | ( (high & 0x3ff) << 6);
570 return (low << 23) | ( (high & 0x1ff) << 7);
573 static int emac_configure(struct emac_instance *dev)
575 struct emac_regs __iomem *p = dev->emacp;
576 struct net_device *ndev = dev->ndev;
577 int tx_size, rx_size, link = netif_carrier_ok(dev->ndev);
580 DBG(dev, "configure" NL);
583 out_be32(&p->mr1, in_be32(&p->mr1)
584 | EMAC_MR1_FDE | EMAC_MR1_ILE);
586 } else if (emac_reset(dev) < 0)
589 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
590 tah_reset(dev->tah_dev);
592 DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n",
593 link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause);
595 /* Default fifo sizes */
596 tx_size = dev->tx_fifo_size;
597 rx_size = dev->rx_fifo_size;
599 /* No link, force loopback */
601 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE;
603 /* Check for full duplex */
604 else if (dev->phy.duplex == DUPLEX_FULL)
605 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
607 /* Adjust fifo sizes, mr1 and timeouts based on link speed */
608 dev->stop_timeout = STOP_TIMEOUT_10;
609 switch (dev->phy.speed) {
611 if (emac_phy_gpcs(dev->phy.mode)) {
612 mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA(
613 (dev->phy.gpcs_address != 0xffffffff) ?
614 dev->phy.gpcs_address : dev->phy.address);
616 /* Put some arbitrary OUI, Manuf & Rev IDs so we can
617 * identify this GPCS PHY later.
619 out_be32(&p->u1.emac4.ipcr, 0xdeadbeef);
621 mr1 |= EMAC_MR1_MF_1000;
623 /* Extended fifo sizes */
624 tx_size = dev->tx_fifo_size_gige;
625 rx_size = dev->rx_fifo_size_gige;
627 if (dev->ndev->mtu > ETH_DATA_LEN) {
628 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
629 mr1 |= EMAC4_MR1_JPSM;
631 mr1 |= EMAC_MR1_JPSM;
632 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
634 dev->stop_timeout = STOP_TIMEOUT_1000;
637 mr1 |= EMAC_MR1_MF_100;
638 dev->stop_timeout = STOP_TIMEOUT_100;
640 default: /* make gcc happy */
644 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
645 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port,
647 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
648 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed);
650 /* on 40x erratum forces us to NOT use integrated flow control,
651 * let's hope it works on 44x ;)
653 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) &&
654 dev->phy.duplex == DUPLEX_FULL) {
656 mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP;
657 else if (dev->phy.asym_pause)
661 /* Add base settings & fifo sizes & program MR1 */
662 mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size);
663 out_be32(&p->mr1, mr1);
665 /* Set individual MAC address */
666 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
667 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
668 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
671 /* VLAN Tag Protocol ID */
672 out_be32(&p->vtpid, 0x8100);
674 /* Receive mode register */
675 r = emac_iff2rmr(ndev);
676 if (r & EMAC_RMR_MAE)
678 out_be32(&p->rmr, r);
680 /* FIFOs thresholds */
681 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
682 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
683 tx_size / 2 / dev->fifo_entry_size);
685 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
686 tx_size / 2 / dev->fifo_entry_size);
687 out_be32(&p->tmr1, r);
688 out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2));
690 /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
691 there should be still enough space in FIFO to allow the our link
692 partner time to process this frame and also time to send PAUSE
695 Here is the worst case scenario for the RX FIFO "headroom"
696 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
698 1) One maximum-length frame on TX 1522 bytes
699 2) One PAUSE frame time 64 bytes
700 3) PAUSE frame decode time allowance 64 bytes
701 4) One maximum-length frame on RX 1522 bytes
702 5) Round-trip propagation delay of the link (100Mb) 15 bytes
706 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
707 low-water mark to RX_FIFO_SIZE / 8 (512 bytes)
709 r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size,
710 rx_size / 4 / dev->fifo_entry_size);
711 out_be32(&p->rwmr, r);
713 /* Set PAUSE timer to the maximum */
714 out_be32(&p->ptr, 0xffff);
717 r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
718 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
719 EMAC_ISR_IRE | EMAC_ISR_TE;
720 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
721 r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE |
723 out_be32(&p->iser, r);
725 /* We need to take GPCS PHY out of isolate mode after EMAC reset */
726 if (emac_phy_gpcs(dev->phy.mode)) {
727 if (dev->phy.gpcs_address != 0xffffffff)
728 emac_mii_reset_gpcs(&dev->phy);
730 emac_mii_reset_phy(&dev->phy);
736 static void emac_reinitialize(struct emac_instance *dev)
738 DBG(dev, "reinitialize" NL);
740 emac_netif_stop(dev);
741 if (!emac_configure(dev)) {
745 emac_netif_start(dev);
748 static void emac_full_tx_reset(struct emac_instance *dev)
750 DBG(dev, "full_tx_reset" NL);
752 emac_tx_disable(dev);
753 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
754 emac_clean_tx_ring(dev);
755 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
759 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
764 static void emac_reset_work(struct work_struct *work)
766 struct emac_instance *dev = container_of(work, struct emac_instance, reset_work);
768 DBG(dev, "reset_work" NL);
770 mutex_lock(&dev->link_lock);
772 emac_netif_stop(dev);
773 emac_full_tx_reset(dev);
774 emac_netif_start(dev);
776 mutex_unlock(&dev->link_lock);
779 static void emac_tx_timeout(struct net_device *ndev)
781 struct emac_instance *dev = netdev_priv(ndev);
783 DBG(dev, "tx_timeout" NL);
785 schedule_work(&dev->reset_work);
789 static inline int emac_phy_done(struct emac_instance *dev, u32 stacr)
791 int done = !!(stacr & EMAC_STACR_OC);
793 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
799 static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg)
801 struct emac_regs __iomem *p = dev->emacp;
803 int n, err = -ETIMEDOUT;
805 mutex_lock(&dev->mdio_lock);
807 DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg);
809 /* Enable proper MDIO port */
810 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
811 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
812 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
813 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
815 /* Wait for management interface to become idle */
817 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
820 DBG2(dev, " -> timeout wait idle\n");
825 /* Issue read command */
826 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
827 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
829 r = EMAC_STACR_BASE(dev->opb_bus_freq);
830 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
832 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
833 r |= EMACX_STACR_STAC_READ;
835 r |= EMAC_STACR_STAC_READ;
836 r |= (reg & EMAC_STACR_PRA_MASK)
837 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT);
838 out_be32(&p->stacr, r);
840 /* Wait for read to complete */
842 while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) {
845 DBG2(dev, " -> timeout wait complete\n");
850 if (unlikely(r & EMAC_STACR_PHYE)) {
851 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg);
856 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
858 DBG2(dev, "mdio_read -> %04x" NL, r);
861 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
862 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
863 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
864 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
865 mutex_unlock(&dev->mdio_lock);
867 return err == 0 ? r : err;
870 static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg,
873 struct emac_regs __iomem *p = dev->emacp;
875 int n, err = -ETIMEDOUT;
877 mutex_lock(&dev->mdio_lock);
879 DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val);
881 /* Enable proper MDIO port */
882 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
883 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
884 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
885 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
887 /* Wait for management interface to be idle */
889 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
892 DBG2(dev, " -> timeout wait idle\n");
897 /* Issue write command */
898 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
899 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
901 r = EMAC_STACR_BASE(dev->opb_bus_freq);
902 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
904 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
905 r |= EMACX_STACR_STAC_WRITE;
907 r |= EMAC_STACR_STAC_WRITE;
908 r |= (reg & EMAC_STACR_PRA_MASK) |
909 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
910 (val << EMAC_STACR_PHYD_SHIFT);
911 out_be32(&p->stacr, r);
913 /* Wait for write to complete */
915 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
918 DBG2(dev, " -> timeout wait complete\n");
924 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
925 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
926 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
927 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
928 mutex_unlock(&dev->mdio_lock);
931 static int emac_mdio_read(struct net_device *ndev, int id, int reg)
933 struct emac_instance *dev = netdev_priv(ndev);
936 res = __emac_mdio_read((dev->mdio_instance &&
937 dev->phy.gpcs_address != id) ?
938 dev->mdio_instance : dev,
943 static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
945 struct emac_instance *dev = netdev_priv(ndev);
947 __emac_mdio_write((dev->mdio_instance &&
948 dev->phy.gpcs_address != id) ?
949 dev->mdio_instance : dev,
950 (u8) id, (u8) reg, (u16) val);
954 static void __emac_set_multicast_list(struct emac_instance *dev)
956 struct emac_regs __iomem *p = dev->emacp;
957 u32 rmr = emac_iff2rmr(dev->ndev);
959 DBG(dev, "__multicast %08x" NL, rmr);
961 /* I decided to relax register access rules here to avoid
964 * There is a real problem with EMAC4 core if we use MWSW_001 bit
965 * in MR1 register and do a full EMAC reset.
966 * One TX BD status update is delayed and, after EMAC reset, it
967 * never happens, resulting in TX hung (it'll be recovered by TX
968 * timeout handler eventually, but this is just gross).
969 * So we either have to do full TX reset or try to cheat here :)
971 * The only required change is to RX mode register, so I *think* all
972 * we need is just to stop RX channel. This seems to work on all
975 * If we need the full reset, we might just trigger the workqueue
976 * and do it async... a bit nasty but should work --BenH
978 dev->mcast_pending = 0;
979 emac_rx_disable(dev);
980 if (rmr & EMAC_RMR_MAE)
982 out_be32(&p->rmr, rmr);
987 static void emac_set_multicast_list(struct net_device *ndev)
989 struct emac_instance *dev = netdev_priv(ndev);
991 DBG(dev, "multicast" NL);
993 BUG_ON(!netif_running(dev->ndev));
996 dev->mcast_pending = 1;
1000 mutex_lock(&dev->link_lock);
1001 __emac_set_multicast_list(dev);
1002 mutex_unlock(&dev->link_lock);
1005 static int emac_set_mac_address(struct net_device *ndev, void *sa)
1007 struct emac_instance *dev = netdev_priv(ndev);
1008 struct sockaddr *addr = sa;
1009 struct emac_regs __iomem *p = dev->emacp;
1011 if (!is_valid_ether_addr(addr->sa_data))
1012 return -EADDRNOTAVAIL;
1014 mutex_lock(&dev->link_lock);
1016 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1018 emac_rx_disable(dev);
1019 emac_tx_disable(dev);
1020 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
1021 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
1022 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
1024 emac_tx_enable(dev);
1025 emac_rx_enable(dev);
1027 mutex_unlock(&dev->link_lock);
1032 static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
1034 int rx_sync_size = emac_rx_sync_size(new_mtu);
1035 int rx_skb_size = emac_rx_skb_size(new_mtu);
1037 int mr1_jumbo_bit_change = 0;
1039 mutex_lock(&dev->link_lock);
1040 emac_netif_stop(dev);
1041 emac_rx_disable(dev);
1042 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1044 if (dev->rx_sg_skb) {
1045 ++dev->estats.rx_dropped_resize;
1046 dev_kfree_skb(dev->rx_sg_skb);
1047 dev->rx_sg_skb = NULL;
1050 /* Make a first pass over RX ring and mark BDs ready, dropping
1051 * non-processed packets on the way. We need this as a separate pass
1052 * to simplify error recovery in the case of allocation failure later.
1054 for (i = 0; i < NUM_RX_BUFF; ++i) {
1055 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
1056 ++dev->estats.rx_dropped_resize;
1058 dev->rx_desc[i].data_len = 0;
1059 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
1060 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1063 /* Reallocate RX ring only if bigger skb buffers are required */
1064 if (rx_skb_size <= dev->rx_skb_size)
1067 /* Second pass, allocate new skbs */
1068 for (i = 0; i < NUM_RX_BUFF; ++i) {
1069 struct sk_buff *skb;
1071 skb = netdev_alloc_skb_ip_align(dev->ndev, rx_skb_size);
1077 BUG_ON(!dev->rx_skb[i]);
1078 dev_kfree_skb(dev->rx_skb[i]);
1080 dev->rx_desc[i].data_ptr =
1081 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1082 rx_sync_size, DMA_FROM_DEVICE)
1084 dev->rx_skb[i] = skb;
1087 /* Check if we need to change "Jumbo" bit in MR1 */
1088 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
1089 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ||
1090 (dev->ndev->mtu > ETH_DATA_LEN);
1092 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ^
1093 (dev->ndev->mtu > ETH_DATA_LEN);
1096 if (mr1_jumbo_bit_change) {
1097 /* This is to prevent starting RX channel in emac_rx_enable() */
1098 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1100 dev->ndev->mtu = new_mtu;
1101 emac_full_tx_reset(dev);
1104 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu));
1107 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1109 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1110 emac_rx_enable(dev);
1111 emac_netif_start(dev);
1112 mutex_unlock(&dev->link_lock);
1117 /* Process ctx, rtnl_lock semaphore */
1118 static int emac_change_mtu(struct net_device *ndev, int new_mtu)
1120 struct emac_instance *dev = netdev_priv(ndev);
1123 DBG(dev, "change_mtu(%d)" NL, new_mtu);
1125 if (netif_running(ndev)) {
1126 /* Check if we really need to reinitialize RX ring */
1127 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
1128 ret = emac_resize_rx_ring(dev, new_mtu);
1132 ndev->mtu = new_mtu;
1133 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
1134 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
1140 static void emac_clean_tx_ring(struct emac_instance *dev)
1144 for (i = 0; i < NUM_TX_BUFF; ++i) {
1145 if (dev->tx_skb[i]) {
1146 dev_kfree_skb(dev->tx_skb[i]);
1147 dev->tx_skb[i] = NULL;
1148 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
1149 ++dev->estats.tx_dropped;
1151 dev->tx_desc[i].ctrl = 0;
1152 dev->tx_desc[i].data_ptr = 0;
1156 static void emac_clean_rx_ring(struct emac_instance *dev)
1160 for (i = 0; i < NUM_RX_BUFF; ++i)
1161 if (dev->rx_skb[i]) {
1162 dev->rx_desc[i].ctrl = 0;
1163 dev_kfree_skb(dev->rx_skb[i]);
1164 dev->rx_skb[i] = NULL;
1165 dev->rx_desc[i].data_ptr = 0;
1168 if (dev->rx_sg_skb) {
1169 dev_kfree_skb(dev->rx_sg_skb);
1170 dev->rx_sg_skb = NULL;
1175 __emac_prepare_rx_skb(struct sk_buff *skb, struct emac_instance *dev, int slot)
1180 dev->rx_skb[slot] = skb;
1181 dev->rx_desc[slot].data_len = 0;
1183 dev->rx_desc[slot].data_ptr =
1184 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1185 dev->rx_sync_size, DMA_FROM_DEVICE) + NET_IP_ALIGN;
1187 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1188 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1194 emac_alloc_rx_skb(struct emac_instance *dev, int slot)
1196 struct sk_buff *skb;
1198 skb = __netdev_alloc_skb_ip_align(dev->ndev, dev->rx_skb_size,
1201 return __emac_prepare_rx_skb(skb, dev, slot);
1205 emac_alloc_rx_skb_napi(struct emac_instance *dev, int slot)
1207 struct sk_buff *skb;
1209 skb = napi_alloc_skb(&dev->mal->napi, dev->rx_skb_size);
1211 return __emac_prepare_rx_skb(skb, dev, slot);
1214 static void emac_print_link_status(struct emac_instance *dev)
1216 if (netif_carrier_ok(dev->ndev))
1217 printk(KERN_INFO "%s: link is up, %d %s%s\n",
1218 dev->ndev->name, dev->phy.speed,
1219 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
1220 dev->phy.pause ? ", pause enabled" :
1221 dev->phy.asym_pause ? ", asymmetric pause enabled" : "");
1223 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
1226 /* Process ctx, rtnl_lock semaphore */
1227 static int emac_open(struct net_device *ndev)
1229 struct emac_instance *dev = netdev_priv(ndev);
1232 DBG(dev, "open" NL);
1234 /* Setup error IRQ handler */
1235 err = request_irq(dev->emac_irq, emac_irq, 0, "EMAC", dev);
1237 printk(KERN_ERR "%s: failed to request IRQ %d\n",
1238 ndev->name, dev->emac_irq);
1242 /* Allocate RX ring */
1243 for (i = 0; i < NUM_RX_BUFF; ++i)
1244 if (emac_alloc_rx_skb(dev, i)) {
1245 printk(KERN_ERR "%s: failed to allocate RX ring\n",
1250 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0;
1251 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1252 dev->rx_sg_skb = NULL;
1254 mutex_lock(&dev->link_lock);
1257 /* Start PHY polling now.
1259 if (dev->phy.address >= 0) {
1260 int link_poll_interval;
1261 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1262 dev->phy.def->ops->read_link(&dev->phy);
1263 emac_rx_clk_default(dev);
1264 netif_carrier_on(dev->ndev);
1265 link_poll_interval = PHY_POLL_LINK_ON;
1267 emac_rx_clk_tx(dev);
1268 netif_carrier_off(dev->ndev);
1269 link_poll_interval = PHY_POLL_LINK_OFF;
1271 dev->link_polling = 1;
1273 schedule_delayed_work(&dev->link_work, link_poll_interval);
1274 emac_print_link_status(dev);
1276 netif_carrier_on(dev->ndev);
1278 /* Required for Pause packet support in EMAC */
1279 dev_mc_add_global(ndev, default_mcast_addr);
1281 emac_configure(dev);
1282 mal_poll_add(dev->mal, &dev->commac);
1283 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
1284 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu));
1285 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1286 emac_tx_enable(dev);
1287 emac_rx_enable(dev);
1288 emac_netif_start(dev);
1290 mutex_unlock(&dev->link_lock);
1294 emac_clean_rx_ring(dev);
1295 free_irq(dev->emac_irq, dev);
1302 static int emac_link_differs(struct emac_instance *dev)
1304 u32 r = in_be32(&dev->emacp->mr1);
1306 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
1307 int speed, pause, asym_pause;
1309 if (r & EMAC_MR1_MF_1000)
1311 else if (r & EMAC_MR1_MF_100)
1316 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
1317 case (EMAC_MR1_EIFC | EMAC_MR1_APP):
1326 pause = asym_pause = 0;
1328 return speed != dev->phy.speed || duplex != dev->phy.duplex ||
1329 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
1333 static void emac_link_timer(struct work_struct *work)
1335 struct emac_instance *dev =
1336 container_of(to_delayed_work(work),
1337 struct emac_instance, link_work);
1338 int link_poll_interval;
1340 mutex_lock(&dev->link_lock);
1341 DBG2(dev, "link timer" NL);
1346 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1347 if (!netif_carrier_ok(dev->ndev)) {
1348 emac_rx_clk_default(dev);
1349 /* Get new link parameters */
1350 dev->phy.def->ops->read_link(&dev->phy);
1352 netif_carrier_on(dev->ndev);
1353 emac_netif_stop(dev);
1354 emac_full_tx_reset(dev);
1355 emac_netif_start(dev);
1356 emac_print_link_status(dev);
1358 link_poll_interval = PHY_POLL_LINK_ON;
1360 if (netif_carrier_ok(dev->ndev)) {
1361 emac_rx_clk_tx(dev);
1362 netif_carrier_off(dev->ndev);
1363 netif_tx_disable(dev->ndev);
1364 emac_reinitialize(dev);
1365 emac_print_link_status(dev);
1367 link_poll_interval = PHY_POLL_LINK_OFF;
1369 schedule_delayed_work(&dev->link_work, link_poll_interval);
1371 mutex_unlock(&dev->link_lock);
1374 static void emac_force_link_update(struct emac_instance *dev)
1376 netif_carrier_off(dev->ndev);
1378 if (dev->link_polling) {
1379 cancel_delayed_work_sync(&dev->link_work);
1380 if (dev->link_polling)
1381 schedule_delayed_work(&dev->link_work, PHY_POLL_LINK_OFF);
1385 /* Process ctx, rtnl_lock semaphore */
1386 static int emac_close(struct net_device *ndev)
1388 struct emac_instance *dev = netdev_priv(ndev);
1390 DBG(dev, "close" NL);
1392 if (dev->phy.address >= 0) {
1393 dev->link_polling = 0;
1394 cancel_delayed_work_sync(&dev->link_work);
1396 mutex_lock(&dev->link_lock);
1397 emac_netif_stop(dev);
1399 mutex_unlock(&dev->link_lock);
1401 emac_rx_disable(dev);
1402 emac_tx_disable(dev);
1403 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1404 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
1405 mal_poll_del(dev->mal, &dev->commac);
1407 emac_clean_tx_ring(dev);
1408 emac_clean_rx_ring(dev);
1410 free_irq(dev->emac_irq, dev);
1412 netif_carrier_off(ndev);
1417 static inline u16 emac_tx_csum(struct emac_instance *dev,
1418 struct sk_buff *skb)
1420 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
1421 (skb->ip_summed == CHECKSUM_PARTIAL)) {
1422 ++dev->stats.tx_packets_csum;
1423 return EMAC_TX_CTRL_TAH_CSUM;
1428 static inline netdev_tx_t emac_xmit_finish(struct emac_instance *dev, int len)
1430 struct emac_regs __iomem *p = dev->emacp;
1431 struct net_device *ndev = dev->ndev;
1433 /* Send the packet out. If the if makes a significant perf
1434 * difference, then we can store the TMR0 value in "dev"
1437 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
1438 out_be32(&p->tmr0, EMAC4_TMR0_XMIT);
1440 out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1442 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1443 netif_stop_queue(ndev);
1444 DBG2(dev, "stopped TX queue" NL);
1447 netif_trans_update(ndev);
1448 ++dev->stats.tx_packets;
1449 dev->stats.tx_bytes += len;
1451 return NETDEV_TX_OK;
1455 static netdev_tx_t emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1457 struct emac_instance *dev = netdev_priv(ndev);
1458 unsigned int len = skb->len;
1461 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1462 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1464 slot = dev->tx_slot++;
1465 if (dev->tx_slot == NUM_TX_BUFF) {
1467 ctrl |= MAL_TX_CTRL_WRAP;
1470 DBG2(dev, "xmit(%u) %d" NL, len, slot);
1472 dev->tx_skb[slot] = skb;
1473 dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev,
1476 dev->tx_desc[slot].data_len = (u16) len;
1478 dev->tx_desc[slot].ctrl = ctrl;
1480 return emac_xmit_finish(dev, len);
1483 static inline int emac_xmit_split(struct emac_instance *dev, int slot,
1484 u32 pd, int len, int last, u16 base_ctrl)
1487 u16 ctrl = base_ctrl;
1488 int chunk = min(len, MAL_MAX_TX_SIZE);
1491 slot = (slot + 1) % NUM_TX_BUFF;
1494 ctrl |= MAL_TX_CTRL_LAST;
1495 if (slot == NUM_TX_BUFF - 1)
1496 ctrl |= MAL_TX_CTRL_WRAP;
1498 dev->tx_skb[slot] = NULL;
1499 dev->tx_desc[slot].data_ptr = pd;
1500 dev->tx_desc[slot].data_len = (u16) chunk;
1501 dev->tx_desc[slot].ctrl = ctrl;
1512 /* Tx lock BH disabled (SG version for TAH equipped EMACs) */
1514 emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1516 struct emac_instance *dev = netdev_priv(ndev);
1517 int nr_frags = skb_shinfo(skb)->nr_frags;
1518 int len = skb->len, chunk;
1523 /* This is common "fast" path */
1524 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1525 return emac_start_xmit(skb, ndev);
1527 len -= skb->data_len;
1529 /* Note, this is only an *estimation*, we can still run out of empty
1530 * slots because of the additional fragmentation into
1531 * MAL_MAX_TX_SIZE-sized chunks
1533 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1536 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1537 emac_tx_csum(dev, skb);
1538 slot = dev->tx_slot;
1541 dev->tx_skb[slot] = NULL;
1542 chunk = min(len, MAL_MAX_TX_SIZE);
1543 dev->tx_desc[slot].data_ptr = pd =
1544 dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE);
1545 dev->tx_desc[slot].data_len = (u16) chunk;
1548 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1551 for (i = 0; i < nr_frags; ++i) {
1552 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1553 len = skb_frag_size(frag);
1555 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1558 pd = skb_frag_dma_map(&dev->ofdev->dev, frag, 0, len,
1561 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1565 DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot);
1567 /* Attach skb to the last slot so we don't release it too early */
1568 dev->tx_skb[slot] = skb;
1570 /* Send the packet out */
1571 if (dev->tx_slot == NUM_TX_BUFF - 1)
1572 ctrl |= MAL_TX_CTRL_WRAP;
1574 dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1575 dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1577 return emac_xmit_finish(dev, skb->len);
1580 /* Well, too bad. Our previous estimation was overly optimistic.
1583 while (slot != dev->tx_slot) {
1584 dev->tx_desc[slot].ctrl = 0;
1587 slot = NUM_TX_BUFF - 1;
1589 ++dev->estats.tx_undo;
1592 netif_stop_queue(ndev);
1593 DBG2(dev, "stopped TX queue" NL);
1594 return NETDEV_TX_BUSY;
1598 static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl)
1600 struct emac_error_stats *st = &dev->estats;
1602 DBG(dev, "BD TX error %04x" NL, ctrl);
1605 if (ctrl & EMAC_TX_ST_BFCS)
1606 ++st->tx_bd_bad_fcs;
1607 if (ctrl & EMAC_TX_ST_LCS)
1608 ++st->tx_bd_carrier_loss;
1609 if (ctrl & EMAC_TX_ST_ED)
1610 ++st->tx_bd_excessive_deferral;
1611 if (ctrl & EMAC_TX_ST_EC)
1612 ++st->tx_bd_excessive_collisions;
1613 if (ctrl & EMAC_TX_ST_LC)
1614 ++st->tx_bd_late_collision;
1615 if (ctrl & EMAC_TX_ST_MC)
1616 ++st->tx_bd_multple_collisions;
1617 if (ctrl & EMAC_TX_ST_SC)
1618 ++st->tx_bd_single_collision;
1619 if (ctrl & EMAC_TX_ST_UR)
1620 ++st->tx_bd_underrun;
1621 if (ctrl & EMAC_TX_ST_SQE)
1625 static void emac_poll_tx(void *param)
1627 struct emac_instance *dev = param;
1630 DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot);
1632 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
1633 bad_mask = EMAC_IS_BAD_TX_TAH;
1635 bad_mask = EMAC_IS_BAD_TX;
1637 netif_tx_lock_bh(dev->ndev);
1640 int slot = dev->ack_slot, n = 0;
1642 ctrl = dev->tx_desc[slot].ctrl;
1643 if (!(ctrl & MAL_TX_CTRL_READY)) {
1644 struct sk_buff *skb = dev->tx_skb[slot];
1649 dev->tx_skb[slot] = NULL;
1651 slot = (slot + 1) % NUM_TX_BUFF;
1653 if (unlikely(ctrl & bad_mask))
1654 emac_parse_tx_error(dev, ctrl);
1660 dev->ack_slot = slot;
1661 if (netif_queue_stopped(dev->ndev) &&
1662 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1663 netif_wake_queue(dev->ndev);
1665 DBG2(dev, "tx %d pkts" NL, n);
1668 netif_tx_unlock_bh(dev->ndev);
1671 static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot,
1674 struct sk_buff *skb = dev->rx_skb[slot];
1676 DBG2(dev, "recycle %d %d" NL, slot, len);
1679 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1680 SKB_DATA_ALIGN(len + NET_IP_ALIGN),
1683 dev->rx_desc[slot].data_len = 0;
1685 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1686 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1689 static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl)
1691 struct emac_error_stats *st = &dev->estats;
1693 DBG(dev, "BD RX error %04x" NL, ctrl);
1696 if (ctrl & EMAC_RX_ST_OE)
1697 ++st->rx_bd_overrun;
1698 if (ctrl & EMAC_RX_ST_BP)
1699 ++st->rx_bd_bad_packet;
1700 if (ctrl & EMAC_RX_ST_RP)
1701 ++st->rx_bd_runt_packet;
1702 if (ctrl & EMAC_RX_ST_SE)
1703 ++st->rx_bd_short_event;
1704 if (ctrl & EMAC_RX_ST_AE)
1705 ++st->rx_bd_alignment_error;
1706 if (ctrl & EMAC_RX_ST_BFCS)
1707 ++st->rx_bd_bad_fcs;
1708 if (ctrl & EMAC_RX_ST_PTL)
1709 ++st->rx_bd_packet_too_long;
1710 if (ctrl & EMAC_RX_ST_ORE)
1711 ++st->rx_bd_out_of_range;
1712 if (ctrl & EMAC_RX_ST_IRE)
1713 ++st->rx_bd_in_range;
1716 static inline void emac_rx_csum(struct emac_instance *dev,
1717 struct sk_buff *skb, u16 ctrl)
1719 #ifdef CONFIG_IBM_EMAC_TAH
1720 if (!ctrl && dev->tah_dev) {
1721 skb->ip_summed = CHECKSUM_UNNECESSARY;
1722 ++dev->stats.rx_packets_csum;
1727 static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
1729 if (likely(dev->rx_sg_skb != NULL)) {
1730 int len = dev->rx_desc[slot].data_len;
1731 int tot_len = dev->rx_sg_skb->len + len;
1733 if (unlikely(tot_len + NET_IP_ALIGN > dev->rx_skb_size)) {
1734 ++dev->estats.rx_dropped_mtu;
1735 dev_kfree_skb(dev->rx_sg_skb);
1736 dev->rx_sg_skb = NULL;
1738 memcpy(skb_tail_pointer(dev->rx_sg_skb),
1739 dev->rx_skb[slot]->data, len);
1740 skb_put(dev->rx_sg_skb, len);
1741 emac_recycle_rx_skb(dev, slot, len);
1745 emac_recycle_rx_skb(dev, slot, 0);
1749 /* NAPI poll context */
1750 static int emac_poll_rx(void *param, int budget)
1752 struct emac_instance *dev = param;
1753 int slot = dev->rx_slot, received = 0;
1755 DBG2(dev, "poll_rx(%d)" NL, budget);
1758 while (budget > 0) {
1760 struct sk_buff *skb;
1761 u16 ctrl = dev->rx_desc[slot].ctrl;
1763 if (ctrl & MAL_RX_CTRL_EMPTY)
1766 skb = dev->rx_skb[slot];
1768 len = dev->rx_desc[slot].data_len;
1770 if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1773 ctrl &= EMAC_BAD_RX_MASK;
1774 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1775 emac_parse_rx_error(dev, ctrl);
1776 ++dev->estats.rx_dropped_error;
1777 emac_recycle_rx_skb(dev, slot, 0);
1782 if (len < ETH_HLEN) {
1783 ++dev->estats.rx_dropped_stack;
1784 emac_recycle_rx_skb(dev, slot, len);
1788 if (len && len < EMAC_RX_COPY_THRESH) {
1789 struct sk_buff *copy_skb;
1791 copy_skb = napi_alloc_skb(&dev->mal->napi, len);
1792 if (unlikely(!copy_skb))
1795 memcpy(copy_skb->data - NET_IP_ALIGN,
1796 skb->data - NET_IP_ALIGN,
1797 len + NET_IP_ALIGN);
1798 emac_recycle_rx_skb(dev, slot, len);
1800 } else if (unlikely(emac_alloc_rx_skb_napi(dev, slot)))
1805 skb->protocol = eth_type_trans(skb, dev->ndev);
1806 emac_rx_csum(dev, skb, ctrl);
1808 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
1809 ++dev->estats.rx_dropped_stack;
1811 ++dev->stats.rx_packets;
1813 dev->stats.rx_bytes += len;
1814 slot = (slot + 1) % NUM_RX_BUFF;
1819 if (ctrl & MAL_RX_CTRL_FIRST) {
1820 BUG_ON(dev->rx_sg_skb);
1821 if (unlikely(emac_alloc_rx_skb_napi(dev, slot))) {
1822 DBG(dev, "rx OOM %d" NL, slot);
1823 ++dev->estats.rx_dropped_oom;
1824 emac_recycle_rx_skb(dev, slot, 0);
1826 dev->rx_sg_skb = skb;
1829 } else if (!emac_rx_sg_append(dev, slot) &&
1830 (ctrl & MAL_RX_CTRL_LAST)) {
1832 skb = dev->rx_sg_skb;
1833 dev->rx_sg_skb = NULL;
1835 ctrl &= EMAC_BAD_RX_MASK;
1836 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1837 emac_parse_rx_error(dev, ctrl);
1838 ++dev->estats.rx_dropped_error;
1846 DBG(dev, "rx OOM %d" NL, slot);
1847 /* Drop the packet and recycle skb */
1848 ++dev->estats.rx_dropped_oom;
1849 emac_recycle_rx_skb(dev, slot, 0);
1854 DBG2(dev, "rx %d BDs" NL, received);
1855 dev->rx_slot = slot;
1858 if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) {
1860 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1861 DBG2(dev, "rx restart" NL);
1866 if (dev->rx_sg_skb) {
1867 DBG2(dev, "dropping partial rx packet" NL);
1868 ++dev->estats.rx_dropped_error;
1869 dev_kfree_skb(dev->rx_sg_skb);
1870 dev->rx_sg_skb = NULL;
1873 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1874 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1875 emac_rx_enable(dev);
1881 /* NAPI poll context */
1882 static int emac_peek_rx(void *param)
1884 struct emac_instance *dev = param;
1886 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1889 /* NAPI poll context */
1890 static int emac_peek_rx_sg(void *param)
1892 struct emac_instance *dev = param;
1894 int slot = dev->rx_slot;
1896 u16 ctrl = dev->rx_desc[slot].ctrl;
1897 if (ctrl & MAL_RX_CTRL_EMPTY)
1899 else if (ctrl & MAL_RX_CTRL_LAST)
1902 slot = (slot + 1) % NUM_RX_BUFF;
1904 /* I'm just being paranoid here :) */
1905 if (unlikely(slot == dev->rx_slot))
1911 static void emac_rxde(void *param)
1913 struct emac_instance *dev = param;
1915 ++dev->estats.rx_stopped;
1916 emac_rx_disable_async(dev);
1920 static irqreturn_t emac_irq(int irq, void *dev_instance)
1922 struct emac_instance *dev = dev_instance;
1923 struct emac_regs __iomem *p = dev->emacp;
1924 struct emac_error_stats *st = &dev->estats;
1927 spin_lock(&dev->lock);
1929 isr = in_be32(&p->isr);
1930 out_be32(&p->isr, isr);
1932 DBG(dev, "isr = %08x" NL, isr);
1934 if (isr & EMAC4_ISR_TXPE)
1936 if (isr & EMAC4_ISR_RXPE)
1938 if (isr & EMAC4_ISR_TXUE)
1940 if (isr & EMAC4_ISR_RXOE)
1941 ++st->rx_fifo_overrun;
1942 if (isr & EMAC_ISR_OVR)
1944 if (isr & EMAC_ISR_BP)
1945 ++st->rx_bad_packet;
1946 if (isr & EMAC_ISR_RP)
1947 ++st->rx_runt_packet;
1948 if (isr & EMAC_ISR_SE)
1949 ++st->rx_short_event;
1950 if (isr & EMAC_ISR_ALE)
1951 ++st->rx_alignment_error;
1952 if (isr & EMAC_ISR_BFCS)
1954 if (isr & EMAC_ISR_PTLE)
1955 ++st->rx_packet_too_long;
1956 if (isr & EMAC_ISR_ORE)
1957 ++st->rx_out_of_range;
1958 if (isr & EMAC_ISR_IRE)
1960 if (isr & EMAC_ISR_SQE)
1962 if (isr & EMAC_ISR_TE)
1965 spin_unlock(&dev->lock);
1970 static struct net_device_stats *emac_stats(struct net_device *ndev)
1972 struct emac_instance *dev = netdev_priv(ndev);
1973 struct emac_stats *st = &dev->stats;
1974 struct emac_error_stats *est = &dev->estats;
1975 struct net_device_stats *nst = &ndev->stats;
1976 unsigned long flags;
1978 DBG2(dev, "stats" NL);
1980 /* Compute "legacy" statistics */
1981 spin_lock_irqsave(&dev->lock, flags);
1982 nst->rx_packets = (unsigned long)st->rx_packets;
1983 nst->rx_bytes = (unsigned long)st->rx_bytes;
1984 nst->tx_packets = (unsigned long)st->tx_packets;
1985 nst->tx_bytes = (unsigned long)st->tx_bytes;
1986 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1987 est->rx_dropped_error +
1988 est->rx_dropped_resize +
1989 est->rx_dropped_mtu);
1990 nst->tx_dropped = (unsigned long)est->tx_dropped;
1992 nst->rx_errors = (unsigned long)est->rx_bd_errors;
1993 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1994 est->rx_fifo_overrun +
1996 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1997 est->rx_alignment_error);
1998 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
2000 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
2001 est->rx_bd_short_event +
2002 est->rx_bd_packet_too_long +
2003 est->rx_bd_out_of_range +
2004 est->rx_bd_in_range +
2005 est->rx_runt_packet +
2006 est->rx_short_event +
2007 est->rx_packet_too_long +
2008 est->rx_out_of_range +
2011 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
2012 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
2014 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
2015 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
2016 est->tx_bd_excessive_collisions +
2017 est->tx_bd_late_collision +
2018 est->tx_bd_multple_collisions);
2019 spin_unlock_irqrestore(&dev->lock, flags);
2023 static struct mal_commac_ops emac_commac_ops = {
2024 .poll_tx = &emac_poll_tx,
2025 .poll_rx = &emac_poll_rx,
2026 .peek_rx = &emac_peek_rx,
2030 static struct mal_commac_ops emac_commac_sg_ops = {
2031 .poll_tx = &emac_poll_tx,
2032 .poll_rx = &emac_poll_rx,
2033 .peek_rx = &emac_peek_rx_sg,
2037 /* Ethtool support */
2038 static int emac_ethtool_get_link_ksettings(struct net_device *ndev,
2039 struct ethtool_link_ksettings *cmd)
2041 struct emac_instance *dev = netdev_priv(ndev);
2042 u32 supported, advertising;
2044 supported = dev->phy.features;
2045 cmd->base.port = PORT_MII;
2046 cmd->base.phy_address = dev->phy.address;
2048 mutex_lock(&dev->link_lock);
2049 advertising = dev->phy.advertising;
2050 cmd->base.autoneg = dev->phy.autoneg;
2051 cmd->base.speed = dev->phy.speed;
2052 cmd->base.duplex = dev->phy.duplex;
2053 mutex_unlock(&dev->link_lock);
2055 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2057 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2064 emac_ethtool_set_link_ksettings(struct net_device *ndev,
2065 const struct ethtool_link_ksettings *cmd)
2067 struct emac_instance *dev = netdev_priv(ndev);
2068 u32 f = dev->phy.features;
2071 ethtool_convert_link_mode_to_legacy_u32(&advertising,
2072 cmd->link_modes.advertising);
2074 DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL,
2075 cmd->base.autoneg, cmd->base.speed, cmd->base.duplex, advertising);
2077 /* Basic sanity checks */
2078 if (dev->phy.address < 0)
2080 if (cmd->base.autoneg != AUTONEG_ENABLE &&
2081 cmd->base.autoneg != AUTONEG_DISABLE)
2083 if (cmd->base.autoneg == AUTONEG_ENABLE && advertising == 0)
2085 if (cmd->base.duplex != DUPLEX_HALF && cmd->base.duplex != DUPLEX_FULL)
2088 if (cmd->base.autoneg == AUTONEG_DISABLE) {
2089 switch (cmd->base.speed) {
2091 if (cmd->base.duplex == DUPLEX_HALF &&
2092 !(f & SUPPORTED_10baseT_Half))
2094 if (cmd->base.duplex == DUPLEX_FULL &&
2095 !(f & SUPPORTED_10baseT_Full))
2099 if (cmd->base.duplex == DUPLEX_HALF &&
2100 !(f & SUPPORTED_100baseT_Half))
2102 if (cmd->base.duplex == DUPLEX_FULL &&
2103 !(f & SUPPORTED_100baseT_Full))
2107 if (cmd->base.duplex == DUPLEX_HALF &&
2108 !(f & SUPPORTED_1000baseT_Half))
2110 if (cmd->base.duplex == DUPLEX_FULL &&
2111 !(f & SUPPORTED_1000baseT_Full))
2118 mutex_lock(&dev->link_lock);
2119 dev->phy.def->ops->setup_forced(&dev->phy, cmd->base.speed,
2121 mutex_unlock(&dev->link_lock);
2124 if (!(f & SUPPORTED_Autoneg))
2127 mutex_lock(&dev->link_lock);
2128 dev->phy.def->ops->setup_aneg(&dev->phy,
2130 (dev->phy.advertising &
2132 ADVERTISED_Asym_Pause)));
2133 mutex_unlock(&dev->link_lock);
2135 emac_force_link_update(dev);
2140 static void emac_ethtool_get_ringparam(struct net_device *ndev,
2141 struct ethtool_ringparam *rp)
2143 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
2144 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
2147 static void emac_ethtool_get_pauseparam(struct net_device *ndev,
2148 struct ethtool_pauseparam *pp)
2150 struct emac_instance *dev = netdev_priv(ndev);
2152 mutex_lock(&dev->link_lock);
2153 if ((dev->phy.features & SUPPORTED_Autoneg) &&
2154 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
2157 if (dev->phy.duplex == DUPLEX_FULL) {
2159 pp->rx_pause = pp->tx_pause = 1;
2160 else if (dev->phy.asym_pause)
2163 mutex_unlock(&dev->link_lock);
2166 static int emac_get_regs_len(struct emac_instance *dev)
2168 return sizeof(struct emac_ethtool_regs_subhdr) +
2169 sizeof(struct emac_regs);
2172 static int emac_ethtool_get_regs_len(struct net_device *ndev)
2174 struct emac_instance *dev = netdev_priv(ndev);
2177 size = sizeof(struct emac_ethtool_regs_hdr) +
2178 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal);
2179 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2180 size += zmii_get_regs_len(dev->zmii_dev);
2181 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2182 size += rgmii_get_regs_len(dev->rgmii_dev);
2183 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2184 size += tah_get_regs_len(dev->tah_dev);
2189 static void *emac_dump_regs(struct emac_instance *dev, void *buf)
2191 struct emac_ethtool_regs_subhdr *hdr = buf;
2193 hdr->index = dev->cell_index;
2194 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2195 hdr->version = EMAC4SYNC_ETHTOOL_REGS_VER;
2196 } else if (emac_has_feature(dev, EMAC_FTR_EMAC4)) {
2197 hdr->version = EMAC4_ETHTOOL_REGS_VER;
2199 hdr->version = EMAC_ETHTOOL_REGS_VER;
2201 memcpy_fromio(hdr + 1, dev->emacp, sizeof(struct emac_regs));
2202 return (void *)(hdr + 1) + sizeof(struct emac_regs);
2205 static void emac_ethtool_get_regs(struct net_device *ndev,
2206 struct ethtool_regs *regs, void *buf)
2208 struct emac_instance *dev = netdev_priv(ndev);
2209 struct emac_ethtool_regs_hdr *hdr = buf;
2211 hdr->components = 0;
2214 buf = mal_dump_regs(dev->mal, buf);
2215 buf = emac_dump_regs(dev, buf);
2216 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) {
2217 hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
2218 buf = zmii_dump_regs(dev->zmii_dev, buf);
2220 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2221 hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
2222 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
2224 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) {
2225 hdr->components |= EMAC_ETHTOOL_REGS_TAH;
2226 buf = tah_dump_regs(dev->tah_dev, buf);
2230 static int emac_ethtool_nway_reset(struct net_device *ndev)
2232 struct emac_instance *dev = netdev_priv(ndev);
2235 DBG(dev, "nway_reset" NL);
2237 if (dev->phy.address < 0)
2240 mutex_lock(&dev->link_lock);
2241 if (!dev->phy.autoneg) {
2246 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
2248 mutex_unlock(&dev->link_lock);
2249 emac_force_link_update(dev);
2253 static int emac_ethtool_get_sset_count(struct net_device *ndev, int stringset)
2255 if (stringset == ETH_SS_STATS)
2256 return EMAC_ETHTOOL_STATS_COUNT;
2261 static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
2264 if (stringset == ETH_SS_STATS)
2265 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
2268 static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
2269 struct ethtool_stats *estats,
2272 struct emac_instance *dev = netdev_priv(ndev);
2274 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
2275 tmp_stats += sizeof(dev->stats) / sizeof(u64);
2276 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
2279 static void emac_ethtool_get_drvinfo(struct net_device *ndev,
2280 struct ethtool_drvinfo *info)
2282 struct emac_instance *dev = netdev_priv(ndev);
2284 strlcpy(info->driver, "ibm_emac", sizeof(info->driver));
2285 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2286 snprintf(info->bus_info, sizeof(info->bus_info), "PPC 4xx EMAC-%d %pOF",
2287 dev->cell_index, dev->ofdev->dev.of_node);
2290 static const struct ethtool_ops emac_ethtool_ops = {
2291 .get_drvinfo = emac_ethtool_get_drvinfo,
2293 .get_regs_len = emac_ethtool_get_regs_len,
2294 .get_regs = emac_ethtool_get_regs,
2296 .nway_reset = emac_ethtool_nway_reset,
2298 .get_ringparam = emac_ethtool_get_ringparam,
2299 .get_pauseparam = emac_ethtool_get_pauseparam,
2301 .get_strings = emac_ethtool_get_strings,
2302 .get_sset_count = emac_ethtool_get_sset_count,
2303 .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
2305 .get_link = ethtool_op_get_link,
2306 .get_link_ksettings = emac_ethtool_get_link_ksettings,
2307 .set_link_ksettings = emac_ethtool_set_link_ksettings,
2310 static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2312 struct emac_instance *dev = netdev_priv(ndev);
2313 struct mii_ioctl_data *data = if_mii(rq);
2315 DBG(dev, "ioctl %08x" NL, cmd);
2317 if (dev->phy.address < 0)
2322 data->phy_id = dev->phy.address;
2325 data->val_out = emac_mdio_read(ndev, dev->phy.address,
2330 emac_mdio_write(ndev, dev->phy.address, data->reg_num,
2338 struct emac_depentry {
2340 struct device_node *node;
2341 struct platform_device *ofdev;
2345 #define EMAC_DEP_MAL_IDX 0
2346 #define EMAC_DEP_ZMII_IDX 1
2347 #define EMAC_DEP_RGMII_IDX 2
2348 #define EMAC_DEP_TAH_IDX 3
2349 #define EMAC_DEP_MDIO_IDX 4
2350 #define EMAC_DEP_PREV_IDX 5
2351 #define EMAC_DEP_COUNT 6
2353 static int emac_check_deps(struct emac_instance *dev,
2354 struct emac_depentry *deps)
2357 struct device_node *np;
2359 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2360 /* no dependency on that item, allright */
2361 if (deps[i].phandle == 0) {
2365 /* special case for blist as the dependency might go away */
2366 if (i == EMAC_DEP_PREV_IDX) {
2367 np = *(dev->blist - 1);
2369 deps[i].phandle = 0;
2373 if (deps[i].node == NULL)
2374 deps[i].node = of_node_get(np);
2376 if (deps[i].node == NULL)
2377 deps[i].node = of_find_node_by_phandle(deps[i].phandle);
2378 if (deps[i].node == NULL)
2380 if (deps[i].ofdev == NULL)
2381 deps[i].ofdev = of_find_device_by_node(deps[i].node);
2382 if (deps[i].ofdev == NULL)
2384 if (deps[i].drvdata == NULL)
2385 deps[i].drvdata = platform_get_drvdata(deps[i].ofdev);
2386 if (deps[i].drvdata != NULL)
2389 return there == EMAC_DEP_COUNT;
2392 static void emac_put_deps(struct emac_instance *dev)
2394 of_dev_put(dev->mal_dev);
2395 of_dev_put(dev->zmii_dev);
2396 of_dev_put(dev->rgmii_dev);
2397 of_dev_put(dev->mdio_dev);
2398 of_dev_put(dev->tah_dev);
2401 static int emac_of_bus_notify(struct notifier_block *nb, unsigned long action,
2404 /* We are only intereted in device addition */
2405 if (action == BUS_NOTIFY_BOUND_DRIVER)
2406 wake_up_all(&emac_probe_wait);
2410 static struct notifier_block emac_of_bus_notifier = {
2411 .notifier_call = emac_of_bus_notify
2414 static int emac_wait_deps(struct emac_instance *dev)
2416 struct emac_depentry deps[EMAC_DEP_COUNT];
2419 memset(&deps, 0, sizeof(deps));
2421 deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph;
2422 deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph;
2423 deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph;
2425 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph;
2427 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph;
2428 if (dev->blist && dev->blist > emac_boot_list)
2429 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu;
2430 bus_register_notifier(&platform_bus_type, &emac_of_bus_notifier);
2431 wait_event_timeout(emac_probe_wait,
2432 emac_check_deps(dev, deps),
2433 EMAC_PROBE_DEP_TIMEOUT);
2434 bus_unregister_notifier(&platform_bus_type, &emac_of_bus_notifier);
2435 err = emac_check_deps(dev, deps) ? 0 : -ENODEV;
2436 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2437 of_node_put(deps[i].node);
2439 of_dev_put(deps[i].ofdev);
2442 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev;
2443 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev;
2444 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev;
2445 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev;
2446 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev;
2448 of_dev_put(deps[EMAC_DEP_PREV_IDX].ofdev);
2452 static int emac_read_uint_prop(struct device_node *np, const char *name,
2453 u32 *val, int fatal)
2456 const u32 *prop = of_get_property(np, name, &len);
2457 if (prop == NULL || len < sizeof(u32)) {
2459 printk(KERN_ERR "%pOF: missing %s property\n",
2467 static void emac_adjust_link(struct net_device *ndev)
2469 struct emac_instance *dev = netdev_priv(ndev);
2470 struct phy_device *phy = dev->phy_dev;
2472 dev->phy.autoneg = phy->autoneg;
2473 dev->phy.speed = phy->speed;
2474 dev->phy.duplex = phy->duplex;
2475 dev->phy.pause = phy->pause;
2476 dev->phy.asym_pause = phy->asym_pause;
2477 ethtool_convert_link_mode_to_legacy_u32(&dev->phy.advertising,
2481 static int emac_mii_bus_read(struct mii_bus *bus, int addr, int regnum)
2483 int ret = emac_mdio_read(bus->priv, addr, regnum);
2484 /* This is a workaround for powered down ports/phys.
2485 * In the wild, this was seen on the Cisco Meraki MX60(W).
2486 * This hardware disables ports as part of the handoff
2487 * procedure. Accessing the ports will lead to errors
2488 * (-ETIMEDOUT, -EREMOTEIO) that do more harm than good.
2490 return ret < 0 ? 0xffff : ret;
2493 static int emac_mii_bus_write(struct mii_bus *bus, int addr,
2494 int regnum, u16 val)
2496 emac_mdio_write(bus->priv, addr, regnum, val);
2500 static int emac_mii_bus_reset(struct mii_bus *bus)
2502 struct emac_instance *dev = netdev_priv(bus->priv);
2504 return emac_reset(dev);
2507 static int emac_mdio_phy_start_aneg(struct mii_phy *phy,
2508 struct phy_device *phy_dev)
2510 phy_dev->autoneg = phy->autoneg;
2511 phy_dev->speed = phy->speed;
2512 phy_dev->duplex = phy->duplex;
2513 ethtool_convert_legacy_u32_to_link_mode(phy_dev->advertising,
2515 return phy_start_aneg(phy_dev);
2518 static int emac_mdio_setup_aneg(struct mii_phy *phy, u32 advertise)
2520 struct net_device *ndev = phy->dev;
2521 struct emac_instance *dev = netdev_priv(ndev);
2523 phy->autoneg = AUTONEG_ENABLE;
2524 phy->advertising = advertise;
2525 return emac_mdio_phy_start_aneg(phy, dev->phy_dev);
2528 static int emac_mdio_setup_forced(struct mii_phy *phy, int speed, int fd)
2530 struct net_device *ndev = phy->dev;
2531 struct emac_instance *dev = netdev_priv(ndev);
2533 phy->autoneg = AUTONEG_DISABLE;
2536 return emac_mdio_phy_start_aneg(phy, dev->phy_dev);
2539 static int emac_mdio_poll_link(struct mii_phy *phy)
2541 struct net_device *ndev = phy->dev;
2542 struct emac_instance *dev = netdev_priv(ndev);
2545 res = phy_read_status(dev->phy_dev);
2547 dev_err(&dev->ofdev->dev, "link update failed (%d).", res);
2548 return ethtool_op_get_link(ndev);
2551 return dev->phy_dev->link;
2554 static int emac_mdio_read_link(struct mii_phy *phy)
2556 struct net_device *ndev = phy->dev;
2557 struct emac_instance *dev = netdev_priv(ndev);
2558 struct phy_device *phy_dev = dev->phy_dev;
2561 res = phy_read_status(phy_dev);
2565 phy->speed = phy_dev->speed;
2566 phy->duplex = phy_dev->duplex;
2567 phy->pause = phy_dev->pause;
2568 phy->asym_pause = phy_dev->asym_pause;
2572 static int emac_mdio_init_phy(struct mii_phy *phy)
2574 struct net_device *ndev = phy->dev;
2575 struct emac_instance *dev = netdev_priv(ndev);
2577 phy_start(dev->phy_dev);
2578 return phy_init_hw(dev->phy_dev);
2581 static const struct mii_phy_ops emac_dt_mdio_phy_ops = {
2582 .init = emac_mdio_init_phy,
2583 .setup_aneg = emac_mdio_setup_aneg,
2584 .setup_forced = emac_mdio_setup_forced,
2585 .poll_link = emac_mdio_poll_link,
2586 .read_link = emac_mdio_read_link,
2589 static int emac_dt_mdio_probe(struct emac_instance *dev)
2591 struct device_node *mii_np;
2594 mii_np = of_get_child_by_name(dev->ofdev->dev.of_node, "mdio");
2596 dev_err(&dev->ofdev->dev, "no mdio definition found.");
2600 if (!of_device_is_available(mii_np)) {
2605 dev->mii_bus = devm_mdiobus_alloc(&dev->ofdev->dev);
2606 if (!dev->mii_bus) {
2611 dev->mii_bus->priv = dev->ndev;
2612 dev->mii_bus->parent = dev->ndev->dev.parent;
2613 dev->mii_bus->name = "emac_mdio";
2614 dev->mii_bus->read = &emac_mii_bus_read;
2615 dev->mii_bus->write = &emac_mii_bus_write;
2616 dev->mii_bus->reset = &emac_mii_bus_reset;
2617 snprintf(dev->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev->ofdev->name);
2618 res = of_mdiobus_register(dev->mii_bus, mii_np);
2620 dev_err(&dev->ofdev->dev, "cannot register MDIO bus %s (%d)",
2621 dev->mii_bus->name, res);
2625 of_node_put(mii_np);
2629 static int emac_dt_phy_connect(struct emac_instance *dev,
2630 struct device_node *phy_handle)
2632 dev->phy.def = devm_kzalloc(&dev->ofdev->dev, sizeof(*dev->phy.def),
2637 dev->phy_dev = of_phy_connect(dev->ndev, phy_handle, &emac_adjust_link,
2639 if (!dev->phy_dev) {
2640 dev_err(&dev->ofdev->dev, "failed to connect to PHY.\n");
2644 dev->phy.def->phy_id = dev->phy_dev->drv->phy_id;
2645 dev->phy.def->phy_id_mask = dev->phy_dev->drv->phy_id_mask;
2646 dev->phy.def->name = dev->phy_dev->drv->name;
2647 dev->phy.def->ops = &emac_dt_mdio_phy_ops;
2648 ethtool_convert_link_mode_to_legacy_u32(&dev->phy.features,
2649 dev->phy_dev->supported);
2650 dev->phy.address = dev->phy_dev->mdio.addr;
2651 dev->phy.mode = dev->phy_dev->interface;
2655 static int emac_dt_phy_probe(struct emac_instance *dev)
2657 struct device_node *np = dev->ofdev->dev.of_node;
2658 struct device_node *phy_handle;
2661 phy_handle = of_parse_phandle(np, "phy-handle", 0);
2664 res = emac_dt_mdio_probe(dev);
2666 res = emac_dt_phy_connect(dev, phy_handle);
2668 mdiobus_unregister(dev->mii_bus);
2672 of_node_put(phy_handle);
2676 static int emac_init_phy(struct emac_instance *dev)
2678 struct device_node *np = dev->ofdev->dev.of_node;
2679 struct net_device *ndev = dev->ndev;
2683 dev->phy.dev = ndev;
2684 dev->phy.mode = dev->phy_mode;
2686 /* PHY-less configuration. */
2687 if ((dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) ||
2688 of_phy_is_fixed_link(np)) {
2691 /* PHY-less configuration. */
2692 dev->phy.address = -1;
2693 dev->phy.features = SUPPORTED_MII;
2694 if (emac_phy_supports_gige(dev->phy_mode))
2695 dev->phy.features |= SUPPORTED_1000baseT_Full;
2697 dev->phy.features |= SUPPORTED_100baseT_Full;
2700 if (of_phy_is_fixed_link(np)) {
2701 int res = emac_dt_mdio_probe(dev);
2706 res = of_phy_register_fixed_link(np);
2707 dev->phy_dev = of_phy_find_device(np);
2708 if (res || !dev->phy_dev) {
2709 mdiobus_unregister(dev->mii_bus);
2710 return res ? res : -EINVAL;
2712 emac_adjust_link(dev->ndev);
2713 put_device(&dev->phy_dev->mdio.dev);
2718 mutex_lock(&emac_phy_map_lock);
2719 phy_map = dev->phy_map | busy_phy_map;
2721 DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map);
2723 dev->phy.mdio_read = emac_mdio_read;
2724 dev->phy.mdio_write = emac_mdio_write;
2726 /* Enable internal clock source */
2727 #ifdef CONFIG_PPC_DCR_NATIVE
2728 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2729 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2731 /* PHY clock workaround */
2732 emac_rx_clk_tx(dev);
2734 /* Enable internal clock source on 440GX*/
2735 #ifdef CONFIG_PPC_DCR_NATIVE
2736 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2737 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2739 /* Configure EMAC with defaults so we can at least use MDIO
2740 * This is needed mostly for 440GX
2742 if (emac_phy_gpcs(dev->phy.mode)) {
2744 * Make GPCS PHY address equal to EMAC index.
2745 * We probably should take into account busy_phy_map
2746 * and/or phy_map here.
2748 * Note that the busy_phy_map is currently global
2749 * while it should probably be per-ASIC...
2751 dev->phy.gpcs_address = dev->gpcs_address;
2752 if (dev->phy.gpcs_address == 0xffffffff)
2753 dev->phy.address = dev->cell_index;
2756 emac_configure(dev);
2758 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2759 int res = emac_dt_phy_probe(dev);
2763 /* No phy-handle property configured.
2764 * Continue with the existing phy probe
2770 mutex_unlock(&emac_phy_map_lock);
2774 mutex_unlock(&emac_phy_map_lock);
2775 dev_err(&dev->ofdev->dev, "failed to attach dt phy (%d).\n",
2781 if (dev->phy_address != 0xffffffff)
2782 phy_map = ~(1 << dev->phy_address);
2784 for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2785 if (!(phy_map & 1)) {
2787 busy_phy_map |= 1 << i;
2789 /* Quick check if there is a PHY at the address */
2790 r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2791 if (r == 0xffff || r < 0)
2793 if (!emac_mii_phy_probe(&dev->phy, i))
2797 /* Enable external clock source */
2798 #ifdef CONFIG_PPC_DCR_NATIVE
2799 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2800 dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0);
2802 mutex_unlock(&emac_phy_map_lock);
2804 printk(KERN_WARNING "%pOF: can't find PHY!\n", np);
2810 if (dev->phy.def->ops->init)
2811 dev->phy.def->ops->init(&dev->phy);
2813 /* Disable any PHY features not supported by the platform */
2814 dev->phy.def->features &= ~dev->phy_feat_exc;
2815 dev->phy.features &= ~dev->phy_feat_exc;
2817 /* Setup initial link parameters */
2818 if (dev->phy.features & SUPPORTED_Autoneg) {
2819 adv = dev->phy.features;
2820 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x))
2821 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2822 /* Restart autonegotiation */
2823 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2825 u32 f = dev->phy.def->features;
2826 int speed = SPEED_10, fd = DUPLEX_HALF;
2828 /* Select highest supported speed/duplex */
2829 if (f & SUPPORTED_1000baseT_Full) {
2832 } else if (f & SUPPORTED_1000baseT_Half)
2834 else if (f & SUPPORTED_100baseT_Full) {
2837 } else if (f & SUPPORTED_100baseT_Half)
2839 else if (f & SUPPORTED_10baseT_Full)
2842 /* Force link parameters */
2843 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2848 static int emac_init_config(struct emac_instance *dev)
2850 struct device_node *np = dev->ofdev->dev.of_node;
2853 /* Read config from device-tree */
2854 if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1))
2856 if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1))
2858 if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1))
2860 if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1))
2862 if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0))
2863 dev->max_mtu = ETH_DATA_LEN;
2864 if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0))
2865 dev->rx_fifo_size = 2048;
2866 if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0))
2867 dev->tx_fifo_size = 2048;
2868 if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0))
2869 dev->rx_fifo_size_gige = dev->rx_fifo_size;
2870 if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0))
2871 dev->tx_fifo_size_gige = dev->tx_fifo_size;
2872 if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0))
2873 dev->phy_address = 0xffffffff;
2874 if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0))
2875 dev->phy_map = 0xffffffff;
2876 if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0))
2877 dev->gpcs_address = 0xffffffff;
2878 if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1))
2880 if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0))
2882 if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0))
2884 if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0))
2886 if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0))
2888 if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0))
2889 dev->zmii_port = 0xffffffff;
2890 if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0))
2892 if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0))
2893 dev->rgmii_port = 0xffffffff;
2894 if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0))
2895 dev->fifo_entry_size = 16;
2896 if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0))
2897 dev->mal_burst_size = 256;
2899 /* PHY mode needs some decoding */
2900 dev->phy_mode = of_get_phy_mode(np);
2901 if (dev->phy_mode < 0)
2902 dev->phy_mode = PHY_INTERFACE_MODE_NA;
2904 /* Check EMAC version */
2905 if (of_device_is_compatible(np, "ibm,emac4sync")) {
2906 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC);
2907 if (of_device_is_compatible(np, "ibm,emac-460ex") ||
2908 of_device_is_compatible(np, "ibm,emac-460gt"))
2909 dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
2910 if (of_device_is_compatible(np, "ibm,emac-405ex") ||
2911 of_device_is_compatible(np, "ibm,emac-405exr"))
2912 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2913 if (of_device_is_compatible(np, "ibm,emac-apm821xx")) {
2914 dev->features |= (EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
2915 EMAC_FTR_APM821XX_NO_HALF_DUPLEX |
2916 EMAC_FTR_460EX_PHY_CLK_FIX);
2918 } else if (of_device_is_compatible(np, "ibm,emac4")) {
2919 dev->features |= EMAC_FTR_EMAC4;
2920 if (of_device_is_compatible(np, "ibm,emac-440gx"))
2921 dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
2923 if (of_device_is_compatible(np, "ibm,emac-440ep") ||
2924 of_device_is_compatible(np, "ibm,emac-440gr"))
2925 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2926 if (of_device_is_compatible(np, "ibm,emac-405ez")) {
2927 #ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL
2928 dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x;
2930 printk(KERN_ERR "%pOF: Flow control not disabled!\n",
2938 /* Fixup some feature bits based on the device tree */
2939 if (of_get_property(np, "has-inverted-stacr-oc", NULL))
2940 dev->features |= EMAC_FTR_STACR_OC_INVERT;
2941 if (of_get_property(np, "has-new-stacr-staopc", NULL))
2942 dev->features |= EMAC_FTR_HAS_NEW_STACR;
2944 /* CAB lacks the appropriate properties */
2945 if (of_device_is_compatible(np, "ibm,emac-axon"))
2946 dev->features |= EMAC_FTR_HAS_NEW_STACR |
2947 EMAC_FTR_STACR_OC_INVERT;
2949 /* Enable TAH/ZMII/RGMII features as found */
2950 if (dev->tah_ph != 0) {
2951 #ifdef CONFIG_IBM_EMAC_TAH
2952 dev->features |= EMAC_FTR_HAS_TAH;
2954 printk(KERN_ERR "%pOF: TAH support not enabled !\n", np);
2959 if (dev->zmii_ph != 0) {
2960 #ifdef CONFIG_IBM_EMAC_ZMII
2961 dev->features |= EMAC_FTR_HAS_ZMII;
2963 printk(KERN_ERR "%pOF: ZMII support not enabled !\n", np);
2968 if (dev->rgmii_ph != 0) {
2969 #ifdef CONFIG_IBM_EMAC_RGMII
2970 dev->features |= EMAC_FTR_HAS_RGMII;
2972 printk(KERN_ERR "%pOF: RGMII support not enabled !\n", np);
2977 /* Read MAC-address */
2978 p = of_get_property(np, "local-mac-address", NULL);
2980 printk(KERN_ERR "%pOF: Can't find local-mac-address property\n",
2984 memcpy(dev->ndev->dev_addr, p, ETH_ALEN);
2986 /* IAHT and GAHT filter parameterization */
2987 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2988 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT;
2989 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT;
2991 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT;
2992 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT;
2995 /* This should never happen */
2996 if (WARN_ON(EMAC_XAHT_REGS(dev) > EMAC_XAHT_MAX_REGS))
2999 DBG(dev, "features : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE);
3000 DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige);
3001 DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige);
3002 DBG(dev, "max_mtu : %d\n", dev->max_mtu);
3003 DBG(dev, "OPB freq : %d\n", dev->opb_bus_freq);
3008 static const struct net_device_ops emac_netdev_ops = {
3009 .ndo_open = emac_open,
3010 .ndo_stop = emac_close,
3011 .ndo_get_stats = emac_stats,
3012 .ndo_set_rx_mode = emac_set_multicast_list,
3013 .ndo_do_ioctl = emac_ioctl,
3014 .ndo_tx_timeout = emac_tx_timeout,
3015 .ndo_validate_addr = eth_validate_addr,
3016 .ndo_set_mac_address = emac_set_mac_address,
3017 .ndo_start_xmit = emac_start_xmit,
3020 static const struct net_device_ops emac_gige_netdev_ops = {
3021 .ndo_open = emac_open,
3022 .ndo_stop = emac_close,
3023 .ndo_get_stats = emac_stats,
3024 .ndo_set_rx_mode = emac_set_multicast_list,
3025 .ndo_do_ioctl = emac_ioctl,
3026 .ndo_tx_timeout = emac_tx_timeout,
3027 .ndo_validate_addr = eth_validate_addr,
3028 .ndo_set_mac_address = emac_set_mac_address,
3029 .ndo_start_xmit = emac_start_xmit_sg,
3030 .ndo_change_mtu = emac_change_mtu,
3033 static int emac_probe(struct platform_device *ofdev)
3035 struct net_device *ndev;
3036 struct emac_instance *dev;
3037 struct device_node *np = ofdev->dev.of_node;
3038 struct device_node **blist = NULL;
3041 /* Skip unused/unwired EMACS. We leave the check for an unused
3042 * property here for now, but new flat device trees should set a
3043 * status property to "disabled" instead.
3045 if (of_get_property(np, "unused", NULL) || !of_device_is_available(np))
3048 /* Find ourselves in the bootlist if we are there */
3049 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3050 if (emac_boot_list[i] == np)
3051 blist = &emac_boot_list[i];
3053 /* Allocate our net_device structure */
3055 ndev = alloc_etherdev(sizeof(struct emac_instance));
3059 dev = netdev_priv(ndev);
3063 SET_NETDEV_DEV(ndev, &ofdev->dev);
3065 /* Initialize some embedded data structures */
3066 mutex_init(&dev->mdio_lock);
3067 mutex_init(&dev->link_lock);
3068 spin_lock_init(&dev->lock);
3069 INIT_WORK(&dev->reset_work, emac_reset_work);
3071 /* Init various config data based on device-tree */
3072 err = emac_init_config(dev);
3076 /* Get interrupts. EMAC irq is mandatory, WOL irq is optional */
3077 dev->emac_irq = irq_of_parse_and_map(np, 0);
3078 dev->wol_irq = irq_of_parse_and_map(np, 1);
3079 if (!dev->emac_irq) {
3080 printk(KERN_ERR "%pOF: Can't map main interrupt\n", np);
3084 ndev->irq = dev->emac_irq;
3087 // TODO : platform_get_resource() and devm_ioremap_resource()
3088 dev->emacp = of_iomap(np, 0);
3089 if (dev->emacp == NULL) {
3090 printk(KERN_ERR "%pOF: Can't map device registers!\n", np);
3095 /* Wait for dependent devices */
3096 err = emac_wait_deps(dev);
3099 "%pOF: Timeout waiting for dependent devices\n", np);
3100 /* display more info about what's missing ? */
3103 dev->mal = platform_get_drvdata(dev->mal_dev);
3104 if (dev->mdio_dev != NULL)
3105 dev->mdio_instance = platform_get_drvdata(dev->mdio_dev);
3107 /* Register with MAL */
3108 dev->commac.ops = &emac_commac_ops;
3109 dev->commac.dev = dev;
3110 dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan);
3111 dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan);
3112 err = mal_register_commac(dev->mal, &dev->commac);
3114 printk(KERN_ERR "%pOF: failed to register with mal %pOF!\n",
3115 np, dev->mal_dev->dev.of_node);
3118 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
3119 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
3121 /* Get pointers to BD rings */
3123 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan);
3125 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan);
3127 DBG(dev, "tx_desc %p" NL, dev->tx_desc);
3128 DBG(dev, "rx_desc %p" NL, dev->rx_desc);
3131 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
3132 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
3133 memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *));
3134 memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *));
3136 /* Attach to ZMII, if needed */
3137 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) &&
3138 (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0)
3139 goto err_unreg_commac;
3141 /* Attach to RGMII, if needed */
3142 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) &&
3143 (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0)
3144 goto err_detach_zmii;
3146 /* Attach to TAH, if needed */
3147 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
3148 (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0)
3149 goto err_detach_rgmii;
3151 /* Set some link defaults before we can find out real parameters */
3152 dev->phy.speed = SPEED_100;
3153 dev->phy.duplex = DUPLEX_FULL;
3154 dev->phy.autoneg = AUTONEG_DISABLE;
3155 dev->phy.pause = dev->phy.asym_pause = 0;
3156 dev->stop_timeout = STOP_TIMEOUT_100;
3157 INIT_DELAYED_WORK(&dev->link_work, emac_link_timer);
3159 /* Some SoCs like APM821xx does not support Half Duplex mode. */
3160 if (emac_has_feature(dev, EMAC_FTR_APM821XX_NO_HALF_DUPLEX)) {
3161 dev->phy_feat_exc = (SUPPORTED_1000baseT_Half |
3162 SUPPORTED_100baseT_Half |
3163 SUPPORTED_10baseT_Half);
3166 /* Find PHY if any */
3167 err = emac_init_phy(dev);
3169 goto err_detach_tah;
3172 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG;
3173 ndev->features |= ndev->hw_features | NETIF_F_RXCSUM;
3175 ndev->watchdog_timeo = 5 * HZ;
3176 if (emac_phy_supports_gige(dev->phy_mode)) {
3177 ndev->netdev_ops = &emac_gige_netdev_ops;
3178 dev->commac.ops = &emac_commac_sg_ops;
3180 ndev->netdev_ops = &emac_netdev_ops;
3181 ndev->ethtool_ops = &emac_ethtool_ops;
3183 /* MTU range: 46 - 1500 or whatever is in OF */
3184 ndev->min_mtu = EMAC_MIN_MTU;
3185 ndev->max_mtu = dev->max_mtu;
3187 netif_carrier_off(ndev);
3189 err = register_netdev(ndev);
3191 printk(KERN_ERR "%pOF: failed to register net device (%d)!\n",
3193 goto err_detach_tah;
3196 /* Set our drvdata last as we don't want them visible until we are
3200 platform_set_drvdata(ofdev, dev);
3202 /* There's a new kid in town ! Let's tell everybody */
3203 wake_up_all(&emac_probe_wait);
3206 printk(KERN_INFO "%s: EMAC-%d %pOF, MAC %pM\n",
3207 ndev->name, dev->cell_index, np, ndev->dev_addr);
3209 if (dev->phy_mode == PHY_INTERFACE_MODE_SGMII)
3210 printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name);
3212 if (dev->phy.address >= 0)
3213 printk("%s: found %s PHY (0x%02x)\n", ndev->name,
3214 dev->phy.def->name, dev->phy.address);
3219 /* I have a bad feeling about this ... */
3222 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
3223 tah_detach(dev->tah_dev, dev->tah_port);
3225 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
3226 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
3228 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
3229 zmii_detach(dev->zmii_dev, dev->zmii_port);
3231 mal_unregister_commac(dev->mal, &dev->commac);
3235 iounmap(dev->emacp);
3238 irq_dispose_mapping(dev->wol_irq);
3240 irq_dispose_mapping(dev->emac_irq);
3244 /* if we were on the bootlist, remove us as we won't show up and
3245 * wake up all waiters to notify them in case they were waiting
3250 wake_up_all(&emac_probe_wait);
3255 static int emac_remove(struct platform_device *ofdev)
3257 struct emac_instance *dev = platform_get_drvdata(ofdev);
3259 DBG(dev, "remove" NL);
3261 unregister_netdev(dev->ndev);
3263 cancel_work_sync(&dev->reset_work);
3265 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
3266 tah_detach(dev->tah_dev, dev->tah_port);
3267 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
3268 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
3269 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
3270 zmii_detach(dev->zmii_dev, dev->zmii_port);
3273 phy_disconnect(dev->phy_dev);
3276 mdiobus_unregister(dev->mii_bus);
3278 busy_phy_map &= ~(1 << dev->phy.address);
3279 DBG(dev, "busy_phy_map now %#x" NL, busy_phy_map);
3281 mal_unregister_commac(dev->mal, &dev->commac);
3284 iounmap(dev->emacp);
3287 irq_dispose_mapping(dev->wol_irq);
3289 irq_dispose_mapping(dev->emac_irq);
3291 free_netdev(dev->ndev);
3296 /* XXX Features in here should be replaced by properties... */
3297 static const struct of_device_id emac_match[] =
3301 .compatible = "ibm,emac",
3305 .compatible = "ibm,emac4",
3309 .compatible = "ibm,emac4sync",
3313 MODULE_DEVICE_TABLE(of, emac_match);
3315 static struct platform_driver emac_driver = {
3318 .of_match_table = emac_match,
3320 .probe = emac_probe,
3321 .remove = emac_remove,
3324 static void __init emac_make_bootlist(void)
3326 struct device_node *np = NULL;
3328 int cell_indices[EMAC_BOOT_LIST_SIZE];
3331 while((np = of_find_all_nodes(np)) != NULL) {
3334 if (of_match_node(emac_match, np) == NULL)
3336 if (of_get_property(np, "unused", NULL))
3338 idx = of_get_property(np, "cell-index", NULL);
3341 cell_indices[i] = *idx;
3342 emac_boot_list[i++] = of_node_get(np);
3343 if (i >= EMAC_BOOT_LIST_SIZE) {
3350 /* Bubble sort them (doh, what a creative algorithm :-) */
3351 for (i = 0; max > 1 && (i < (max - 1)); i++)
3352 for (j = i; j < max; j++) {
3353 if (cell_indices[i] > cell_indices[j]) {
3354 swap(emac_boot_list[i], emac_boot_list[j]);
3355 swap(cell_indices[i], cell_indices[j]);
3360 static int __init emac_init(void)
3364 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
3366 /* Build EMAC boot list */
3367 emac_make_bootlist();
3369 /* Init submodules */
3382 rc = platform_driver_register(&emac_driver);
3400 static void __exit emac_exit(void)
3404 platform_driver_unregister(&emac_driver);
3411 /* Destroy EMAC boot list */
3412 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3413 of_node_put(emac_boot_list[i]);
3416 module_init(emac_init);
3417 module_exit(emac_exit);