1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Huawei HiNIC PCI Express Linux driver
4 * Copyright(c) 2017 Huawei Technologies Co., Ltd
10 #include <linux/types.h>
11 #include <linux/etherdevice.h>
12 #include <linux/bitops.h>
14 #include "hinic_dev.h"
16 #define HINIC_RSS_KEY_SIZE 40
17 #define HINIC_RSS_INDIR_SIZE 256
18 #define HINIC_PORT_STATS_VERSION 0
19 #define HINIC_FW_VERSION_NAME 16
20 #define HINIC_COMPILE_TIME_LEN 20
21 #define HINIC_MGMT_VERSION_MAX_LEN 32
23 struct hinic_version_info {
28 u8 ver[HINIC_FW_VERSION_NAME];
29 u8 time[HINIC_COMPILE_TIME_LEN];
33 HINIC_RX_MODE_UC = BIT(0),
34 HINIC_RX_MODE_MC = BIT(1),
35 HINIC_RX_MODE_BC = BIT(2),
36 HINIC_RX_MODE_MC_ALL = BIT(3),
37 HINIC_RX_MODE_PROMISC = BIT(4),
40 enum hinic_port_link_state {
41 HINIC_LINK_STATE_DOWN,
45 enum hinic_port_state {
46 HINIC_PORT_DISABLE = 0,
47 HINIC_PORT_ENABLE = 3,
50 enum hinic_func_port_state {
51 HINIC_FUNC_PORT_DISABLE = 0,
52 HINIC_FUNC_PORT_ENABLE = 2,
55 enum hinic_autoneg_cap {
56 HINIC_AUTONEG_UNSUPPORTED,
57 HINIC_AUTONEG_SUPPORTED,
60 enum hinic_autoneg_state {
61 HINIC_AUTONEG_DISABLED,
71 HINIC_SPEED_10MB_LINK = 0,
72 HINIC_SPEED_100MB_LINK,
73 HINIC_SPEED_1000MB_LINK,
74 HINIC_SPEED_10GB_LINK,
75 HINIC_SPEED_25GB_LINK,
76 HINIC_SPEED_40GB_LINK,
77 HINIC_SPEED_100GB_LINK,
79 HINIC_SPEED_UNKNOWN = 0xFF,
82 enum hinic_tso_state {
83 HINIC_TSO_DISABLE = 0,
87 struct hinic_port_mac_cmd {
95 unsigned char mac[ETH_ALEN];
98 struct hinic_port_mtu_cmd {
108 struct hinic_port_vlan_cmd {
117 struct hinic_port_rx_mode_cmd {
127 struct hinic_port_link_cmd {
137 struct hinic_port_state_cmd {
146 struct hinic_port_link_status {
156 struct hinic_port_func_state_cmd {
167 struct hinic_port_cap {
182 struct hinic_tso_config {
193 struct hinic_checksum_offload {
203 struct hinic_rq_num {
214 struct hinic_lro_config {
227 struct hinic_lro_timer {
232 u8 type; /* 0: set timer value, 1: get timer value */
233 u8 enable; /* when set lro time, enable should be 1 */
238 struct hinic_vlan_cfg {
248 struct hinic_rss_template_mgmt {
259 struct hinic_rss_template_key {
267 u8 key[HINIC_RSS_KEY_SIZE];
270 struct hinic_rss_context_tbl {
278 struct hinic_rss_context_table {
289 struct hinic_rss_indirect_tbl {
294 u8 entry[HINIC_RSS_INDIR_SIZE];
297 struct hinic_rss_indir_table {
305 u8 indir[HINIC_RSS_INDIR_SIZE];
308 struct hinic_rss_key {
316 u8 key[HINIC_RSS_KEY_SIZE];
319 struct hinic_rss_engine_type {
330 struct hinic_rss_config {
338 u8 rq_priority_number;
343 char name[ETH_GSTRING_LEN];
348 struct hinic_vport_stats {
349 u64 tx_unicast_pkts_vport;
350 u64 tx_unicast_bytes_vport;
351 u64 tx_multicast_pkts_vport;
352 u64 tx_multicast_bytes_vport;
353 u64 tx_broadcast_pkts_vport;
354 u64 tx_broadcast_bytes_vport;
356 u64 rx_unicast_pkts_vport;
357 u64 rx_unicast_bytes_vport;
358 u64 rx_multicast_pkts_vport;
359 u64 rx_multicast_bytes_vport;
360 u64 rx_broadcast_pkts_vport;
361 u64 rx_broadcast_bytes_vport;
363 u64 tx_discard_vport;
364 u64 rx_discard_vport;
369 struct hinic_phy_port_stats {
370 u64 mac_rx_total_pkt_num;
371 u64 mac_rx_total_oct_num;
372 u64 mac_rx_bad_pkt_num;
373 u64 mac_rx_bad_oct_num;
374 u64 mac_rx_good_pkt_num;
375 u64 mac_rx_good_oct_num;
376 u64 mac_rx_uni_pkt_num;
377 u64 mac_rx_multi_pkt_num;
378 u64 mac_rx_broad_pkt_num;
380 u64 mac_tx_total_pkt_num;
381 u64 mac_tx_total_oct_num;
382 u64 mac_tx_bad_pkt_num;
383 u64 mac_tx_bad_oct_num;
384 u64 mac_tx_good_pkt_num;
385 u64 mac_tx_good_oct_num;
386 u64 mac_tx_uni_pkt_num;
387 u64 mac_tx_multi_pkt_num;
388 u64 mac_tx_broad_pkt_num;
390 u64 mac_rx_fragment_pkt_num;
391 u64 mac_rx_undersize_pkt_num;
392 u64 mac_rx_undermin_pkt_num;
393 u64 mac_rx_64_oct_pkt_num;
394 u64 mac_rx_65_127_oct_pkt_num;
395 u64 mac_rx_128_255_oct_pkt_num;
396 u64 mac_rx_256_511_oct_pkt_num;
397 u64 mac_rx_512_1023_oct_pkt_num;
398 u64 mac_rx_1024_1518_oct_pkt_num;
399 u64 mac_rx_1519_2047_oct_pkt_num;
400 u64 mac_rx_2048_4095_oct_pkt_num;
401 u64 mac_rx_4096_8191_oct_pkt_num;
402 u64 mac_rx_8192_9216_oct_pkt_num;
403 u64 mac_rx_9217_12287_oct_pkt_num;
404 u64 mac_rx_12288_16383_oct_pkt_num;
405 u64 mac_rx_1519_max_bad_pkt_num;
406 u64 mac_rx_1519_max_good_pkt_num;
407 u64 mac_rx_oversize_pkt_num;
408 u64 mac_rx_jabber_pkt_num;
410 u64 mac_rx_pause_num;
411 u64 mac_rx_pfc_pkt_num;
412 u64 mac_rx_pfc_pri0_pkt_num;
413 u64 mac_rx_pfc_pri1_pkt_num;
414 u64 mac_rx_pfc_pri2_pkt_num;
415 u64 mac_rx_pfc_pri3_pkt_num;
416 u64 mac_rx_pfc_pri4_pkt_num;
417 u64 mac_rx_pfc_pri5_pkt_num;
418 u64 mac_rx_pfc_pri6_pkt_num;
419 u64 mac_rx_pfc_pri7_pkt_num;
420 u64 mac_rx_control_pkt_num;
421 u64 mac_rx_y1731_pkt_num;
422 u64 mac_rx_sym_err_pkt_num;
423 u64 mac_rx_fcs_err_pkt_num;
424 u64 mac_rx_send_app_good_pkt_num;
425 u64 mac_rx_send_app_bad_pkt_num;
427 u64 mac_tx_fragment_pkt_num;
428 u64 mac_tx_undersize_pkt_num;
429 u64 mac_tx_undermin_pkt_num;
430 u64 mac_tx_64_oct_pkt_num;
431 u64 mac_tx_65_127_oct_pkt_num;
432 u64 mac_tx_128_255_oct_pkt_num;
433 u64 mac_tx_256_511_oct_pkt_num;
434 u64 mac_tx_512_1023_oct_pkt_num;
435 u64 mac_tx_1024_1518_oct_pkt_num;
436 u64 mac_tx_1519_2047_oct_pkt_num;
437 u64 mac_tx_2048_4095_oct_pkt_num;
438 u64 mac_tx_4096_8191_oct_pkt_num;
439 u64 mac_tx_8192_9216_oct_pkt_num;
440 u64 mac_tx_9217_12287_oct_pkt_num;
441 u64 mac_tx_12288_16383_oct_pkt_num;
442 u64 mac_tx_1519_max_bad_pkt_num;
443 u64 mac_tx_1519_max_good_pkt_num;
444 u64 mac_tx_oversize_pkt_num;
445 u64 mac_tx_jabber_pkt_num;
447 u64 mac_tx_pause_num;
448 u64 mac_tx_pfc_pkt_num;
449 u64 mac_tx_pfc_pri0_pkt_num;
450 u64 mac_tx_pfc_pri1_pkt_num;
451 u64 mac_tx_pfc_pri2_pkt_num;
452 u64 mac_tx_pfc_pri3_pkt_num;
453 u64 mac_tx_pfc_pri4_pkt_num;
454 u64 mac_tx_pfc_pri5_pkt_num;
455 u64 mac_tx_pfc_pri6_pkt_num;
456 u64 mac_tx_pfc_pri7_pkt_num;
457 u64 mac_tx_control_pkt_num;
458 u64 mac_tx_y1731_pkt_num;
459 u64 mac_tx_1588_pkt_num;
460 u64 mac_tx_err_all_pkt_num;
461 u64 mac_tx_from_app_good_pkt_num;
462 u64 mac_tx_from_app_bad_pkt_num;
464 u64 mac_rx_higig2_ext_pkt_num;
465 u64 mac_rx_higig2_message_pkt_num;
466 u64 mac_rx_higig2_error_pkt_num;
467 u64 mac_rx_higig2_cpu_ctrl_pkt_num;
468 u64 mac_rx_higig2_unicast_pkt_num;
469 u64 mac_rx_higig2_broadcast_pkt_num;
470 u64 mac_rx_higig2_l2_multicast_pkt_num;
471 u64 mac_rx_higig2_l3_multicast_pkt_num;
473 u64 mac_tx_higig2_message_pkt_num;
474 u64 mac_tx_higig2_ext_pkt_num;
475 u64 mac_tx_higig2_cpu_ctrl_pkt_num;
476 u64 mac_tx_higig2_unicast_pkt_num;
477 u64 mac_tx_higig2_broadcast_pkt_num;
478 u64 mac_tx_higig2_l2_multicast_pkt_num;
479 u64 mac_tx_higig2_l3_multicast_pkt_num;
482 struct hinic_port_stats_info {
493 struct hinic_port_stats {
498 struct hinic_phy_port_stats stats;
501 struct hinic_cmd_vport_stats {
506 struct hinic_vport_stats stats;
509 int hinic_port_add_mac(struct hinic_dev *nic_dev, const u8 *addr,
512 int hinic_port_del_mac(struct hinic_dev *nic_dev, const u8 *addr,
515 int hinic_port_get_mac(struct hinic_dev *nic_dev, u8 *addr);
517 int hinic_port_set_mtu(struct hinic_dev *nic_dev, int new_mtu);
519 int hinic_port_add_vlan(struct hinic_dev *nic_dev, u16 vlan_id);
521 int hinic_port_del_vlan(struct hinic_dev *nic_dev, u16 vlan_id);
523 int hinic_port_set_rx_mode(struct hinic_dev *nic_dev, u32 rx_mode);
525 int hinic_port_link_state(struct hinic_dev *nic_dev,
526 enum hinic_port_link_state *link_state);
528 int hinic_port_set_state(struct hinic_dev *nic_dev,
529 enum hinic_port_state state);
531 int hinic_port_set_func_state(struct hinic_dev *nic_dev,
532 enum hinic_func_port_state state);
534 int hinic_port_get_cap(struct hinic_dev *nic_dev,
535 struct hinic_port_cap *port_cap);
537 int hinic_set_max_qnum(struct hinic_dev *nic_dev, u8 num_rqs);
539 int hinic_port_set_tso(struct hinic_dev *nic_dev, enum hinic_tso_state state);
541 int hinic_set_rx_csum_offload(struct hinic_dev *nic_dev, u32 en);
543 int hinic_set_rx_lro_state(struct hinic_dev *nic_dev, u8 lro_en,
544 u32 lro_timer, u32 wqe_num);
546 int hinic_set_rss_type(struct hinic_dev *nic_dev, u32 tmpl_idx,
547 struct hinic_rss_type rss_type);
549 int hinic_rss_set_indir_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
550 const u32 *indir_table);
552 int hinic_rss_set_template_tbl(struct hinic_dev *nic_dev, u32 template_id,
555 int hinic_rss_set_hash_engine(struct hinic_dev *nic_dev, u8 template_id,
558 int hinic_rss_cfg(struct hinic_dev *nic_dev, u8 rss_en, u8 template_id);
560 int hinic_rss_template_alloc(struct hinic_dev *nic_dev, u8 *tmpl_idx);
562 int hinic_rss_template_free(struct hinic_dev *nic_dev, u8 tmpl_idx);
564 void hinic_set_ethtool_ops(struct net_device *netdev);
566 int hinic_get_rss_type(struct hinic_dev *nic_dev, u32 tmpl_idx,
567 struct hinic_rss_type *rss_type);
569 int hinic_rss_get_indir_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
572 int hinic_rss_get_template_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
575 int hinic_rss_get_hash_engine(struct hinic_dev *nic_dev, u8 tmpl_idx,
578 int hinic_get_phy_port_stats(struct hinic_dev *nic_dev,
579 struct hinic_phy_port_stats *stats);
581 int hinic_get_vport_stats(struct hinic_dev *nic_dev,
582 struct hinic_vport_stats *stats);
584 int hinic_set_rx_vlan_offload(struct hinic_dev *nic_dev, u8 en);
586 int hinic_get_mgmt_version(struct hinic_dev *nic_dev, u8 *mgmt_ver);