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13 * derived from this software without specific prior written permission.
16 * ALTERNATIVELY, this software may be distributed under the terms of the
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30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
35 #include <linux/slab.h>
37 #include "fman_keygen.h"
39 /* Maximum number of HW Ports */
40 #define FMAN_MAX_NUM_OF_HW_PORTS 64
42 /* Maximum number of KeyGen Schemes */
43 #define FM_KG_MAX_NUM_OF_SCHEMES 32
45 /* Number of generic KeyGen Generic Extract Command Registers */
46 #define FM_KG_NUM_OF_GENERIC_REGS 8
49 #define DUMMY_PORT_ID 0
51 /* Select Scheme Value Register */
52 #define KG_SCH_DEF_USE_KGSE_DV_0 2
53 #define KG_SCH_DEF_USE_KGSE_DV_1 3
55 /* Registers Shifting values */
56 #define FM_KG_KGAR_NUM_SHIFT 16
57 #define KG_SCH_DEF_L4_PORT_SHIFT 8
58 #define KG_SCH_DEF_IP_ADDR_SHIFT 18
59 #define KG_SCH_HASH_CONFIG_SHIFT_SHIFT 24
61 /* KeyGen Registers bit field masks: */
63 /* Enable bit field mask for KeyGen General Configuration Register */
64 #define FM_KG_KGGCR_EN 0x80000000
66 /* KeyGen Global Registers bit field masks */
67 #define FM_KG_KGAR_GO 0x80000000
68 #define FM_KG_KGAR_READ 0x40000000
69 #define FM_KG_KGAR_WRITE 0x00000000
70 #define FM_KG_KGAR_SEL_SCHEME_ENTRY 0x00000000
71 #define FM_KG_KGAR_SCM_WSEL_UPDATE_CNT 0x00008000
73 #define FM_KG_KGAR_ERR 0x20000000
74 #define FM_KG_KGAR_SEL_CLS_PLAN_ENTRY 0x01000000
75 #define FM_KG_KGAR_SEL_PORT_ENTRY 0x02000000
76 #define FM_KG_KGAR_SEL_PORT_WSEL_SP 0x00008000
77 #define FM_KG_KGAR_SEL_PORT_WSEL_CPP 0x00004000
79 /* Error events exceptions */
80 #define FM_EX_KG_DOUBLE_ECC 0x80000000
81 #define FM_EX_KG_KEYSIZE_OVERFLOW 0x40000000
83 /* Scheme Registers bit field masks */
84 #define KG_SCH_MODE_EN 0x80000000
85 #define KG_SCH_VSP_NO_KSP_EN 0x80000000
86 #define KG_SCH_HASH_CONFIG_SYM 0x40000000
88 /* Known Protocol field codes */
89 #define KG_SCH_KN_PORT_ID 0x80000000
90 #define KG_SCH_KN_MACDST 0x40000000
91 #define KG_SCH_KN_MACSRC 0x20000000
92 #define KG_SCH_KN_TCI1 0x10000000
93 #define KG_SCH_KN_TCI2 0x08000000
94 #define KG_SCH_KN_ETYPE 0x04000000
95 #define KG_SCH_KN_PPPSID 0x02000000
96 #define KG_SCH_KN_PPPID 0x01000000
97 #define KG_SCH_KN_MPLS1 0x00800000
98 #define KG_SCH_KN_MPLS2 0x00400000
99 #define KG_SCH_KN_MPLS_LAST 0x00200000
100 #define KG_SCH_KN_IPSRC1 0x00100000
101 #define KG_SCH_KN_IPDST1 0x00080000
102 #define KG_SCH_KN_PTYPE1 0x00040000
103 #define KG_SCH_KN_IPTOS_TC1 0x00020000
104 #define KG_SCH_KN_IPV6FL1 0x00010000
105 #define KG_SCH_KN_IPSRC2 0x00008000
106 #define KG_SCH_KN_IPDST2 0x00004000
107 #define KG_SCH_KN_PTYPE2 0x00002000
108 #define KG_SCH_KN_IPTOS_TC2 0x00001000
109 #define KG_SCH_KN_IPV6FL2 0x00000800
110 #define KG_SCH_KN_GREPTYPE 0x00000400
111 #define KG_SCH_KN_IPSEC_SPI 0x00000200
112 #define KG_SCH_KN_IPSEC_NH 0x00000100
113 #define KG_SCH_KN_IPPID 0x00000080
114 #define KG_SCH_KN_L4PSRC 0x00000004
115 #define KG_SCH_KN_L4PDST 0x00000002
116 #define KG_SCH_KN_TFLG 0x00000001
119 #define NIA_ENG_BMI 0x00500000
120 #define NIA_BMI_AC_ENQ_FRAME 0x00000002
121 #define ENQUEUE_KG_DFLT_NIA (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME)
123 /* Hard-coded configuration:
124 * These values are used as hard-coded values for KeyGen configuration
125 * and they replace user selections for this hard-coded version
128 /* Hash distribution shift */
129 #define DEFAULT_HASH_DIST_FQID_SHIFT 0
132 #define DEFAULT_HASH_SHIFT 0
134 /* Symmetric hash usage:
136 * - the value for symmetric hash usage must be in accordance with hash
138 * - according to tests performed, spreading is not working if symmetric
139 * hash is set on true
140 * So ultimately symmetric hash functionality should be always disabled:
142 #define DEFAULT_SYMMETRIC_HASH false
144 /* Hash Key extraction fields: */
145 #define DEFAULT_HASH_KEY_EXTRACT_FIELDS \
146 (KG_SCH_KN_IPSRC1 | KG_SCH_KN_IPDST1 | \
147 KG_SCH_KN_L4PSRC | KG_SCH_KN_L4PDST)
149 /* Default values to be used as hash key in case IPv4 or L4 (TCP, UDP)
150 * don't exist in the frame
152 /* Default IPv4 address */
153 #define DEFAULT_HASH_KEY_IPv4_ADDR 0x0A0A0A0A
154 /* Default L4 port */
155 #define DEFAULT_HASH_KEY_L4_PORT 0x0B0B0B0B
157 /* KeyGen Memory Mapped Registers: */
159 /* Scheme Configuration RAM Registers */
160 struct fman_kg_scheme_regs {
161 u32 kgse_mode; /* 0x100: MODE */
162 u32 kgse_ekfc; /* 0x104: Extract Known Fields Command */
163 u32 kgse_ekdv; /* 0x108: Extract Known Default Value */
164 u32 kgse_bmch; /* 0x10C: Bit Mask Command High */
165 u32 kgse_bmcl; /* 0x110: Bit Mask Command Low */
166 u32 kgse_fqb; /* 0x114: Frame Queue Base */
167 u32 kgse_hc; /* 0x118: Hash Command */
168 u32 kgse_ppc; /* 0x11C: Policer Profile Command */
169 u32 kgse_gec[FM_KG_NUM_OF_GENERIC_REGS];
170 /* 0x120: Generic Extract Command */
172 /* 0x140: KeyGen Scheme Entry Statistic Packet Counter */
173 u32 kgse_dv0; /* 0x144: KeyGen Scheme Entry Default Value 0 */
174 u32 kgse_dv1; /* 0x148: KeyGen Scheme Entry Default Value 1 */
176 /* 0x14C: KeyGen Scheme Entry Coarse Classification Bit*/
177 u32 kgse_mv; /* 0x150: KeyGen Scheme Entry Match vector */
178 u32 kgse_om; /* 0x154: KeyGen Scheme Entry Operation Mode bits */
180 /* 0x158: KeyGen Scheme Entry Virtual Storage Profile */
183 /* Port Partition Configuration Registers */
184 struct fman_kg_pe_regs {
185 u32 fmkg_pe_sp; /* 0x100: KeyGen Port entry Scheme Partition */
187 /* 0x104: KeyGen Port Entry Classification Plan Partition */
190 /* General Configuration and Status Registers
191 * Global Statistic Counters
192 * KeyGen Global Registers
194 struct fman_kg_regs {
195 u32 fmkg_gcr; /* 0x000: KeyGen General Configuration Register */
196 u32 res004; /* 0x004: Reserved */
197 u32 res008; /* 0x008: Reserved */
198 u32 fmkg_eer; /* 0x00C: KeyGen Error Event Register */
199 u32 fmkg_eeer; /* 0x010: KeyGen Error Event Enable Register */
200 u32 res014; /* 0x014: Reserved */
201 u32 res018; /* 0x018: Reserved */
202 u32 fmkg_seer; /* 0x01C: KeyGen Scheme Error Event Register */
203 u32 fmkg_seeer; /* 0x020: KeyGen Scheme Error Event Enable Register */
204 u32 fmkg_gsr; /* 0x024: KeyGen Global Status Register */
205 u32 fmkg_tpc; /* 0x028: Total Packet Counter Register */
206 u32 fmkg_serc; /* 0x02C: Soft Error Capture Register */
207 u32 res030[4]; /* 0x030: Reserved */
208 u32 fmkg_fdor; /* 0x034: Frame Data Offset Register */
209 u32 fmkg_gdv0r; /* 0x038: Global Default Value Register 0 */
210 u32 fmkg_gdv1r; /* 0x03C: Global Default Value Register 1 */
211 u32 res04c[6]; /* 0x040: Reserved */
212 u32 fmkg_feer; /* 0x044: Force Error Event Register */
213 u32 res068[38]; /* 0x048: Reserved */
215 u32 fmkg_indirect[63]; /* 0x100: Indirect Access Registers */
216 struct fman_kg_scheme_regs fmkg_sch; /* Scheme Registers */
217 struct fman_kg_pe_regs fmkg_pe; /* Port Partition Registers */
219 u32 fmkg_ar; /* 0x1FC: KeyGen Action Register */
222 /* KeyGen Scheme data */
223 struct keygen_scheme {
224 bool used; /* Specifies if this scheme is used */
227 * schemes sharing between multiple ports is not
228 * currently supported
229 * so we have only one port id bound to a scheme
233 * Must be between 1 and 2^24-1
234 * If hash is used and an even distribution is
235 * expected according to hash_fqid_count,
236 * base_fqid must be aligned to hash_fqid_count
239 /* FQ range for hash distribution:
240 * Must be a power of 2
241 * Represents the range of queues for spreading
243 bool use_hashing; /* Usage of Hashing and spreading over FQ */
244 bool symmetric_hash; /* Symmetric Hash option usage */
246 /* Hash result right shift.
247 * Select the 24 bits out of the 64 hash result.
248 * 0 means using the 24 LSB's, otherwise
249 * use the 24 LSB's after shifting right
251 u32 match_vector; /* Match Vector */
254 /* KeyGen driver data */
256 struct keygen_scheme schemes[FM_KG_MAX_NUM_OF_SCHEMES];
257 /* Array of schemes */
258 struct fman_kg_regs __iomem *keygen_regs; /* KeyGen registers */
261 /* keygen_write_ar_wait
263 * Write Action Register with specified value, wait for GO bit field to be
264 * idle and then read the error
266 * regs: KeyGen registers
267 * fmkg_ar: Action Register value
269 * Return: Zero for success or error code in case of failure
271 static int keygen_write_ar_wait(struct fman_kg_regs __iomem *regs, u32 fmkg_ar)
273 iowrite32be(fmkg_ar, ®s->fmkg_ar);
275 /* Wait for GO bit field to be idle */
276 while (fmkg_ar & FM_KG_KGAR_GO)
277 fmkg_ar = ioread32be(®s->fmkg_ar);
279 if (fmkg_ar & FM_KG_KGAR_ERR)
287 * Build Action Register value for scheme settings
289 * scheme_id: Scheme ID
290 * update_counter: update scheme counter
291 * write: true for action to write the scheme or false for read action
295 static u32 build_ar_scheme(u8 scheme_id, bool update_counter, bool write)
297 u32 rw = (u32)(write ? FM_KG_KGAR_WRITE : FM_KG_KGAR_READ);
299 return (u32)(FM_KG_KGAR_GO |
301 FM_KG_KGAR_SEL_SCHEME_ENTRY |
303 ((u32)scheme_id << FM_KG_KGAR_NUM_SHIFT) |
304 (update_counter ? FM_KG_KGAR_SCM_WSEL_UPDATE_CNT : 0));
307 /* build_ar_bind_scheme
309 * Build Action Register value for port binding to schemes
311 * hwport_id: HW Port ID
312 * write: true for action to write the bind or false for read action
316 static u32 build_ar_bind_scheme(u8 hwport_id, bool write)
318 u32 rw = write ? (u32)FM_KG_KGAR_WRITE : (u32)FM_KG_KGAR_READ;
320 return (u32)(FM_KG_KGAR_GO |
322 FM_KG_KGAR_SEL_PORT_ENTRY |
324 FM_KG_KGAR_SEL_PORT_WSEL_SP);
329 * Write Scheme Partition Register with specified value
331 * regs: KeyGen Registers
332 * sp: Scheme Partition register value
333 * add: true to add a scheme partition or false to clear
337 static void keygen_write_sp(struct fman_kg_regs __iomem *regs, u32 sp, bool add)
341 tmp = ioread32be(®s->fmkg_pe.fmkg_pe_sp);
348 iowrite32be(tmp, ®s->fmkg_pe.fmkg_pe_sp);
351 /* build_ar_bind_cls_plan
353 * Build Action Register value for Classification Plan
355 * hwport_id: HW Port ID
356 * write: true for action to write the CP or false for read action
360 static u32 build_ar_bind_cls_plan(u8 hwport_id, bool write)
362 u32 rw = write ? (u32)FM_KG_KGAR_WRITE : (u32)FM_KG_KGAR_READ;
364 return (u32)(FM_KG_KGAR_GO |
366 FM_KG_KGAR_SEL_PORT_ENTRY |
368 FM_KG_KGAR_SEL_PORT_WSEL_CPP);
373 * Write Classification Plan Partition Register with specified value
375 * regs: KeyGen Registers
376 * cpp: CPP register value
380 static void keygen_write_cpp(struct fman_kg_regs __iomem *regs, u32 cpp)
382 iowrite32be(cpp, ®s->fmkg_pe.fmkg_pe_cpp);
385 /* keygen_write_scheme
387 * Write all Schemes Registers with specified values
389 * regs: KeyGen Registers
390 * scheme_id: Scheme ID
391 * scheme_regs: Scheme registers values desired to be written
392 * update_counter: update scheme counter
394 * Return: Zero for success or error code in case of failure
396 static int keygen_write_scheme(struct fman_kg_regs __iomem *regs, u8 scheme_id,
397 struct fman_kg_scheme_regs *scheme_regs,
403 /* Write indirect scheme registers */
404 iowrite32be(scheme_regs->kgse_mode, ®s->fmkg_sch.kgse_mode);
405 iowrite32be(scheme_regs->kgse_ekfc, ®s->fmkg_sch.kgse_ekfc);
406 iowrite32be(scheme_regs->kgse_ekdv, ®s->fmkg_sch.kgse_ekdv);
407 iowrite32be(scheme_regs->kgse_bmch, ®s->fmkg_sch.kgse_bmch);
408 iowrite32be(scheme_regs->kgse_bmcl, ®s->fmkg_sch.kgse_bmcl);
409 iowrite32be(scheme_regs->kgse_fqb, ®s->fmkg_sch.kgse_fqb);
410 iowrite32be(scheme_regs->kgse_hc, ®s->fmkg_sch.kgse_hc);
411 iowrite32be(scheme_regs->kgse_ppc, ®s->fmkg_sch.kgse_ppc);
412 iowrite32be(scheme_regs->kgse_spc, ®s->fmkg_sch.kgse_spc);
413 iowrite32be(scheme_regs->kgse_dv0, ®s->fmkg_sch.kgse_dv0);
414 iowrite32be(scheme_regs->kgse_dv1, ®s->fmkg_sch.kgse_dv1);
415 iowrite32be(scheme_regs->kgse_ccbs, ®s->fmkg_sch.kgse_ccbs);
416 iowrite32be(scheme_regs->kgse_mv, ®s->fmkg_sch.kgse_mv);
417 iowrite32be(scheme_regs->kgse_om, ®s->fmkg_sch.kgse_om);
418 iowrite32be(scheme_regs->kgse_vsp, ®s->fmkg_sch.kgse_vsp);
420 for (i = 0 ; i < FM_KG_NUM_OF_GENERIC_REGS ; i++)
421 iowrite32be(scheme_regs->kgse_gec[i],
422 ®s->fmkg_sch.kgse_gec[i]);
424 /* Write AR (Action register) */
425 ar_reg = build_ar_scheme(scheme_id, update_counter, true);
426 err = keygen_write_ar_wait(regs, ar_reg);
428 pr_err("Writing Action Register failed\n");
435 /* get_free_scheme_id
437 * Find the first free scheme available to be used
439 * keygen: KeyGen handle
440 * scheme_id: pointer to scheme id
442 * Return: 0 on success, -EINVAL when the are no available free schemes
444 static int get_free_scheme_id(struct fman_keygen *keygen, u8 *scheme_id)
448 for (i = 0; i < FM_KG_MAX_NUM_OF_SCHEMES; i++)
449 if (!keygen->schemes[i].used) {
459 * Provides the scheme for specified ID
461 * keygen: KeyGen handle
462 * scheme_id: Scheme ID
464 * Return: handle to required scheme
466 static struct keygen_scheme *get_scheme(struct fman_keygen *keygen,
469 if (scheme_id >= FM_KG_MAX_NUM_OF_SCHEMES)
471 return &keygen->schemes[scheme_id];
474 /* keygen_bind_port_to_schemes
476 * Bind the port to schemes
478 * keygen: KeyGen handle
479 * scheme_id: id of the scheme to bind to
480 * bind: true to bind the port or false to unbind it
482 * Return: Zero for success or error code in case of failure
484 static int keygen_bind_port_to_schemes(struct fman_keygen *keygen,
488 struct fman_kg_regs __iomem *keygen_regs = keygen->keygen_regs;
489 struct keygen_scheme *scheme;
491 u32 schemes_vector = 0;
494 scheme = get_scheme(keygen, scheme_id);
496 pr_err("Requested Scheme does not exist\n");
500 pr_err("Cannot bind port to an invalid scheme\n");
504 schemes_vector |= 1 << (31 - scheme_id);
506 ar_reg = build_ar_bind_scheme(scheme->hw_port_id, false);
507 err = keygen_write_ar_wait(keygen_regs, ar_reg);
509 pr_err("Reading Action Register failed\n");
513 keygen_write_sp(keygen_regs, schemes_vector, bind);
515 ar_reg = build_ar_bind_scheme(scheme->hw_port_id, true);
516 err = keygen_write_ar_wait(keygen_regs, ar_reg);
518 pr_err("Writing Action Register failed\n");
525 /* keygen_scheme_setup
527 * Setup the scheme according to required configuration
529 * keygen: KeyGen handle
530 * scheme_id: scheme ID
531 * enable: true to enable scheme or false to disable it
533 * Return: Zero for success or error code in case of failure
535 static int keygen_scheme_setup(struct fman_keygen *keygen, u8 scheme_id,
538 struct fman_kg_regs __iomem *keygen_regs = keygen->keygen_regs;
539 struct fman_kg_scheme_regs scheme_regs;
540 struct keygen_scheme *scheme;
544 scheme = get_scheme(keygen, scheme_id);
546 pr_err("Requested Scheme does not exist\n");
549 if (enable && scheme->used) {
550 pr_err("The requested Scheme is already used\n");
554 /* Clear scheme registers */
555 memset(&scheme_regs, 0, sizeof(struct fman_kg_scheme_regs));
557 /* Setup all scheme registers: */
562 tmp_reg |= KG_SCH_MODE_EN;
563 /* Enqueue frame NIA */
564 tmp_reg |= ENQUEUE_KG_DFLT_NIA;
567 scheme_regs.kgse_mode = tmp_reg;
569 scheme_regs.kgse_mv = scheme->match_vector;
571 /* Scheme don't override StorageProfile:
572 * valid only for DPAA_VERSION >= 11
574 scheme_regs.kgse_vsp = KG_SCH_VSP_NO_KSP_EN;
576 /* Configure Hard-Coded Rx Hashing: */
578 if (scheme->use_hashing) {
579 /* configure kgse_ekfc */
580 scheme_regs.kgse_ekfc = DEFAULT_HASH_KEY_EXTRACT_FIELDS;
582 /* configure kgse_ekdv */
584 tmp_reg |= (KG_SCH_DEF_USE_KGSE_DV_0 <<
585 KG_SCH_DEF_IP_ADDR_SHIFT);
586 tmp_reg |= (KG_SCH_DEF_USE_KGSE_DV_1 <<
587 KG_SCH_DEF_L4_PORT_SHIFT);
588 scheme_regs.kgse_ekdv = tmp_reg;
590 /* configure kgse_dv0 */
591 scheme_regs.kgse_dv0 = DEFAULT_HASH_KEY_IPv4_ADDR;
592 /* configure kgse_dv1 */
593 scheme_regs.kgse_dv1 = DEFAULT_HASH_KEY_L4_PORT;
595 /* configure kgse_hc */
597 tmp_reg |= ((scheme->hash_fqid_count - 1) <<
598 DEFAULT_HASH_DIST_FQID_SHIFT);
599 tmp_reg |= scheme->hashShift << KG_SCH_HASH_CONFIG_SHIFT_SHIFT;
601 if (scheme->symmetric_hash) {
602 /* Normally extraction key should be verified if
603 * complies with symmetric hash
604 * But because extraction is hard-coded, we are sure
605 * the key is symmetric
607 tmp_reg |= KG_SCH_HASH_CONFIG_SYM;
609 scheme_regs.kgse_hc = tmp_reg;
611 scheme_regs.kgse_ekfc = 0;
612 scheme_regs.kgse_hc = 0;
613 scheme_regs.kgse_ekdv = 0;
614 scheme_regs.kgse_dv0 = 0;
615 scheme_regs.kgse_dv1 = 0;
618 /* configure kgse_fqb: Scheme FQID base */
620 tmp_reg |= scheme->base_fqid;
621 scheme_regs.kgse_fqb = tmp_reg;
623 /* features not used by hard-coded configuration */
624 scheme_regs.kgse_bmch = 0;
625 scheme_regs.kgse_bmcl = 0;
626 scheme_regs.kgse_spc = 0;
628 /* Write scheme registers */
629 err = keygen_write_scheme(keygen_regs, scheme_id, &scheme_regs, true);
631 pr_err("Writing scheme registers failed\n");
635 /* Update used field for Scheme */
636 scheme->used = enable;
643 * KeyGen initialization:
644 * Initializes and enables KeyGen, allocate driver memory, setup registers,
645 * clear port bindings, invalidate all schemes
647 * keygen_regs: KeyGen registers base address
649 * Return: Handle to KeyGen driver
651 struct fman_keygen *keygen_init(struct fman_kg_regs __iomem *keygen_regs)
653 struct fman_keygen *keygen;
657 /* Allocate memory for KeyGen driver */
658 keygen = kzalloc(sizeof(*keygen), GFP_KERNEL);
662 keygen->keygen_regs = keygen_regs;
664 /* KeyGen initialization (for Master partition):
665 * Setup KeyGen registers
667 iowrite32be(ENQUEUE_KG_DFLT_NIA, &keygen_regs->fmkg_gcr);
669 iowrite32be(FM_EX_KG_DOUBLE_ECC | FM_EX_KG_KEYSIZE_OVERFLOW,
670 &keygen_regs->fmkg_eer);
672 iowrite32be(0, &keygen_regs->fmkg_fdor);
673 iowrite32be(0, &keygen_regs->fmkg_gdv0r);
674 iowrite32be(0, &keygen_regs->fmkg_gdv1r);
676 /* Clear binding between ports to schemes and classification plans
677 * so that all ports are not bound to any scheme/classification plan
679 for (i = 0; i < FMAN_MAX_NUM_OF_HW_PORTS; i++) {
680 /* Clear all pe sp schemes registers */
681 keygen_write_sp(keygen_regs, 0xffffffff, false);
682 ar = build_ar_bind_scheme(i, true);
683 keygen_write_ar_wait(keygen_regs, ar);
685 /* Clear all pe cpp classification plans registers */
686 keygen_write_cpp(keygen_regs, 0);
687 ar = build_ar_bind_cls_plan(i, true);
688 keygen_write_ar_wait(keygen_regs, ar);
691 /* Enable all scheme interrupts */
692 iowrite32be(0xFFFFFFFF, &keygen_regs->fmkg_seer);
693 iowrite32be(0xFFFFFFFF, &keygen_regs->fmkg_seeer);
696 iowrite32be(ioread32be(&keygen_regs->fmkg_gcr) | FM_KG_KGGCR_EN,
697 &keygen_regs->fmkg_gcr);
701 EXPORT_SYMBOL(keygen_init);
703 /* keygen_port_hashing_init
705 * Initializes a port for Rx Hashing with specified configuration parameters
707 * keygen: KeyGen handle
708 * hw_port_id: HW Port ID
709 * hash_base_fqid: Hashing Base FQID used for spreading
710 * hash_size: Hashing size
712 * Return: Zero for success or error code in case of failure
714 int keygen_port_hashing_init(struct fman_keygen *keygen, u8 hw_port_id,
715 u32 hash_base_fqid, u32 hash_size)
717 struct keygen_scheme *scheme;
721 /* Validate Scheme configuration parameters */
722 if (hash_base_fqid == 0 || (hash_base_fqid & ~0x00FFFFFF)) {
723 pr_err("Base FQID must be between 1 and 2^24-1\n");
726 if (hash_size == 0 || (hash_size & (hash_size - 1)) != 0) {
727 pr_err("Hash size must be power of two\n");
731 /* Find a free scheme */
732 err = get_free_scheme_id(keygen, &scheme_id);
734 pr_err("The maximum number of available Schemes has been exceeded\n");
738 /* Create and configure Hard-Coded Scheme: */
740 scheme = get_scheme(keygen, scheme_id);
742 pr_err("Requested Scheme does not exist\n");
746 pr_err("The requested Scheme is already used\n");
750 /* Clear all scheme fields because the scheme may have been
753 memset(scheme, 0, sizeof(struct keygen_scheme));
756 scheme->hw_port_id = hw_port_id;
757 scheme->use_hashing = true;
758 scheme->base_fqid = hash_base_fqid;
759 scheme->hash_fqid_count = hash_size;
760 scheme->symmetric_hash = DEFAULT_SYMMETRIC_HASH;
761 scheme->hashShift = DEFAULT_HASH_SHIFT;
763 /* All Schemes in hard-coded configuration
764 * are Indirect Schemes
766 scheme->match_vector = 0;
768 err = keygen_scheme_setup(keygen, scheme_id, true);
770 pr_err("Scheme setup failed\n");
774 /* Bind Rx port to Scheme */
775 err = keygen_bind_port_to_schemes(keygen, scheme_id, true);
777 pr_err("Binding port to schemes failed\n");
783 EXPORT_SYMBOL(keygen_port_hashing_init);