2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
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10 * OpenIB.org BSD license below:
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17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
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23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F)
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
204 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
209 for ( ; nflit; nflit--, mbox_addr += 8)
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
214 * Handle a FW assertion reported in a mailbox.
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
218 struct fw_debug_cmd asrt;
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
221 dev_alert(adap->pdev_dev,
222 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
223 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
224 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
228 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
229 * @adapter: the adapter
230 * @cmd: the Firmware Mailbox Command or Reply
231 * @size: command length in bytes
232 * @access: the time (ms) needed to access the Firmware Mailbox
233 * @execute: the time (ms) the command spent being executed
235 static void t4_record_mbox(struct adapter *adapter,
236 const __be64 *cmd, unsigned int size,
237 int access, int execute)
239 struct mbox_cmd_log *log = adapter->mbox_log;
240 struct mbox_cmd *entry;
243 entry = mbox_cmd_log_entry(log, log->cursor++);
244 if (log->cursor == log->size)
247 for (i = 0; i < size / 8; i++)
248 entry->cmd[i] = be64_to_cpu(cmd[i]);
249 while (i < MBOX_LEN / 8)
251 entry->timestamp = jiffies;
252 entry->seqno = log->seqno++;
253 entry->access = access;
254 entry->execute = execute;
258 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
260 * @mbox: index of the mailbox to use
261 * @cmd: the command to write
262 * @size: command length in bytes
263 * @rpl: where to optionally store the reply
264 * @sleep_ok: if true we may sleep while awaiting command completion
265 * @timeout: time to wait for command to finish before timing out
267 * Sends the given command to FW through the selected mailbox and waits
268 * for the FW to execute the command. If @rpl is not %NULL it is used to
269 * store the FW's reply to the command. The command and its optional
270 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
271 * to respond. @sleep_ok determines whether we may sleep while awaiting
272 * the response. If sleeping is allowed we use progressive backoff
275 * The return value is 0 on success or a negative errno on failure. A
276 * failure can happen either because we are not able to execute the
277 * command or FW executes it but signals an error. In the latter case
278 * the return value is the error code indicated by FW (negated).
280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
281 int size, void *rpl, bool sleep_ok, int timeout)
283 static const int delay[] = {
284 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
291 int i, ms, delay_idx, ret;
292 const __be64 *p = cmd;
293 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
294 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
295 __be64 cmd_rpl[MBOX_LEN / 8];
298 if ((size & 15) || size > MBOX_LEN)
302 * If the device is off-line, as in EEH, commands will time out.
303 * Fail them early so we don't waste time waiting.
305 if (adap->pdev->error_state != pci_channel_io_normal)
308 /* If we have a negative timeout, that implies that we can't sleep. */
314 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
315 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
316 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
318 if (v != MBOX_OWNER_DRV) {
319 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
320 t4_record_mbox(adap, cmd, size, access, ret);
324 /* Copy in the new mailbox command and send it on its way ... */
325 t4_record_mbox(adap, cmd, size, access, 0);
326 for (i = 0; i < size; i += 8)
327 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
329 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
330 t4_read_reg(adap, ctl_reg); /* flush write */
336 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
340 ms = delay[delay_idx]; /* last element may repeat */
341 if (delay_idx < ARRAY_SIZE(delay) - 1)
347 v = t4_read_reg(adap, ctl_reg);
348 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
349 if (!(v & MBMSGVALID_F)) {
350 t4_write_reg(adap, ctl_reg, 0);
354 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
355 res = be64_to_cpu(cmd_rpl[0]);
357 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
358 fw_asrt(adap, data_reg);
359 res = FW_CMD_RETVAL_V(EIO);
361 memcpy(rpl, cmd_rpl, size);
364 t4_write_reg(adap, ctl_reg, 0);
367 t4_record_mbox(adap, cmd_rpl,
368 MBOX_LEN, access, execute);
369 return -FW_CMD_RETVAL_G((int)res);
373 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
374 t4_record_mbox(adap, cmd, size, access, ret);
375 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
376 *(const u8 *)cmd, mbox);
377 t4_report_fw_error(adap);
381 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
382 void *rpl, bool sleep_ok)
384 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
388 static int t4_edc_err_read(struct adapter *adap, int idx)
390 u32 edc_ecc_err_addr_reg;
393 if (is_t4(adap->params.chip)) {
394 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
397 if (idx != 0 && idx != 1) {
398 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
402 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
403 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
406 "edc%d err addr 0x%x: 0x%x.\n",
407 idx, edc_ecc_err_addr_reg,
408 t4_read_reg(adap, edc_ecc_err_addr_reg));
410 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
412 (unsigned long long)t4_read_reg64(adap, rdata_reg),
413 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
414 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
415 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
416 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
417 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
418 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
419 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
420 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
426 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
428 * @win: PCI-E Memory Window to use
429 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
430 * @addr: address within indicated memory type
431 * @len: amount of memory to transfer
432 * @hbuf: host memory buffer
433 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
435 * Reads/writes an [almost] arbitrary memory region in the firmware: the
436 * firmware memory address and host buffer must be aligned on 32-bit
437 * boudaries; the length may be arbitrary. The memory is transferred as
438 * a raw byte sequence from/to the firmware's memory. If this memory
439 * contains data structures which contain multi-byte integers, it's the
440 * caller's responsibility to perform appropriate byte order conversions.
442 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
443 u32 len, void *hbuf, int dir)
445 u32 pos, offset, resid, memoffset;
446 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
449 /* Argument sanity checks ...
451 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
455 /* It's convenient to be able to handle lengths which aren't a
456 * multiple of 32-bits because we often end up transferring files to
457 * the firmware. So we'll handle that by normalizing the length here
458 * and then handling any residual transfer at the end.
463 /* Offset into the region of memory which is being accessed
466 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
467 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
469 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
470 if (mtype != MEM_MC1)
471 memoffset = (mtype * (edc_size * 1024 * 1024));
473 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
474 MA_EXT_MEMORY0_BAR_A));
475 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
478 /* Determine the PCIE_MEM_ACCESS_OFFSET */
479 addr = addr + memoffset;
481 /* Each PCI-E Memory Window is programmed with a window size -- or
482 * "aperture" -- which controls the granularity of its mapping onto
483 * adapter memory. We need to grab that aperture in order to know
484 * how to use the specified window. The window is also programmed
485 * with the base address of the Memory Window in BAR0's address
486 * space. For T4 this is an absolute PCI-E Bus Address. For T5
487 * the address is relative to BAR0.
489 mem_reg = t4_read_reg(adap,
490 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
492 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
493 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
494 if (is_t4(adap->params.chip))
495 mem_base -= adap->t4_bar0;
496 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
498 /* Calculate our initial PCI-E Memory Window Position and Offset into
501 pos = addr & ~(mem_aperture-1);
504 /* Set up initial PCI-E Memory Window to cover the start of our
505 * transfer. (Read it back to ensure that changes propagate before we
506 * attempt to use the new value.)
509 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
512 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
514 /* Transfer data to/from the adapter as long as there's an integral
515 * number of 32-bit transfers to complete.
517 * A note on Endianness issues:
519 * The "register" reads and writes below from/to the PCI-E Memory
520 * Window invoke the standard adapter Big-Endian to PCI-E Link
521 * Little-Endian "swizzel." As a result, if we have the following
522 * data in adapter memory:
524 * Memory: ... | b0 | b1 | b2 | b3 | ...
525 * Address: i+0 i+1 i+2 i+3
527 * Then a read of the adapter memory via the PCI-E Memory Window
532 * [ b3 | b2 | b1 | b0 ]
534 * If this value is stored into local memory on a Little-Endian system
535 * it will show up correctly in local memory as:
537 * ( ..., b0, b1, b2, b3, ... )
539 * But on a Big-Endian system, the store will show up in memory
540 * incorrectly swizzled as:
542 * ( ..., b3, b2, b1, b0, ... )
544 * So we need to account for this in the reads and writes to the
545 * PCI-E Memory Window below by undoing the register read/write
549 if (dir == T4_MEMORY_READ)
550 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
553 t4_write_reg(adap, mem_base + offset,
554 (__force u32)cpu_to_le32(*buf++));
555 offset += sizeof(__be32);
556 len -= sizeof(__be32);
558 /* If we've reached the end of our current window aperture,
559 * move the PCI-E Memory Window on to the next. Note that
560 * doing this here after "len" may be 0 allows us to set up
561 * the PCI-E Memory Window for a possible final residual
564 if (offset == mem_aperture) {
568 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
571 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
576 /* If the original transfer had a length which wasn't a multiple of
577 * 32-bits, now's where we need to finish off the transfer of the
578 * residual amount. The PCI-E Memory Window has already been moved
579 * above (if necessary) to cover this final transfer.
589 if (dir == T4_MEMORY_READ) {
590 last.word = le32_to_cpu(
591 (__force __le32)t4_read_reg(adap,
593 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
594 bp[i] = last.byte[i];
597 for (i = resid; i < 4; i++)
599 t4_write_reg(adap, mem_base + offset,
600 (__force u32)cpu_to_le32(last.word));
607 /* Return the specified PCI-E Configuration Space register from our Physical
608 * Function. We try first via a Firmware LDST Command since we prefer to let
609 * the firmware own all of these registers, but if that fails we go for it
610 * directly ourselves.
612 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
614 u32 val, ldst_addrspace;
616 /* If fw_attach != 0, construct and send the Firmware LDST Command to
617 * retrieve the specified PCI-E Configuration Space register.
619 struct fw_ldst_cmd ldst_cmd;
622 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
623 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
624 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
628 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
629 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
630 ldst_cmd.u.pcie.ctrl_to_fn =
631 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
632 ldst_cmd.u.pcie.r = reg;
634 /* If the LDST Command succeeds, return the result, otherwise
635 * fall through to reading it directly ourselves ...
637 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
640 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
642 /* Read the desired Configuration Space register via the PCI-E
643 * Backdoor mechanism.
645 t4_hw_pci_read_cfg4(adap, reg, &val);
649 /* Get the window based on base passed to it.
650 * Window aperture is currently unhandled, but there is no use case for it
653 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
658 if (is_t4(adap->params.chip)) {
661 /* Truncation intentional: we only read the bottom 32-bits of
662 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
663 * mechanism to read BAR0 instead of using
664 * pci_resource_start() because we could be operating from
665 * within a Virtual Machine which is trapping our accesses to
666 * our Configuration Space and we need to set up the PCI-E
667 * Memory Window decoders with the actual addresses which will
668 * be coming across the PCI-E link.
670 bar0 = t4_read_pcie_cfg4(adap, pci_base);
672 adap->t4_bar0 = bar0;
674 ret = bar0 + memwin_base;
676 /* For T5, only relative offset inside the PCIe BAR is passed */
682 /* Get the default utility window (win0) used by everyone */
683 u32 t4_get_util_window(struct adapter *adap)
685 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
686 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
689 /* Set up memory window for accessing adapter memory ranges. (Read
690 * back MA register to ensure that changes propagate before we attempt
691 * to use the new values.)
693 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
696 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
697 memwin_base | BIR_V(0) |
698 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
700 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
704 * t4_get_regs_len - return the size of the chips register set
705 * @adapter: the adapter
707 * Returns the size of the chip's BAR0 register space.
709 unsigned int t4_get_regs_len(struct adapter *adapter)
711 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
713 switch (chip_version) {
715 return T4_REGMAP_SIZE;
719 return T5_REGMAP_SIZE;
722 dev_err(adapter->pdev_dev,
723 "Unsupported chip version %d\n", chip_version);
728 * t4_get_regs - read chip registers into provided buffer
730 * @buf: register buffer
731 * @buf_size: size (in bytes) of register buffer
733 * If the provided register buffer isn't large enough for the chip's
734 * full register range, the register dump will be truncated to the
735 * register buffer's size.
737 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
739 static const unsigned int t4_reg_ranges[] = {
1197 static const unsigned int t5_reg_ranges[] = {
1972 static const unsigned int t6_reg_ranges[] = {
2549 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2550 const unsigned int *reg_ranges;
2551 int reg_ranges_size, range;
2552 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2554 /* Select the right set of register ranges to dump depending on the
2555 * adapter chip type.
2557 switch (chip_version) {
2559 reg_ranges = t4_reg_ranges;
2560 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2564 reg_ranges = t5_reg_ranges;
2565 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2569 reg_ranges = t6_reg_ranges;
2570 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2574 dev_err(adap->pdev_dev,
2575 "Unsupported chip version %d\n", chip_version);
2579 /* Clear the register buffer and insert the appropriate register
2580 * values selected by the above register ranges.
2582 memset(buf, 0, buf_size);
2583 for (range = 0; range < reg_ranges_size; range += 2) {
2584 unsigned int reg = reg_ranges[range];
2585 unsigned int last_reg = reg_ranges[range + 1];
2586 u32 *bufp = (u32 *)((char *)buf + reg);
2588 /* Iterate across the register range filling in the register
2589 * buffer but don't write past the end of the register buffer.
2591 while (reg <= last_reg && bufp < buf_end) {
2592 *bufp++ = t4_read_reg(adap, reg);
2598 #define EEPROM_STAT_ADDR 0x7bfc
2599 #define VPD_BASE 0x400
2600 #define VPD_BASE_OLD 0
2601 #define VPD_LEN 1024
2602 #define CHELSIO_VPD_UNIQUE_ID 0x82
2605 * t4_seeprom_wp - enable/disable EEPROM write protection
2606 * @adapter: the adapter
2607 * @enable: whether to enable or disable write protection
2609 * Enables or disables write protection on the serial EEPROM.
2611 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2613 unsigned int v = enable ? 0xc : 0;
2614 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2615 return ret < 0 ? ret : 0;
2619 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2620 * @adapter: adapter to read
2621 * @p: where to store the parameters
2623 * Reads card parameters stored in VPD EEPROM.
2625 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2627 int i, ret = 0, addr;
2630 unsigned int vpdr_len, kw_offset, id_len;
2632 vpd = vmalloc(VPD_LEN);
2636 /* Card information normally starts at VPD_BASE but early cards had
2639 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2643 /* The VPD shall have a unique identifier specified by the PCI SIG.
2644 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2645 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2646 * is expected to automatically put this entry at the
2647 * beginning of the VPD.
2649 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2651 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2655 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2656 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2661 id_len = pci_vpd_lrdt_size(vpd);
2662 if (id_len > ID_LEN)
2665 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2667 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2672 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2673 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2674 if (vpdr_len + kw_offset > VPD_LEN) {
2675 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2680 #define FIND_VPD_KW(var, name) do { \
2681 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2683 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2687 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2690 FIND_VPD_KW(i, "RV");
2691 for (csum = 0; i >= 0; i--)
2695 dev_err(adapter->pdev_dev,
2696 "corrupted VPD EEPROM, actual csum %u\n", csum);
2701 FIND_VPD_KW(ec, "EC");
2702 FIND_VPD_KW(sn, "SN");
2703 FIND_VPD_KW(pn, "PN");
2704 FIND_VPD_KW(na, "NA");
2707 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2709 memcpy(p->ec, vpd + ec, EC_LEN);
2711 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2712 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2714 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2715 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2717 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2718 strim((char *)p->na);
2722 return ret < 0 ? ret : 0;
2726 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2727 * @adapter: adapter to read
2728 * @p: where to store the parameters
2730 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2731 * Clock. This can only be called after a connection to the firmware
2734 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2736 u32 cclk_param, cclk_val;
2739 /* Grab the raw VPD parameters.
2741 ret = t4_get_raw_vpd_params(adapter, p);
2745 /* Ask firmware for the Core Clock since it knows how to translate the
2746 * Reference Clock ('V2') VPD field into a Core Clock value ...
2748 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2749 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2750 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2751 1, &cclk_param, &cclk_val);
2760 /* serial flash and firmware constants */
2762 SF_ATTEMPTS = 10, /* max retries for SF operations */
2764 /* flash command opcodes */
2765 SF_PROG_PAGE = 2, /* program page */
2766 SF_WR_DISABLE = 4, /* disable writes */
2767 SF_RD_STATUS = 5, /* read status register */
2768 SF_WR_ENABLE = 6, /* enable writes */
2769 SF_RD_DATA_FAST = 0xb, /* read flash */
2770 SF_RD_ID = 0x9f, /* read ID */
2771 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2773 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2777 * sf1_read - read data from the serial flash
2778 * @adapter: the adapter
2779 * @byte_cnt: number of bytes to read
2780 * @cont: whether another operation will be chained
2781 * @lock: whether to lock SF for PL access only
2782 * @valp: where to store the read data
2784 * Reads up to 4 bytes of data from the serial flash. The location of
2785 * the read needs to be specified prior to calling this by issuing the
2786 * appropriate commands to the serial flash.
2788 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2789 int lock, u32 *valp)
2793 if (!byte_cnt || byte_cnt > 4)
2795 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2797 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2798 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2799 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2801 *valp = t4_read_reg(adapter, SF_DATA_A);
2806 * sf1_write - write data to the serial flash
2807 * @adapter: the adapter
2808 * @byte_cnt: number of bytes to write
2809 * @cont: whether another operation will be chained
2810 * @lock: whether to lock SF for PL access only
2811 * @val: value to write
2813 * Writes up to 4 bytes of data to the serial flash. The location of
2814 * the write needs to be specified prior to calling this by issuing the
2815 * appropriate commands to the serial flash.
2817 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2820 if (!byte_cnt || byte_cnt > 4)
2822 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2824 t4_write_reg(adapter, SF_DATA_A, val);
2825 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2826 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2827 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2831 * flash_wait_op - wait for a flash operation to complete
2832 * @adapter: the adapter
2833 * @attempts: max number of polls of the status register
2834 * @delay: delay between polls in ms
2836 * Wait for a flash operation to complete by polling the status register.
2838 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2844 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2845 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2849 if (--attempts == 0)
2857 * t4_read_flash - read words from serial flash
2858 * @adapter: the adapter
2859 * @addr: the start address for the read
2860 * @nwords: how many 32-bit words to read
2861 * @data: where to store the read data
2862 * @byte_oriented: whether to store data as bytes or as words
2864 * Read the specified number of 32-bit words from the serial flash.
2865 * If @byte_oriented is set the read data is stored as a byte array
2866 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2867 * natural endianness.
2869 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2870 unsigned int nwords, u32 *data, int byte_oriented)
2874 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2877 addr = swab32(addr) | SF_RD_DATA_FAST;
2879 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2880 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2883 for ( ; nwords; nwords--, data++) {
2884 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2886 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2890 *data = (__force __u32)(cpu_to_be32(*data));
2896 * t4_write_flash - write up to a page of data to the serial flash
2897 * @adapter: the adapter
2898 * @addr: the start address to write
2899 * @n: length of data to write in bytes
2900 * @data: the data to write
2902 * Writes up to a page of data (256 bytes) to the serial flash starting
2903 * at the given address. All the data must be written to the same page.
2905 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2906 unsigned int n, const u8 *data)
2910 unsigned int i, c, left, val, offset = addr & 0xff;
2912 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2915 val = swab32(addr) | SF_PROG_PAGE;
2917 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2918 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2921 for (left = n; left; left -= c) {
2923 for (val = 0, i = 0; i < c; ++i)
2924 val = (val << 8) + *data++;
2926 ret = sf1_write(adapter, c, c != left, 1, val);
2930 ret = flash_wait_op(adapter, 8, 1);
2934 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2936 /* Read the page to verify the write succeeded */
2937 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2941 if (memcmp(data - n, (u8 *)buf + offset, n)) {
2942 dev_err(adapter->pdev_dev,
2943 "failed to correctly write the flash page at %#x\n",
2950 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2955 * t4_get_fw_version - read the firmware version
2956 * @adapter: the adapter
2957 * @vers: where to place the version
2959 * Reads the FW version from flash.
2961 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2963 return t4_read_flash(adapter, FLASH_FW_START +
2964 offsetof(struct fw_hdr, fw_ver), 1,
2969 * t4_get_bs_version - read the firmware bootstrap version
2970 * @adapter: the adapter
2971 * @vers: where to place the version
2973 * Reads the FW Bootstrap version from flash.
2975 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2977 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2978 offsetof(struct fw_hdr, fw_ver), 1,
2983 * t4_get_tp_version - read the TP microcode version
2984 * @adapter: the adapter
2985 * @vers: where to place the version
2987 * Reads the TP microcode version from flash.
2989 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2991 return t4_read_flash(adapter, FLASH_FW_START +
2992 offsetof(struct fw_hdr, tp_microcode_ver),
2997 * t4_get_exprom_version - return the Expansion ROM version (if any)
2998 * @adapter: the adapter
2999 * @vers: where to place the version
3001 * Reads the Expansion ROM header from FLASH and returns the version
3002 * number (if present) through the @vers return value pointer. We return
3003 * this in the Firmware Version Format since it's convenient. Return
3004 * 0 on success, -ENOENT if no Expansion ROM is present.
3006 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3008 struct exprom_header {
3009 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3010 unsigned char hdr_ver[4]; /* Expansion ROM version */
3012 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3016 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3017 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3022 hdr = (struct exprom_header *)exprom_header_buf;
3023 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3026 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3027 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3028 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3029 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3034 * t4_check_fw_version - check if the FW is supported with this driver
3035 * @adap: the adapter
3037 * Checks if an adapter's FW is compatible with the driver. Returns 0
3038 * if there's exact match, a negative error if the version could not be
3039 * read or there's a major version mismatch
3041 int t4_check_fw_version(struct adapter *adap)
3043 int i, ret, major, minor, micro;
3044 int exp_major, exp_minor, exp_micro;
3045 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3047 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3048 /* Try multiple times before returning error */
3049 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3050 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3055 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3056 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3057 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3059 switch (chip_version) {
3061 exp_major = T4FW_MIN_VERSION_MAJOR;
3062 exp_minor = T4FW_MIN_VERSION_MINOR;
3063 exp_micro = T4FW_MIN_VERSION_MICRO;
3066 exp_major = T5FW_MIN_VERSION_MAJOR;
3067 exp_minor = T5FW_MIN_VERSION_MINOR;
3068 exp_micro = T5FW_MIN_VERSION_MICRO;
3071 exp_major = T6FW_MIN_VERSION_MAJOR;
3072 exp_minor = T6FW_MIN_VERSION_MINOR;
3073 exp_micro = T6FW_MIN_VERSION_MICRO;
3076 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3081 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3082 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3083 dev_err(adap->pdev_dev,
3084 "Card has firmware version %u.%u.%u, minimum "
3085 "supported firmware is %u.%u.%u.\n", major, minor,
3086 micro, exp_major, exp_minor, exp_micro);
3092 /* Is the given firmware API compatible with the one the driver was compiled
3095 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3098 /* short circuit if it's the exact same firmware version */
3099 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3102 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3103 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3104 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3111 /* The firmware in the filesystem is usable, but should it be installed?
3112 * This routine explains itself in detail if it indicates the filesystem
3113 * firmware should be installed.
3115 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3120 if (!card_fw_usable) {
3121 reason = "incompatible or unusable";
3126 reason = "older than the version supported with this driver";
3133 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3134 "installing firmware %u.%u.%u.%u on card.\n",
3135 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3136 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3137 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3138 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3143 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3144 const u8 *fw_data, unsigned int fw_size,
3145 struct fw_hdr *card_fw, enum dev_state state,
3148 int ret, card_fw_usable, fs_fw_usable;
3149 const struct fw_hdr *fs_fw;
3150 const struct fw_hdr *drv_fw;
3152 drv_fw = &fw_info->fw_hdr;
3154 /* Read the header of the firmware on the card */
3155 ret = -t4_read_flash(adap, FLASH_FW_START,
3156 sizeof(*card_fw) / sizeof(uint32_t),
3157 (uint32_t *)card_fw, 1);
3159 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3161 dev_err(adap->pdev_dev,
3162 "Unable to read card's firmware header: %d\n", ret);
3166 if (fw_data != NULL) {
3167 fs_fw = (const void *)fw_data;
3168 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3174 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3175 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3176 /* Common case: the firmware on the card is an exact match and
3177 * the filesystem one is an exact match too, or the filesystem
3178 * one is absent/incompatible.
3180 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3181 should_install_fs_fw(adap, card_fw_usable,
3182 be32_to_cpu(fs_fw->fw_ver),
3183 be32_to_cpu(card_fw->fw_ver))) {
3184 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3187 dev_err(adap->pdev_dev,
3188 "failed to install firmware: %d\n", ret);
3192 /* Installed successfully, update the cached header too. */
3195 *reset = 0; /* already reset as part of load_fw */
3198 if (!card_fw_usable) {
3201 d = be32_to_cpu(drv_fw->fw_ver);
3202 c = be32_to_cpu(card_fw->fw_ver);
3203 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3205 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3207 "driver compiled with %d.%d.%d.%d, "
3208 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3210 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3211 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3212 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3213 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3214 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3215 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3220 /* We're using whatever's on the card and it's known to be good. */
3221 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3222 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3229 * t4_flash_erase_sectors - erase a range of flash sectors
3230 * @adapter: the adapter
3231 * @start: the first sector to erase
3232 * @end: the last sector to erase
3234 * Erases the sectors in the given inclusive range.
3236 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3240 if (end >= adapter->params.sf_nsec)
3243 while (start <= end) {
3244 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3245 (ret = sf1_write(adapter, 4, 0, 1,
3246 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3247 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3248 dev_err(adapter->pdev_dev,
3249 "erase of flash sector %d failed, error %d\n",
3255 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3260 * t4_flash_cfg_addr - return the address of the flash configuration file
3261 * @adapter: the adapter
3263 * Return the address within the flash where the Firmware Configuration
3266 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3268 if (adapter->params.sf_size == 0x100000)
3269 return FLASH_FPGA_CFG_START;
3271 return FLASH_CFG_START;
3274 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3275 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3276 * and emit an error message for mismatched firmware to save our caller the
3279 static bool t4_fw_matches_chip(const struct adapter *adap,
3280 const struct fw_hdr *hdr)
3282 /* The expression below will return FALSE for any unsupported adapter
3283 * which will keep us "honest" in the future ...
3285 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3286 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3287 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3290 dev_err(adap->pdev_dev,
3291 "FW image (%d) is not suitable for this adapter (%d)\n",
3292 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3297 * t4_load_fw - download firmware
3298 * @adap: the adapter
3299 * @fw_data: the firmware image to write
3302 * Write the supplied firmware image to the card's serial flash.
3304 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3309 u8 first_page[SF_PAGE_SIZE];
3310 const __be32 *p = (const __be32 *)fw_data;
3311 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3312 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3313 unsigned int fw_img_start = adap->params.sf_fw_start;
3314 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3317 dev_err(adap->pdev_dev, "FW image has no data\n");
3321 dev_err(adap->pdev_dev,
3322 "FW image size not multiple of 512 bytes\n");
3325 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3326 dev_err(adap->pdev_dev,
3327 "FW image size differs from size in FW header\n");
3330 if (size > FW_MAX_SIZE) {
3331 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3335 if (!t4_fw_matches_chip(adap, hdr))
3338 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3339 csum += be32_to_cpu(p[i]);
3341 if (csum != 0xffffffff) {
3342 dev_err(adap->pdev_dev,
3343 "corrupted firmware image, checksum %#x\n", csum);
3347 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3348 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3353 * We write the correct version at the end so the driver can see a bad
3354 * version if the FW write fails. Start by writing a copy of the
3355 * first page with a bad version.
3357 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3358 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3359 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3363 addr = fw_img_start;
3364 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3365 addr += SF_PAGE_SIZE;
3366 fw_data += SF_PAGE_SIZE;
3367 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3372 ret = t4_write_flash(adap,
3373 fw_img_start + offsetof(struct fw_hdr, fw_ver),
3374 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3377 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3380 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3385 * t4_phy_fw_ver - return current PHY firmware version
3386 * @adap: the adapter
3387 * @phy_fw_ver: return value buffer for PHY firmware version
3389 * Returns the current version of external PHY firmware on the
3392 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3397 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3398 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3399 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3400 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3401 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3410 * t4_load_phy_fw - download port PHY firmware
3411 * @adap: the adapter
3412 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3413 * @win_lock: the lock to use to guard the memory copy
3414 * @phy_fw_version: function to check PHY firmware versions
3415 * @phy_fw_data: the PHY firmware image to write
3416 * @phy_fw_size: image size
3418 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3419 * @phy_fw_version is supplied, then it will be used to determine if
3420 * it's necessary to perform the transfer by comparing the version
3421 * of any existing adapter PHY firmware with that of the passed in
3422 * PHY firmware image. If @win_lock is non-NULL then it will be used
3423 * around the call to t4_memory_rw() which transfers the PHY firmware
3426 * A negative error number will be returned if an error occurs. If
3427 * version number support is available and there's no need to upgrade
3428 * the firmware, 0 will be returned. If firmware is successfully
3429 * transferred to the adapter, 1 will be retured.
3431 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3432 * a result, a RESET of the adapter would cause that RAM to lose its
3433 * contents. Thus, loading PHY firmware on such adapters must happen
3434 * after any FW_RESET_CMDs ...
3436 int t4_load_phy_fw(struct adapter *adap,
3437 int win, spinlock_t *win_lock,
3438 int (*phy_fw_version)(const u8 *, size_t),
3439 const u8 *phy_fw_data, size_t phy_fw_size)
3441 unsigned long mtype = 0, maddr = 0;
3443 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3446 /* If we have version number support, then check to see if the adapter
3447 * already has up-to-date PHY firmware loaded.
3449 if (phy_fw_version) {
3450 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3451 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3455 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3456 CH_WARN(adap, "PHY Firmware already up-to-date, "
3457 "version %#x\n", cur_phy_fw_ver);
3462 /* Ask the firmware where it wants us to copy the PHY firmware image.
3463 * The size of the file requires a special version of the READ coommand
3464 * which will pass the file size via the values field in PARAMS_CMD and
3465 * retrieve the return value from firmware and place it in the same
3468 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3469 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3470 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3471 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3473 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3478 maddr = (val & 0xff) << 16;
3480 /* Copy the supplied PHY Firmware image to the adapter memory location
3481 * allocated by the adapter firmware.
3484 spin_lock_bh(win_lock);
3485 ret = t4_memory_rw(adap, win, mtype, maddr,
3486 phy_fw_size, (__be32 *)phy_fw_data,
3489 spin_unlock_bh(win_lock);
3493 /* Tell the firmware that the PHY firmware image has been written to
3494 * RAM and it can now start copying it over to the PHYs. The chip
3495 * firmware will RESET the affected PHYs as part of this operation
3496 * leaving them running the new PHY firmware image.
3498 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3499 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3500 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3501 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3502 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3503 ¶m, &val, 30000);
3505 /* If we have version number support, then check to see that the new
3506 * firmware got loaded properly.
3508 if (phy_fw_version) {
3509 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3513 if (cur_phy_fw_ver != new_phy_fw_vers) {
3514 CH_WARN(adap, "PHY Firmware did not update: "
3515 "version on adapter %#x, "
3516 "version flashed %#x\n",
3517 cur_phy_fw_ver, new_phy_fw_vers);
3526 * t4_fwcache - firmware cache operation
3527 * @adap: the adapter
3528 * @op : the operation (flush or flush and invalidate)
3530 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3532 struct fw_params_cmd c;
3534 memset(&c, 0, sizeof(c));
3536 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3537 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3538 FW_PARAMS_CMD_PFN_V(adap->pf) |
3539 FW_PARAMS_CMD_VFN_V(0));
3540 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3542 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3543 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3544 c.param[0].val = (__force __be32)op;
3546 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3549 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3550 unsigned int *pif_req_wrptr,
3551 unsigned int *pif_rsp_wrptr)
3554 u32 cfg, val, req, rsp;
3556 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3557 if (cfg & LADBGEN_F)
3558 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3560 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3561 req = POLADBGWRPTR_G(val);
3562 rsp = PILADBGWRPTR_G(val);
3564 *pif_req_wrptr = req;
3566 *pif_rsp_wrptr = rsp;
3568 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3569 for (j = 0; j < 6; j++) {
3570 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3571 PILADBGRDPTR_V(rsp));
3572 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3573 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3577 req = (req + 2) & POLADBGRDPTR_M;
3578 rsp = (rsp + 2) & PILADBGRDPTR_M;
3580 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3583 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3588 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3589 if (cfg & LADBGEN_F)
3590 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3592 for (i = 0; i < CIM_MALA_SIZE; i++) {
3593 for (j = 0; j < 5; j++) {
3595 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3596 PILADBGRDPTR_V(idx));
3597 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3598 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3601 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3604 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3608 for (i = 0; i < 8; i++) {
3609 u32 *p = la_buf + i;
3611 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3612 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3613 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3614 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3615 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3619 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3620 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_25G | \
3621 FW_PORT_CAP_SPEED_40G | FW_PORT_CAP_SPEED_100G | \
3625 * t4_link_l1cfg - apply link configuration to MAC/PHY
3626 * @phy: the PHY to setup
3627 * @mac: the MAC to setup
3628 * @lc: the requested link configuration
3630 * Set up a port's MAC and PHY according to a desired link configuration.
3631 * - If the PHY can auto-negotiate first decide what to advertise, then
3632 * enable/disable auto-negotiation as desired, and reset.
3633 * - If the PHY does not auto-negotiate just reset it.
3634 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3635 * otherwise do it later based on the outcome of auto-negotiation.
3637 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3638 struct link_config *lc)
3640 struct fw_port_cmd c;
3641 unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3644 if (lc->requested_fc & PAUSE_RX)
3645 fc |= FW_PORT_CAP_FC_RX;
3646 if (lc->requested_fc & PAUSE_TX)
3647 fc |= FW_PORT_CAP_FC_TX;
3649 memset(&c, 0, sizeof(c));
3650 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3651 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3652 FW_PORT_CMD_PORTID_V(port));
3654 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3657 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3658 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3660 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3661 } else if (lc->autoneg == AUTONEG_DISABLE) {
3662 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3663 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3665 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3667 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3671 * t4_restart_aneg - restart autonegotiation
3672 * @adap: the adapter
3673 * @mbox: mbox to use for the FW command
3674 * @port: the port id
3676 * Restarts autonegotiation for the selected port.
3678 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3680 struct fw_port_cmd c;
3682 memset(&c, 0, sizeof(c));
3683 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3684 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3685 FW_PORT_CMD_PORTID_V(port));
3687 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3689 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3690 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3693 typedef void (*int_handler_t)(struct adapter *adap);
3696 unsigned int mask; /* bits to check in interrupt status */
3697 const char *msg; /* message to print or NULL */
3698 short stat_idx; /* stat counter to increment or -1 */
3699 unsigned short fatal; /* whether the condition reported is fatal */
3700 int_handler_t int_handler; /* platform-specific int handler */
3704 * t4_handle_intr_status - table driven interrupt handler
3705 * @adapter: the adapter that generated the interrupt
3706 * @reg: the interrupt status register to process
3707 * @acts: table of interrupt actions
3709 * A table driven interrupt handler that applies a set of masks to an
3710 * interrupt status word and performs the corresponding actions if the
3711 * interrupts described by the mask have occurred. The actions include
3712 * optionally emitting a warning or alert message. The table is terminated
3713 * by an entry specifying mask 0. Returns the number of fatal interrupt
3716 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3717 const struct intr_info *acts)
3720 unsigned int mask = 0;
3721 unsigned int status = t4_read_reg(adapter, reg);
3723 for ( ; acts->mask; ++acts) {
3724 if (!(status & acts->mask))
3728 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3729 status & acts->mask);
3730 } else if (acts->msg && printk_ratelimit())
3731 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3732 status & acts->mask);
3733 if (acts->int_handler)
3734 acts->int_handler(adapter);
3738 if (status) /* clear processed interrupts */
3739 t4_write_reg(adapter, reg, status);
3744 * Interrupt handler for the PCIE module.
3746 static void pcie_intr_handler(struct adapter *adapter)
3748 static const struct intr_info sysbus_intr_info[] = {
3749 { RNPP_F, "RXNP array parity error", -1, 1 },
3750 { RPCP_F, "RXPC array parity error", -1, 1 },
3751 { RCIP_F, "RXCIF array parity error", -1, 1 },
3752 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3753 { RFTP_F, "RXFT array parity error", -1, 1 },
3756 static const struct intr_info pcie_port_intr_info[] = {
3757 { TPCP_F, "TXPC array parity error", -1, 1 },
3758 { TNPP_F, "TXNP array parity error", -1, 1 },
3759 { TFTP_F, "TXFT array parity error", -1, 1 },
3760 { TCAP_F, "TXCA array parity error", -1, 1 },
3761 { TCIP_F, "TXCIF array parity error", -1, 1 },
3762 { RCAP_F, "RXCA array parity error", -1, 1 },
3763 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3764 { RDPE_F, "Rx data parity error", -1, 1 },
3765 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3768 static const struct intr_info pcie_intr_info[] = {
3769 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3770 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3771 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3772 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3773 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3774 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3775 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3776 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3777 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3778 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3779 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3780 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3781 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3782 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3783 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3784 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3785 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3786 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3787 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3788 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3789 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3790 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3791 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3792 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3793 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3794 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3795 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3796 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3797 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3798 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3803 static struct intr_info t5_pcie_intr_info[] = {
3804 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3806 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3807 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3808 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3809 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3810 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3811 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3812 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3814 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3816 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3817 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3818 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3819 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3820 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3822 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3823 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3824 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3825 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3826 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3827 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3828 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3829 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3830 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3831 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3832 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3834 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3836 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3837 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3838 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3839 { READRSPERR_F, "Outbound read error", -1, 0 },
3845 if (is_t4(adapter->params.chip))
3846 fat = t4_handle_intr_status(adapter,
3847 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3849 t4_handle_intr_status(adapter,
3850 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3851 pcie_port_intr_info) +
3852 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3855 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3859 t4_fatal_err(adapter);
3863 * TP interrupt handler.
3865 static void tp_intr_handler(struct adapter *adapter)
3867 static const struct intr_info tp_intr_info[] = {
3868 { 0x3fffffff, "TP parity error", -1, 1 },
3869 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3873 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3874 t4_fatal_err(adapter);
3878 * SGE interrupt handler.
3880 static void sge_intr_handler(struct adapter *adapter)
3885 static const struct intr_info sge_intr_info[] = {
3886 { ERR_CPL_EXCEED_IQE_SIZE_F,
3887 "SGE received CPL exceeding IQE size", -1, 1 },
3888 { ERR_INVALID_CIDX_INC_F,
3889 "SGE GTS CIDX increment too large", -1, 0 },
3890 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3891 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3892 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3893 "SGE IQID > 1023 received CPL for FL", -1, 0 },
3894 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3896 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3898 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3900 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3902 { ERR_ING_CTXT_PRIO_F,
3903 "SGE too many priority ingress contexts", -1, 0 },
3904 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3905 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3909 static struct intr_info t4t5_sge_intr_info[] = {
3910 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3911 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3912 { ERR_EGR_CTXT_PRIO_F,
3913 "SGE too many priority egress contexts", -1, 0 },
3917 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3918 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3920 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
3921 (unsigned long long)v);
3922 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
3923 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
3926 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
3927 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3928 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
3929 t4t5_sge_intr_info);
3931 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
3932 if (err & ERROR_QID_VALID_F) {
3933 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
3935 if (err & UNCAPTURED_ERROR_F)
3936 dev_err(adapter->pdev_dev,
3937 "SGE UNCAPTURED_ERROR set (clearing)\n");
3938 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
3939 UNCAPTURED_ERROR_F);
3943 t4_fatal_err(adapter);
3946 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
3947 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
3948 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
3949 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
3952 * CIM interrupt handler.
3954 static void cim_intr_handler(struct adapter *adapter)
3956 static const struct intr_info cim_intr_info[] = {
3957 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
3958 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3959 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3960 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
3961 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
3962 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
3963 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
3966 static const struct intr_info cim_upintr_info[] = {
3967 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
3968 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
3969 { ILLWRINT_F, "CIM illegal write", -1, 1 },
3970 { ILLRDINT_F, "CIM illegal read", -1, 1 },
3971 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
3972 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
3973 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
3974 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
3975 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
3976 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
3977 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
3978 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
3979 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
3980 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
3981 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
3982 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
3983 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
3984 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
3985 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
3986 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
3987 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
3988 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
3989 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
3990 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
3991 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
3992 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
3993 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
3994 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4000 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
4001 t4_report_fw_error(adapter);
4003 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4005 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4008 t4_fatal_err(adapter);
4012 * ULP RX interrupt handler.
4014 static void ulprx_intr_handler(struct adapter *adapter)
4016 static const struct intr_info ulprx_intr_info[] = {
4017 { 0x1800000, "ULPRX context error", -1, 1 },
4018 { 0x7fffff, "ULPRX parity error", -1, 1 },
4022 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4023 t4_fatal_err(adapter);
4027 * ULP TX interrupt handler.
4029 static void ulptx_intr_handler(struct adapter *adapter)
4031 static const struct intr_info ulptx_intr_info[] = {
4032 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4034 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4036 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4038 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4040 { 0xfffffff, "ULPTX parity error", -1, 1 },
4044 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4045 t4_fatal_err(adapter);
4049 * PM TX interrupt handler.
4051 static void pmtx_intr_handler(struct adapter *adapter)
4053 static const struct intr_info pmtx_intr_info[] = {
4054 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4055 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4056 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4057 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4058 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4059 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4060 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4062 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4063 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4067 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4068 t4_fatal_err(adapter);
4072 * PM RX interrupt handler.
4074 static void pmrx_intr_handler(struct adapter *adapter)
4076 static const struct intr_info pmrx_intr_info[] = {
4077 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4078 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4079 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4080 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4082 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4083 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4087 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4088 t4_fatal_err(adapter);
4092 * CPL switch interrupt handler.
4094 static void cplsw_intr_handler(struct adapter *adapter)
4096 static const struct intr_info cplsw_intr_info[] = {
4097 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4098 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4099 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4100 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4101 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4102 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4106 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4107 t4_fatal_err(adapter);
4111 * LE interrupt handler.
4113 static void le_intr_handler(struct adapter *adap)
4115 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4116 static const struct intr_info le_intr_info[] = {
4117 { LIPMISS_F, "LE LIP miss", -1, 0 },
4118 { LIP0_F, "LE 0 LIP error", -1, 0 },
4119 { PARITYERR_F, "LE parity error", -1, 1 },
4120 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4121 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4125 static struct intr_info t6_le_intr_info[] = {
4126 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4127 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4128 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4129 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4130 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4134 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4135 (chip <= CHELSIO_T5) ?
4136 le_intr_info : t6_le_intr_info))
4141 * MPS interrupt handler.
4143 static void mps_intr_handler(struct adapter *adapter)
4145 static const struct intr_info mps_rx_intr_info[] = {
4146 { 0xffffff, "MPS Rx parity error", -1, 1 },
4149 static const struct intr_info mps_tx_intr_info[] = {
4150 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4151 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4152 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4154 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4156 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4157 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4158 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4161 static const struct intr_info mps_trc_intr_info[] = {
4162 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4163 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4165 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4168 static const struct intr_info mps_stat_sram_intr_info[] = {
4169 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4172 static const struct intr_info mps_stat_tx_intr_info[] = {
4173 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4176 static const struct intr_info mps_stat_rx_intr_info[] = {
4177 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4180 static const struct intr_info mps_cls_intr_info[] = {
4181 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4182 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4183 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4189 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4191 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4193 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4194 mps_trc_intr_info) +
4195 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4196 mps_stat_sram_intr_info) +
4197 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4198 mps_stat_tx_intr_info) +
4199 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4200 mps_stat_rx_intr_info) +
4201 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4204 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4205 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4207 t4_fatal_err(adapter);
4210 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4214 * EDC/MC interrupt handler.
4216 static void mem_intr_handler(struct adapter *adapter, int idx)
4218 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4220 unsigned int addr, cnt_addr, v;
4222 if (idx <= MEM_EDC1) {
4223 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4224 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4225 } else if (idx == MEM_MC) {
4226 if (is_t4(adapter->params.chip)) {
4227 addr = MC_INT_CAUSE_A;
4228 cnt_addr = MC_ECC_STATUS_A;
4230 addr = MC_P_INT_CAUSE_A;
4231 cnt_addr = MC_P_ECC_STATUS_A;
4234 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4235 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4238 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4239 if (v & PERR_INT_CAUSE_F)
4240 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4242 if (v & ECC_CE_INT_CAUSE_F) {
4243 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4245 t4_edc_err_read(adapter, idx);
4247 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4248 if (printk_ratelimit())
4249 dev_warn(adapter->pdev_dev,
4250 "%u %s correctable ECC data error%s\n",
4251 cnt, name[idx], cnt > 1 ? "s" : "");
4253 if (v & ECC_UE_INT_CAUSE_F)
4254 dev_alert(adapter->pdev_dev,
4255 "%s uncorrectable ECC data error\n", name[idx]);
4257 t4_write_reg(adapter, addr, v);
4258 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4259 t4_fatal_err(adapter);
4263 * MA interrupt handler.
4265 static void ma_intr_handler(struct adapter *adap)
4267 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4269 if (status & MEM_PERR_INT_CAUSE_F) {
4270 dev_alert(adap->pdev_dev,
4271 "MA parity error, parity status %#x\n",
4272 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4273 if (is_t5(adap->params.chip))
4274 dev_alert(adap->pdev_dev,
4275 "MA parity error, parity status %#x\n",
4277 MA_PARITY_ERROR_STATUS2_A));
4279 if (status & MEM_WRAP_INT_CAUSE_F) {
4280 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4281 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4282 "client %u to address %#x\n",
4283 MEM_WRAP_CLIENT_NUM_G(v),
4284 MEM_WRAP_ADDRESS_G(v) << 4);
4286 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4291 * SMB interrupt handler.
4293 static void smb_intr_handler(struct adapter *adap)
4295 static const struct intr_info smb_intr_info[] = {
4296 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4297 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4298 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4302 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4307 * NC-SI interrupt handler.
4309 static void ncsi_intr_handler(struct adapter *adap)
4311 static const struct intr_info ncsi_intr_info[] = {
4312 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4313 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4314 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4315 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4319 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4324 * XGMAC interrupt handler.
4326 static void xgmac_intr_handler(struct adapter *adap, int port)
4328 u32 v, int_cause_reg;
4330 if (is_t4(adap->params.chip))
4331 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4333 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4335 v = t4_read_reg(adap, int_cause_reg);
4337 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4341 if (v & TXFIFO_PRTY_ERR_F)
4342 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4344 if (v & RXFIFO_PRTY_ERR_F)
4345 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4347 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4352 * PL interrupt handler.
4354 static void pl_intr_handler(struct adapter *adap)
4356 static const struct intr_info pl_intr_info[] = {
4357 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4358 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4362 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4366 #define PF_INTR_MASK (PFSW_F)
4367 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4368 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4369 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4372 * t4_slow_intr_handler - control path interrupt handler
4373 * @adapter: the adapter
4375 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4376 * The designation 'slow' is because it involves register reads, while
4377 * data interrupts typically don't involve any MMIOs.
4379 int t4_slow_intr_handler(struct adapter *adapter)
4381 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4383 if (!(cause & GLBL_INTR_MASK))
4386 cim_intr_handler(adapter);
4388 mps_intr_handler(adapter);
4390 ncsi_intr_handler(adapter);
4392 pl_intr_handler(adapter);
4394 smb_intr_handler(adapter);
4395 if (cause & XGMAC0_F)
4396 xgmac_intr_handler(adapter, 0);
4397 if (cause & XGMAC1_F)
4398 xgmac_intr_handler(adapter, 1);
4399 if (cause & XGMAC_KR0_F)
4400 xgmac_intr_handler(adapter, 2);
4401 if (cause & XGMAC_KR1_F)
4402 xgmac_intr_handler(adapter, 3);
4404 pcie_intr_handler(adapter);
4406 mem_intr_handler(adapter, MEM_MC);
4407 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4408 mem_intr_handler(adapter, MEM_MC1);
4410 mem_intr_handler(adapter, MEM_EDC0);
4412 mem_intr_handler(adapter, MEM_EDC1);
4414 le_intr_handler(adapter);
4416 tp_intr_handler(adapter);
4418 ma_intr_handler(adapter);
4419 if (cause & PM_TX_F)
4420 pmtx_intr_handler(adapter);
4421 if (cause & PM_RX_F)
4422 pmrx_intr_handler(adapter);
4423 if (cause & ULP_RX_F)
4424 ulprx_intr_handler(adapter);
4425 if (cause & CPL_SWITCH_F)
4426 cplsw_intr_handler(adapter);
4428 sge_intr_handler(adapter);
4429 if (cause & ULP_TX_F)
4430 ulptx_intr_handler(adapter);
4432 /* Clear the interrupts just processed for which we are the master. */
4433 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4434 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4439 * t4_intr_enable - enable interrupts
4440 * @adapter: the adapter whose interrupts should be enabled
4442 * Enable PF-specific interrupts for the calling function and the top-level
4443 * interrupt concentrator for global interrupts. Interrupts are already
4444 * enabled at each module, here we just enable the roots of the interrupt
4447 * Note: this function should be called only when the driver manages
4448 * non PF-specific interrupts from the various HW modules. Only one PCI
4449 * function at a time should be doing this.
4451 void t4_intr_enable(struct adapter *adapter)
4454 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4455 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4456 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4458 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4459 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4460 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4461 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4462 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4463 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4464 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4465 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4466 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4467 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4468 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4472 * t4_intr_disable - disable interrupts
4473 * @adapter: the adapter whose interrupts should be disabled
4475 * Disable interrupts. We only disable the top-level interrupt
4476 * concentrators. The caller must be a PCI function managing global
4479 void t4_intr_disable(struct adapter *adapter)
4481 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4482 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4483 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4485 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4486 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4490 * t4_config_rss_range - configure a portion of the RSS mapping table
4491 * @adapter: the adapter
4492 * @mbox: mbox to use for the FW command
4493 * @viid: virtual interface whose RSS subtable is to be written
4494 * @start: start entry in the table to write
4495 * @n: how many table entries to write
4496 * @rspq: values for the response queue lookup table
4497 * @nrspq: number of values in @rspq
4499 * Programs the selected part of the VI's RSS mapping table with the
4500 * provided values. If @nrspq < @n the supplied values are used repeatedly
4501 * until the full table range is populated.
4503 * The caller must ensure the values in @rspq are in the range allowed for
4506 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4507 int start, int n, const u16 *rspq, unsigned int nrspq)
4510 const u16 *rsp = rspq;
4511 const u16 *rsp_end = rspq + nrspq;
4512 struct fw_rss_ind_tbl_cmd cmd;
4514 memset(&cmd, 0, sizeof(cmd));
4515 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4516 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4517 FW_RSS_IND_TBL_CMD_VIID_V(viid));
4518 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4520 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4522 int nq = min(n, 32);
4523 __be32 *qp = &cmd.iq0_to_iq2;
4525 cmd.niqid = cpu_to_be16(nq);
4526 cmd.startidx = cpu_to_be16(start);
4534 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4535 if (++rsp >= rsp_end)
4537 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4538 if (++rsp >= rsp_end)
4540 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4541 if (++rsp >= rsp_end)
4544 *qp++ = cpu_to_be32(v);
4548 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4556 * t4_config_glbl_rss - configure the global RSS mode
4557 * @adapter: the adapter
4558 * @mbox: mbox to use for the FW command
4559 * @mode: global RSS mode
4560 * @flags: mode-specific flags
4562 * Sets the global RSS mode.
4564 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4567 struct fw_rss_glb_config_cmd c;
4569 memset(&c, 0, sizeof(c));
4570 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4571 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4572 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4573 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4574 c.u.manual.mode_pkd =
4575 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4576 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4577 c.u.basicvirtual.mode_pkd =
4578 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4579 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4582 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4586 * t4_config_vi_rss - configure per VI RSS settings
4587 * @adapter: the adapter
4588 * @mbox: mbox to use for the FW command
4591 * @defq: id of the default RSS queue for the VI.
4593 * Configures VI-specific RSS properties.
4595 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4596 unsigned int flags, unsigned int defq)
4598 struct fw_rss_vi_config_cmd c;
4600 memset(&c, 0, sizeof(c));
4601 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4602 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4603 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4604 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4605 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4606 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4607 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4610 /* Read an RSS table row */
4611 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4613 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4614 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4619 * t4_read_rss - read the contents of the RSS mapping table
4620 * @adapter: the adapter
4621 * @map: holds the contents of the RSS mapping table
4623 * Reads the contents of the RSS hash->queue mapping table.
4625 int t4_read_rss(struct adapter *adapter, u16 *map)
4630 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4631 ret = rd_rss_row(adapter, i, &val);
4634 *map++ = LKPTBLQUEUE0_G(val);
4635 *map++ = LKPTBLQUEUE1_G(val);
4640 static unsigned int t4_use_ldst(struct adapter *adap)
4642 return (adap->flags & FW_OK) || !adap->use_bd;
4646 * t4_fw_tp_pio_rw - Access TP PIO through LDST
4647 * @adap: the adapter
4648 * @vals: where the indirect register values are stored/written
4649 * @nregs: how many indirect registers to read/write
4650 * @start_idx: index of first indirect register to read/write
4651 * @rw: Read (1) or Write (0)
4653 * Access TP PIO registers through LDST
4655 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4656 unsigned int start_index, unsigned int rw)
4659 int cmd = FW_LDST_ADDRSPC_TP_PIO;
4660 struct fw_ldst_cmd c;
4662 for (i = 0 ; i < nregs; i++) {
4663 memset(&c, 0, sizeof(c));
4664 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4666 (rw ? FW_CMD_READ_F :
4668 FW_LDST_CMD_ADDRSPACE_V(cmd));
4669 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4671 c.u.addrval.addr = cpu_to_be32(start_index + i);
4672 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
4673 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4675 vals[i] = be32_to_cpu(c.u.addrval.val);
4680 * t4_read_rss_key - read the global RSS key
4681 * @adap: the adapter
4682 * @key: 10-entry array holding the 320-bit RSS key
4684 * Reads the global 320-bit RSS key.
4686 void t4_read_rss_key(struct adapter *adap, u32 *key)
4688 if (t4_use_ldst(adap))
4689 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4691 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4692 TP_RSS_SECRET_KEY0_A);
4696 * t4_write_rss_key - program one of the RSS keys
4697 * @adap: the adapter
4698 * @key: 10-entry array holding the 320-bit RSS key
4699 * @idx: which RSS key to write
4701 * Writes one of the RSS keys with the given 320-bit value. If @idx is
4702 * 0..15 the corresponding entry in the RSS key table is written,
4703 * otherwise the global RSS key is written.
4705 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4707 u8 rss_key_addr_cnt = 16;
4708 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4710 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4711 * allows access to key addresses 16-63 by using KeyWrAddrX
4712 * as index[5:4](upper 2) into key table
4714 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4715 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4716 rss_key_addr_cnt = 32;
4718 if (t4_use_ldst(adap))
4719 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4721 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4722 TP_RSS_SECRET_KEY0_A);
4724 if (idx >= 0 && idx < rss_key_addr_cnt) {
4725 if (rss_key_addr_cnt > 16)
4726 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4727 KEYWRADDRX_V(idx >> 4) |
4728 T6_VFWRADDR_V(idx) | KEYWREN_F);
4730 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4731 KEYWRADDR_V(idx) | KEYWREN_F);
4736 * t4_read_rss_pf_config - read PF RSS Configuration Table
4737 * @adapter: the adapter
4738 * @index: the entry in the PF RSS table to read
4739 * @valp: where to store the returned value
4741 * Reads the PF RSS Configuration Table at the specified index and returns
4742 * the value found there.
4744 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4747 if (t4_use_ldst(adapter))
4748 t4_fw_tp_pio_rw(adapter, valp, 1,
4749 TP_RSS_PF0_CONFIG_A + index, 1);
4751 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4752 valp, 1, TP_RSS_PF0_CONFIG_A + index);
4756 * t4_read_rss_vf_config - read VF RSS Configuration Table
4757 * @adapter: the adapter
4758 * @index: the entry in the VF RSS table to read
4759 * @vfl: where to store the returned VFL
4760 * @vfh: where to store the returned VFH
4762 * Reads the VF RSS Configuration Table at the specified index and returns
4763 * the (VFL, VFH) values found there.
4765 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4768 u32 vrt, mask, data;
4770 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4771 mask = VFWRADDR_V(VFWRADDR_M);
4772 data = VFWRADDR_V(index);
4774 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
4775 data = T6_VFWRADDR_V(index);
4778 /* Request that the index'th VF Table values be read into VFL/VFH.
4780 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4781 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4782 vrt |= data | VFRDEN_F;
4783 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4785 /* Grab the VFL/VFH values ...
4787 if (t4_use_ldst(adapter)) {
4788 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4789 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4791 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4792 vfl, 1, TP_RSS_VFL_CONFIG_A);
4793 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4794 vfh, 1, TP_RSS_VFH_CONFIG_A);
4799 * t4_read_rss_pf_map - read PF RSS Map
4800 * @adapter: the adapter
4802 * Reads the PF RSS Map register and returns its value.
4804 u32 t4_read_rss_pf_map(struct adapter *adapter)
4808 if (t4_use_ldst(adapter))
4809 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4811 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4812 &pfmap, 1, TP_RSS_PF_MAP_A);
4817 * t4_read_rss_pf_mask - read PF RSS Mask
4818 * @adapter: the adapter
4820 * Reads the PF RSS Mask register and returns its value.
4822 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4826 if (t4_use_ldst(adapter))
4827 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4829 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4830 &pfmask, 1, TP_RSS_PF_MSK_A);
4835 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
4836 * @adap: the adapter
4837 * @v4: holds the TCP/IP counter values
4838 * @v6: holds the TCP/IPv6 counter values
4840 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4841 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4843 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4844 struct tp_tcp_stats *v6)
4846 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4848 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4849 #define STAT(x) val[STAT_IDX(x)]
4850 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4853 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4854 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4855 v4->tcp_out_rsts = STAT(OUT_RST);
4856 v4->tcp_in_segs = STAT64(IN_SEG);
4857 v4->tcp_out_segs = STAT64(OUT_SEG);
4858 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4861 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4862 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4863 v6->tcp_out_rsts = STAT(OUT_RST);
4864 v6->tcp_in_segs = STAT64(IN_SEG);
4865 v6->tcp_out_segs = STAT64(OUT_SEG);
4866 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4874 * t4_tp_get_err_stats - read TP's error MIB counters
4875 * @adap: the adapter
4876 * @st: holds the counter values
4878 * Returns the values of TP's error counters.
4880 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4882 int nchan = adap->params.arch.nchan;
4884 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4885 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4886 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4887 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4888 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4889 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4890 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4891 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4892 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4893 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4894 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4895 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4896 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4897 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4898 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4899 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4901 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4902 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4906 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
4907 * @adap: the adapter
4908 * @st: holds the counter values
4910 * Returns the values of TP's CPL counters.
4912 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4914 int nchan = adap->params.arch.nchan;
4916 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
4917 nchan, TP_MIB_CPL_IN_REQ_0_A);
4918 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
4919 nchan, TP_MIB_CPL_OUT_RSP_0_A);
4924 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
4925 * @adap: the adapter
4926 * @st: holds the counter values
4928 * Returns the values of TP's RDMA counters.
4930 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
4932 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
4933 2, TP_MIB_RQE_DFR_PKT_A);
4937 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
4938 * @adap: the adapter
4939 * @idx: the port index
4940 * @st: holds the counter values
4942 * Returns the values of TP's FCoE counters for the selected port.
4944 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
4945 struct tp_fcoe_stats *st)
4949 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
4950 1, TP_MIB_FCOE_DDP_0_A + idx);
4951 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
4952 1, TP_MIB_FCOE_DROP_0_A + idx);
4953 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4954 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
4955 st->octets_ddp = ((u64)val[0] << 32) | val[1];
4959 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
4960 * @adap: the adapter
4961 * @st: holds the counter values
4963 * Returns the values of TP's counters for non-TCP directly-placed packets.
4965 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
4969 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
4971 st->frames = val[0];
4973 st->octets = ((u64)val[2] << 32) | val[3];
4977 * t4_read_mtu_tbl - returns the values in the HW path MTU table
4978 * @adap: the adapter
4979 * @mtus: where to store the MTU values
4980 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
4982 * Reads the HW path MTU table.
4984 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
4989 for (i = 0; i < NMTUS; ++i) {
4990 t4_write_reg(adap, TP_MTU_TABLE_A,
4991 MTUINDEX_V(0xff) | MTUVALUE_V(i));
4992 v = t4_read_reg(adap, TP_MTU_TABLE_A);
4993 mtus[i] = MTUVALUE_G(v);
4995 mtu_log[i] = MTUWIDTH_G(v);
5000 * t4_read_cong_tbl - reads the congestion control table
5001 * @adap: the adapter
5002 * @incr: where to store the alpha values
5004 * Reads the additive increments programmed into the HW congestion
5007 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5009 unsigned int mtu, w;
5011 for (mtu = 0; mtu < NMTUS; ++mtu)
5012 for (w = 0; w < NCCTRL_WIN; ++w) {
5013 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5014 ROWINDEX_V(0xffff) | (mtu << 5) | w);
5015 incr[mtu][w] = (u16)t4_read_reg(adap,
5016 TP_CCTRL_TABLE_A) & 0x1fff;
5021 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5022 * @adap: the adapter
5023 * @addr: the indirect TP register address
5024 * @mask: specifies the field within the register to modify
5025 * @val: new value for the field
5027 * Sets a field of an indirect TP register to the given value.
5029 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5030 unsigned int mask, unsigned int val)
5032 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5033 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5034 t4_write_reg(adap, TP_PIO_DATA_A, val);
5038 * init_cong_ctrl - initialize congestion control parameters
5039 * @a: the alpha values for congestion control
5040 * @b: the beta values for congestion control
5042 * Initialize the congestion control parameters.
5044 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5046 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5071 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5074 b[13] = b[14] = b[15] = b[16] = 3;
5075 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5076 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5081 /* The minimum additive increment value for the congestion control table */
5082 #define CC_MIN_INCR 2U
5085 * t4_load_mtus - write the MTU and congestion control HW tables
5086 * @adap: the adapter
5087 * @mtus: the values for the MTU table
5088 * @alpha: the values for the congestion control alpha parameter
5089 * @beta: the values for the congestion control beta parameter
5091 * Write the HW MTU table with the supplied MTUs and the high-speed
5092 * congestion control table with the supplied alpha, beta, and MTUs.
5093 * We write the two tables together because the additive increments
5094 * depend on the MTUs.
5096 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5097 const unsigned short *alpha, const unsigned short *beta)
5099 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5100 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5101 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5102 28672, 40960, 57344, 81920, 114688, 163840, 229376
5107 for (i = 0; i < NMTUS; ++i) {
5108 unsigned int mtu = mtus[i];
5109 unsigned int log2 = fls(mtu);
5111 if (!(mtu & ((1 << log2) >> 2))) /* round */
5113 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5114 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5116 for (w = 0; w < NCCTRL_WIN; ++w) {
5119 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5122 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5123 (w << 16) | (beta[w] << 13) | inc);
5128 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5129 * clocks. The formula is
5131 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5133 * which is equivalent to
5135 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5137 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5139 u64 v = bytes256 * adap->params.vpd.cclk;
5141 return v * 62 + v / 2;
5145 * t4_get_chan_txrate - get the current per channel Tx rates
5146 * @adap: the adapter
5147 * @nic_rate: rates for NIC traffic
5148 * @ofld_rate: rates for offloaded traffic
5150 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5153 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5157 v = t4_read_reg(adap, TP_TX_TRATE_A);
5158 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5159 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5160 if (adap->params.arch.nchan == NCHAN) {
5161 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5162 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5165 v = t4_read_reg(adap, TP_TX_ORATE_A);
5166 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5167 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5168 if (adap->params.arch.nchan == NCHAN) {
5169 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5170 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5175 * t4_set_trace_filter - configure one of the tracing filters
5176 * @adap: the adapter
5177 * @tp: the desired trace filter parameters
5178 * @idx: which filter to configure
5179 * @enable: whether to enable or disable the filter
5181 * Configures one of the tracing filters available in HW. If @enable is
5182 * %0 @tp is not examined and may be %NULL. The user is responsible to
5183 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5185 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5186 int idx, int enable)
5188 int i, ofst = idx * 4;
5189 u32 data_reg, mask_reg, cfg;
5190 u32 multitrc = TRCMULTIFILTER_F;
5193 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5197 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5198 if (cfg & TRCMULTIFILTER_F) {
5199 /* If multiple tracers are enabled, then maximum
5200 * capture size is 2.5KB (FIFO size of a single channel)
5201 * minus 2 flits for CPL_TRACE_PKT header.
5203 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5206 /* If multiple tracers are disabled, to avoid deadlocks
5207 * maximum packet capture size of 9600 bytes is recommended.
5208 * Also in this mode, only trace0 can be enabled and running.
5211 if (tp->snap_len > 9600 || idx)
5215 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5216 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5217 tp->min_len > TFMINPKTSIZE_M)
5220 /* stop the tracer we'll be changing */
5221 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5223 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5224 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5225 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5227 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5228 t4_write_reg(adap, data_reg, tp->data[i]);
5229 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5231 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5232 TFCAPTUREMAX_V(tp->snap_len) |
5233 TFMINPKTSIZE_V(tp->min_len));
5234 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5235 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5236 (is_t4(adap->params.chip) ?
5237 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5238 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5239 T5_TFINVERTMATCH_V(tp->invert)));
5245 * t4_get_trace_filter - query one of the tracing filters
5246 * @adap: the adapter
5247 * @tp: the current trace filter parameters
5248 * @idx: which trace filter to query
5249 * @enabled: non-zero if the filter is enabled
5251 * Returns the current settings of one of the HW tracing filters.
5253 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5257 int i, ofst = idx * 4;
5258 u32 data_reg, mask_reg;
5260 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5261 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5263 if (is_t4(adap->params.chip)) {
5264 *enabled = !!(ctla & TFEN_F);
5265 tp->port = TFPORT_G(ctla);
5266 tp->invert = !!(ctla & TFINVERTMATCH_F);
5268 *enabled = !!(ctla & T5_TFEN_F);
5269 tp->port = T5_TFPORT_G(ctla);
5270 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5272 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5273 tp->min_len = TFMINPKTSIZE_G(ctlb);
5274 tp->skip_ofst = TFOFFSET_G(ctla);
5275 tp->skip_len = TFLENGTH_G(ctla);
5277 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5278 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5279 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5281 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5282 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5283 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5288 * t4_pmtx_get_stats - returns the HW stats from PMTX
5289 * @adap: the adapter
5290 * @cnt: where to store the count statistics
5291 * @cycles: where to store the cycle statistics
5293 * Returns performance statistics from PMTX.
5295 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5300 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5301 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5302 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5303 if (is_t4(adap->params.chip)) {
5304 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5306 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5307 PM_TX_DBG_DATA_A, data, 2,
5308 PM_TX_DBG_STAT_MSB_A);
5309 cycles[i] = (((u64)data[0] << 32) | data[1]);
5315 * t4_pmrx_get_stats - returns the HW stats from PMRX
5316 * @adap: the adapter
5317 * @cnt: where to store the count statistics
5318 * @cycles: where to store the cycle statistics
5320 * Returns performance statistics from PMRX.
5322 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5327 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5328 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5329 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5330 if (is_t4(adap->params.chip)) {
5331 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5333 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5334 PM_RX_DBG_DATA_A, data, 2,
5335 PM_RX_DBG_STAT_MSB_A);
5336 cycles[i] = (((u64)data[0] << 32) | data[1]);
5342 * t4_get_mps_bg_map - return the buffer groups associated with a port
5343 * @adap: the adapter
5344 * @idx: the port index
5346 * Returns a bitmap indicating which MPS buffer groups are associated
5347 * with the given port. Bit i is set if buffer group i is used by the
5350 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5352 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5355 return idx == 0 ? 0xf : 0;
5356 /* In T6 (which is a 2 port card),
5357 * port 0 is mapped to channel 0 and port 1 is mapped to channel 1.
5358 * For 2 port T4/T5 adapter,
5359 * port 0 is mapped to channel 0 and 1,
5360 * port 1 is mapped to channel 2 and 3.
5363 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
5364 return idx < 2 ? (3 << (2 * idx)) : 0;
5369 * t4_get_port_type_description - return Port Type string description
5370 * @port_type: firmware Port Type enumeration
5372 const char *t4_get_port_type_description(enum fw_port_type port_type)
5374 static const char *const port_type_description[] = {
5393 if (port_type < ARRAY_SIZE(port_type_description))
5394 return port_type_description[port_type];
5399 * t4_get_port_stats_offset - collect port stats relative to a previous
5401 * @adap: The adapter
5403 * @stats: Current stats to fill
5404 * @offset: Previous stats snapshot
5406 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5407 struct port_stats *stats,
5408 struct port_stats *offset)
5413 t4_get_port_stats(adap, idx, stats);
5414 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5415 i < (sizeof(struct port_stats) / sizeof(u64));
5421 * t4_get_port_stats - collect port statistics
5422 * @adap: the adapter
5423 * @idx: the port index
5424 * @p: the stats structure to fill
5426 * Collect statistics related to the given port from HW.
5428 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5430 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5432 #define GET_STAT(name) \
5433 t4_read_reg64(adap, \
5434 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5435 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5436 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5438 p->tx_octets = GET_STAT(TX_PORT_BYTES);
5439 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
5440 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
5441 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
5442 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
5443 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
5444 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
5445 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
5446 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
5447 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
5448 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
5449 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5450 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
5451 p->tx_drop = GET_STAT(TX_PORT_DROP);
5452 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
5453 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
5454 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
5455 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
5456 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
5457 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
5458 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
5459 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
5460 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
5462 p->rx_octets = GET_STAT(RX_PORT_BYTES);
5463 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
5464 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
5465 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
5466 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
5467 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
5468 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5469 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
5470 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
5471 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
5472 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
5473 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
5474 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
5475 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
5476 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
5477 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
5478 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5479 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
5480 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
5481 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
5482 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
5483 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
5484 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
5485 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
5486 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
5487 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
5488 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
5490 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5491 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5492 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5493 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5494 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5495 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5496 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5497 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5504 * t4_get_lb_stats - collect loopback port statistics
5505 * @adap: the adapter
5506 * @idx: the loopback port index
5507 * @p: the stats structure to fill
5509 * Return HW statistics for the given loopback port.
5511 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5513 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5515 #define GET_STAT(name) \
5516 t4_read_reg64(adap, \
5517 (is_t4(adap->params.chip) ? \
5518 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5519 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5520 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5522 p->octets = GET_STAT(BYTES);
5523 p->frames = GET_STAT(FRAMES);
5524 p->bcast_frames = GET_STAT(BCAST);
5525 p->mcast_frames = GET_STAT(MCAST);
5526 p->ucast_frames = GET_STAT(UCAST);
5527 p->error_frames = GET_STAT(ERROR);
5529 p->frames_64 = GET_STAT(64B);
5530 p->frames_65_127 = GET_STAT(65B_127B);
5531 p->frames_128_255 = GET_STAT(128B_255B);
5532 p->frames_256_511 = GET_STAT(256B_511B);
5533 p->frames_512_1023 = GET_STAT(512B_1023B);
5534 p->frames_1024_1518 = GET_STAT(1024B_1518B);
5535 p->frames_1519_max = GET_STAT(1519B_MAX);
5536 p->drop = GET_STAT(DROP_FRAMES);
5538 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5539 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5540 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5541 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5542 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5543 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5544 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5545 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5551 /* t4_mk_filtdelwr - create a delete filter WR
5552 * @ftid: the filter ID
5553 * @wr: the filter work request to populate
5554 * @qid: ingress queue to receive the delete notification
5556 * Creates a filter work request to delete the supplied filter. If @qid is
5557 * negative the delete notification is suppressed.
5559 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5561 memset(wr, 0, sizeof(*wr));
5562 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5563 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5564 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5565 FW_FILTER_WR_NOREPLY_V(qid < 0));
5566 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5568 wr->rx_chan_rx_rpl_iq =
5569 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5572 #define INIT_CMD(var, cmd, rd_wr) do { \
5573 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5574 FW_CMD_REQUEST_F | \
5575 FW_CMD_##rd_wr##_F); \
5576 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5579 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5583 struct fw_ldst_cmd c;
5585 memset(&c, 0, sizeof(c));
5586 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5587 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5591 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5592 c.u.addrval.addr = cpu_to_be32(addr);
5593 c.u.addrval.val = cpu_to_be32(val);
5595 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5599 * t4_mdio_rd - read a PHY register through MDIO
5600 * @adap: the adapter
5601 * @mbox: mailbox to use for the FW command
5602 * @phy_addr: the PHY address
5603 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5604 * @reg: the register to read
5605 * @valp: where to store the value
5607 * Issues a FW command through the given mailbox to read a PHY register.
5609 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5610 unsigned int mmd, unsigned int reg, u16 *valp)
5614 struct fw_ldst_cmd c;
5616 memset(&c, 0, sizeof(c));
5617 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5618 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5619 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5621 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5622 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5623 FW_LDST_CMD_MMD_V(mmd));
5624 c.u.mdio.raddr = cpu_to_be16(reg);
5626 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5628 *valp = be16_to_cpu(c.u.mdio.rval);
5633 * t4_mdio_wr - write a PHY register through MDIO
5634 * @adap: the adapter
5635 * @mbox: mailbox to use for the FW command
5636 * @phy_addr: the PHY address
5637 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5638 * @reg: the register to write
5639 * @valp: value to write
5641 * Issues a FW command through the given mailbox to write a PHY register.
5643 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5644 unsigned int mmd, unsigned int reg, u16 val)
5647 struct fw_ldst_cmd c;
5649 memset(&c, 0, sizeof(c));
5650 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5651 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5652 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5654 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5655 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5656 FW_LDST_CMD_MMD_V(mmd));
5657 c.u.mdio.raddr = cpu_to_be16(reg);
5658 c.u.mdio.rval = cpu_to_be16(val);
5660 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5664 * t4_sge_decode_idma_state - decode the idma state
5665 * @adap: the adapter
5666 * @state: the state idma is stuck in
5668 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5670 static const char * const t4_decode[] = {
5672 "IDMA_PUSH_MORE_CPL_FIFO",
5673 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5675 "IDMA_PHYSADDR_SEND_PCIEHDR",
5676 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5677 "IDMA_PHYSADDR_SEND_PAYLOAD",
5678 "IDMA_SEND_FIFO_TO_IMSG",
5679 "IDMA_FL_REQ_DATA_FL_PREP",
5680 "IDMA_FL_REQ_DATA_FL",
5682 "IDMA_FL_H_REQ_HEADER_FL",
5683 "IDMA_FL_H_SEND_PCIEHDR",
5684 "IDMA_FL_H_PUSH_CPL_FIFO",
5685 "IDMA_FL_H_SEND_CPL",
5686 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5687 "IDMA_FL_H_SEND_IP_HDR",
5688 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5689 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5690 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5691 "IDMA_FL_D_SEND_PCIEHDR",
5692 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5693 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5694 "IDMA_FL_SEND_PCIEHDR",
5695 "IDMA_FL_PUSH_CPL_FIFO",
5697 "IDMA_FL_SEND_PAYLOAD_FIRST",
5698 "IDMA_FL_SEND_PAYLOAD",
5699 "IDMA_FL_REQ_NEXT_DATA_FL",
5700 "IDMA_FL_SEND_NEXT_PCIEHDR",
5701 "IDMA_FL_SEND_PADDING",
5702 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5703 "IDMA_FL_SEND_FIFO_TO_IMSG",
5704 "IDMA_FL_REQ_DATAFL_DONE",
5705 "IDMA_FL_REQ_HEADERFL_DONE",
5707 static const char * const t5_decode[] = {
5710 "IDMA_PUSH_MORE_CPL_FIFO",
5711 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5712 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5713 "IDMA_PHYSADDR_SEND_PCIEHDR",
5714 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5715 "IDMA_PHYSADDR_SEND_PAYLOAD",
5716 "IDMA_SEND_FIFO_TO_IMSG",
5717 "IDMA_FL_REQ_DATA_FL",
5719 "IDMA_FL_DROP_SEND_INC",
5720 "IDMA_FL_H_REQ_HEADER_FL",
5721 "IDMA_FL_H_SEND_PCIEHDR",
5722 "IDMA_FL_H_PUSH_CPL_FIFO",
5723 "IDMA_FL_H_SEND_CPL",
5724 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5725 "IDMA_FL_H_SEND_IP_HDR",
5726 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5727 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5728 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5729 "IDMA_FL_D_SEND_PCIEHDR",
5730 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5731 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5732 "IDMA_FL_SEND_PCIEHDR",
5733 "IDMA_FL_PUSH_CPL_FIFO",
5735 "IDMA_FL_SEND_PAYLOAD_FIRST",
5736 "IDMA_FL_SEND_PAYLOAD",
5737 "IDMA_FL_REQ_NEXT_DATA_FL",
5738 "IDMA_FL_SEND_NEXT_PCIEHDR",
5739 "IDMA_FL_SEND_PADDING",
5740 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5742 static const char * const t6_decode[] = {
5744 "IDMA_PUSH_MORE_CPL_FIFO",
5745 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5746 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5747 "IDMA_PHYSADDR_SEND_PCIEHDR",
5748 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5749 "IDMA_PHYSADDR_SEND_PAYLOAD",
5750 "IDMA_FL_REQ_DATA_FL",
5752 "IDMA_FL_DROP_SEND_INC",
5753 "IDMA_FL_H_REQ_HEADER_FL",
5754 "IDMA_FL_H_SEND_PCIEHDR",
5755 "IDMA_FL_H_PUSH_CPL_FIFO",
5756 "IDMA_FL_H_SEND_CPL",
5757 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5758 "IDMA_FL_H_SEND_IP_HDR",
5759 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5760 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5761 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5762 "IDMA_FL_D_SEND_PCIEHDR",
5763 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5764 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5765 "IDMA_FL_SEND_PCIEHDR",
5766 "IDMA_FL_PUSH_CPL_FIFO",
5768 "IDMA_FL_SEND_PAYLOAD_FIRST",
5769 "IDMA_FL_SEND_PAYLOAD",
5770 "IDMA_FL_REQ_NEXT_DATA_FL",
5771 "IDMA_FL_SEND_NEXT_PCIEHDR",
5772 "IDMA_FL_SEND_PADDING",
5773 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5775 static const u32 sge_regs[] = {
5776 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5777 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5778 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5780 const char **sge_idma_decode;
5781 int sge_idma_decode_nstates;
5783 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5785 /* Select the right set of decode strings to dump depending on the
5786 * adapter chip type.
5788 switch (chip_version) {
5790 sge_idma_decode = (const char **)t4_decode;
5791 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5795 sge_idma_decode = (const char **)t5_decode;
5796 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5800 sge_idma_decode = (const char **)t6_decode;
5801 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
5805 dev_err(adapter->pdev_dev,
5806 "Unsupported chip version %d\n", chip_version);
5810 if (is_t4(adapter->params.chip)) {
5811 sge_idma_decode = (const char **)t4_decode;
5812 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5814 sge_idma_decode = (const char **)t5_decode;
5815 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5818 if (state < sge_idma_decode_nstates)
5819 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5821 CH_WARN(adapter, "idma state %d unknown\n", state);
5823 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5824 CH_WARN(adapter, "SGE register %#x value %#x\n",
5825 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5829 * t4_sge_ctxt_flush - flush the SGE context cache
5830 * @adap: the adapter
5831 * @mbox: mailbox to use for the FW command
5833 * Issues a FW command through the given mailbox to flush the
5834 * SGE context cache.
5836 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5840 struct fw_ldst_cmd c;
5842 memset(&c, 0, sizeof(c));
5843 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5844 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5845 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5847 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5848 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5850 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5855 * t4_fw_hello - establish communication with FW
5856 * @adap: the adapter
5857 * @mbox: mailbox to use for the FW command
5858 * @evt_mbox: mailbox to receive async FW events
5859 * @master: specifies the caller's willingness to be the device master
5860 * @state: returns the current device state (if non-NULL)
5862 * Issues a command to establish communication with FW. Returns either
5863 * an error (negative integer) or the mailbox of the Master PF.
5865 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5866 enum dev_master master, enum dev_state *state)
5869 struct fw_hello_cmd c;
5871 unsigned int master_mbox;
5872 int retries = FW_CMD_HELLO_RETRIES;
5875 memset(&c, 0, sizeof(c));
5876 INIT_CMD(c, HELLO, WRITE);
5877 c.err_to_clearinit = cpu_to_be32(
5878 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5879 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5880 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5881 mbox : FW_HELLO_CMD_MBMASTER_M) |
5882 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5883 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5884 FW_HELLO_CMD_CLEARINIT_F);
5887 * Issue the HELLO command to the firmware. If it's not successful
5888 * but indicates that we got a "busy" or "timeout" condition, retry
5889 * the HELLO until we exhaust our retry limit. If we do exceed our
5890 * retry limit, check to see if the firmware left us any error
5891 * information and report that if so.
5893 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5895 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
5897 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
5898 t4_report_fw_error(adap);
5902 v = be32_to_cpu(c.err_to_clearinit);
5903 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
5905 if (v & FW_HELLO_CMD_ERR_F)
5906 *state = DEV_STATE_ERR;
5907 else if (v & FW_HELLO_CMD_INIT_F)
5908 *state = DEV_STATE_INIT;
5910 *state = DEV_STATE_UNINIT;
5914 * If we're not the Master PF then we need to wait around for the
5915 * Master PF Driver to finish setting up the adapter.
5917 * Note that we also do this wait if we're a non-Master-capable PF and
5918 * there is no current Master PF; a Master PF may show up momentarily
5919 * and we wouldn't want to fail pointlessly. (This can happen when an
5920 * OS loads lots of different drivers rapidly at the same time). In
5921 * this case, the Master PF returned by the firmware will be
5922 * PCIE_FW_MASTER_M so the test below will work ...
5924 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
5925 master_mbox != mbox) {
5926 int waiting = FW_CMD_HELLO_TIMEOUT;
5929 * Wait for the firmware to either indicate an error or
5930 * initialized state. If we see either of these we bail out
5931 * and report the issue to the caller. If we exhaust the
5932 * "hello timeout" and we haven't exhausted our retries, try
5933 * again. Otherwise bail with a timeout error.
5942 * If neither Error nor Initialialized are indicated
5943 * by the firmware keep waiting till we exaust our
5944 * timeout ... and then retry if we haven't exhausted
5947 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
5948 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
5959 * We either have an Error or Initialized condition
5960 * report errors preferentially.
5963 if (pcie_fw & PCIE_FW_ERR_F)
5964 *state = DEV_STATE_ERR;
5965 else if (pcie_fw & PCIE_FW_INIT_F)
5966 *state = DEV_STATE_INIT;
5970 * If we arrived before a Master PF was selected and
5971 * there's not a valid Master PF, grab its identity
5974 if (master_mbox == PCIE_FW_MASTER_M &&
5975 (pcie_fw & PCIE_FW_MASTER_VLD_F))
5976 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
5985 * t4_fw_bye - end communication with FW
5986 * @adap: the adapter
5987 * @mbox: mailbox to use for the FW command
5989 * Issues a command to terminate communication with FW.
5991 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
5993 struct fw_bye_cmd c;
5995 memset(&c, 0, sizeof(c));
5996 INIT_CMD(c, BYE, WRITE);
5997 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6001 * t4_init_cmd - ask FW to initialize the device
6002 * @adap: the adapter
6003 * @mbox: mailbox to use for the FW command
6005 * Issues a command to FW to partially initialize the device. This
6006 * performs initialization that generally doesn't depend on user input.
6008 int t4_early_init(struct adapter *adap, unsigned int mbox)
6010 struct fw_initialize_cmd c;
6012 memset(&c, 0, sizeof(c));
6013 INIT_CMD(c, INITIALIZE, WRITE);
6014 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6018 * t4_fw_reset - issue a reset to FW
6019 * @adap: the adapter
6020 * @mbox: mailbox to use for the FW command
6021 * @reset: specifies the type of reset to perform
6023 * Issues a reset command of the specified type to FW.
6025 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6027 struct fw_reset_cmd c;
6029 memset(&c, 0, sizeof(c));
6030 INIT_CMD(c, RESET, WRITE);
6031 c.val = cpu_to_be32(reset);
6032 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6036 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6037 * @adap: the adapter
6038 * @mbox: mailbox to use for the FW RESET command (if desired)
6039 * @force: force uP into RESET even if FW RESET command fails
6041 * Issues a RESET command to firmware (if desired) with a HALT indication
6042 * and then puts the microprocessor into RESET state. The RESET command
6043 * will only be issued if a legitimate mailbox is provided (mbox <=
6044 * PCIE_FW_MASTER_M).
6046 * This is generally used in order for the host to safely manipulate the
6047 * adapter without fear of conflicting with whatever the firmware might
6048 * be doing. The only way out of this state is to RESTART the firmware
6051 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6056 * If a legitimate mailbox is provided, issue a RESET command
6057 * with a HALT indication.
6059 if (mbox <= PCIE_FW_MASTER_M) {
6060 struct fw_reset_cmd c;
6062 memset(&c, 0, sizeof(c));
6063 INIT_CMD(c, RESET, WRITE);
6064 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6065 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6066 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6070 * Normally we won't complete the operation if the firmware RESET
6071 * command fails but if our caller insists we'll go ahead and put the
6072 * uP into RESET. This can be useful if the firmware is hung or even
6073 * missing ... We'll have to take the risk of putting the uP into
6074 * RESET without the cooperation of firmware in that case.
6076 * We also force the firmware's HALT flag to be on in case we bypassed
6077 * the firmware RESET command above or we're dealing with old firmware
6078 * which doesn't have the HALT capability. This will serve as a flag
6079 * for the incoming firmware to know that it's coming out of a HALT
6080 * rather than a RESET ... if it's new enough to understand that ...
6082 if (ret == 0 || force) {
6083 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6084 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6089 * And we always return the result of the firmware RESET command
6090 * even when we force the uP into RESET ...
6096 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6097 * @adap: the adapter
6098 * @reset: if we want to do a RESET to restart things
6100 * Restart firmware previously halted by t4_fw_halt(). On successful
6101 * return the previous PF Master remains as the new PF Master and there
6102 * is no need to issue a new HELLO command, etc.
6104 * We do this in two ways:
6106 * 1. If we're dealing with newer firmware we'll simply want to take
6107 * the chip's microprocessor out of RESET. This will cause the
6108 * firmware to start up from its start vector. And then we'll loop
6109 * until the firmware indicates it's started again (PCIE_FW.HALT
6110 * reset to 0) or we timeout.
6112 * 2. If we're dealing with older firmware then we'll need to RESET
6113 * the chip since older firmware won't recognize the PCIE_FW.HALT
6114 * flag and automatically RESET itself on startup.
6116 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6120 * Since we're directing the RESET instead of the firmware
6121 * doing it automatically, we need to clear the PCIE_FW.HALT
6124 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6127 * If we've been given a valid mailbox, first try to get the
6128 * firmware to do the RESET. If that works, great and we can
6129 * return success. Otherwise, if we haven't been given a
6130 * valid mailbox or the RESET command failed, fall back to
6131 * hitting the chip with a hammer.
6133 if (mbox <= PCIE_FW_MASTER_M) {
6134 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6136 if (t4_fw_reset(adap, mbox,
6137 PIORST_F | PIORSTMODE_F) == 0)
6141 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6146 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6147 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6148 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6159 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6160 * @adap: the adapter
6161 * @mbox: mailbox to use for the FW RESET command (if desired)
6162 * @fw_data: the firmware image to write
6164 * @force: force upgrade even if firmware doesn't cooperate
6166 * Perform all of the steps necessary for upgrading an adapter's
6167 * firmware image. Normally this requires the cooperation of the
6168 * existing firmware in order to halt all existing activities
6169 * but if an invalid mailbox token is passed in we skip that step
6170 * (though we'll still put the adapter microprocessor into RESET in
6173 * On successful return the new firmware will have been loaded and
6174 * the adapter will have been fully RESET losing all previous setup
6175 * state. On unsuccessful return the adapter may be completely hosed ...
6176 * positive errno indicates that the adapter is ~probably~ intact, a
6177 * negative errno indicates that things are looking bad ...
6179 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6180 const u8 *fw_data, unsigned int size, int force)
6182 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6185 if (!t4_fw_matches_chip(adap, fw_hdr))
6188 /* Disable FW_OK flag so that mbox commands with FW_OK flag set
6189 * wont be sent when we are flashing FW.
6191 adap->flags &= ~FW_OK;
6193 ret = t4_fw_halt(adap, mbox, force);
6194 if (ret < 0 && !force)
6197 ret = t4_load_fw(adap, fw_data, size);
6202 * Older versions of the firmware don't understand the new
6203 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6204 * restart. So for newly loaded older firmware we'll have to do the
6205 * RESET for it so it starts up on a clean slate. We can tell if
6206 * the newly loaded firmware will handle this right by checking
6207 * its header flags to see if it advertises the capability.
6209 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6210 ret = t4_fw_restart(adap, mbox, reset);
6212 /* Grab potentially new Firmware Device Log parameters so we can see
6213 * how healthy the new Firmware is. It's okay to contact the new
6214 * Firmware for these parameters even though, as far as it's
6215 * concerned, we've never said "HELLO" to it ...
6217 (void)t4_init_devlog_params(adap);
6219 adap->flags |= FW_OK;
6224 * t4_fl_pkt_align - return the fl packet alignment
6225 * @adap: the adapter
6227 * T4 has a single field to specify the packing and padding boundary.
6228 * T5 onwards has separate fields for this and hence the alignment for
6229 * next packet offset is maximum of these two.
6232 int t4_fl_pkt_align(struct adapter *adap)
6234 u32 sge_control, sge_control2;
6235 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6237 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6239 /* T4 uses a single control field to specify both the PCIe Padding and
6240 * Packing Boundary. T5 introduced the ability to specify these
6241 * separately. The actual Ingress Packet Data alignment boundary
6242 * within Packed Buffer Mode is the maximum of these two
6243 * specifications. (Note that it makes no real practical sense to
6244 * have the Pading Boudary be larger than the Packing Boundary but you
6245 * could set the chip up that way and, in fact, legacy T4 code would
6246 * end doing this because it would initialize the Padding Boundary and
6247 * leave the Packing Boundary initialized to 0 (16 bytes).)
6248 * Padding Boundary values in T6 starts from 8B,
6249 * where as it is 32B for T4 and T5.
6251 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6252 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6254 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6256 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6258 fl_align = ingpadboundary;
6259 if (!is_t4(adap->params.chip)) {
6260 /* T5 has a weird interpretation of one of the PCIe Packing
6261 * Boundary values. No idea why ...
6263 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6264 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6265 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6266 ingpackboundary = 16;
6268 ingpackboundary = 1 << (ingpackboundary +
6269 INGPACKBOUNDARY_SHIFT_X);
6271 fl_align = max(ingpadboundary, ingpackboundary);
6277 * t4_fixup_host_params - fix up host-dependent parameters
6278 * @adap: the adapter
6279 * @page_size: the host's Base Page Size
6280 * @cache_line_size: the host's Cache Line Size
6282 * Various registers in T4 contain values which are dependent on the
6283 * host's Base Page and Cache Line Sizes. This function will fix all of
6284 * those registers with the appropriate values as passed in ...
6286 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6287 unsigned int cache_line_size)
6289 unsigned int page_shift = fls(page_size) - 1;
6290 unsigned int sge_hps = page_shift - 10;
6291 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6292 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6293 unsigned int fl_align_log = fls(fl_align) - 1;
6294 unsigned int ingpad;
6296 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6297 HOSTPAGESIZEPF0_V(sge_hps) |
6298 HOSTPAGESIZEPF1_V(sge_hps) |
6299 HOSTPAGESIZEPF2_V(sge_hps) |
6300 HOSTPAGESIZEPF3_V(sge_hps) |
6301 HOSTPAGESIZEPF4_V(sge_hps) |
6302 HOSTPAGESIZEPF5_V(sge_hps) |
6303 HOSTPAGESIZEPF6_V(sge_hps) |
6304 HOSTPAGESIZEPF7_V(sge_hps));
6306 if (is_t4(adap->params.chip)) {
6307 t4_set_reg_field(adap, SGE_CONTROL_A,
6308 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6309 EGRSTATUSPAGESIZE_F,
6310 INGPADBOUNDARY_V(fl_align_log -
6311 INGPADBOUNDARY_SHIFT_X) |
6312 EGRSTATUSPAGESIZE_V(stat_len != 64));
6314 /* T5 introduced the separation of the Free List Padding and
6315 * Packing Boundaries. Thus, we can select a smaller Padding
6316 * Boundary to avoid uselessly chewing up PCIe Link and Memory
6317 * Bandwidth, and use a Packing Boundary which is large enough
6318 * to avoid false sharing between CPUs, etc.
6320 * For the PCI Link, the smaller the Padding Boundary the
6321 * better. For the Memory Controller, a smaller Padding
6322 * Boundary is better until we cross under the Memory Line
6323 * Size (the minimum unit of transfer to/from Memory). If we
6324 * have a Padding Boundary which is smaller than the Memory
6325 * Line Size, that'll involve a Read-Modify-Write cycle on the
6326 * Memory Controller which is never good. For T5 the smallest
6327 * Padding Boundary which we can select is 32 bytes which is
6328 * larger than any known Memory Controller Line Size so we'll
6331 * T5 has a different interpretation of the "0" value for the
6332 * Packing Boundary. This corresponds to 16 bytes instead of
6333 * the expected 32 bytes. We never have a Packing Boundary
6334 * less than 32 bytes so we can't use that special value but
6335 * on the other hand, if we wanted 32 bytes, the best we can
6336 * really do is 64 bytes.
6338 if (fl_align <= 32) {
6343 if (is_t5(adap->params.chip))
6344 ingpad = INGPCIEBOUNDARY_32B_X;
6346 ingpad = T6_INGPADBOUNDARY_32B_X;
6348 t4_set_reg_field(adap, SGE_CONTROL_A,
6349 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6350 EGRSTATUSPAGESIZE_F,
6351 INGPADBOUNDARY_V(ingpad) |
6352 EGRSTATUSPAGESIZE_V(stat_len != 64));
6353 t4_set_reg_field(adap, SGE_CONTROL2_A,
6354 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6355 INGPACKBOUNDARY_V(fl_align_log -
6356 INGPACKBOUNDARY_SHIFT_X));
6359 * Adjust various SGE Free List Host Buffer Sizes.
6361 * This is something of a crock since we're using fixed indices into
6362 * the array which are also known by the sge.c code and the T4
6363 * Firmware Configuration File. We need to come up with a much better
6364 * approach to managing this array. For now, the first four entries
6369 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6370 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6372 * For the single-MTU buffers in unpacked mode we need to include
6373 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6374 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6375 * Padding boundary. All of these are accommodated in the Factory
6376 * Default Firmware Configuration File but we need to adjust it for
6377 * this host's cache line size.
6379 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6380 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6381 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6383 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6384 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6387 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6393 * t4_fw_initialize - ask FW to initialize the device
6394 * @adap: the adapter
6395 * @mbox: mailbox to use for the FW command
6397 * Issues a command to FW to partially initialize the device. This
6398 * performs initialization that generally doesn't depend on user input.
6400 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6402 struct fw_initialize_cmd c;
6404 memset(&c, 0, sizeof(c));
6405 INIT_CMD(c, INITIALIZE, WRITE);
6406 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6410 * t4_query_params_rw - query FW or device parameters
6411 * @adap: the adapter
6412 * @mbox: mailbox to use for the FW command
6415 * @nparams: the number of parameters
6416 * @params: the parameter names
6417 * @val: the parameter values
6418 * @rw: Write and read flag
6420 * Reads the value of FW or device parameters. Up to 7 parameters can be
6423 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6424 unsigned int vf, unsigned int nparams, const u32 *params,
6428 struct fw_params_cmd c;
6429 __be32 *p = &c.param[0].mnem;
6434 memset(&c, 0, sizeof(c));
6435 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6436 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6437 FW_PARAMS_CMD_PFN_V(pf) |
6438 FW_PARAMS_CMD_VFN_V(vf));
6439 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6441 for (i = 0; i < nparams; i++) {
6442 *p++ = cpu_to_be32(*params++);
6444 *p = cpu_to_be32(*(val + i));
6448 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6450 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6451 *val++ = be32_to_cpu(*p);
6455 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6456 unsigned int vf, unsigned int nparams, const u32 *params,
6459 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6463 * t4_set_params_timeout - sets FW or device parameters
6464 * @adap: the adapter
6465 * @mbox: mailbox to use for the FW command
6468 * @nparams: the number of parameters
6469 * @params: the parameter names
6470 * @val: the parameter values
6471 * @timeout: the timeout time
6473 * Sets the value of FW or device parameters. Up to 7 parameters can be
6474 * specified at once.
6476 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6477 unsigned int pf, unsigned int vf,
6478 unsigned int nparams, const u32 *params,
6479 const u32 *val, int timeout)
6481 struct fw_params_cmd c;
6482 __be32 *p = &c.param[0].mnem;
6487 memset(&c, 0, sizeof(c));
6488 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6489 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6490 FW_PARAMS_CMD_PFN_V(pf) |
6491 FW_PARAMS_CMD_VFN_V(vf));
6492 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6495 *p++ = cpu_to_be32(*params++);
6496 *p++ = cpu_to_be32(*val++);
6499 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6503 * t4_set_params - sets FW or device parameters
6504 * @adap: the adapter
6505 * @mbox: mailbox to use for the FW command
6508 * @nparams: the number of parameters
6509 * @params: the parameter names
6510 * @val: the parameter values
6512 * Sets the value of FW or device parameters. Up to 7 parameters can be
6513 * specified at once.
6515 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6516 unsigned int vf, unsigned int nparams, const u32 *params,
6519 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6520 FW_CMD_MAX_TIMEOUT);
6524 * t4_cfg_pfvf - configure PF/VF resource limits
6525 * @adap: the adapter
6526 * @mbox: mailbox to use for the FW command
6527 * @pf: the PF being configured
6528 * @vf: the VF being configured
6529 * @txq: the max number of egress queues
6530 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
6531 * @rxqi: the max number of interrupt-capable ingress queues
6532 * @rxq: the max number of interruptless ingress queues
6533 * @tc: the PCI traffic class
6534 * @vi: the max number of virtual interfaces
6535 * @cmask: the channel access rights mask for the PF/VF
6536 * @pmask: the port access rights mask for the PF/VF
6537 * @nexact: the maximum number of exact MPS filters
6538 * @rcaps: read capabilities
6539 * @wxcaps: write/execute capabilities
6541 * Configures resource limits and capabilities for a physical or virtual
6544 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6545 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6546 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6547 unsigned int vi, unsigned int cmask, unsigned int pmask,
6548 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6550 struct fw_pfvf_cmd c;
6552 memset(&c, 0, sizeof(c));
6553 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6554 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6555 FW_PFVF_CMD_VFN_V(vf));
6556 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6557 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6558 FW_PFVF_CMD_NIQ_V(rxq));
6559 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6560 FW_PFVF_CMD_PMASK_V(pmask) |
6561 FW_PFVF_CMD_NEQ_V(txq));
6562 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6563 FW_PFVF_CMD_NVI_V(vi) |
6564 FW_PFVF_CMD_NEXACTF_V(nexact));
6565 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6566 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6567 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6568 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6572 * t4_alloc_vi - allocate a virtual interface
6573 * @adap: the adapter
6574 * @mbox: mailbox to use for the FW command
6575 * @port: physical port associated with the VI
6576 * @pf: the PF owning the VI
6577 * @vf: the VF owning the VI
6578 * @nmac: number of MAC addresses needed (1 to 5)
6579 * @mac: the MAC addresses of the VI
6580 * @rss_size: size of RSS table slice associated with this VI
6582 * Allocates a virtual interface for the given physical port. If @mac is
6583 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
6584 * @mac should be large enough to hold @nmac Ethernet addresses, they are
6585 * stored consecutively so the space needed is @nmac * 6 bytes.
6586 * Returns a negative error number or the non-negative VI id.
6588 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6589 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6590 unsigned int *rss_size)
6595 memset(&c, 0, sizeof(c));
6596 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6597 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6598 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6599 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6600 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6603 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6608 memcpy(mac, c.mac, sizeof(c.mac));
6611 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6613 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6615 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6617 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
6621 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6622 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6626 * t4_free_vi - free a virtual interface
6627 * @adap: the adapter
6628 * @mbox: mailbox to use for the FW command
6629 * @pf: the PF owning the VI
6630 * @vf: the VF owning the VI
6631 * @viid: virtual interface identifiler
6633 * Free a previously allocated virtual interface.
6635 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6636 unsigned int vf, unsigned int viid)
6640 memset(&c, 0, sizeof(c));
6641 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6644 FW_VI_CMD_PFN_V(pf) |
6645 FW_VI_CMD_VFN_V(vf));
6646 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6647 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6649 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6653 * t4_set_rxmode - set Rx properties of a virtual interface
6654 * @adap: the adapter
6655 * @mbox: mailbox to use for the FW command
6657 * @mtu: the new MTU or -1
6658 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6659 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6660 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6661 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6662 * @sleep_ok: if true we may sleep while awaiting command completion
6664 * Sets Rx properties of a virtual interface.
6666 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6667 int mtu, int promisc, int all_multi, int bcast, int vlanex,
6670 struct fw_vi_rxmode_cmd c;
6672 /* convert to FW values */
6674 mtu = FW_RXMODE_MTU_NO_CHG;
6676 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6678 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6680 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6682 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6684 memset(&c, 0, sizeof(c));
6685 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6686 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6687 FW_VI_RXMODE_CMD_VIID_V(viid));
6688 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6690 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6691 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6692 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6693 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6694 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6695 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6699 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6700 * @adap: the adapter
6701 * @mbox: mailbox to use for the FW command
6703 * @free: if true any existing filters for this VI id are first removed
6704 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6705 * @addr: the MAC address(es)
6706 * @idx: where to store the index of each allocated filter
6707 * @hash: pointer to hash address filter bitmap
6708 * @sleep_ok: call is allowed to sleep
6710 * Allocates an exact-match filter for each of the supplied addresses and
6711 * sets it to the corresponding address. If @idx is not %NULL it should
6712 * have at least @naddr entries, each of which will be set to the index of
6713 * the filter allocated for the corresponding MAC address. If a filter
6714 * could not be allocated for an address its index is set to 0xffff.
6715 * If @hash is not %NULL addresses that fail to allocate an exact filter
6716 * are hashed and update the hash filter bitmap pointed at by @hash.
6718 * Returns a negative error number or the number of filters allocated.
6720 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6721 unsigned int viid, bool free, unsigned int naddr,
6722 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6724 int offset, ret = 0;
6725 struct fw_vi_mac_cmd c;
6726 unsigned int nfilters = 0;
6727 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6728 unsigned int rem = naddr;
6730 if (naddr > max_naddr)
6733 for (offset = 0; offset < naddr ; /**/) {
6734 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6735 rem : ARRAY_SIZE(c.u.exact));
6736 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6737 u.exact[fw_naddr]), 16);
6738 struct fw_vi_mac_exact *p;
6741 memset(&c, 0, sizeof(c));
6742 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6745 FW_CMD_EXEC_V(free) |
6746 FW_VI_MAC_CMD_VIID_V(viid));
6747 c.freemacs_to_len16 =
6748 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6749 FW_CMD_LEN16_V(len16));
6751 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6753 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6754 FW_VI_MAC_CMD_IDX_V(
6755 FW_VI_MAC_ADD_MAC));
6756 memcpy(p->macaddr, addr[offset + i],
6757 sizeof(p->macaddr));
6760 /* It's okay if we run out of space in our MAC address arena.
6761 * Some of the addresses we submit may get stored so we need
6762 * to run through the reply to see what the results were ...
6764 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6765 if (ret && ret != -FW_ENOMEM)
6768 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6769 u16 index = FW_VI_MAC_CMD_IDX_G(
6770 be16_to_cpu(p->valid_to_idx));
6773 idx[offset + i] = (index >= max_naddr ?
6775 if (index < max_naddr)
6779 hash_mac_addr(addr[offset + i]));
6787 if (ret == 0 || ret == -FW_ENOMEM)
6793 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
6794 * @adap: the adapter
6795 * @mbox: mailbox to use for the FW command
6797 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6798 * @addr: the MAC address(es)
6799 * @sleep_ok: call is allowed to sleep
6801 * Frees the exact-match filter for each of the supplied addresses
6803 * Returns a negative error number or the number of filters freed.
6805 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
6806 unsigned int viid, unsigned int naddr,
6807 const u8 **addr, bool sleep_ok)
6809 int offset, ret = 0;
6810 struct fw_vi_mac_cmd c;
6811 unsigned int nfilters = 0;
6812 unsigned int max_naddr = is_t4(adap->params.chip) ?
6813 NUM_MPS_CLS_SRAM_L_INSTANCES :
6814 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6815 unsigned int rem = naddr;
6817 if (naddr > max_naddr)
6820 for (offset = 0; offset < (int)naddr ; /**/) {
6821 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6823 : ARRAY_SIZE(c.u.exact));
6824 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6825 u.exact[fw_naddr]), 16);
6826 struct fw_vi_mac_exact *p;
6829 memset(&c, 0, sizeof(c));
6830 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6834 FW_VI_MAC_CMD_VIID_V(viid));
6835 c.freemacs_to_len16 =
6836 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
6837 FW_CMD_LEN16_V(len16));
6839 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
6840 p->valid_to_idx = cpu_to_be16(
6841 FW_VI_MAC_CMD_VALID_F |
6842 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
6843 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6846 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6850 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6851 u16 index = FW_VI_MAC_CMD_IDX_G(
6852 be16_to_cpu(p->valid_to_idx));
6854 if (index < max_naddr)
6868 * t4_change_mac - modifies the exact-match filter for a MAC address
6869 * @adap: the adapter
6870 * @mbox: mailbox to use for the FW command
6872 * @idx: index of existing filter for old value of MAC address, or -1
6873 * @addr: the new MAC address value
6874 * @persist: whether a new MAC allocation should be persistent
6875 * @add_smt: if true also add the address to the HW SMT
6877 * Modifies an exact-match filter and sets it to the new MAC address.
6878 * Note that in general it is not possible to modify the value of a given
6879 * filter so the generic way to modify an address filter is to free the one
6880 * being used by the old address value and allocate a new filter for the
6881 * new address value. @idx can be -1 if the address is a new addition.
6883 * Returns a negative error number or the index of the filter with the new
6886 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
6887 int idx, const u8 *addr, bool persist, bool add_smt)
6890 struct fw_vi_mac_cmd c;
6891 struct fw_vi_mac_exact *p = c.u.exact;
6892 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
6894 if (idx < 0) /* new allocation */
6895 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
6896 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
6898 memset(&c, 0, sizeof(c));
6899 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6900 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6901 FW_VI_MAC_CMD_VIID_V(viid));
6902 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
6903 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6904 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
6905 FW_VI_MAC_CMD_IDX_V(idx));
6906 memcpy(p->macaddr, addr, sizeof(p->macaddr));
6908 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6910 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
6911 if (ret >= max_mac_addr)
6918 * t4_set_addr_hash - program the MAC inexact-match hash filter
6919 * @adap: the adapter
6920 * @mbox: mailbox to use for the FW command
6922 * @ucast: whether the hash filter should also match unicast addresses
6923 * @vec: the value to be written to the hash filter
6924 * @sleep_ok: call is allowed to sleep
6926 * Sets the 64-bit inexact-match hash filter for a virtual interface.
6928 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
6929 bool ucast, u64 vec, bool sleep_ok)
6931 struct fw_vi_mac_cmd c;
6933 memset(&c, 0, sizeof(c));
6934 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6935 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6936 FW_VI_ENABLE_CMD_VIID_V(viid));
6937 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
6938 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
6940 c.u.hash.hashvec = cpu_to_be64(vec);
6941 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6945 * t4_enable_vi_params - enable/disable a virtual interface
6946 * @adap: the adapter
6947 * @mbox: mailbox to use for the FW command
6949 * @rx_en: 1=enable Rx, 0=disable Rx
6950 * @tx_en: 1=enable Tx, 0=disable Tx
6951 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
6953 * Enables/disables a virtual interface. Note that setting DCB Enable
6954 * only makes sense when enabling a Virtual Interface ...
6956 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
6957 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
6959 struct fw_vi_enable_cmd c;
6961 memset(&c, 0, sizeof(c));
6962 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6963 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6964 FW_VI_ENABLE_CMD_VIID_V(viid));
6965 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
6966 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
6967 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
6969 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
6973 * t4_enable_vi - enable/disable a virtual interface
6974 * @adap: the adapter
6975 * @mbox: mailbox to use for the FW command
6977 * @rx_en: 1=enable Rx, 0=disable Rx
6978 * @tx_en: 1=enable Tx, 0=disable Tx
6980 * Enables/disables a virtual interface.
6982 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
6983 bool rx_en, bool tx_en)
6985 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
6989 * t4_identify_port - identify a VI's port by blinking its LED
6990 * @adap: the adapter
6991 * @mbox: mailbox to use for the FW command
6993 * @nblinks: how many times to blink LED at 2.5 Hz
6995 * Identifies a VI's port by blinking its LED.
6997 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
6998 unsigned int nblinks)
7000 struct fw_vi_enable_cmd c;
7002 memset(&c, 0, sizeof(c));
7003 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7004 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7005 FW_VI_ENABLE_CMD_VIID_V(viid));
7006 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
7007 c.blinkdur = cpu_to_be16(nblinks);
7008 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7012 * t4_iq_stop - stop an ingress queue and its FLs
7013 * @adap: the adapter
7014 * @mbox: mailbox to use for the FW command
7015 * @pf: the PF owning the queues
7016 * @vf: the VF owning the queues
7017 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7018 * @iqid: ingress queue id
7019 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7020 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7022 * Stops an ingress queue and its associated FLs, if any. This causes
7023 * any current or future data/messages destined for these queues to be
7026 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7027 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7028 unsigned int fl0id, unsigned int fl1id)
7032 memset(&c, 0, sizeof(c));
7033 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7034 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7035 FW_IQ_CMD_VFN_V(vf));
7036 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7037 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7038 c.iqid = cpu_to_be16(iqid);
7039 c.fl0id = cpu_to_be16(fl0id);
7040 c.fl1id = cpu_to_be16(fl1id);
7041 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7045 * t4_iq_free - free an ingress queue and its FLs
7046 * @adap: the adapter
7047 * @mbox: mailbox to use for the FW command
7048 * @pf: the PF owning the queues
7049 * @vf: the VF owning the queues
7050 * @iqtype: the ingress queue type
7051 * @iqid: ingress queue id
7052 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7053 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7055 * Frees an ingress queue and its associated FLs, if any.
7057 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7058 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7059 unsigned int fl0id, unsigned int fl1id)
7063 memset(&c, 0, sizeof(c));
7064 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7065 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7066 FW_IQ_CMD_VFN_V(vf));
7067 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7068 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7069 c.iqid = cpu_to_be16(iqid);
7070 c.fl0id = cpu_to_be16(fl0id);
7071 c.fl1id = cpu_to_be16(fl1id);
7072 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7076 * t4_eth_eq_free - free an Ethernet egress queue
7077 * @adap: the adapter
7078 * @mbox: mailbox to use for the FW command
7079 * @pf: the PF owning the queue
7080 * @vf: the VF owning the queue
7081 * @eqid: egress queue id
7083 * Frees an Ethernet egress queue.
7085 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7086 unsigned int vf, unsigned int eqid)
7088 struct fw_eq_eth_cmd c;
7090 memset(&c, 0, sizeof(c));
7091 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7092 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7093 FW_EQ_ETH_CMD_PFN_V(pf) |
7094 FW_EQ_ETH_CMD_VFN_V(vf));
7095 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7096 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7097 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7101 * t4_ctrl_eq_free - free a control egress queue
7102 * @adap: the adapter
7103 * @mbox: mailbox to use for the FW command
7104 * @pf: the PF owning the queue
7105 * @vf: the VF owning the queue
7106 * @eqid: egress queue id
7108 * Frees a control egress queue.
7110 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7111 unsigned int vf, unsigned int eqid)
7113 struct fw_eq_ctrl_cmd c;
7115 memset(&c, 0, sizeof(c));
7116 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7117 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7118 FW_EQ_CTRL_CMD_PFN_V(pf) |
7119 FW_EQ_CTRL_CMD_VFN_V(vf));
7120 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7121 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7122 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7126 * t4_ofld_eq_free - free an offload egress queue
7127 * @adap: the adapter
7128 * @mbox: mailbox to use for the FW command
7129 * @pf: the PF owning the queue
7130 * @vf: the VF owning the queue
7131 * @eqid: egress queue id
7133 * Frees a control egress queue.
7135 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7136 unsigned int vf, unsigned int eqid)
7138 struct fw_eq_ofld_cmd c;
7140 memset(&c, 0, sizeof(c));
7141 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7142 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7143 FW_EQ_OFLD_CMD_PFN_V(pf) |
7144 FW_EQ_OFLD_CMD_VFN_V(vf));
7145 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7146 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7147 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7151 * t4_link_down_rc_str - return a string for a Link Down Reason Code
7152 * @adap: the adapter
7153 * @link_down_rc: Link Down Reason Code
7155 * Returns a string representation of the Link Down Reason Code.
7157 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7159 static const char * const reason[] = {
7162 "Auto-negotiation Failure",
7164 "Insufficient Airflow",
7165 "Unable To Determine Reason",
7166 "No RX Signal Detected",
7170 if (link_down_rc >= ARRAY_SIZE(reason))
7171 return "Bad Reason Code";
7173 return reason[link_down_rc];
7177 * t4_handle_get_port_info - process a FW reply message
7178 * @pi: the port info
7179 * @rpl: start of the FW message
7181 * Processes a GET_PORT_INFO FW reply message.
7183 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
7185 const struct fw_port_cmd *p = (const void *)rpl;
7186 struct adapter *adap = pi->adapter;
7188 /* link/module state change message */
7189 int speed = 0, fc = 0;
7190 struct link_config *lc;
7191 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7192 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
7193 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
7195 if (stat & FW_PORT_CMD_RXPAUSE_F)
7197 if (stat & FW_PORT_CMD_TXPAUSE_F)
7199 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7201 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7203 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7205 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
7207 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7209 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
7214 if (mod != pi->mod_type) {
7216 t4_os_portmod_changed(adap, pi->port_id);
7218 if (link_ok != lc->link_ok || speed != lc->speed ||
7219 fc != lc->fc) { /* something changed */
7220 if (!link_ok && lc->link_ok) {
7221 unsigned char rc = FW_PORT_CMD_LINKDNRC_G(stat);
7223 lc->link_down_rc = rc;
7224 dev_warn(adap->pdev_dev,
7225 "Port %d link down, reason: %s\n",
7226 pi->port_id, t4_link_down_rc_str(rc));
7228 lc->link_ok = link_ok;
7231 lc->supported = be16_to_cpu(p->u.info.pcap);
7232 lc->lp_advertising = be16_to_cpu(p->u.info.lpacap);
7233 t4_os_link_changed(adap, pi->port_id, link_ok);
7238 * t4_handle_fw_rpl - process a FW reply message
7239 * @adap: the adapter
7240 * @rpl: start of the FW message
7242 * Processes a FW message, such as link state change messages.
7244 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7246 u8 opcode = *(const u8 *)rpl;
7248 /* This might be a port command ... this simplifies the following
7249 * conditionals ... We can get away with pre-dereferencing
7250 * action_to_len16 because it's in the first 16 bytes and all messages
7251 * will be at least that long.
7253 const struct fw_port_cmd *p = (const void *)rpl;
7254 unsigned int action =
7255 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
7257 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7259 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
7260 struct port_info *pi = NULL;
7262 for_each_port(adap, i) {
7263 pi = adap2pinfo(adap, i);
7264 if (pi->tx_chan == chan)
7268 t4_handle_get_port_info(pi, rpl);
7270 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n", opcode);
7276 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
7280 if (pci_is_pcie(adapter->pdev)) {
7281 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
7282 p->speed = val & PCI_EXP_LNKSTA_CLS;
7283 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7288 * init_link_config - initialize a link's SW state
7289 * @lc: structure holding the link state
7290 * @caps: link capabilities
7292 * Initializes the SW state maintained for each link, including the link's
7293 * capabilities and default speed/flow-control/autonegotiation settings.
7295 static void init_link_config(struct link_config *lc, unsigned int caps)
7297 lc->supported = caps;
7298 lc->lp_advertising = 0;
7299 lc->requested_speed = 0;
7301 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7302 if (lc->supported & FW_PORT_CAP_ANEG) {
7303 lc->advertising = lc->supported & ADVERT_MASK;
7304 lc->autoneg = AUTONEG_ENABLE;
7305 lc->requested_fc |= PAUSE_AUTONEG;
7307 lc->advertising = 0;
7308 lc->autoneg = AUTONEG_DISABLE;
7312 #define CIM_PF_NOACCESS 0xeeeeeeee
7314 int t4_wait_dev_ready(void __iomem *regs)
7318 whoami = readl(regs + PL_WHOAMI_A);
7319 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7323 whoami = readl(regs + PL_WHOAMI_A);
7324 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7328 u32 vendor_and_model_id;
7332 static int get_flash_params(struct adapter *adap)
7334 /* Table for non-Numonix supported flash parts. Numonix parts are left
7335 * to the preexisting code. All flash parts have 64KB sectors.
7337 static struct flash_desc supported_flash[] = {
7338 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
7344 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7346 ret = sf1_read(adap, 3, 0, 1, &info);
7347 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
7351 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7352 if (supported_flash[ret].vendor_and_model_id == info) {
7353 adap->params.sf_size = supported_flash[ret].size_mb;
7354 adap->params.sf_nsec =
7355 adap->params.sf_size / SF_SEC_SIZE;
7359 if ((info & 0xff) != 0x20) /* not a Numonix flash */
7361 info >>= 16; /* log2 of size */
7362 if (info >= 0x14 && info < 0x18)
7363 adap->params.sf_nsec = 1 << (info - 16);
7364 else if (info == 0x18)
7365 adap->params.sf_nsec = 64;
7368 adap->params.sf_size = 1 << info;
7369 adap->params.sf_fw_start =
7370 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7372 if (adap->params.sf_size < FLASH_MIN_SIZE)
7373 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7374 adap->params.sf_size, FLASH_MIN_SIZE);
7378 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7383 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7385 pci_read_config_word(adapter->pdev,
7386 pcie_cap + PCI_EXP_DEVCTL2, &val);
7387 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7389 pci_write_config_word(adapter->pdev,
7390 pcie_cap + PCI_EXP_DEVCTL2, val);
7395 * t4_prep_adapter - prepare SW and HW for operation
7396 * @adapter: the adapter
7397 * @reset: if true perform a HW reset
7399 * Initialize adapter SW state for the various HW modules, set initial
7400 * values for some adapter tunables, take PHYs out of reset, and
7401 * initialize the MDIO interface.
7403 int t4_prep_adapter(struct adapter *adapter)
7409 get_pci_mode(adapter, &adapter->params.pci);
7410 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7412 ret = get_flash_params(adapter);
7414 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7418 /* Retrieve adapter's device ID
7420 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7421 ver = device_id >> 12;
7422 adapter->params.chip = 0;
7425 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7426 adapter->params.arch.sge_fl_db = DBPRIO_F;
7427 adapter->params.arch.mps_tcam_size =
7428 NUM_MPS_CLS_SRAM_L_INSTANCES;
7429 adapter->params.arch.mps_rplc_size = 128;
7430 adapter->params.arch.nchan = NCHAN;
7431 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7432 adapter->params.arch.vfcount = 128;
7433 /* Congestion map is for 4 channels so that
7434 * MPS can have 4 priority per port.
7436 adapter->params.arch.cng_ch_bits_log = 2;
7439 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7440 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7441 adapter->params.arch.mps_tcam_size =
7442 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7443 adapter->params.arch.mps_rplc_size = 128;
7444 adapter->params.arch.nchan = NCHAN;
7445 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7446 adapter->params.arch.vfcount = 128;
7447 adapter->params.arch.cng_ch_bits_log = 2;
7450 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7451 adapter->params.arch.sge_fl_db = 0;
7452 adapter->params.arch.mps_tcam_size =
7453 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7454 adapter->params.arch.mps_rplc_size = 256;
7455 adapter->params.arch.nchan = 2;
7456 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7457 adapter->params.arch.vfcount = 256;
7458 /* Congestion map will be for 2 channels so that
7459 * MPS can have 8 priority per port.
7461 adapter->params.arch.cng_ch_bits_log = 3;
7464 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7469 adapter->params.cim_la_size = CIMLA_SIZE;
7470 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7473 * Default port for debugging in case we can't reach FW.
7475 adapter->params.nports = 1;
7476 adapter->params.portvec = 1;
7477 adapter->params.vpd.cclk = 50000;
7479 /* Set pci completion timeout value to 4 seconds. */
7480 set_pcie_completion_timeout(adapter, 0xd);
7485 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7486 * @adapter: the adapter
7487 * @qid: the Queue ID
7488 * @qtype: the Ingress or Egress type for @qid
7489 * @user: true if this request is for a user mode queue
7490 * @pbar2_qoffset: BAR2 Queue Offset
7491 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7493 * Returns the BAR2 SGE Queue Registers information associated with the
7494 * indicated Absolute Queue ID. These are passed back in return value
7495 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7496 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7498 * This may return an error which indicates that BAR2 SGE Queue
7499 * registers aren't available. If an error is not returned, then the
7500 * following values are returned:
7502 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7503 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7505 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7506 * require the "Inferred Queue ID" ability may be used. E.g. the
7507 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7508 * then these "Inferred Queue ID" register may not be used.
7510 int t4_bar2_sge_qregs(struct adapter *adapter,
7512 enum t4_bar2_qtype qtype,
7515 unsigned int *pbar2_qid)
7517 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7518 u64 bar2_page_offset, bar2_qoffset;
7519 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7521 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7522 if (!user && is_t4(adapter->params.chip))
7525 /* Get our SGE Page Size parameters.
7527 page_shift = adapter->params.sge.hps + 10;
7528 page_size = 1 << page_shift;
7530 /* Get the right Queues per Page parameters for our Queue.
7532 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7533 ? adapter->params.sge.eq_qpp
7534 : adapter->params.sge.iq_qpp);
7535 qpp_mask = (1 << qpp_shift) - 1;
7537 /* Calculate the basics of the BAR2 SGE Queue register area:
7538 * o The BAR2 page the Queue registers will be in.
7539 * o The BAR2 Queue ID.
7540 * o The BAR2 Queue ID Offset into the BAR2 page.
7542 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7543 bar2_qid = qid & qpp_mask;
7544 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7546 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7547 * hardware will infer the Absolute Queue ID simply from the writes to
7548 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7549 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
7550 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7551 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7552 * from the BAR2 Page and BAR2 Queue ID.
7554 * One important censequence of this is that some BAR2 SGE registers
7555 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7556 * there. But other registers synthesize the SGE Queue ID purely
7557 * from the writes to the registers -- the Write Combined Doorbell
7558 * Buffer is a good example. These BAR2 SGE Registers are only
7559 * available for those BAR2 SGE Register areas where the SGE Absolute
7560 * Queue ID can be inferred from simple writes.
7562 bar2_qoffset = bar2_page_offset;
7563 bar2_qinferred = (bar2_qid_offset < page_size);
7564 if (bar2_qinferred) {
7565 bar2_qoffset += bar2_qid_offset;
7569 *pbar2_qoffset = bar2_qoffset;
7570 *pbar2_qid = bar2_qid;
7575 * t4_init_devlog_params - initialize adapter->params.devlog
7576 * @adap: the adapter
7578 * Initialize various fields of the adapter's Firmware Device Log
7579 * Parameters structure.
7581 int t4_init_devlog_params(struct adapter *adap)
7583 struct devlog_params *dparams = &adap->params.devlog;
7585 unsigned int devlog_meminfo;
7586 struct fw_devlog_cmd devlog_cmd;
7589 /* If we're dealing with newer firmware, the Device Log Paramerters
7590 * are stored in a designated register which allows us to access the
7591 * Device Log even if we can't talk to the firmware.
7594 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7596 unsigned int nentries, nentries128;
7598 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7599 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7601 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7602 nentries = (nentries128 + 1) * 128;
7603 dparams->size = nentries * sizeof(struct fw_devlog_e);
7608 /* Otherwise, ask the firmware for it's Device Log Parameters.
7610 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7611 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7612 FW_CMD_REQUEST_F | FW_CMD_READ_F);
7613 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7614 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7620 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7621 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7622 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7623 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7629 * t4_init_sge_params - initialize adap->params.sge
7630 * @adapter: the adapter
7632 * Initialize various fields of the adapter's SGE Parameters structure.
7634 int t4_init_sge_params(struct adapter *adapter)
7636 struct sge_params *sge_params = &adapter->params.sge;
7638 unsigned int s_hps, s_qpp;
7640 /* Extract the SGE Page Size for our PF.
7642 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7643 s_hps = (HOSTPAGESIZEPF0_S +
7644 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7645 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7647 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7649 s_qpp = (QUEUESPERPAGEPF0_S +
7650 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7651 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7652 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7653 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7654 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7660 * t4_init_tp_params - initialize adap->params.tp
7661 * @adap: the adapter
7663 * Initialize various fields of the adapter's TP Parameters structure.
7665 int t4_init_tp_params(struct adapter *adap)
7670 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7671 adap->params.tp.tre = TIMERRESOLUTION_G(v);
7672 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7674 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7675 for (chan = 0; chan < NCHAN; chan++)
7676 adap->params.tp.tx_modq[chan] = chan;
7678 /* Cache the adapter's Compressed Filter Mode and global Incress
7681 if (t4_use_ldst(adap)) {
7682 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7683 TP_VLAN_PRI_MAP_A, 1);
7684 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7685 TP_INGRESS_CONFIG_A, 1);
7687 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7688 &adap->params.tp.vlan_pri_map, 1,
7690 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7691 &adap->params.tp.ingress_config, 1,
7692 TP_INGRESS_CONFIG_A);
7695 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7696 * shift positions of several elements of the Compressed Filter Tuple
7697 * for this adapter which we need frequently ...
7699 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7700 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7701 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7702 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7705 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7706 * represents the presence of an Outer VLAN instead of a VNIC ID.
7708 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7709 adap->params.tp.vnic_shift = -1;
7715 * t4_filter_field_shift - calculate filter field shift
7716 * @adap: the adapter
7717 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7719 * Return the shift position of a filter field within the Compressed
7720 * Filter Tuple. The filter field is specified via its selection bit
7721 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
7723 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7725 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7729 if ((filter_mode & filter_sel) == 0)
7732 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7733 switch (filter_mode & sel) {
7735 field_shift += FT_FCOE_W;
7738 field_shift += FT_PORT_W;
7741 field_shift += FT_VNIC_ID_W;
7744 field_shift += FT_VLAN_W;
7747 field_shift += FT_TOS_W;
7750 field_shift += FT_PROTOCOL_W;
7753 field_shift += FT_ETHERTYPE_W;
7756 field_shift += FT_MACMATCH_W;
7759 field_shift += FT_MPSHITTYPE_W;
7761 case FRAGMENTATION_F:
7762 field_shift += FT_FRAGMENTATION_W;
7769 int t4_init_rss_mode(struct adapter *adap, int mbox)
7772 struct fw_rss_vi_config_cmd rvc;
7774 memset(&rvc, 0, sizeof(rvc));
7776 for_each_port(adap, i) {
7777 struct port_info *p = adap2pinfo(adap, i);
7780 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7781 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7782 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7783 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7784 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7787 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7793 * t4_init_portinfo - allocate a virtual interface amd initialize port_info
7794 * @pi: the port_info
7795 * @mbox: mailbox to use for the FW command
7796 * @port: physical port associated with the VI
7797 * @pf: the PF owning the VI
7798 * @vf: the VF owning the VI
7799 * @mac: the MAC address of the VI
7801 * Allocates a virtual interface for the given physical port. If @mac is
7802 * not %NULL it contains the MAC address of the VI as assigned by FW.
7803 * @mac should be large enough to hold an Ethernet address.
7804 * Returns < 0 on error.
7806 int t4_init_portinfo(struct port_info *pi, int mbox,
7807 int port, int pf, int vf, u8 mac[])
7810 struct fw_port_cmd c;
7811 unsigned int rss_size;
7813 memset(&c, 0, sizeof(c));
7814 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7815 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7816 FW_PORT_CMD_PORTID_V(port));
7817 c.action_to_len16 = cpu_to_be32(
7818 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
7820 ret = t4_wr_mbox(pi->adapter, mbox, &c, sizeof(c), &c);
7824 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
7831 pi->rss_size = rss_size;
7833 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
7834 pi->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
7835 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
7836 pi->port_type = FW_PORT_CMD_PTYPE_G(ret);
7837 pi->mod_type = FW_PORT_MOD_TYPE_NA;
7839 init_link_config(&pi->link_cfg, be16_to_cpu(c.u.info.pcap));
7843 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
7848 for_each_port(adap, i) {
7849 struct port_info *pi = adap2pinfo(adap, i);
7851 while ((adap->params.portvec & (1 << j)) == 0)
7854 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
7858 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
7865 * t4_read_cimq_cfg - read CIM queue configuration
7866 * @adap: the adapter
7867 * @base: holds the queue base addresses in bytes
7868 * @size: holds the queue sizes in bytes
7869 * @thres: holds the queue full thresholds in bytes
7871 * Returns the current configuration of the CIM queues, starting with
7872 * the IBQs, then the OBQs.
7874 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
7877 int cim_num_obq = is_t4(adap->params.chip) ?
7878 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7880 for (i = 0; i < CIM_NUM_IBQ; i++) {
7881 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
7883 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7884 /* value is in 256-byte units */
7885 *base++ = CIMQBASE_G(v) * 256;
7886 *size++ = CIMQSIZE_G(v) * 256;
7887 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
7889 for (i = 0; i < cim_num_obq; i++) {
7890 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7892 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7893 /* value is in 256-byte units */
7894 *base++ = CIMQBASE_G(v) * 256;
7895 *size++ = CIMQSIZE_G(v) * 256;
7900 * t4_read_cim_ibq - read the contents of a CIM inbound queue
7901 * @adap: the adapter
7902 * @qid: the queue index
7903 * @data: where to store the queue contents
7904 * @n: capacity of @data in 32-bit words
7906 * Reads the contents of the selected CIM queue starting at address 0 up
7907 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7908 * error and the number of 32-bit words actually read on success.
7910 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7912 int i, err, attempts;
7914 const unsigned int nwords = CIM_IBQ_SIZE * 4;
7916 if (qid > 5 || (n & 3))
7919 addr = qid * nwords;
7923 /* It might take 3-10ms before the IBQ debug read access is allowed.
7924 * Wait for 1 Sec with a delay of 1 usec.
7928 for (i = 0; i < n; i++, addr++) {
7929 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
7931 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
7935 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
7937 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
7942 * t4_read_cim_obq - read the contents of a CIM outbound queue
7943 * @adap: the adapter
7944 * @qid: the queue index
7945 * @data: where to store the queue contents
7946 * @n: capacity of @data in 32-bit words
7948 * Reads the contents of the selected CIM queue starting at address 0 up
7949 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7950 * error and the number of 32-bit words actually read on success.
7952 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7955 unsigned int addr, v, nwords;
7956 int cim_num_obq = is_t4(adap->params.chip) ?
7957 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7959 if ((qid > (cim_num_obq - 1)) || (n & 3))
7962 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7963 QUENUMSELECT_V(qid));
7964 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7966 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
7967 nwords = CIMQSIZE_G(v) * 64; /* same */
7971 for (i = 0; i < n; i++, addr++) {
7972 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
7974 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
7978 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
7980 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
7985 * t4_cim_read - read a block from CIM internal address space
7986 * @adap: the adapter
7987 * @addr: the start address within the CIM address space
7988 * @n: number of words to read
7989 * @valp: where to store the result
7991 * Reads a block of 4-byte words from the CIM intenal address space.
7993 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
7998 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8001 for ( ; !ret && n--; addr += 4) {
8002 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
8003 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8006 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
8012 * t4_cim_write - write a block into CIM internal address space
8013 * @adap: the adapter
8014 * @addr: the start address within the CIM address space
8015 * @n: number of words to write
8016 * @valp: set of values to write
8018 * Writes a block of 4-byte words into the CIM intenal address space.
8020 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8021 const unsigned int *valp)
8025 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8028 for ( ; !ret && n--; addr += 4) {
8029 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
8030 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
8031 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8037 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8040 return t4_cim_write(adap, addr, 1, &val);
8044 * t4_cim_read_la - read CIM LA capture buffer
8045 * @adap: the adapter
8046 * @la_buf: where to store the LA data
8047 * @wrptr: the HW write pointer within the capture buffer
8049 * Reads the contents of the CIM LA buffer with the most recent entry at
8050 * the end of the returned data and with the entry at @wrptr first.
8051 * We try to leave the LA in the running state we find it in.
8053 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
8056 unsigned int cfg, val, idx;
8058 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
8062 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
8063 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
8068 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8072 idx = UPDBGLAWRPTR_G(val);
8076 for (i = 0; i < adap->params.cim_la_size; i++) {
8077 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8078 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
8081 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8084 if (val & UPDBGLARDEN_F) {
8088 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
8092 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
8093 * identify the 32-bit portion of the full 312-bit data
8095 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
8096 idx = (idx & 0xff0) + 0x10;
8099 /* address can't exceed 0xfff */
8100 idx &= UPDBGLARDPTR_M;
8103 if (cfg & UPDBGLAEN_F) {
8104 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8105 cfg & ~UPDBGLARDEN_F);
8113 * t4_tp_read_la - read TP LA capture buffer
8114 * @adap: the adapter
8115 * @la_buf: where to store the LA data
8116 * @wrptr: the HW write pointer within the capture buffer
8118 * Reads the contents of the TP LA buffer with the most recent entry at
8119 * the end of the returned data and with the entry at @wrptr first.
8120 * We leave the LA in the running state we find it in.
8122 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8124 bool last_incomplete;
8125 unsigned int i, cfg, val, idx;
8127 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
8128 if (cfg & DBGLAENABLE_F) /* freeze LA */
8129 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8130 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
8132 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
8133 idx = DBGLAWPTR_G(val);
8134 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
8135 if (last_incomplete)
8136 idx = (idx + 1) & DBGLARPTR_M;
8141 val &= ~DBGLARPTR_V(DBGLARPTR_M);
8142 val |= adap->params.tp.la_mask;
8144 for (i = 0; i < TPLA_SIZE; i++) {
8145 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
8146 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
8147 idx = (idx + 1) & DBGLARPTR_M;
8150 /* Wipe out last entry if it isn't valid */
8151 if (last_incomplete)
8152 la_buf[TPLA_SIZE - 1] = ~0ULL;
8154 if (cfg & DBGLAENABLE_F) /* restore running state */
8155 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8156 cfg | adap->params.tp.la_mask);
8159 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8160 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
8161 * state for more than the Warning Threshold then we'll issue a warning about
8162 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
8163 * appears to be hung every Warning Repeat second till the situation clears.
8164 * If the situation clears, we'll note that as well.
8166 #define SGE_IDMA_WARN_THRESH 1
8167 #define SGE_IDMA_WARN_REPEAT 300
8170 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8171 * @adapter: the adapter
8172 * @idma: the adapter IDMA Monitor state
8174 * Initialize the state of an SGE Ingress DMA Monitor.
8176 void t4_idma_monitor_init(struct adapter *adapter,
8177 struct sge_idma_monitor_state *idma)
8179 /* Initialize the state variables for detecting an SGE Ingress DMA
8180 * hang. The SGE has internal counters which count up on each clock
8181 * tick whenever the SGE finds its Ingress DMA State Engines in the
8182 * same state they were on the previous clock tick. The clock used is
8183 * the Core Clock so we have a limit on the maximum "time" they can
8184 * record; typically a very small number of seconds. For instance,
8185 * with a 600MHz Core Clock, we can only count up to a bit more than
8186 * 7s. So we'll synthesize a larger counter in order to not run the
8187 * risk of having the "timers" overflow and give us the flexibility to
8188 * maintain a Hung SGE State Machine of our own which operates across
8189 * a longer time frame.
8191 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8192 idma->idma_stalled[0] = 0;
8193 idma->idma_stalled[1] = 0;
8197 * t4_idma_monitor - monitor SGE Ingress DMA state
8198 * @adapter: the adapter
8199 * @idma: the adapter IDMA Monitor state
8200 * @hz: number of ticks/second
8201 * @ticks: number of ticks since the last IDMA Monitor call
8203 void t4_idma_monitor(struct adapter *adapter,
8204 struct sge_idma_monitor_state *idma,
8207 int i, idma_same_state_cnt[2];
8209 /* Read the SGE Debug Ingress DMA Same State Count registers. These
8210 * are counters inside the SGE which count up on each clock when the
8211 * SGE finds its Ingress DMA State Engines in the same states they
8212 * were in the previous clock. The counters will peg out at
8213 * 0xffffffff without wrapping around so once they pass the 1s
8214 * threshold they'll stay above that till the IDMA state changes.
8216 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
8217 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
8218 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8220 for (i = 0; i < 2; i++) {
8221 u32 debug0, debug11;
8223 /* If the Ingress DMA Same State Counter ("timer") is less
8224 * than 1s, then we can reset our synthesized Stall Timer and
8225 * continue. If we have previously emitted warnings about a
8226 * potential stalled Ingress Queue, issue a note indicating
8227 * that the Ingress Queue has resumed forward progress.
8229 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8230 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
8231 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
8232 "resumed after %d seconds\n",
8233 i, idma->idma_qid[i],
8234 idma->idma_stalled[i] / hz);
8235 idma->idma_stalled[i] = 0;
8239 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8240 * domain. The first time we get here it'll be because we
8241 * passed the 1s Threshold; each additional time it'll be
8242 * because the RX Timer Callback is being fired on its regular
8245 * If the stall is below our Potential Hung Ingress Queue
8246 * Warning Threshold, continue.
8248 if (idma->idma_stalled[i] == 0) {
8249 idma->idma_stalled[i] = hz;
8250 idma->idma_warn[i] = 0;
8252 idma->idma_stalled[i] += ticks;
8253 idma->idma_warn[i] -= ticks;
8256 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
8259 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8261 if (idma->idma_warn[i] > 0)
8263 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
8265 /* Read and save the SGE IDMA State and Queue ID information.
8266 * We do this every time in case it changes across time ...
8267 * can't be too careful ...
8269 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
8270 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8271 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8273 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
8274 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8275 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8277 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
8278 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8279 i, idma->idma_qid[i], idma->idma_state[i],
8280 idma->idma_stalled[i] / hz,
8282 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8287 * t4_set_vf_mac - Set MAC address for the specified VF
8288 * @adapter: The adapter
8289 * @vf: one of the VFs instantiated by the specified PF
8290 * @naddr: the number of MAC addresses
8291 * @addr: the MAC address(es) to be set to the specified VF
8293 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
8294 unsigned int naddr, u8 *addr)
8296 struct fw_acl_mac_cmd cmd;
8298 memset(&cmd, 0, sizeof(cmd));
8299 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
8302 FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
8303 FW_ACL_MAC_CMD_VFN_V(vf));
8305 /* Note: Do not enable the ACL */
8306 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
8309 switch (adapter->pf) {
8311 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
8314 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
8317 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
8320 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
8324 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
8327 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
8328 int rateunit, int ratemode, int channel, int class,
8329 int minrate, int maxrate, int weight, int pktsize)
8331 struct fw_sched_cmd cmd;
8333 memset(&cmd, 0, sizeof(cmd));
8334 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
8337 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
8339 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
8340 cmd.u.params.type = type;
8341 cmd.u.params.level = level;
8342 cmd.u.params.mode = mode;
8343 cmd.u.params.ch = channel;
8344 cmd.u.params.cl = class;
8345 cmd.u.params.unit = rateunit;
8346 cmd.u.params.rate = ratemode;
8347 cmd.u.params.min = cpu_to_be32(minrate);
8348 cmd.u.params.max = cpu_to_be32(maxrate);
8349 cmd.u.params.weight = cpu_to_be16(weight);
8350 cmd.u.params.pktsize = cpu_to_be16(pktsize);
8352 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),