drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.
   4  */
   5
   6 #ifndef __CUDBG_ENTITY_H__
   7 #define __CUDBG_ENTITY_H__
   8
   9 #define EDC0_FLAG 0
  10 #define EDC1_FLAG 1
  11 #define MC_FLAG 2
  12 #define MC0_FLAG 3
  13 #define MC1_FLAG 4
  14 #define HMA_FLAG 5
  15
  16 #define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
  17
  18 struct cudbg_mbox_log {
  19         struct mbox_cmd entry;
  20         u32 hi[MBOX_LEN / 8];
  21         u32 lo[MBOX_LEN / 8];
  22 };
  23
  24 struct cudbg_cim_qcfg {
  25         u8 chip;
  26         u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
  27         u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
  28         u16 thres[CIM_NUM_IBQ];
  29         u32 obq_wr[2 * CIM_NUM_OBQ_T5];
  30         u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
  31 };
  32
  33 struct cudbg_rss_vf_conf {
  34         u32 rss_vf_vfl;
  35         u32 rss_vf_vfh;
  36 };
  37
  38 struct cudbg_pm_stats {
  39         u32 tx_cnt[T6_PM_NSTATS];
  40         u32 rx_cnt[T6_PM_NSTATS];
  41         u64 tx_cyc[T6_PM_NSTATS];
  42         u64 rx_cyc[T6_PM_NSTATS];
  43 };
  44
  45 struct cudbg_hw_sched {
  46         u32 kbps[NTX_SCHED];
  47         u32 ipg[NTX_SCHED];
  48         u32 pace_tab[NTX_SCHED];
  49         u32 mode;
  50         u32 map;
  51 };
  52
  53 #define SGE_QBASE_DATA_REG_NUM 4
  54
  55 struct sge_qbase_reg_field {
  56         u32 reg_addr;
  57         u32 reg_data[SGE_QBASE_DATA_REG_NUM];
  58         /* Max supported PFs */
  59         u32 pf_data_value[PCIE_FW_MASTER_M + 1][SGE_QBASE_DATA_REG_NUM];
  60         /* Max supported VFs */
  61         u32 vf_data_value[T6_VF_M + 1][SGE_QBASE_DATA_REG_NUM];
  62         u32 vfcount; /* Actual number of max vfs in current configuration */
  63 };
  64
  65 struct ireg_field {
  66         u32 ireg_addr;
  67         u32 ireg_data;
  68         u32 ireg_local_offset;
  69         u32 ireg_offset_range;
  70 };
  71
  72 struct ireg_buf {
  73         struct ireg_field tp_pio;
  74         u32 outbuf[32];
  75 };
  76
  77 struct cudbg_ulprx_la {
  78         u32 data[ULPRX_LA_SIZE * 8];
  79         u32 size;
  80 };
  81
  82 struct cudbg_tp_la {
  83         u32 size;
  84         u32 mode;
  85         u8 data[0];
  86 };
  87
  88 static const char * const cudbg_region[] = {
  89         "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
  90         "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
  91         "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
  92         "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
  93         "RQUDP region:", "PBL region:", "TXPBL region:",
  94         "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
  95         "On-chip queues:"
  96 };
  97
  98 /* Memory region info relative to current memory (i.e. wrt 0). */
  99 struct cudbg_region_info {
 100         bool exist; /* Does region exists in current memory? */
 101         u32 start;  /* Start wrt 0 */
 102         u32 end;    /* End wrt 0 */
 103 };
 104
 105 struct cudbg_mem_desc {
 106         u32 base;
 107         u32 limit;
 108         u32 idx;
 109 };
 110
 111 #define CUDBG_MEMINFO_REV 1
 112
 113 struct cudbg_meminfo {
 114         struct cudbg_mem_desc avail[4];
 115         struct cudbg_mem_desc mem[ARRAY_SIZE(cudbg_region) + 3];
 116         u32 avail_c;
 117         u32 mem_c;
 118         u32 up_ram_lo;
 119         u32 up_ram_hi;
 120         u32 up_extmem2_lo;
 121         u32 up_extmem2_hi;
 122         u32 rx_pages_data[3];
 123         u32 tx_pages_data[4];
 124         u32 p_structs;
 125         u32 reserved[12];
 126         u32 port_used[4];
 127         u32 port_alloc[4];
 128         u32 loopback_used[NCHAN];
 129         u32 loopback_alloc[NCHAN];
 130         u32 p_structs_free_cnt;
 131         u32 free_rx_cnt;
 132         u32 free_tx_cnt;
 133 };
 134
 135 struct cudbg_cim_pif_la {
 136         int size;
 137         u8 data[0];
 138 };
 139
 140 struct cudbg_clk_info {
 141         u64 retransmit_min;
 142         u64 retransmit_max;
 143         u64 persist_timer_min;
 144         u64 persist_timer_max;
 145         u64 keepalive_idle_timer;
 146         u64 keepalive_interval;
 147         u64 initial_srtt;
 148         u64 finwait2_timer;
 149         u32 dack_timer;
 150         u32 res;
 151         u32 cclk_ps;
 152         u32 tre;
 153         u32 dack_re;
 154 };
 155
 156 struct cudbg_tid_info_region {
 157         u32 ntids;
 158         u32 nstids;
 159         u32 stid_base;
 160         u32 hash_base;
 161
 162         u32 natids;
 163         u32 nftids;
 164         u32 ftid_base;
 165         u32 aftid_base;
 166         u32 aftid_end;
 167
 168         u32 sftid_base;
 169         u32 nsftids;
 170
 171         u32 uotid_base;
 172         u32 nuotids;
 173
 174         u32 sb;
 175         u32 flags;
 176         u32 le_db_conf;
 177         u32 ip_users;
 178         u32 ipv6_users;
 179
 180         u32 hpftid_base;
 181         u32 nhpftids;
 182 };
 183
 184 #define CUDBG_TID_INFO_REV 1
 185
 186 struct cudbg_tid_info_region_rev1 {
 187         struct cudbg_ver_hdr ver_hdr;
 188         struct cudbg_tid_info_region tid;
 189         u32 tid_start;
 190         u32 reserved[16];
 191 };
 192
 193 #define CUDBG_LOWMEM_MAX_CTXT_QIDS 256
 194 #define CUDBG_MAX_FL_QIDS 1024
 195
 196 struct cudbg_ch_cntxt {
 197         u32 cntxt_type;
 198         u32 cntxt_id;
 199         u32 data[SGE_CTXT_SIZE / 4];
 200 };
 201
 202 #define CUDBG_MAX_RPLC_SIZE 128
 203
 204 struct cudbg_mps_tcam {
 205         u64 mask;
 206         u32 rplc[8];
 207         u32 idx;
 208         u32 cls_lo;
 209         u32 cls_hi;
 210         u32 rplc_size;
 211         u32 vniy;
 212         u32 vnix;
 213         u32 dip_hit;
 214         u32 vlan_vld;
 215         u32 repli;
 216         u16 ivlan;
 217         u8 addr[ETH_ALEN];
 218         u8 lookup_type;
 219         u8 port_num;
 220         u8 reserved[2];
 221 };
 222
 223 #define CUDBG_VPD_PF_SIZE 0x800
 224 #define CUDBG_SCFG_VER_ADDR 0x06
 225 #define CUDBG_SCFG_VER_LEN 4
 226 #define CUDBG_VPD_VER_ADDR 0x18c7
 227 #define CUDBG_VPD_VER_LEN 2
 228
 229 struct cudbg_vpd_data {
 230         u8 sn[SERNUM_LEN + 1];
 231         u8 bn[PN_LEN + 1];
 232         u8 na[MACADDR_LEN + 1];
 233         u8 mn[ID_LEN + 1];
 234         u16 fw_major;
 235         u16 fw_minor;
 236         u16 fw_micro;
 237         u16 fw_build;
 238         u32 scfg_vers;
 239         u32 vpd_vers;
 240 };
 241
 242 #define CUDBG_MAX_TCAM_TID 0x800
 243 #define CUDBG_T6_CLIP 1536
 244 #define CUDBG_MAX_TID_COMP_EN 6144
 245 #define CUDBG_MAX_TID_COMP_DIS 3072
 246
 247 enum cudbg_le_entry_types {
 248         LE_ET_UNKNOWN = 0,
 249         LE_ET_TCAM_CON = 1,
 250         LE_ET_TCAM_SERVER = 2,
 251         LE_ET_TCAM_FILTER = 3,
 252         LE_ET_TCAM_CLIP = 4,
 253         LE_ET_TCAM_ROUTING = 5,
 254         LE_ET_HASH_CON = 6,
 255         LE_ET_INVALID_TID = 8,
 256 };
 257
 258 struct cudbg_tcam {
 259         u32 filter_start;
 260         u32 server_start;
 261         u32 clip_start;
 262         u32 routing_start;
 263         u32 tid_hash_base;
 264         u32 max_tid;
 265 };
 266
 267 struct cudbg_tid_data {
 268         u32 tid;
 269         u32 dbig_cmd;
 270         u32 dbig_conf;
 271         u32 dbig_rsp_stat;
 272         u32 data[NUM_LE_DB_DBGI_RSP_DATA_INSTANCES];
 273 };
 274
 275 #define CUDBG_NUM_ULPTX 11
 276 #define CUDBG_NUM_ULPTX_READ 512
 277 #define CUDBG_NUM_ULPTX_ASIC 6
 278 #define CUDBG_NUM_ULPTX_ASIC_READ 128
 279
 280 #define CUDBG_ULPTX_LA_REV 1
 281
 282 struct cudbg_ulptx_la {
 283         u32 rdptr[CUDBG_NUM_ULPTX];
 284         u32 wrptr[CUDBG_NUM_ULPTX];
 285         u32 rddata[CUDBG_NUM_ULPTX];
 286         u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ];
 287         u32 rdptr_asic[CUDBG_NUM_ULPTX_ASIC_READ];
 288         u32 rddata_asic[CUDBG_NUM_ULPTX_ASIC_READ][CUDBG_NUM_ULPTX_ASIC];
 289 };
 290
 291 #define CUDBG_CHAC_PBT_ADDR 0x2800
 292 #define CUDBG_CHAC_PBT_LRF  0x3000
 293 #define CUDBG_CHAC_PBT_DATA 0x3800
 294 #define CUDBG_PBT_DYNAMIC_ENTRIES 8
 295 #define CUDBG_PBT_STATIC_ENTRIES 16
 296 #define CUDBG_LRF_ENTRIES 8
 297 #define CUDBG_PBT_DATA_ENTRIES 512
 298
 299 struct cudbg_pbt_tables {
 300         u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES];
 301         u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES];
 302         u32 lrf_table[CUDBG_LRF_ENTRIES];
 303         u32 pbt_data[CUDBG_PBT_DATA_ENTRIES];
 304 };
 305
 306 enum cudbg_qdesc_qtype {
 307         CUDBG_QTYPE_UNKNOWN = 0,
 308         CUDBG_QTYPE_NIC_TXQ,
 309         CUDBG_QTYPE_NIC_RXQ,
 310         CUDBG_QTYPE_NIC_FLQ,
 311         CUDBG_QTYPE_CTRLQ,
 312         CUDBG_QTYPE_FWEVTQ,
 313         CUDBG_QTYPE_INTRQ,
 314         CUDBG_QTYPE_PTP_TXQ,
 315         CUDBG_QTYPE_OFLD_TXQ,
 316         CUDBG_QTYPE_RDMA_RXQ,
 317         CUDBG_QTYPE_RDMA_FLQ,
 318         CUDBG_QTYPE_RDMA_CIQ,
 319         CUDBG_QTYPE_ISCSI_RXQ,
 320         CUDBG_QTYPE_ISCSI_FLQ,
 321         CUDBG_QTYPE_ISCSIT_RXQ,
 322         CUDBG_QTYPE_ISCSIT_FLQ,
 323         CUDBG_QTYPE_CRYPTO_TXQ,
 324         CUDBG_QTYPE_CRYPTO_RXQ,
 325         CUDBG_QTYPE_CRYPTO_FLQ,
 326         CUDBG_QTYPE_TLS_RXQ,
 327         CUDBG_QTYPE_TLS_FLQ,
 328         CUDBG_QTYPE_MAX,
 329 };
 330
 331 #define CUDBG_QDESC_REV 1
 332
 333 struct cudbg_qdesc_entry {
 334         u32 data_size;
 335         u32 qtype;
 336         u32 qid;
 337         u32 desc_size;
 338         u32 num_desc;
 339         u8 data[0]; /* Must be last */
 340 };
 341
 342 struct cudbg_qdesc_info {
 343         u32 qdesc_entry_size;
 344         u32 num_queues;
 345         u8 data[0]; /* Must be last */
 346 };
 347
 348 #define IREG_NUM_ELEM 4
 349
 350 static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {
 351         {0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
 352         {0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
 353         {0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
 354         {0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
 355         {0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
 356         {0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
 357         {0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
 358         {0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
 359         {0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
 360         {0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
 361         {0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */
 362         {0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */
 363 };
 364
 365 static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = {
 366         {0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */
 367         {0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */
 368         {0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */
 369         {0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */
 370         {0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */
 371         {0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */
 372         {0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */
 373         {0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */
 374         {0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */
 375         {0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */
 376         {0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */
 377 };
 378
 379 static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = {
 380         {0x7e18, 0x7e1c, 0x0, 12}
 381 };
 382
 383 static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = {
 384         {0x7e18, 0x7e1c, 0x0, 12}
 385 };
 386
 387 static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = {
 388         {0x7e50, 0x7e54, 0x0, 13},
 389         {0x7e50, 0x7e54, 0x10, 6},
 390         {0x7e50, 0x7e54, 0x18, 21},
 391         {0x7e50, 0x7e54, 0x30, 32},
 392         {0x7e50, 0x7e54, 0x50, 22},
 393         {0x7e50, 0x7e54, 0x68, 12}
 394 };
 395
 396 static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = {
 397         {0x7e50, 0x7e54, 0x0, 13},
 398         {0x7e50, 0x7e54, 0x10, 6},
 399         {0x7e50, 0x7e54, 0x18, 8},
 400         {0x7e50, 0x7e54, 0x20, 13},
 401         {0x7e50, 0x7e54, 0x30, 16},
 402         {0x7e50, 0x7e54, 0x40, 16},
 403         {0x7e50, 0x7e54, 0x50, 16},
 404         {0x7e50, 0x7e54, 0x60, 6},
 405         {0x7e50, 0x7e54, 0x68, 4}
 406 };
 407
 408 static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {
 409         {0x10cc, 0x10d0, 0x0, 16},
 410         {0x10cc, 0x10d4, 0x0, 16},
 411 };
 412
 413 static const u32 t6_sge_qbase_index_array[] = {
 414         /* 1 addr reg SGE_QBASE_INDEX and 4 data reg SGE_QBASE_MAP[0-3] */
 415         0x1250, 0x1240, 0x1244, 0x1248, 0x124c,
 416 };
 417
 418 static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {
 419         {0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
 420         {0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
 421         {0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */
 422 };
 423
 424 static const u32 t5_pcie_cdbg_array[][IREG_NUM_ELEM] = {
 425         {0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */
 426         {0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */
 427 };
 428
 429 static const u32 t5_pm_rx_array[][IREG_NUM_ELEM] = {
 430         {0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */
 431         {0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */
 432 };
 433
 434 static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = {
 435         {0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */
 436         {0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */
 437 };
 438
 439 #define CUDBG_NUM_PCIE_CONFIG_REGS 0x61
 440
 441 static const u32 t5_pcie_config_array[][2] = {
 442         {0x0, 0x34},
 443         {0x3c, 0x40},
 444         {0x50, 0x64},
 445         {0x70, 0x80},
 446         {0x94, 0xa0},
 447         {0xb0, 0xb8},
 448         {0xd0, 0xd4},
 449         {0x100, 0x128},
 450         {0x140, 0x148},
 451         {0x150, 0x164},
 452         {0x170, 0x178},
 453         {0x180, 0x194},
 454         {0x1a0, 0x1b8},
 455         {0x1c0, 0x208},
 456 };
 457
 458 static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {
 459         {0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */
 460         {0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */
 461         {0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */
 462 };
 463
 464 static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {
 465         {0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */
 466         {0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
 467 };
 468
 469 static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
 470         {0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
 471         {0x7b50, 0x7b54, 0x2080, 0x1d, 0}, /* up_cim_2080_to_20fc */
 472         {0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
 473         {0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
 474         {0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
 475         {0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
 476         {0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
 477         {0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
 478         {0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
 479         {0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
 480         {0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
 481         {0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
 482         {0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
 483         {0x7b50, 0x7b54, 0x4900, 0x4, 0x4}, /* up_cim_4900_to_4c60 */
 484         {0x7b50, 0x7b54, 0x4904, 0x4, 0x4}, /* up_cim_4904_to_4c64 */
 485         {0x7b50, 0x7b54, 0x4908, 0x4, 0x4}, /* up_cim_4908_to_4c68 */
 486         {0x7b50, 0x7b54, 0x4910, 0x4, 0x4}, /* up_cim_4910_to_4c70 */
 487         {0x7b50, 0x7b54, 0x4914, 0x4, 0x4}, /* up_cim_4914_to_4c74 */
 488         {0x7b50, 0x7b54, 0x4920, 0x10, 0x10}, /* up_cim_4920_to_4a10 */
 489         {0x7b50, 0x7b54, 0x4924, 0x10, 0x10}, /* up_cim_4924_to_4a14 */
 490         {0x7b50, 0x7b54, 0x4928, 0x10, 0x10}, /* up_cim_4928_to_4a18 */
 491         {0x7b50, 0x7b54, 0x492c, 0x10, 0x10}, /* up_cim_492c_to_4a1c */
 492 };
 493
 494 static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
 495         {0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
 496         {0x7b50, 0x7b54, 0x2080, 0x19, 0}, /* up_cim_2080_to_20ec */
 497         {0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
 498         {0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
 499         {0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
 500         {0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
 501         {0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
 502         {0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
 503         {0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
 504         {0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
 505         {0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
 506         {0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
 507         {0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
 508 };
 509
 510 static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {
 511         {0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */
 512 };
 513 #endif /* __CUDBG_ENTITY_H__ */