drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2019 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/mdio.h>
  35 #include <linux/if.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/if_bridge.h>
  38 #include <linux/rtc.h>
  39 #include <linux/bpf.h>
  40 #include <net/ip.h>
  41 #include <net/tcp.h>
  42 #include <net/udp.h>
  43 #include <net/checksum.h>
  44 #include <net/ip6_checksum.h>
  45 #include <net/udp_tunnel.h>
  46 #include <linux/workqueue.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/log2.h>
  50 #include <linux/aer.h>
  51 #include <linux/bitmap.h>
  52 #include <linux/cpu_rmap.h>
  53 #include <linux/cpumask.h>
  54 #include <net/pkt_cls.h>
  55 #include <linux/hwmon.h>
  56 #include <linux/hwmon-sysfs.h>
  57 #include <net/page_pool.h>
  58
  59 #include "bnxt_hsi.h"
  60 #include "bnxt.h"
  61 #include "bnxt_ulp.h"
  62 #include "bnxt_sriov.h"
  63 #include "bnxt_ethtool.h"
  64 #include "bnxt_dcb.h"
  65 #include "bnxt_xdp.h"
  66 #include "bnxt_vfr.h"
  67 #include "bnxt_tc.h"
  68 #include "bnxt_devlink.h"
  69 #include "bnxt_debugfs.h"
  70
  71 #define BNXT_TX_TIMEOUT         (5 * HZ)
  72
  73 static const char version[] =
  74         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  75
  76 MODULE_LICENSE("GPL");
  77 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  78 MODULE_VERSION(DRV_MODULE_VERSION);
  79
  80 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  81 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  82 #define BNXT_RX_COPY_THRESH 256
  83
  84 #define BNXT_TX_PUSH_THRESH 164
  85
  86 enum board_idx {
  87         BCM57301,
  88         BCM57302,
  89         BCM57304,
  90         BCM57417_NPAR,
  91         BCM58700,
  92         BCM57311,
  93         BCM57312,
  94         BCM57402,
  95         BCM57404,
  96         BCM57406,
  97         BCM57402_NPAR,
  98         BCM57407,
  99         BCM57412,
 100         BCM57414,
 101         BCM57416,
 102         BCM57417,
 103         BCM57412_NPAR,
 104         BCM57314,
 105         BCM57417_SFP,
 106         BCM57416_SFP,
 107         BCM57404_NPAR,
 108         BCM57406_NPAR,
 109         BCM57407_SFP,
 110         BCM57407_NPAR,
 111         BCM57414_NPAR,
 112         BCM57416_NPAR,
 113         BCM57452,
 114         BCM57454,
 115         BCM5745x_NPAR,
 116         BCM57508,
 117         BCM57504,
 118         BCM57502,
 119         BCM58802,
 120         BCM58804,
 121         BCM58808,
 122         NETXTREME_E_VF,
 123         NETXTREME_C_VF,
 124         NETXTREME_S_VF,
 125         NETXTREME_E_P5_VF,
 126 };
 127
 128 /* indexed by enum above */
 129 static const struct {
 130         char *name;
 131 } board_info[] = {
 132         [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 133         [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 134         [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 135         [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 136         [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 137         [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 138         [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 139         [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 140         [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 141         [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 142         [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 143         [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 144         [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 145         [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 146         [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 147         [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 148         [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 149         [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 150         [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 151         [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 152         [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 153         [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 154         [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 155         [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 156         [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 157         [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 158         [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 159         [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 160         [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
 161         [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 162         [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 163         [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
 164         [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
 165         [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 166         [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 167         [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 168         [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 169         [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
 170         [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
 171 };
 172
 173 static const struct pci_device_id bnxt_pci_tbl[] = {
 174         { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
 175         { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
 176         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 177         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 178         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 179         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 180         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 181         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 182         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 183         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 184         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 185         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 186         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 187         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 188         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 189         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 190         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 191         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 192         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 193         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 194         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 195         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 196         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 197         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 198         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 199         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 200         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 201         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 202         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 203         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 204         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 205         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 206         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 207         { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
 208         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 209         { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
 210         { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
 211         { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
 212         { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
 213         { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
 214 #ifdef CONFIG_BNXT_SRIOV
 215         { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
 216         { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
 217         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 218         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 219         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 220         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 221         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 222         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 223         { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
 224         { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
 225         { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
 226 #endif
 227         { 0 }
 228 };
 229
 230 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 231
 232 static const u16 bnxt_vf_req_snif[] = {
 233         HWRM_FUNC_CFG,
 234         HWRM_FUNC_VF_CFG,
 235         HWRM_PORT_PHY_QCFG,
 236         HWRM_CFA_L2_FILTER_ALLOC,
 237 };
 238
 239 static const u16 bnxt_async_events_arr[] = {
 240         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 241         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 242         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 243         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 244         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 245 };
 246
 247 static struct workqueue_struct *bnxt_pf_wq;
 248
 249 static bool bnxt_vf_pciid(enum board_idx idx)
 250 {
 251         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
 252                 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF);
 253 }
 254
 255 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 256 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 257 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 258
 259 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 260                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 261
 262 #define BNXT_DB_CQ(db, idx)                                             \
 263         writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
 264
 265 #define BNXT_DB_NQ_P5(db, idx)                                          \
 266         writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
 267
 268 #define BNXT_DB_CQ_ARM(db, idx)                                         \
 269         writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
 270
 271 #define BNXT_DB_NQ_ARM_P5(db, idx)                                      \
 272         writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
 273
 274 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 275 {
 276         if (bp->flags & BNXT_FLAG_CHIP_P5)
 277                 BNXT_DB_NQ_P5(db, idx);
 278         else
 279                 BNXT_DB_CQ(db, idx);
 280 }
 281
 282 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 283 {
 284         if (bp->flags & BNXT_FLAG_CHIP_P5)
 285                 BNXT_DB_NQ_ARM_P5(db, idx);
 286         else
 287                 BNXT_DB_CQ_ARM(db, idx);
 288 }
 289
 290 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 291 {
 292         if (bp->flags & BNXT_FLAG_CHIP_P5)
 293                 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
 294                        db->doorbell);
 295         else
 296                 BNXT_DB_CQ(db, idx);
 297 }
 298
 299 const u16 bnxt_lhint_arr[] = {
 300         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 301         TX_BD_FLAGS_LHINT_512_TO_1023,
 302         TX_BD_FLAGS_LHINT_1024_TO_2047,
 303         TX_BD_FLAGS_LHINT_1024_TO_2047,
 304         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 305         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 306         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 307         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 308         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 309         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 310         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 311         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 312         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 313         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 314         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 315         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 316         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 317         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 318         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 319 };
 320
 321 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
 322 {
 323         struct metadata_dst *md_dst = skb_metadata_dst(skb);
 324
 325         if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
 326                 return 0;
 327
 328         return md_dst->u.port_info.port_id;
 329 }
 330
 331 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 332 {
 333         struct bnxt *bp = netdev_priv(dev);
 334         struct tx_bd *txbd;
 335         struct tx_bd_ext *txbd1;
 336         struct netdev_queue *txq;
 337         int i;
 338         dma_addr_t mapping;
 339         unsigned int length, pad = 0;
 340         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 341         u16 prod, last_frag;
 342         struct pci_dev *pdev = bp->pdev;
 343         struct bnxt_tx_ring_info *txr;
 344         struct bnxt_sw_tx_bd *tx_buf;
 345
 346         i = skb_get_queue_mapping(skb);
 347         if (unlikely(i >= bp->tx_nr_rings)) {
 348                 dev_kfree_skb_any(skb);
 349                 return NETDEV_TX_OK;
 350         }
 351
 352         txq = netdev_get_tx_queue(dev, i);
 353         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 354         prod = txr->tx_prod;
 355
 356         free_size = bnxt_tx_avail(bp, txr);
 357         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 358                 netif_tx_stop_queue(txq);
 359                 return NETDEV_TX_BUSY;
 360         }
 361
 362         length = skb->len;
 363         len = skb_headlen(skb);
 364         last_frag = skb_shinfo(skb)->nr_frags;
 365
 366         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 367
 368         txbd->tx_bd_opaque = prod;
 369
 370         tx_buf = &txr->tx_buf_ring[prod];
 371         tx_buf->skb = skb;
 372         tx_buf->nr_frags = last_frag;
 373
 374         vlan_tag_flags = 0;
 375         cfa_action = bnxt_xmit_get_cfa_action(skb);
 376         if (skb_vlan_tag_present(skb)) {
 377                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 378                                  skb_vlan_tag_get(skb);
 379                 /* Currently supports 8021Q, 8021AD vlan offloads
 380                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 381                  */
 382                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 383                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 384         }
 385
 386         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 387                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 388                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 389                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 390                 void __iomem *db = txr->tx_db.doorbell;
 391                 void *pdata = tx_push_buf->data;
 392                 u64 *end;
 393                 int j, push_len;
 394
 395                 /* Set COAL_NOW to be ready quickly for the next push */
 396                 tx_push->tx_bd_len_flags_type =
 397                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 398                                         TX_BD_TYPE_LONG_TX_BD |
 399                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 400                                         TX_BD_FLAGS_COAL_NOW |
 401                                         TX_BD_FLAGS_PACKET_END |
 402                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 403
 404                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 405                         tx_push1->tx_bd_hsize_lflags =
 406                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 407                 else
 408                         tx_push1->tx_bd_hsize_lflags = 0;
 409
 410                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 411                 tx_push1->tx_bd_cfa_action =
 412                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 413
 414                 end = pdata + length;
 415                 end = PTR_ALIGN(end, 8) - 1;
 416                 *end = 0;
 417
 418                 skb_copy_from_linear_data(skb, pdata, len);
 419                 pdata += len;
 420                 for (j = 0; j < last_frag; j++) {
 421                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 422                         void *fptr;
 423
 424                         fptr = skb_frag_address_safe(frag);
 425                         if (!fptr)
 426                                 goto normal_tx;
 427
 428                         memcpy(pdata, fptr, skb_frag_size(frag));
 429                         pdata += skb_frag_size(frag);
 430                 }
 431
 432                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 433                 txbd->tx_bd_haddr = txr->data_mapping;
 434                 prod = NEXT_TX(prod);
 435                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 436                 memcpy(txbd, tx_push1, sizeof(*txbd));
 437                 prod = NEXT_TX(prod);
 438                 tx_push->doorbell =
 439                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 440                 txr->tx_prod = prod;
 441
 442                 tx_buf->is_push = 1;
 443                 netdev_tx_sent_queue(txq, skb->len);
 444                 wmb();  /* Sync is_push and byte queue before pushing data */
 445
 446                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 447                 if (push_len > 16) {
 448                         __iowrite64_copy(db, tx_push_buf, 16);
 449                         __iowrite32_copy(db + 4, tx_push_buf + 1,
 450                                          (push_len - 16) << 1);
 451                 } else {
 452                         __iowrite64_copy(db, tx_push_buf, push_len);
 453                 }
 454
 455                 goto tx_done;
 456         }
 457
 458 normal_tx:
 459         if (length < BNXT_MIN_PKT_SIZE) {
 460                 pad = BNXT_MIN_PKT_SIZE - length;
 461                 if (skb_pad(skb, pad)) {
 462                         /* SKB already freed. */
 463                         tx_buf->skb = NULL;
 464                         return NETDEV_TX_OK;
 465                 }
 466                 length = BNXT_MIN_PKT_SIZE;
 467         }
 468
 469         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 470
 471         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 472                 dev_kfree_skb_any(skb);
 473                 tx_buf->skb = NULL;
 474                 return NETDEV_TX_OK;
 475         }
 476
 477         dma_unmap_addr_set(tx_buf, mapping, mapping);
 478         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 479                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 480
 481         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 482
 483         prod = NEXT_TX(prod);
 484         txbd1 = (struct tx_bd_ext *)
 485                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 486
 487         txbd1->tx_bd_hsize_lflags = 0;
 488         if (skb_is_gso(skb)) {
 489                 u32 hdr_len;
 490
 491                 if (skb->encapsulation)
 492                         hdr_len = skb_inner_network_offset(skb) +
 493                                 skb_inner_network_header_len(skb) +
 494                                 inner_tcp_hdrlen(skb);
 495                 else
 496                         hdr_len = skb_transport_offset(skb) +
 497                                 tcp_hdrlen(skb);
 498
 499                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 500                                         TX_BD_FLAGS_T_IPID |
 501                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 502                 length = skb_shinfo(skb)->gso_size;
 503                 txbd1->tx_bd_mss = cpu_to_le32(length);
 504                 length += hdr_len;
 505         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 506                 txbd1->tx_bd_hsize_lflags =
 507                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 508                 txbd1->tx_bd_mss = 0;
 509         }
 510
 511         length >>= 9;
 512         if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
 513                 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
 514                                      skb->len);
 515                 i = 0;
 516                 goto tx_dma_error;
 517         }
 518         flags |= bnxt_lhint_arr[length];
 519         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 520
 521         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 522         txbd1->tx_bd_cfa_action =
 523                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 524         for (i = 0; i < last_frag; i++) {
 525                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 526
 527                 prod = NEXT_TX(prod);
 528                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 529
 530                 len = skb_frag_size(frag);
 531                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 532                                            DMA_TO_DEVICE);
 533
 534                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 535                         goto tx_dma_error;
 536
 537                 tx_buf = &txr->tx_buf_ring[prod];
 538                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 539
 540                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 541
 542                 flags = len << TX_BD_LEN_SHIFT;
 543                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 544         }
 545
 546         flags &= ~TX_BD_LEN;
 547         txbd->tx_bd_len_flags_type =
 548                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 549                             TX_BD_FLAGS_PACKET_END);
 550
 551         netdev_tx_sent_queue(txq, skb->len);
 552
 553         /* Sync BD data before updating doorbell */
 554         wmb();
 555
 556         prod = NEXT_TX(prod);
 557         txr->tx_prod = prod;
 558
 559         if (!netdev_xmit_more() || netif_xmit_stopped(txq))
 560                 bnxt_db_write(bp, &txr->tx_db, prod);
 561
 562 tx_done:
 563
 564         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 565                 if (netdev_xmit_more() && !tx_buf->is_push)
 566                         bnxt_db_write(bp, &txr->tx_db, prod);
 567
 568                 netif_tx_stop_queue(txq);
 569
 570                 /* netif_tx_stop_queue() must be done before checking
 571                  * tx index in bnxt_tx_avail() below, because in
 572                  * bnxt_tx_int(), we update tx index before checking for
 573                  * netif_tx_queue_stopped().
 574                  */
 575                 smp_mb();
 576                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 577                         netif_tx_wake_queue(txq);
 578         }
 579         return NETDEV_TX_OK;
 580
 581 tx_dma_error:
 582         last_frag = i;
 583
 584         /* start back at beginning and unmap skb */
 585         prod = txr->tx_prod;
 586         tx_buf = &txr->tx_buf_ring[prod];
 587         tx_buf->skb = NULL;
 588         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 589                          skb_headlen(skb), PCI_DMA_TODEVICE);
 590         prod = NEXT_TX(prod);
 591
 592         /* unmap remaining mapped pages */
 593         for (i = 0; i < last_frag; i++) {
 594                 prod = NEXT_TX(prod);
 595                 tx_buf = &txr->tx_buf_ring[prod];
 596                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 597                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 598                                PCI_DMA_TODEVICE);
 599         }
 600
 601         dev_kfree_skb_any(skb);
 602         return NETDEV_TX_OK;
 603 }
 604
 605 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 606 {
 607         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 608         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 609         u16 cons = txr->tx_cons;
 610         struct pci_dev *pdev = bp->pdev;
 611         int i;
 612         unsigned int tx_bytes = 0;
 613
 614         for (i = 0; i < nr_pkts; i++) {
 615                 struct bnxt_sw_tx_bd *tx_buf;
 616                 struct sk_buff *skb;
 617                 int j, last;
 618
 619                 tx_buf = &txr->tx_buf_ring[cons];
 620                 cons = NEXT_TX(cons);
 621                 skb = tx_buf->skb;
 622                 tx_buf->skb = NULL;
 623
 624                 if (tx_buf->is_push) {
 625                         tx_buf->is_push = 0;
 626                         goto next_tx_int;
 627                 }
 628
 629                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 630                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 631                 last = tx_buf->nr_frags;
 632
 633                 for (j = 0; j < last; j++) {
 634                         cons = NEXT_TX(cons);
 635                         tx_buf = &txr->tx_buf_ring[cons];
 636                         dma_unmap_page(
 637                                 &pdev->dev,
 638                                 dma_unmap_addr(tx_buf, mapping),
 639                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 640                                 PCI_DMA_TODEVICE);
 641                 }
 642
 643 next_tx_int:
 644                 cons = NEXT_TX(cons);
 645
 646                 tx_bytes += skb->len;
 647                 dev_kfree_skb_any(skb);
 648         }
 649
 650         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 651         txr->tx_cons = cons;
 652
 653         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 654          * before checking for netif_tx_queue_stopped().  Without the
 655          * memory barrier, there is a small possibility that bnxt_start_xmit()
 656          * will miss it and cause the queue to be stopped forever.
 657          */
 658         smp_mb();
 659
 660         if (unlikely(netif_tx_queue_stopped(txq)) &&
 661             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 662                 __netif_tx_lock(txq, smp_processor_id());
 663                 if (netif_tx_queue_stopped(txq) &&
 664                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 665                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 666                         netif_tx_wake_queue(txq);
 667                 __netif_tx_unlock(txq);
 668         }
 669 }
 670
 671 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 672                                          struct bnxt_rx_ring_info *rxr,
 673                                          gfp_t gfp)
 674 {
 675         struct device *dev = &bp->pdev->dev;
 676         struct page *page;
 677
 678         page = page_pool_dev_alloc_pages(rxr->page_pool);
 679         if (!page)
 680                 return NULL;
 681
 682         *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
 683                                       DMA_ATTR_WEAK_ORDERING);
 684         if (dma_mapping_error(dev, *mapping)) {
 685                 page_pool_recycle_direct(rxr->page_pool, page);
 686                 return NULL;
 687         }
 688         *mapping += bp->rx_dma_offset;
 689         return page;
 690 }
 691
 692 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 693                                        gfp_t gfp)
 694 {
 695         u8 *data;
 696         struct pci_dev *pdev = bp->pdev;
 697
 698         data = kmalloc(bp->rx_buf_size, gfp);
 699         if (!data)
 700                 return NULL;
 701
 702         *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
 703                                         bp->rx_buf_use_size, bp->rx_dir,
 704                                         DMA_ATTR_WEAK_ORDERING);
 705
 706         if (dma_mapping_error(&pdev->dev, *mapping)) {
 707                 kfree(data);
 708                 data = NULL;
 709         }
 710         return data;
 711 }
 712
 713 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 714                        u16 prod, gfp_t gfp)
 715 {
 716         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 717         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 718         dma_addr_t mapping;
 719
 720         if (BNXT_RX_PAGE_MODE(bp)) {
 721                 struct page *page =
 722                         __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp);
 723
 724                 if (!page)
 725                         return -ENOMEM;
 726
 727                 rx_buf->data = page;
 728                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 729         } else {
 730                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 731
 732                 if (!data)
 733                         return -ENOMEM;
 734
 735                 rx_buf->data = data;
 736                 rx_buf->data_ptr = data + bp->rx_offset;
 737         }
 738         rx_buf->mapping = mapping;
 739
 740         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 741         return 0;
 742 }
 743
 744 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 745 {
 746         u16 prod = rxr->rx_prod;
 747         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 748         struct rx_bd *cons_bd, *prod_bd;
 749
 750         prod_rx_buf = &rxr->rx_buf_ring[prod];
 751         cons_rx_buf = &rxr->rx_buf_ring[cons];
 752
 753         prod_rx_buf->data = data;
 754         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 755
 756         prod_rx_buf->mapping = cons_rx_buf->mapping;
 757
 758         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 759         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 760
 761         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 762 }
 763
 764 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 765 {
 766         u16 next, max = rxr->rx_agg_bmap_size;
 767
 768         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 769         if (next >= max)
 770                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 771         return next;
 772 }
 773
 774 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 775                                      struct bnxt_rx_ring_info *rxr,
 776                                      u16 prod, gfp_t gfp)
 777 {
 778         struct rx_bd *rxbd =
 779                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 780         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 781         struct pci_dev *pdev = bp->pdev;
 782         struct page *page;
 783         dma_addr_t mapping;
 784         u16 sw_prod = rxr->rx_sw_agg_prod;
 785         unsigned int offset = 0;
 786
 787         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 788                 page = rxr->rx_page;
 789                 if (!page) {
 790                         page = alloc_page(gfp);
 791                         if (!page)
 792                                 return -ENOMEM;
 793                         rxr->rx_page = page;
 794                         rxr->rx_page_offset = 0;
 795                 }
 796                 offset = rxr->rx_page_offset;
 797                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 798                 if (rxr->rx_page_offset == PAGE_SIZE)
 799                         rxr->rx_page = NULL;
 800                 else
 801                         get_page(page);
 802         } else {
 803                 page = alloc_page(gfp);
 804                 if (!page)
 805                         return -ENOMEM;
 806         }
 807
 808         mapping = dma_map_page_attrs(&pdev->dev, page, offset,
 809                                      BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
 810                                      DMA_ATTR_WEAK_ORDERING);
 811         if (dma_mapping_error(&pdev->dev, mapping)) {
 812                 __free_page(page);
 813                 return -EIO;
 814         }
 815
 816         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 817                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 818
 819         __set_bit(sw_prod, rxr->rx_agg_bmap);
 820         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 821         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 822
 823         rx_agg_buf->page = page;
 824         rx_agg_buf->offset = offset;
 825         rx_agg_buf->mapping = mapping;
 826         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 827         rxbd->rx_bd_opaque = sw_prod;
 828         return 0;
 829 }
 830
 831 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
 832                                    u32 agg_bufs)
 833 {
 834         struct bnxt_napi *bnapi = cpr->bnapi;
 835         struct bnxt *bp = bnapi->bp;
 836         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 837         u16 prod = rxr->rx_agg_prod;
 838         u16 sw_prod = rxr->rx_sw_agg_prod;
 839         u32 i;
 840
 841         for (i = 0; i < agg_bufs; i++) {
 842                 u16 cons;
 843                 struct rx_agg_cmp *agg;
 844                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 845                 struct rx_bd *prod_bd;
 846                 struct page *page;
 847
 848                 agg = (struct rx_agg_cmp *)
 849                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 850                 cons = agg->rx_agg_cmp_opaque;
 851                 __clear_bit(cons, rxr->rx_agg_bmap);
 852
 853                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 854                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 855
 856                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 857                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 858                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 859
 860                 /* It is possible for sw_prod to be equal to cons, so
 861                  * set cons_rx_buf->page to NULL first.
 862                  */
 863                 page = cons_rx_buf->page;
 864                 cons_rx_buf->page = NULL;
 865                 prod_rx_buf->page = page;
 866                 prod_rx_buf->offset = cons_rx_buf->offset;
 867
 868                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 869
 870                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 871
 872                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 873                 prod_bd->rx_bd_opaque = sw_prod;
 874
 875                 prod = NEXT_RX_AGG(prod);
 876                 sw_prod = NEXT_RX_AGG(sw_prod);
 877                 cp_cons = NEXT_CMP(cp_cons);
 878         }
 879         rxr->rx_agg_prod = prod;
 880         rxr->rx_sw_agg_prod = sw_prod;
 881 }
 882
 883 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 884                                         struct bnxt_rx_ring_info *rxr,
 885                                         u16 cons, void *data, u8 *data_ptr,
 886                                         dma_addr_t dma_addr,
 887                                         unsigned int offset_and_len)
 888 {
 889         unsigned int payload = offset_and_len >> 16;
 890         unsigned int len = offset_and_len & 0xffff;
 891         struct skb_frag_struct *frag;
 892         struct page *page = data;
 893         u16 prod = rxr->rx_prod;
 894         struct sk_buff *skb;
 895         int off, err;
 896
 897         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 898         if (unlikely(err)) {
 899                 bnxt_reuse_rx_data(rxr, cons, data);
 900                 return NULL;
 901         }
 902         dma_addr -= bp->rx_dma_offset;
 903         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
 904                              DMA_ATTR_WEAK_ORDERING);
 905
 906         if (unlikely(!payload))
 907                 payload = eth_get_headlen(bp->dev, data_ptr, len);
 908
 909         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 910         if (!skb) {
 911                 __free_page(page);
 912                 return NULL;
 913         }
 914
 915         off = (void *)data_ptr - page_address(page);
 916         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 917         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 918                payload + NET_IP_ALIGN);
 919
 920         frag = &skb_shinfo(skb)->frags[0];
 921         skb_frag_size_sub(frag, payload);
 922         frag->page_offset += payload;
 923         skb->data_len -= payload;
 924         skb->tail += payload;
 925
 926         return skb;
 927 }
 928
 929 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 930                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 931                                    void *data, u8 *data_ptr,
 932                                    dma_addr_t dma_addr,
 933                                    unsigned int offset_and_len)
 934 {
 935         u16 prod = rxr->rx_prod;
 936         struct sk_buff *skb;
 937         int err;
 938
 939         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 940         if (unlikely(err)) {
 941                 bnxt_reuse_rx_data(rxr, cons, data);
 942                 return NULL;
 943         }
 944
 945         skb = build_skb(data, 0);
 946         dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 947                                bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
 948         if (!skb) {
 949                 kfree(data);
 950                 return NULL;
 951         }
 952
 953         skb_reserve(skb, bp->rx_offset);
 954         skb_put(skb, offset_and_len & 0xffff);
 955         return skb;
 956 }
 957
 958 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
 959                                      struct bnxt_cp_ring_info *cpr,
 960                                      struct sk_buff *skb, u16 cp_cons,
 961                                      u32 agg_bufs)
 962 {
 963         struct bnxt_napi *bnapi = cpr->bnapi;
 964         struct pci_dev *pdev = bp->pdev;
 965         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 966         u16 prod = rxr->rx_agg_prod;
 967         u32 i;
 968
 969         for (i = 0; i < agg_bufs; i++) {
 970                 u16 cons, frag_len;
 971                 struct rx_agg_cmp *agg;
 972                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 973                 struct page *page;
 974                 dma_addr_t mapping;
 975
 976                 agg = (struct rx_agg_cmp *)
 977                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 978                 cons = agg->rx_agg_cmp_opaque;
 979                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 980                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 981
 982                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 983                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 984                                    cons_rx_buf->offset, frag_len);
 985                 __clear_bit(cons, rxr->rx_agg_bmap);
 986
 987                 /* It is possible for bnxt_alloc_rx_page() to allocate
 988                  * a sw_prod index that equals the cons index, so we
 989                  * need to clear the cons entry now.
 990                  */
 991                 mapping = cons_rx_buf->mapping;
 992                 page = cons_rx_buf->page;
 993                 cons_rx_buf->page = NULL;
 994
 995                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 996                         struct skb_shared_info *shinfo;
 997                         unsigned int nr_frags;
 998
 999                         shinfo = skb_shinfo(skb);
1000                         nr_frags = --shinfo->nr_frags;
1001                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
1002
1003                         dev_kfree_skb(skb);
1004
1005                         cons_rx_buf->page = page;
1006
1007                         /* Update prod since possibly some pages have been
1008                          * allocated already.
1009                          */
1010                         rxr->rx_agg_prod = prod;
1011                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs - i);
1012                         return NULL;
1013                 }
1014
1015                 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1016                                      PCI_DMA_FROMDEVICE,
1017                                      DMA_ATTR_WEAK_ORDERING);
1018
1019                 skb->data_len += frag_len;
1020                 skb->len += frag_len;
1021                 skb->truesize += PAGE_SIZE;
1022
1023                 prod = NEXT_RX_AGG(prod);
1024                 cp_cons = NEXT_CMP(cp_cons);
1025         }
1026         rxr->rx_agg_prod = prod;
1027         return skb;
1028 }
1029
1030 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1031                                u8 agg_bufs, u32 *raw_cons)
1032 {
1033         u16 last;
1034         struct rx_agg_cmp *agg;
1035
1036         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1037         last = RING_CMP(*raw_cons);
1038         agg = (struct rx_agg_cmp *)
1039                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1040         return RX_AGG_CMP_VALID(agg, *raw_cons);
1041 }
1042
1043 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1044                                             unsigned int len,
1045                                             dma_addr_t mapping)
1046 {
1047         struct bnxt *bp = bnapi->bp;
1048         struct pci_dev *pdev = bp->pdev;
1049         struct sk_buff *skb;
1050
1051         skb = napi_alloc_skb(&bnapi->napi, len);
1052         if (!skb)
1053                 return NULL;
1054
1055         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1056                                 bp->rx_dir);
1057
1058         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1059                len + NET_IP_ALIGN);
1060
1061         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1062                                    bp->rx_dir);
1063
1064         skb_put(skb, len);
1065         return skb;
1066 }
1067
1068 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1069                            u32 *raw_cons, void *cmp)
1070 {
1071         struct rx_cmp *rxcmp = cmp;
1072         u32 tmp_raw_cons = *raw_cons;
1073         u8 cmp_type, agg_bufs = 0;
1074
1075         cmp_type = RX_CMP_TYPE(rxcmp);
1076
1077         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1078                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1079                             RX_CMP_AGG_BUFS) >>
1080                            RX_CMP_AGG_BUFS_SHIFT;
1081         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1082                 struct rx_tpa_end_cmp *tpa_end = cmp;
1083
1084                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1085                             RX_TPA_END_CMP_AGG_BUFS) >>
1086                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1087         }
1088
1089         if (agg_bufs) {
1090                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1091                         return -EBUSY;
1092         }
1093         *raw_cons = tmp_raw_cons;
1094         return 0;
1095 }
1096
1097 static void bnxt_queue_sp_work(struct bnxt *bp)
1098 {
1099         if (BNXT_PF(bp))
1100                 queue_work(bnxt_pf_wq, &bp->sp_task);
1101         else
1102                 schedule_work(&bp->sp_task);
1103 }
1104
1105 static void bnxt_cancel_sp_work(struct bnxt *bp)
1106 {
1107         if (BNXT_PF(bp))
1108                 flush_workqueue(bnxt_pf_wq);
1109         else
1110                 cancel_work_sync(&bp->sp_task);
1111 }
1112
1113 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1114 {
1115         if (!rxr->bnapi->in_reset) {
1116                 rxr->bnapi->in_reset = true;
1117                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1118                 bnxt_queue_sp_work(bp);
1119         }
1120         rxr->rx_next_cons = 0xffff;
1121 }
1122
1123 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1124                            struct rx_tpa_start_cmp *tpa_start,
1125                            struct rx_tpa_start_cmp_ext *tpa_start1)
1126 {
1127         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1128         u16 cons, prod;
1129         struct bnxt_tpa_info *tpa_info;
1130         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1131         struct rx_bd *prod_bd;
1132         dma_addr_t mapping;
1133
1134         cons = tpa_start->rx_tpa_start_cmp_opaque;
1135         prod = rxr->rx_prod;
1136         cons_rx_buf = &rxr->rx_buf_ring[cons];
1137         prod_rx_buf = &rxr->rx_buf_ring[prod];
1138         tpa_info = &rxr->rx_tpa[agg_id];
1139
1140         if (unlikely(cons != rxr->rx_next_cons)) {
1141                 netdev_warn(bp->dev, "TPA cons %x != expected cons %x\n",
1142                             cons, rxr->rx_next_cons);
1143                 bnxt_sched_reset(bp, rxr);
1144                 return;
1145         }
1146         /* Store cfa_code in tpa_info to use in tpa_end
1147          * completion processing.
1148          */
1149         tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1150         prod_rx_buf->data = tpa_info->data;
1151         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1152
1153         mapping = tpa_info->mapping;
1154         prod_rx_buf->mapping = mapping;
1155
1156         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1157
1158         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1159
1160         tpa_info->data = cons_rx_buf->data;
1161         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1162         cons_rx_buf->data = NULL;
1163         tpa_info->mapping = cons_rx_buf->mapping;
1164
1165         tpa_info->len =
1166                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1167                                 RX_TPA_START_CMP_LEN_SHIFT;
1168         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1169                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1170
1171                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1172                 tpa_info->gso_type = SKB_GSO_TCPV4;
1173                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1174                 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1175                         tpa_info->gso_type = SKB_GSO_TCPV6;
1176                 tpa_info->rss_hash =
1177                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1178         } else {
1179                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1180                 tpa_info->gso_type = 0;
1181                 if (netif_msg_rx_err(bp))
1182                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1183         }
1184         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1185         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1186         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1187
1188         rxr->rx_prod = NEXT_RX(prod);
1189         cons = NEXT_RX(cons);
1190         rxr->rx_next_cons = NEXT_RX(cons);
1191         cons_rx_buf = &rxr->rx_buf_ring[cons];
1192
1193         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1194         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1195         cons_rx_buf->data = NULL;
1196 }
1197
1198 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
1199                            u32 agg_bufs)
1200 {
1201         if (agg_bufs)
1202                 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1203 }
1204
1205 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1206                                            int payload_off, int tcp_ts,
1207                                            struct sk_buff *skb)
1208 {
1209 #ifdef CONFIG_INET
1210         struct tcphdr *th;
1211         int len, nw_off;
1212         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1213         u32 hdr_info = tpa_info->hdr_info;
1214         bool loopback = false;
1215
1216         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1217         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1218         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1219
1220         /* If the packet is an internal loopback packet, the offsets will
1221          * have an extra 4 bytes.
1222          */
1223         if (inner_mac_off == 4) {
1224                 loopback = true;
1225         } else if (inner_mac_off > 4) {
1226                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1227                                             ETH_HLEN - 2));
1228
1229                 /* We only support inner iPv4/ipv6.  If we don't see the
1230                  * correct protocol ID, it must be a loopback packet where
1231                  * the offsets are off by 4.
1232                  */
1233                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1234                         loopback = true;
1235         }
1236         if (loopback) {
1237                 /* internal loopback packet, subtract all offsets by 4 */
1238                 inner_ip_off -= 4;
1239                 inner_mac_off -= 4;
1240                 outer_ip_off -= 4;
1241         }
1242
1243         nw_off = inner_ip_off - ETH_HLEN;
1244         skb_set_network_header(skb, nw_off);
1245         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1246                 struct ipv6hdr *iph = ipv6_hdr(skb);
1247
1248                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1249                 len = skb->len - skb_transport_offset(skb);
1250                 th = tcp_hdr(skb);
1251                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1252         } else {
1253                 struct iphdr *iph = ip_hdr(skb);
1254
1255                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1256                 len = skb->len - skb_transport_offset(skb);
1257                 th = tcp_hdr(skb);
1258                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1259         }
1260
1261         if (inner_mac_off) { /* tunnel */
1262                 struct udphdr *uh = NULL;
1263                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1264                                             ETH_HLEN - 2));
1265
1266                 if (proto == htons(ETH_P_IP)) {
1267                         struct iphdr *iph = (struct iphdr *)skb->data;
1268
1269                         if (iph->protocol == IPPROTO_UDP)
1270                                 uh = (struct udphdr *)(iph + 1);
1271                 } else {
1272                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1273
1274                         if (iph->nexthdr == IPPROTO_UDP)
1275                                 uh = (struct udphdr *)(iph + 1);
1276                 }
1277                 if (uh) {
1278                         if (uh->check)
1279                                 skb_shinfo(skb)->gso_type |=
1280                                         SKB_GSO_UDP_TUNNEL_CSUM;
1281                         else
1282                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1283                 }
1284         }
1285 #endif
1286         return skb;
1287 }
1288
1289 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1290 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1291
1292 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1293                                            int payload_off, int tcp_ts,
1294                                            struct sk_buff *skb)
1295 {
1296 #ifdef CONFIG_INET
1297         struct tcphdr *th;
1298         int len, nw_off, tcp_opt_len = 0;
1299
1300         if (tcp_ts)
1301                 tcp_opt_len = 12;
1302
1303         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1304                 struct iphdr *iph;
1305
1306                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1307                          ETH_HLEN;
1308                 skb_set_network_header(skb, nw_off);
1309                 iph = ip_hdr(skb);
1310                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1311                 len = skb->len - skb_transport_offset(skb);
1312                 th = tcp_hdr(skb);
1313                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1314         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1315                 struct ipv6hdr *iph;
1316
1317                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1318                          ETH_HLEN;
1319                 skb_set_network_header(skb, nw_off);
1320                 iph = ipv6_hdr(skb);
1321                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1322                 len = skb->len - skb_transport_offset(skb);
1323                 th = tcp_hdr(skb);
1324                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1325         } else {
1326                 dev_kfree_skb_any(skb);
1327                 return NULL;
1328         }
1329
1330         if (nw_off) { /* tunnel */
1331                 struct udphdr *uh = NULL;
1332
1333                 if (skb->protocol == htons(ETH_P_IP)) {
1334                         struct iphdr *iph = (struct iphdr *)skb->data;
1335
1336                         if (iph->protocol == IPPROTO_UDP)
1337                                 uh = (struct udphdr *)(iph + 1);
1338                 } else {
1339                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1340
1341                         if (iph->nexthdr == IPPROTO_UDP)
1342                                 uh = (struct udphdr *)(iph + 1);
1343                 }
1344                 if (uh) {
1345                         if (uh->check)
1346                                 skb_shinfo(skb)->gso_type |=
1347                                         SKB_GSO_UDP_TUNNEL_CSUM;
1348                         else
1349                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1350                 }
1351         }
1352 #endif
1353         return skb;
1354 }
1355
1356 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1357                                            struct bnxt_tpa_info *tpa_info,
1358                                            struct rx_tpa_end_cmp *tpa_end,
1359                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1360                                            struct sk_buff *skb)
1361 {
1362 #ifdef CONFIG_INET
1363         int payload_off;
1364         u16 segs;
1365
1366         segs = TPA_END_TPA_SEGS(tpa_end);
1367         if (segs == 1)
1368                 return skb;
1369
1370         NAPI_GRO_CB(skb)->count = segs;
1371         skb_shinfo(skb)->gso_size =
1372                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1373         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1374         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1375                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1376                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1377         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1378         if (likely(skb))
1379                 tcp_gro_complete(skb);
1380 #endif
1381         return skb;
1382 }
1383
1384 /* Given the cfa_code of a received packet determine which
1385  * netdev (vf-rep or PF) the packet is destined to.
1386  */
1387 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1388 {
1389         struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1390
1391         /* if vf-rep dev is NULL, the must belongs to the PF */
1392         return dev ? dev : bp->dev;
1393 }
1394
1395 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1396                                            struct bnxt_cp_ring_info *cpr,
1397                                            u32 *raw_cons,
1398                                            struct rx_tpa_end_cmp *tpa_end,
1399                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1400                                            u8 *event)
1401 {
1402         struct bnxt_napi *bnapi = cpr->bnapi;
1403         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1404         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1405         u8 *data_ptr, agg_bufs;
1406         u16 cp_cons = RING_CMP(*raw_cons);
1407         unsigned int len;
1408         struct bnxt_tpa_info *tpa_info;
1409         dma_addr_t mapping;
1410         struct sk_buff *skb;
1411         void *data;
1412
1413         if (unlikely(bnapi->in_reset)) {
1414                 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1415
1416                 if (rc < 0)
1417                         return ERR_PTR(-EBUSY);
1418                 return NULL;
1419         }
1420
1421         tpa_info = &rxr->rx_tpa[agg_id];
1422         data = tpa_info->data;
1423         data_ptr = tpa_info->data_ptr;
1424         prefetch(data_ptr);
1425         len = tpa_info->len;
1426         mapping = tpa_info->mapping;
1427
1428         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1429                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1430
1431         if (agg_bufs) {
1432                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1433                         return ERR_PTR(-EBUSY);
1434
1435                 *event |= BNXT_AGG_EVENT;
1436                 cp_cons = NEXT_CMP(cp_cons);
1437         }
1438
1439         if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1440                 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1441                 if (agg_bufs > MAX_SKB_FRAGS)
1442                         netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1443                                     agg_bufs, (int)MAX_SKB_FRAGS);
1444                 return NULL;
1445         }
1446
1447         if (len <= bp->rx_copy_thresh) {
1448                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1449                 if (!skb) {
1450                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1451                         return NULL;
1452                 }
1453         } else {
1454                 u8 *new_data;
1455                 dma_addr_t new_mapping;
1456
1457                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1458                 if (!new_data) {
1459                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1460                         return NULL;
1461                 }
1462
1463                 tpa_info->data = new_data;
1464                 tpa_info->data_ptr = new_data + bp->rx_offset;
1465                 tpa_info->mapping = new_mapping;
1466
1467                 skb = build_skb(data, 0);
1468                 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1469                                        bp->rx_buf_use_size, bp->rx_dir,
1470                                        DMA_ATTR_WEAK_ORDERING);
1471
1472                 if (!skb) {
1473                         kfree(data);
1474                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1475                         return NULL;
1476                 }
1477                 skb_reserve(skb, bp->rx_offset);
1478                 skb_put(skb, len);
1479         }
1480
1481         if (agg_bufs) {
1482                 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1483                 if (!skb) {
1484                         /* Page reuse already handled by bnxt_rx_pages(). */
1485                         return NULL;
1486                 }
1487         }
1488
1489         skb->protocol =
1490                 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1491
1492         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1493                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1494
1495         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1496             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1497                 u16 vlan_proto = tpa_info->metadata >>
1498                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1499                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1500
1501                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1502         }
1503
1504         skb_checksum_none_assert(skb);
1505         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1506                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1507                 skb->csum_level =
1508                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1509         }
1510
1511         if (TPA_END_GRO(tpa_end))
1512                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1513
1514         return skb;
1515 }
1516
1517 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1518                              struct sk_buff *skb)
1519 {
1520         if (skb->dev != bp->dev) {
1521                 /* this packet belongs to a vf-rep */
1522                 bnxt_vf_rep_rx(bp, skb);
1523                 return;
1524         }
1525         skb_record_rx_queue(skb, bnapi->index);
1526         napi_gro_receive(&bnapi->napi, skb);
1527 }
1528
1529 /* returns the following:
1530  * 1       - 1 packet successfully received
1531  * 0       - successful TPA_START, packet not completed yet
1532  * -EBUSY  - completion ring does not have all the agg buffers yet
1533  * -ENOMEM - packet aborted due to out of memory
1534  * -EIO    - packet aborted due to hw error indicated in BD
1535  */
1536 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1537                        u32 *raw_cons, u8 *event)
1538 {
1539         struct bnxt_napi *bnapi = cpr->bnapi;
1540         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1541         struct net_device *dev = bp->dev;
1542         struct rx_cmp *rxcmp;
1543         struct rx_cmp_ext *rxcmp1;
1544         u32 tmp_raw_cons = *raw_cons;
1545         u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1546         struct bnxt_sw_rx_bd *rx_buf;
1547         unsigned int len;
1548         u8 *data_ptr, agg_bufs, cmp_type;
1549         dma_addr_t dma_addr;
1550         struct sk_buff *skb;
1551         void *data;
1552         int rc = 0;
1553         u32 misc;
1554
1555         rxcmp = (struct rx_cmp *)
1556                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1557
1558         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1559         cp_cons = RING_CMP(tmp_raw_cons);
1560         rxcmp1 = (struct rx_cmp_ext *)
1561                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1562
1563         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1564                 return -EBUSY;
1565
1566         cmp_type = RX_CMP_TYPE(rxcmp);
1567
1568         prod = rxr->rx_prod;
1569
1570         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1571                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1572                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1573
1574                 *event |= BNXT_RX_EVENT;
1575                 goto next_rx_no_prod_no_len;
1576
1577         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1578                 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1579                                    (struct rx_tpa_end_cmp *)rxcmp,
1580                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1581
1582                 if (IS_ERR(skb))
1583                         return -EBUSY;
1584
1585                 rc = -ENOMEM;
1586                 if (likely(skb)) {
1587                         bnxt_deliver_skb(bp, bnapi, skb);
1588                         rc = 1;
1589                 }
1590                 *event |= BNXT_RX_EVENT;
1591                 goto next_rx_no_prod_no_len;
1592         }
1593
1594         cons = rxcmp->rx_cmp_opaque;
1595         if (unlikely(cons != rxr->rx_next_cons)) {
1596                 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp);
1597
1598                 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1599                             cons, rxr->rx_next_cons);
1600                 bnxt_sched_reset(bp, rxr);
1601                 return rc1;
1602         }
1603         rx_buf = &rxr->rx_buf_ring[cons];
1604         data = rx_buf->data;
1605         data_ptr = rx_buf->data_ptr;
1606         prefetch(data_ptr);
1607
1608         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1609         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1610
1611         if (agg_bufs) {
1612                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1613                         return -EBUSY;
1614
1615                 cp_cons = NEXT_CMP(cp_cons);
1616                 *event |= BNXT_AGG_EVENT;
1617         }
1618         *event |= BNXT_RX_EVENT;
1619
1620         rx_buf->data = NULL;
1621         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1622                 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1623
1624                 bnxt_reuse_rx_data(rxr, cons, data);
1625                 if (agg_bufs)
1626                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1627
1628                 rc = -EIO;
1629                 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1630                         netdev_warn(bp->dev, "RX buffer error %x\n", rx_err);
1631                         bnxt_sched_reset(bp, rxr);
1632                 }
1633                 goto next_rx_no_len;
1634         }
1635
1636         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1637         dma_addr = rx_buf->mapping;
1638
1639         if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1640                 rc = 1;
1641                 goto next_rx;
1642         }
1643
1644         if (len <= bp->rx_copy_thresh) {
1645                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1646                 bnxt_reuse_rx_data(rxr, cons, data);
1647                 if (!skb) {
1648                         if (agg_bufs)
1649                                 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1650                         rc = -ENOMEM;
1651                         goto next_rx;
1652                 }
1653         } else {
1654                 u32 payload;
1655
1656                 if (rx_buf->data_ptr == data_ptr)
1657                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1658                 else
1659                         payload = 0;
1660                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1661                                       payload | len);
1662                 if (!skb) {
1663                         rc = -ENOMEM;
1664                         goto next_rx;
1665                 }
1666         }
1667
1668         if (agg_bufs) {
1669                 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1670                 if (!skb) {
1671                         rc = -ENOMEM;
1672                         goto next_rx;
1673                 }
1674         }
1675
1676         if (RX_CMP_HASH_VALID(rxcmp)) {
1677                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1678                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1679
1680                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1681                 if (hash_type != 1 && hash_type != 3)
1682                         type = PKT_HASH_TYPE_L3;
1683                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1684         }
1685
1686         cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1687         skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1688
1689         if ((rxcmp1->rx_cmp_flags2 &
1690              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1691             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1692                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1693                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1694                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1695
1696                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1697         }
1698
1699         skb_checksum_none_assert(skb);
1700         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1701                 if (dev->features & NETIF_F_RXCSUM) {
1702                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1703                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1704                 }
1705         } else {
1706                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1707                         if (dev->features & NETIF_F_RXCSUM)
1708                                 bnapi->cp_ring.rx_l4_csum_errors++;
1709                 }
1710         }
1711
1712         bnxt_deliver_skb(bp, bnapi, skb);
1713         rc = 1;
1714
1715 next_rx:
1716         cpr->rx_packets += 1;
1717         cpr->rx_bytes += len;
1718
1719 next_rx_no_len:
1720         rxr->rx_prod = NEXT_RX(prod);
1721         rxr->rx_next_cons = NEXT_RX(cons);
1722
1723 next_rx_no_prod_no_len:
1724         *raw_cons = tmp_raw_cons;
1725
1726         return rc;
1727 }
1728
1729 /* In netpoll mode, if we are using a combined completion ring, we need to
1730  * discard the rx packets and recycle the buffers.
1731  */
1732 static int bnxt_force_rx_discard(struct bnxt *bp,
1733                                  struct bnxt_cp_ring_info *cpr,
1734                                  u32 *raw_cons, u8 *event)
1735 {
1736         u32 tmp_raw_cons = *raw_cons;
1737         struct rx_cmp_ext *rxcmp1;
1738         struct rx_cmp *rxcmp;
1739         u16 cp_cons;
1740         u8 cmp_type;
1741
1742         cp_cons = RING_CMP(tmp_raw_cons);
1743         rxcmp = (struct rx_cmp *)
1744                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1745
1746         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1747         cp_cons = RING_CMP(tmp_raw_cons);
1748         rxcmp1 = (struct rx_cmp_ext *)
1749                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1750
1751         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1752                 return -EBUSY;
1753
1754         cmp_type = RX_CMP_TYPE(rxcmp);
1755         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1756                 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1757                         cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1758         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1759                 struct rx_tpa_end_cmp_ext *tpa_end1;
1760
1761                 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1762                 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1763                         cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1764         }
1765         return bnxt_rx_pkt(bp, cpr, raw_cons, event);
1766 }
1767
1768 #define BNXT_GET_EVENT_PORT(data)       \
1769         ((data) &                       \
1770          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1771
1772 static int bnxt_async_event_process(struct bnxt *bp,
1773                                     struct hwrm_async_event_cmpl *cmpl)
1774 {
1775         u16 event_id = le16_to_cpu(cmpl->event_id);
1776
1777         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1778         switch (event_id) {
1779         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1780                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1781                 struct bnxt_link_info *link_info = &bp->link_info;
1782
1783                 if (BNXT_VF(bp))
1784                         goto async_event_process_exit;
1785
1786                 /* print unsupported speed warning in forced speed mode only */
1787                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1788                     (data1 & 0x20000)) {
1789                         u16 fw_speed = link_info->force_link_speed;
1790                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1791
1792                         if (speed != SPEED_UNKNOWN)
1793                                 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1794                                             speed);
1795                 }
1796                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1797         }
1798         /* fall through */
1799         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1800                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1801                 break;
1802         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1803                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1804                 break;
1805         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1806                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1807                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1808
1809                 if (BNXT_VF(bp))
1810                         break;
1811
1812                 if (bp->pf.port_id != port_id)
1813                         break;
1814
1815                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1816                 break;
1817         }
1818         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1819                 if (BNXT_PF(bp))
1820                         goto async_event_process_exit;
1821                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1822                 break;
1823         default:
1824                 goto async_event_process_exit;
1825         }
1826         bnxt_queue_sp_work(bp);
1827 async_event_process_exit:
1828         bnxt_ulp_async_events(bp, cmpl);
1829         return 0;
1830 }
1831
1832 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1833 {
1834         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1835         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1836         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1837                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1838
1839         switch (cmpl_type) {
1840         case CMPL_BASE_TYPE_HWRM_DONE:
1841                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1842                 if (seq_id == bp->hwrm_intr_seq_id)
1843                         bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
1844                 else
1845                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1846                 break;
1847
1848         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1849                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1850
1851                 if ((vf_id < bp->pf.first_vf_id) ||
1852                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1853                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1854                                    vf_id);
1855                         return -EINVAL;
1856                 }
1857
1858                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1859                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1860                 bnxt_queue_sp_work(bp);
1861                 break;
1862
1863         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1864                 bnxt_async_event_process(bp,
1865                                          (struct hwrm_async_event_cmpl *)txcmp);
1866
1867         default:
1868                 break;
1869         }
1870
1871         return 0;
1872 }
1873
1874 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1875 {
1876         struct bnxt_napi *bnapi = dev_instance;
1877         struct bnxt *bp = bnapi->bp;
1878         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1879         u32 cons = RING_CMP(cpr->cp_raw_cons);
1880
1881         cpr->event_ctr++;
1882         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1883         napi_schedule(&bnapi->napi);
1884         return IRQ_HANDLED;
1885 }
1886
1887 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1888 {
1889         u32 raw_cons = cpr->cp_raw_cons;
1890         u16 cons = RING_CMP(raw_cons);
1891         struct tx_cmp *txcmp;
1892
1893         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1894
1895         return TX_CMP_VALID(txcmp, raw_cons);
1896 }
1897
1898 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1899 {
1900         struct bnxt_napi *bnapi = dev_instance;
1901         struct bnxt *bp = bnapi->bp;
1902         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1903         u32 cons = RING_CMP(cpr->cp_raw_cons);
1904         u32 int_status;
1905
1906         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1907
1908         if (!bnxt_has_work(bp, cpr)) {
1909                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1910                 /* return if erroneous interrupt */
1911                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1912                         return IRQ_NONE;
1913         }
1914
1915         /* disable ring IRQ */
1916         BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
1917
1918         /* Return here if interrupt is shared and is disabled. */
1919         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1920                 return IRQ_HANDLED;
1921
1922         napi_schedule(&bnapi->napi);
1923         return IRQ_HANDLED;
1924 }
1925
1926 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1927                             int budget)
1928 {
1929         struct bnxt_napi *bnapi = cpr->bnapi;
1930         u32 raw_cons = cpr->cp_raw_cons;
1931         u32 cons;
1932         int tx_pkts = 0;
1933         int rx_pkts = 0;
1934         u8 event = 0;
1935         struct tx_cmp *txcmp;
1936
1937         cpr->has_more_work = 0;
1938         while (1) {
1939                 int rc;
1940
1941                 cons = RING_CMP(raw_cons);
1942                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1943
1944                 if (!TX_CMP_VALID(txcmp, raw_cons))
1945                         break;
1946
1947                 /* The valid test of the entry must be done first before
1948                  * reading any further.
1949                  */
1950                 dma_rmb();
1951                 cpr->had_work_done = 1;
1952                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1953                         tx_pkts++;
1954                         /* return full budget so NAPI will complete. */
1955                         if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
1956                                 rx_pkts = budget;
1957                                 raw_cons = NEXT_RAW_CMP(raw_cons);
1958                                 if (budget)
1959                                         cpr->has_more_work = 1;
1960                                 break;
1961                         }
1962                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1963                         if (likely(budget))
1964                                 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
1965                         else
1966                                 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
1967                                                            &event);
1968                         if (likely(rc >= 0))
1969                                 rx_pkts += rc;
1970                         /* Increment rx_pkts when rc is -ENOMEM to count towards
1971                          * the NAPI budget.  Otherwise, we may potentially loop
1972                          * here forever if we consistently cannot allocate
1973                          * buffers.
1974                          */
1975                         else if (rc == -ENOMEM && budget)
1976                                 rx_pkts++;
1977                         else if (rc == -EBUSY)  /* partial completion */
1978                                 break;
1979                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1980                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1981                                     (TX_CMP_TYPE(txcmp) ==
1982                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1983                                     (TX_CMP_TYPE(txcmp) ==
1984                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1985                         bnxt_hwrm_handler(bp, txcmp);
1986                 }
1987                 raw_cons = NEXT_RAW_CMP(raw_cons);
1988
1989                 if (rx_pkts && rx_pkts == budget) {
1990                         cpr->has_more_work = 1;
1991                         break;
1992                 }
1993         }
1994
1995         if (event & BNXT_REDIRECT_EVENT)
1996                 xdp_do_flush_map();
1997
1998         if (event & BNXT_TX_EVENT) {
1999                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
2000                 u16 prod = txr->tx_prod;
2001
2002                 /* Sync BD data before updating doorbell */
2003                 wmb();
2004
2005                 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
2006         }
2007
2008         cpr->cp_raw_cons = raw_cons;
2009         bnapi->tx_pkts += tx_pkts;
2010         bnapi->events |= event;
2011         return rx_pkts;
2012 }
2013
2014 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
2015 {
2016         if (bnapi->tx_pkts) {
2017                 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2018                 bnapi->tx_pkts = 0;
2019         }
2020
2021         if (bnapi->events & BNXT_RX_EVENT) {
2022                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2023
2024                 if (bnapi->events & BNXT_AGG_EVENT)
2025                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2026                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2027         }
2028         bnapi->events = 0;
2029 }
2030
2031 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2032                           int budget)
2033 {
2034         struct bnxt_napi *bnapi = cpr->bnapi;
2035         int rx_pkts;
2036
2037         rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2038
2039         /* ACK completion ring before freeing tx ring and producing new
2040          * buffers in rx/agg rings to prevent overflowing the completion
2041          * ring.
2042          */
2043         bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2044
2045         __bnxt_poll_work_done(bp, bnapi);
2046         return rx_pkts;
2047 }
2048
2049 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2050 {
2051         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2052         struct bnxt *bp = bnapi->bp;
2053         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2054         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2055         struct tx_cmp *txcmp;
2056         struct rx_cmp_ext *rxcmp1;
2057         u32 cp_cons, tmp_raw_cons;
2058         u32 raw_cons = cpr->cp_raw_cons;
2059         u32 rx_pkts = 0;
2060         u8 event = 0;
2061
2062         while (1) {
2063                 int rc;
2064
2065                 cp_cons = RING_CMP(raw_cons);
2066                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2067
2068                 if (!TX_CMP_VALID(txcmp, raw_cons))
2069                         break;
2070
2071                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2072                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2073                         cp_cons = RING_CMP(tmp_raw_cons);
2074                         rxcmp1 = (struct rx_cmp_ext *)
2075                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2076
2077                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2078                                 break;
2079
2080                         /* force an error to recycle the buffer */
2081                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2082                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2083
2084                         rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2085                         if (likely(rc == -EIO) && budget)
2086                                 rx_pkts++;
2087                         else if (rc == -EBUSY)  /* partial completion */
2088                                 break;
2089                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2090                                     CMPL_BASE_TYPE_HWRM_DONE)) {
2091                         bnxt_hwrm_handler(bp, txcmp);
2092                 } else {
2093                         netdev_err(bp->dev,
2094                                    "Invalid completion received on special ring\n");
2095                 }
2096                 raw_cons = NEXT_RAW_CMP(raw_cons);
2097
2098                 if (rx_pkts == budget)
2099                         break;
2100         }
2101
2102         cpr->cp_raw_cons = raw_cons;
2103         BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2104         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2105
2106         if (event & BNXT_AGG_EVENT)
2107                 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2108
2109         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2110                 napi_complete_done(napi, rx_pkts);
2111                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2112         }
2113         return rx_pkts;
2114 }
2115
2116 static int bnxt_poll(struct napi_struct *napi, int budget)
2117 {
2118         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2119         struct bnxt *bp = bnapi->bp;
2120         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2121         int work_done = 0;
2122
2123         while (1) {
2124                 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2125
2126                 if (work_done >= budget) {
2127                         if (!budget)
2128                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2129                         break;
2130                 }
2131
2132                 if (!bnxt_has_work(bp, cpr)) {
2133                         if (napi_complete_done(napi, work_done))
2134                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2135                         break;
2136                 }
2137         }
2138         if (bp->flags & BNXT_FLAG_DIM) {
2139                 struct dim_sample dim_sample = {};
2140
2141                 dim_update_sample(cpr->event_ctr,
2142                                   cpr->rx_packets,
2143                                   cpr->rx_bytes,
2144                                   &dim_sample);
2145                 net_dim(&cpr->dim, dim_sample);
2146         }
2147         return work_done;
2148 }
2149
2150 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2151 {
2152         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2153         int i, work_done = 0;
2154
2155         for (i = 0; i < 2; i++) {
2156                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2157
2158                 if (cpr2) {
2159                         work_done += __bnxt_poll_work(bp, cpr2,
2160                                                       budget - work_done);
2161                         cpr->has_more_work |= cpr2->has_more_work;
2162                 }
2163         }
2164         return work_done;
2165 }
2166
2167 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2168                                  u64 dbr_type, bool all)
2169 {
2170         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2171         int i;
2172
2173         for (i = 0; i < 2; i++) {
2174                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2175                 struct bnxt_db_info *db;
2176
2177                 if (cpr2 && (all || cpr2->had_work_done)) {
2178                         db = &cpr2->cp_db;
2179                         writeq(db->db_key64 | dbr_type |
2180                                RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2181                         cpr2->had_work_done = 0;
2182                 }
2183         }
2184         __bnxt_poll_work_done(bp, bnapi);
2185 }
2186
2187 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2188 {
2189         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2190         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2191         u32 raw_cons = cpr->cp_raw_cons;
2192         struct bnxt *bp = bnapi->bp;
2193         struct nqe_cn *nqcmp;
2194         int work_done = 0;
2195         u32 cons;
2196
2197         if (cpr->has_more_work) {
2198                 cpr->has_more_work = 0;
2199                 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2200                 if (cpr->has_more_work) {
2201                         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false);
2202                         return work_done;
2203                 }
2204                 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true);
2205                 if (napi_complete_done(napi, work_done))
2206                         BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons);
2207                 return work_done;
2208         }
2209         while (1) {
2210                 cons = RING_CMP(raw_cons);
2211                 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2212
2213                 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2214                         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL,
2215                                              false);
2216                         cpr->cp_raw_cons = raw_cons;
2217                         if (napi_complete_done(napi, work_done))
2218                                 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2219                                                   cpr->cp_raw_cons);
2220                         return work_done;
2221                 }
2222
2223                 /* The valid test of the entry must be done first before
2224                  * reading any further.
2225                  */
2226                 dma_rmb();
2227
2228                 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2229                         u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2230                         struct bnxt_cp_ring_info *cpr2;
2231
2232                         cpr2 = cpr->cp_ring_arr[idx];
2233                         work_done += __bnxt_poll_work(bp, cpr2,
2234                                                       budget - work_done);
2235                         cpr->has_more_work = cpr2->has_more_work;
2236                 } else {
2237                         bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2238                 }
2239                 raw_cons = NEXT_RAW_CMP(raw_cons);
2240                 if (cpr->has_more_work)
2241                         break;
2242         }
2243         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true);
2244         cpr->cp_raw_cons = raw_cons;
2245         return work_done;
2246 }
2247
2248 static void bnxt_free_tx_skbs(struct bnxt *bp)
2249 {
2250         int i, max_idx;
2251         struct pci_dev *pdev = bp->pdev;
2252
2253         if (!bp->tx_ring)
2254                 return;
2255
2256         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2257         for (i = 0; i < bp->tx_nr_rings; i++) {
2258                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2259                 int j;
2260
2261                 for (j = 0; j < max_idx;) {
2262                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2263                         struct sk_buff *skb;
2264                         int k, last;
2265
2266                         if (i < bp->tx_nr_rings_xdp &&
2267                             tx_buf->action == XDP_REDIRECT) {
2268                                 dma_unmap_single(&pdev->dev,
2269                                         dma_unmap_addr(tx_buf, mapping),
2270                                         dma_unmap_len(tx_buf, len),
2271                                         PCI_DMA_TODEVICE);
2272                                 xdp_return_frame(tx_buf->xdpf);
2273                                 tx_buf->action = 0;
2274                                 tx_buf->xdpf = NULL;
2275                                 j++;
2276                                 continue;
2277                         }
2278
2279                         skb = tx_buf->skb;
2280                         if (!skb) {
2281                                 j++;
2282                                 continue;
2283                         }
2284
2285                         tx_buf->skb = NULL;
2286
2287                         if (tx_buf->is_push) {
2288                                 dev_kfree_skb(skb);
2289                                 j += 2;
2290                                 continue;
2291                         }
2292
2293                         dma_unmap_single(&pdev->dev,
2294                                          dma_unmap_addr(tx_buf, mapping),
2295                                          skb_headlen(skb),
2296                                          PCI_DMA_TODEVICE);
2297
2298                         last = tx_buf->nr_frags;
2299                         j += 2;
2300                         for (k = 0; k < last; k++, j++) {
2301                                 int ring_idx = j & bp->tx_ring_mask;
2302                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2303
2304                                 tx_buf = &txr->tx_buf_ring[ring_idx];
2305                                 dma_unmap_page(
2306                                         &pdev->dev,
2307                                         dma_unmap_addr(tx_buf, mapping),
2308                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
2309                         }
2310                         dev_kfree_skb(skb);
2311                 }
2312                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2313         }
2314 }
2315
2316 static void bnxt_free_rx_skbs(struct bnxt *bp)
2317 {
2318         int i, max_idx, max_agg_idx;
2319         struct pci_dev *pdev = bp->pdev;
2320
2321         if (!bp->rx_ring)
2322                 return;
2323
2324         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2325         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2326         for (i = 0; i < bp->rx_nr_rings; i++) {
2327                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2328                 int j;
2329
2330                 if (rxr->rx_tpa) {
2331                         for (j = 0; j < MAX_TPA; j++) {
2332                                 struct bnxt_tpa_info *tpa_info =
2333                                                         &rxr->rx_tpa[j];
2334                                 u8 *data = tpa_info->data;
2335
2336                                 if (!data)
2337                                         continue;
2338
2339                                 dma_unmap_single_attrs(&pdev->dev,
2340                                                        tpa_info->mapping,
2341                                                        bp->rx_buf_use_size,
2342                                                        bp->rx_dir,
2343                                                        DMA_ATTR_WEAK_ORDERING);
2344
2345                                 tpa_info->data = NULL;
2346
2347                                 kfree(data);
2348                         }
2349                 }
2350
2351                 for (j = 0; j < max_idx; j++) {
2352                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2353                         dma_addr_t mapping = rx_buf->mapping;
2354                         void *data = rx_buf->data;
2355
2356                         if (!data)
2357                                 continue;
2358
2359                         rx_buf->data = NULL;
2360
2361                         if (BNXT_RX_PAGE_MODE(bp)) {
2362                                 mapping -= bp->rx_dma_offset;
2363                                 dma_unmap_page_attrs(&pdev->dev, mapping,
2364                                                      PAGE_SIZE, bp->rx_dir,
2365                                                      DMA_ATTR_WEAK_ORDERING);
2366                                 page_pool_recycle_direct(rxr->page_pool, data);
2367                         } else {
2368                                 dma_unmap_single_attrs(&pdev->dev, mapping,
2369                                                        bp->rx_buf_use_size,
2370                                                        bp->rx_dir,
2371                                                        DMA_ATTR_WEAK_ORDERING);
2372                                 kfree(data);
2373                         }
2374                 }
2375
2376                 for (j = 0; j < max_agg_idx; j++) {
2377                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2378                                 &rxr->rx_agg_ring[j];
2379                         struct page *page = rx_agg_buf->page;
2380
2381                         if (!page)
2382                                 continue;
2383
2384                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2385                                              BNXT_RX_PAGE_SIZE,
2386                                              PCI_DMA_FROMDEVICE,
2387                                              DMA_ATTR_WEAK_ORDERING);
2388
2389                         rx_agg_buf->page = NULL;
2390                         __clear_bit(j, rxr->rx_agg_bmap);
2391
2392                         __free_page(page);
2393                 }
2394                 if (rxr->rx_page) {
2395                         __free_page(rxr->rx_page);
2396                         rxr->rx_page = NULL;
2397                 }
2398         }
2399 }
2400
2401 static void bnxt_free_skbs(struct bnxt *bp)
2402 {
2403         bnxt_free_tx_skbs(bp);
2404         bnxt_free_rx_skbs(bp);
2405 }
2406
2407 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2408 {
2409         struct pci_dev *pdev = bp->pdev;
2410         int i;
2411
2412         for (i = 0; i < rmem->nr_pages; i++) {
2413                 if (!rmem->pg_arr[i])
2414                         continue;
2415
2416                 dma_free_coherent(&pdev->dev, rmem->page_size,
2417                                   rmem->pg_arr[i], rmem->dma_arr[i]);
2418
2419                 rmem->pg_arr[i] = NULL;
2420         }
2421         if (rmem->pg_tbl) {
2422                 size_t pg_tbl_size = rmem->nr_pages * 8;
2423
2424                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2425                         pg_tbl_size = rmem->page_size;
2426                 dma_free_coherent(&pdev->dev, pg_tbl_size,
2427                                   rmem->pg_tbl, rmem->pg_tbl_map);
2428                 rmem->pg_tbl = NULL;
2429         }
2430         if (rmem->vmem_size && *rmem->vmem) {
2431                 vfree(*rmem->vmem);
2432                 *rmem->vmem = NULL;
2433         }
2434 }
2435
2436 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2437 {
2438         struct pci_dev *pdev = bp->pdev;
2439         u64 valid_bit = 0;
2440         int i;
2441
2442         if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2443                 valid_bit = PTU_PTE_VALID;
2444         if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2445                 size_t pg_tbl_size = rmem->nr_pages * 8;
2446
2447                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2448                         pg_tbl_size = rmem->page_size;
2449                 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2450                                                   &rmem->pg_tbl_map,
2451                                                   GFP_KERNEL);
2452                 if (!rmem->pg_tbl)
2453                         return -ENOMEM;
2454         }
2455
2456         for (i = 0; i < rmem->nr_pages; i++) {
2457                 u64 extra_bits = valid_bit;
2458
2459                 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2460                                                      rmem->page_size,
2461                                                      &rmem->dma_arr[i],
2462                                                      GFP_KERNEL);
2463                 if (!rmem->pg_arr[i])
2464                         return -ENOMEM;
2465
2466                 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2467                         if (i == rmem->nr_pages - 2 &&
2468                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2469                                 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2470                         else if (i == rmem->nr_pages - 1 &&
2471                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2472                                 extra_bits |= PTU_PTE_LAST;
2473                         rmem->pg_tbl[i] =
2474                                 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2475                 }
2476         }
2477
2478         if (rmem->vmem_size) {
2479                 *rmem->vmem = vzalloc(rmem->vmem_size);
2480                 if (!(*rmem->vmem))
2481                         return -ENOMEM;
2482         }
2483         return 0;
2484 }
2485
2486 static void bnxt_free_rx_rings(struct bnxt *bp)
2487 {
2488         int i;
2489
2490         if (!bp->rx_ring)
2491                 return;
2492
2493         for (i = 0; i < bp->rx_nr_rings; i++) {
2494                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2495                 struct bnxt_ring_struct *ring;
2496
2497                 if (rxr->xdp_prog)
2498                         bpf_prog_put(rxr->xdp_prog);
2499
2500                 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2501                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
2502
2503                 page_pool_destroy(rxr->page_pool);
2504                 rxr->page_pool = NULL;
2505
2506                 kfree(rxr->rx_tpa);
2507                 rxr->rx_tpa = NULL;
2508
2509                 kfree(rxr->rx_agg_bmap);
2510                 rxr->rx_agg_bmap = NULL;
2511
2512                 ring = &rxr->rx_ring_struct;
2513                 bnxt_free_ring(bp, &ring->ring_mem);
2514
2515                 ring = &rxr->rx_agg_ring_struct;
2516                 bnxt_free_ring(bp, &ring->ring_mem);
2517         }
2518 }
2519
2520 static int bnxt_alloc_rx_page_pool(struct bnxt *bp,
2521                                    struct bnxt_rx_ring_info *rxr)
2522 {
2523         struct page_pool_params pp = { 0 };
2524
2525         pp.pool_size = bp->rx_ring_size;
2526         pp.nid = dev_to_node(&bp->pdev->dev);
2527         pp.dev = &bp->pdev->dev;
2528         pp.dma_dir = DMA_BIDIRECTIONAL;
2529
2530         rxr->page_pool = page_pool_create(&pp);
2531         if (IS_ERR(rxr->page_pool)) {
2532                 int err = PTR_ERR(rxr->page_pool);
2533
2534                 rxr->page_pool = NULL;
2535                 return err;
2536         }
2537         return 0;
2538 }
2539
2540 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2541 {
2542         int i, rc, agg_rings = 0, tpa_rings = 0;
2543
2544         if (!bp->rx_ring)
2545                 return -ENOMEM;
2546
2547         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2548                 agg_rings = 1;
2549
2550         if (bp->flags & BNXT_FLAG_TPA)
2551                 tpa_rings = 1;
2552
2553         for (i = 0; i < bp->rx_nr_rings; i++) {
2554                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2555                 struct bnxt_ring_struct *ring;
2556
2557                 ring = &rxr->rx_ring_struct;
2558
2559                 rc = bnxt_alloc_rx_page_pool(bp, rxr);
2560                 if (rc)
2561                         return rc;
2562
2563                 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2564                 if (rc < 0)
2565                         return rc;
2566
2567                 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq,
2568                                                 MEM_TYPE_PAGE_POOL,
2569                                                 rxr->page_pool);
2570                 if (rc) {
2571                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
2572                         return rc;
2573                 }
2574
2575                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2576                 if (rc)
2577                         return rc;
2578
2579                 ring->grp_idx = i;
2580                 if (agg_rings) {
2581                         u16 mem_size;
2582
2583                         ring = &rxr->rx_agg_ring_struct;
2584                         rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2585                         if (rc)
2586                                 return rc;
2587
2588                         ring->grp_idx = i;
2589                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2590                         mem_size = rxr->rx_agg_bmap_size / 8;
2591                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2592                         if (!rxr->rx_agg_bmap)
2593                                 return -ENOMEM;
2594
2595                         if (tpa_rings) {
2596                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2597                                                 sizeof(struct bnxt_tpa_info),
2598                                                 GFP_KERNEL);
2599                                 if (!rxr->rx_tpa)
2600                                         return -ENOMEM;
2601                         }
2602                 }
2603         }
2604         return 0;
2605 }
2606
2607 static void bnxt_free_tx_rings(struct bnxt *bp)
2608 {
2609         int i;
2610         struct pci_dev *pdev = bp->pdev;
2611
2612         if (!bp->tx_ring)
2613                 return;
2614
2615         for (i = 0; i < bp->tx_nr_rings; i++) {
2616                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2617                 struct bnxt_ring_struct *ring;
2618
2619                 if (txr->tx_push) {
2620                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2621                                           txr->tx_push, txr->tx_push_mapping);
2622                         txr->tx_push = NULL;
2623                 }
2624
2625                 ring = &txr->tx_ring_struct;
2626
2627                 bnxt_free_ring(bp, &ring->ring_mem);
2628         }
2629 }
2630
2631 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2632 {
2633         int i, j, rc;
2634         struct pci_dev *pdev = bp->pdev;
2635
2636         bp->tx_push_size = 0;
2637         if (bp->tx_push_thresh) {
2638                 int push_size;
2639
2640                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2641                                         bp->tx_push_thresh);
2642
2643                 if (push_size > 256) {
2644                         push_size = 0;
2645                         bp->tx_push_thresh = 0;
2646                 }
2647
2648                 bp->tx_push_size = push_size;
2649         }
2650
2651         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2652                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2653                 struct bnxt_ring_struct *ring;
2654                 u8 qidx;
2655
2656                 ring = &txr->tx_ring_struct;
2657
2658                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2659                 if (rc)
2660                         return rc;
2661
2662                 ring->grp_idx = txr->bnapi->index;
2663                 if (bp->tx_push_size) {
2664                         dma_addr_t mapping;
2665
2666                         /* One pre-allocated DMA buffer to backup
2667                          * TX push operation
2668                          */
2669                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2670                                                 bp->tx_push_size,
2671                                                 &txr->tx_push_mapping,
2672                                                 GFP_KERNEL);
2673
2674                         if (!txr->tx_push)
2675                                 return -ENOMEM;
2676
2677                         mapping = txr->tx_push_mapping +
2678                                 sizeof(struct tx_push_bd);
2679                         txr->data_mapping = cpu_to_le64(mapping);
2680                 }
2681                 qidx = bp->tc_to_qidx[j];
2682                 ring->queue_id = bp->q_info[qidx].queue_id;
2683                 if (i < bp->tx_nr_rings_xdp)
2684                         continue;
2685                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2686                         j++;
2687         }
2688         return 0;
2689 }
2690
2691 static void bnxt_free_cp_rings(struct bnxt *bp)
2692 {
2693         int i;
2694
2695         if (!bp->bnapi)
2696                 return;
2697
2698         for (i = 0; i < bp->cp_nr_rings; i++) {
2699                 struct bnxt_napi *bnapi = bp->bnapi[i];
2700                 struct bnxt_cp_ring_info *cpr;
2701                 struct bnxt_ring_struct *ring;
2702                 int j;
2703
2704                 if (!bnapi)
2705                         continue;
2706
2707                 cpr = &bnapi->cp_ring;
2708                 ring = &cpr->cp_ring_struct;
2709
2710                 bnxt_free_ring(bp, &ring->ring_mem);
2711
2712                 for (j = 0; j < 2; j++) {
2713                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2714
2715                         if (cpr2) {
2716                                 ring = &cpr2->cp_ring_struct;
2717                                 bnxt_free_ring(bp, &ring->ring_mem);
2718                                 kfree(cpr2);
2719                                 cpr->cp_ring_arr[j] = NULL;
2720                         }
2721                 }
2722         }
2723 }
2724
2725 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
2726 {
2727         struct bnxt_ring_mem_info *rmem;
2728         struct bnxt_ring_struct *ring;
2729         struct bnxt_cp_ring_info *cpr;
2730         int rc;
2731
2732         cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
2733         if (!cpr)
2734                 return NULL;
2735
2736         ring = &cpr->cp_ring_struct;
2737         rmem = &ring->ring_mem;
2738         rmem->nr_pages = bp->cp_nr_pages;
2739         rmem->page_size = HW_CMPD_RING_SIZE;
2740         rmem->pg_arr = (void **)cpr->cp_desc_ring;
2741         rmem->dma_arr = cpr->cp_desc_mapping;
2742         rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
2743         rc = bnxt_alloc_ring(bp, rmem);
2744         if (rc) {
2745                 bnxt_free_ring(bp, rmem);
2746                 kfree(cpr);
2747                 cpr = NULL;
2748         }
2749         return cpr;
2750 }
2751
2752 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2753 {
2754         bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
2755         int i, rc, ulp_base_vec, ulp_msix;
2756
2757         ulp_msix = bnxt_get_ulp_msix_num(bp);
2758         ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2759         for (i = 0; i < bp->cp_nr_rings; i++) {
2760                 struct bnxt_napi *bnapi = bp->bnapi[i];
2761                 struct bnxt_cp_ring_info *cpr;
2762                 struct bnxt_ring_struct *ring;
2763
2764                 if (!bnapi)
2765                         continue;
2766
2767                 cpr = &bnapi->cp_ring;
2768                 cpr->bnapi = bnapi;
2769                 ring = &cpr->cp_ring_struct;
2770
2771                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2772                 if (rc)
2773                         return rc;
2774
2775                 if (ulp_msix && i >= ulp_base_vec)
2776                         ring->map_idx = i + ulp_msix;
2777                 else
2778                         ring->map_idx = i;
2779
2780                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2781                         continue;
2782
2783                 if (i < bp->rx_nr_rings) {
2784                         struct bnxt_cp_ring_info *cpr2 =
2785                                 bnxt_alloc_cp_sub_ring(bp);
2786
2787                         cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
2788                         if (!cpr2)
2789                                 return -ENOMEM;
2790                         cpr2->bnapi = bnapi;
2791                 }
2792                 if ((sh && i < bp->tx_nr_rings) ||
2793                     (!sh && i >= bp->rx_nr_rings)) {
2794                         struct bnxt_cp_ring_info *cpr2 =
2795                                 bnxt_alloc_cp_sub_ring(bp);
2796
2797                         cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
2798                         if (!cpr2)
2799                                 return -ENOMEM;
2800                         cpr2->bnapi = bnapi;
2801                 }
2802         }
2803         return 0;
2804 }
2805
2806 static void bnxt_init_ring_struct(struct bnxt *bp)
2807 {
2808         int i;
2809
2810         for (i = 0; i < bp->cp_nr_rings; i++) {
2811                 struct bnxt_napi *bnapi = bp->bnapi[i];
2812                 struct bnxt_ring_mem_info *rmem;
2813                 struct bnxt_cp_ring_info *cpr;
2814                 struct bnxt_rx_ring_info *rxr;
2815                 struct bnxt_tx_ring_info *txr;
2816                 struct bnxt_ring_struct *ring;
2817
2818                 if (!bnapi)
2819                         continue;
2820
2821                 cpr = &bnapi->cp_ring;
2822                 ring = &cpr->cp_ring_struct;
2823                 rmem = &ring->ring_mem;
2824                 rmem->nr_pages = bp->cp_nr_pages;
2825                 rmem->page_size = HW_CMPD_RING_SIZE;
2826                 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2827                 rmem->dma_arr = cpr->cp_desc_mapping;
2828                 rmem->vmem_size = 0;
2829
2830                 rxr = bnapi->rx_ring;
2831                 if (!rxr)
2832                         goto skip_rx;
2833
2834                 ring = &rxr->rx_ring_struct;
2835                 rmem = &ring->ring_mem;
2836                 rmem->nr_pages = bp->rx_nr_pages;
2837                 rmem->page_size = HW_RXBD_RING_SIZE;
2838                 rmem->pg_arr = (void **)rxr->rx_desc_ring;
2839                 rmem->dma_arr = rxr->rx_desc_mapping;
2840                 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2841                 rmem->vmem = (void **)&rxr->rx_buf_ring;
2842
2843                 ring = &rxr->rx_agg_ring_struct;
2844                 rmem = &ring->ring_mem;
2845                 rmem->nr_pages = bp->rx_agg_nr_pages;
2846                 rmem->page_size = HW_RXBD_RING_SIZE;
2847                 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
2848                 rmem->dma_arr = rxr->rx_agg_desc_mapping;
2849                 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2850                 rmem->vmem = (void **)&rxr->rx_agg_ring;
2851
2852 skip_rx:
2853                 txr = bnapi->tx_ring;
2854                 if (!txr)
2855                         continue;
2856
2857                 ring = &txr->tx_ring_struct;
2858                 rmem = &ring->ring_mem;
2859                 rmem->nr_pages = bp->tx_nr_pages;
2860                 rmem->page_size = HW_RXBD_RING_SIZE;
2861                 rmem->pg_arr = (void **)txr->tx_desc_ring;
2862                 rmem->dma_arr = txr->tx_desc_mapping;
2863                 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2864                 rmem->vmem = (void **)&txr->tx_buf_ring;
2865         }
2866 }
2867
2868 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2869 {
2870         int i;
2871         u32 prod;
2872         struct rx_bd **rx_buf_ring;
2873
2874         rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
2875         for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
2876                 int j;
2877                 struct rx_bd *rxbd;
2878
2879                 rxbd = rx_buf_ring[i];
2880                 if (!rxbd)
2881                         continue;
2882
2883                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2884                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2885                         rxbd->rx_bd_opaque = prod;
2886                 }
2887         }
2888 }
2889
2890 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2891 {
2892         struct net_device *dev = bp->dev;
2893         struct bnxt_rx_ring_info *rxr;
2894         struct bnxt_ring_struct *ring;
2895         u32 prod, type;
2896         int i;
2897
2898         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2899                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2900
2901         if (NET_IP_ALIGN == 2)
2902                 type |= RX_BD_FLAGS_SOP;
2903
2904         rxr = &bp->rx_ring[ring_nr];
2905         ring = &rxr->rx_ring_struct;
2906         bnxt_init_rxbd_pages(ring, type);
2907
2908         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2909                 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2910                 if (IS_ERR(rxr->xdp_prog)) {
2911                         int rc = PTR_ERR(rxr->xdp_prog);
2912
2913                         rxr->xdp_prog = NULL;
2914                         return rc;
2915                 }
2916         }
2917         prod = rxr->rx_prod;
2918         for (i = 0; i < bp->rx_ring_size; i++) {
2919                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2920                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2921                                     ring_nr, i, bp->rx_ring_size);
2922                         break;
2923                 }
2924                 prod = NEXT_RX(prod);
2925         }
2926         rxr->rx_prod = prod;
2927         ring->fw_ring_id = INVALID_HW_RING_ID;
2928
2929         ring = &rxr->rx_agg_ring_struct;
2930         ring->fw_ring_id = INVALID_HW_RING_ID;
2931
2932         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2933                 return 0;
2934
2935         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2936                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2937
2938         bnxt_init_rxbd_pages(ring, type);
2939
2940         prod = rxr->rx_agg_prod;
2941         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2942                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2943                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2944                                     ring_nr, i, bp->rx_ring_size);
2945                         break;
2946                 }
2947                 prod = NEXT_RX_AGG(prod);
2948         }
2949         rxr->rx_agg_prod = prod;
2950
2951         if (bp->flags & BNXT_FLAG_TPA) {
2952                 if (rxr->rx_tpa) {
2953                         u8 *data;
2954                         dma_addr_t mapping;
2955
2956                         for (i = 0; i < MAX_TPA; i++) {
2957                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2958                                                             GFP_KERNEL);
2959                                 if (!data)
2960                                         return -ENOMEM;
2961
2962                                 rxr->rx_tpa[i].data = data;
2963                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2964                                 rxr->rx_tpa[i].mapping = mapping;
2965                         }
2966                 } else {
2967                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2968                         return -ENOMEM;
2969                 }
2970         }
2971
2972         return 0;
2973 }
2974
2975 static void bnxt_init_cp_rings(struct bnxt *bp)
2976 {
2977         int i, j;
2978
2979         for (i = 0; i < bp->cp_nr_rings; i++) {
2980                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2981                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2982
2983                 ring->fw_ring_id = INVALID_HW_RING_ID;
2984                 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2985                 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2986                 for (j = 0; j < 2; j++) {
2987                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2988
2989                         if (!cpr2)
2990                                 continue;
2991
2992                         ring = &cpr2->cp_ring_struct;
2993                         ring->fw_ring_id = INVALID_HW_RING_ID;
2994                         cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2995                         cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2996                 }
2997         }
2998 }
2999
3000 static int bnxt_init_rx_rings(struct bnxt *bp)
3001 {
3002         int i, rc = 0;
3003
3004         if (BNXT_RX_PAGE_MODE(bp)) {
3005                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
3006                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
3007         } else {
3008                 bp->rx_offset = BNXT_RX_OFFSET;
3009                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
3010         }
3011
3012         for (i = 0; i < bp->rx_nr_rings; i++) {
3013                 rc = bnxt_init_one_rx_ring(bp, i);
3014                 if (rc)
3015                         break;
3016         }
3017
3018         return rc;
3019 }
3020
3021 static int bnxt_init_tx_rings(struct bnxt *bp)
3022 {
3023         u16 i;
3024
3025         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
3026                                    MAX_SKB_FRAGS + 1);
3027
3028         for (i = 0; i < bp->tx_nr_rings; i++) {
3029                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3030                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3031
3032                 ring->fw_ring_id = INVALID_HW_RING_ID;
3033         }
3034
3035         return 0;
3036 }
3037
3038 static void bnxt_free_ring_grps(struct bnxt *bp)
3039 {
3040         kfree(bp->grp_info);
3041         bp->grp_info = NULL;
3042 }
3043
3044 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
3045 {
3046         int i;
3047
3048         if (irq_re_init) {
3049                 bp->grp_info = kcalloc(bp->cp_nr_rings,
3050                                        sizeof(struct bnxt_ring_grp_info),
3051                                        GFP_KERNEL);
3052                 if (!bp->grp_info)
3053                         return -ENOMEM;
3054         }
3055         for (i = 0; i < bp->cp_nr_rings; i++) {
3056                 if (irq_re_init)
3057                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3058                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3059                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3060                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3061                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3062         }
3063         return 0;
3064 }
3065
3066 static void bnxt_free_vnics(struct bnxt *bp)
3067 {
3068         kfree(bp->vnic_info);
3069         bp->vnic_info = NULL;
3070         bp->nr_vnics = 0;
3071 }
3072
3073 static int bnxt_alloc_vnics(struct bnxt *bp)
3074 {
3075         int num_vnics = 1;
3076
3077 #ifdef CONFIG_RFS_ACCEL
3078         if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
3079                 num_vnics += bp->rx_nr_rings;
3080 #endif
3081
3082         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3083                 num_vnics++;
3084
3085         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3086                                 GFP_KERNEL);
3087         if (!bp->vnic_info)
3088                 return -ENOMEM;
3089
3090         bp->nr_vnics = num_vnics;
3091         return 0;
3092 }
3093
3094 static void bnxt_init_vnics(struct bnxt *bp)
3095 {
3096         int i;
3097
3098         for (i = 0; i < bp->nr_vnics; i++) {
3099                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3100                 int j;
3101
3102                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3103                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3104                         vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3105
3106                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3107
3108                 if (bp->vnic_info[i].rss_hash_key) {
3109                         if (i == 0)
3110                                 prandom_bytes(vnic->rss_hash_key,
3111                                               HW_HASH_KEY_SIZE);
3112                         else
3113                                 memcpy(vnic->rss_hash_key,
3114                                        bp->vnic_info[0].rss_hash_key,
3115                                        HW_HASH_KEY_SIZE);
3116                 }
3117         }
3118 }
3119
3120 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3121 {
3122         int pages;
3123
3124         pages = ring_size / desc_per_pg;
3125
3126         if (!pages)
3127                 return 1;
3128
3129         pages++;
3130
3131         while (pages & (pages - 1))
3132                 pages++;
3133
3134         return pages;
3135 }
3136
3137 void bnxt_set_tpa_flags(struct bnxt *bp)
3138 {
3139         bp->flags &= ~BNXT_FLAG_TPA;
3140         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3141                 return;
3142         if (bp->dev->features & NETIF_F_LRO)
3143                 bp->flags |= BNXT_FLAG_LRO;
3144         else if (bp->dev->features & NETIF_F_GRO_HW)
3145                 bp->flags |= BNXT_FLAG_GRO;
3146 }
3147
3148 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3149  * be set on entry.
3150  */
3151 void bnxt_set_ring_params(struct bnxt *bp)
3152 {
3153         u32 ring_size, rx_size, rx_space;
3154         u32 agg_factor = 0, agg_ring_size = 0;
3155
3156         /* 8 for CRC and VLAN */
3157         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3158
3159         rx_space = rx_size + NET_SKB_PAD +
3160                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3161
3162         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3163         ring_size = bp->rx_ring_size;
3164         bp->rx_agg_ring_size = 0;
3165         bp->rx_agg_nr_pages = 0;
3166
3167         if (bp->flags & BNXT_FLAG_TPA)
3168                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3169
3170         bp->flags &= ~BNXT_FLAG_JUMBO;
3171         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3172                 u32 jumbo_factor;
3173
3174                 bp->flags |= BNXT_FLAG_JUMBO;
3175                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3176                 if (jumbo_factor > agg_factor)
3177                         agg_factor = jumbo_factor;
3178         }
3179         agg_ring_size = ring_size * agg_factor;
3180
3181         if (agg_ring_size) {
3182                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3183                                                         RX_DESC_CNT);
3184                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3185                         u32 tmp = agg_ring_size;
3186
3187                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3188                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3189                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3190                                     tmp, agg_ring_size);
3191                 }
3192                 bp->rx_agg_ring_size = agg_ring_size;
3193                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3194                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3195                 rx_space = rx_size + NET_SKB_PAD +
3196                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3197         }
3198
3199         bp->rx_buf_use_size = rx_size;
3200         bp->rx_buf_size = rx_space;
3201
3202         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3203         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3204
3205         ring_size = bp->tx_ring_size;
3206         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3207         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3208
3209         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
3210         bp->cp_ring_size = ring_size;
3211
3212         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3213         if (bp->cp_nr_pages > MAX_CP_PAGES) {
3214                 bp->cp_nr_pages = MAX_CP_PAGES;
3215                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3216                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3217                             ring_size, bp->cp_ring_size);
3218         }
3219         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3220         bp->cp_ring_mask = bp->cp_bit - 1;
3221 }
3222
3223 /* Changing allocation mode of RX rings.
3224  * TODO: Update when extending xdp_rxq_info to support allocation modes.
3225  */
3226 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3227 {
3228         if (page_mode) {
3229                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3230                         return -EOPNOTSUPP;
3231                 bp->dev->max_mtu =
3232                         min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3233                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3234                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3235                 bp->rx_dir = DMA_BIDIRECTIONAL;
3236                 bp->rx_skb_func = bnxt_rx_page_skb;
3237                 /* Disable LRO or GRO_HW */
3238                 netdev_update_features(bp->dev);
3239         } else {
3240                 bp->dev->max_mtu = bp->max_mtu;
3241                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3242                 bp->rx_dir = DMA_FROM_DEVICE;
3243                 bp->rx_skb_func = bnxt_rx_skb;
3244         }
3245         return 0;
3246 }
3247
3248 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3249 {
3250         int i;
3251         struct bnxt_vnic_info *vnic;
3252         struct pci_dev *pdev = bp->pdev;
3253
3254         if (!bp->vnic_info)
3255                 return;
3256
3257         for (i = 0; i < bp->nr_vnics; i++) {
3258                 vnic = &bp->vnic_info[i];
3259
3260                 kfree(vnic->fw_grp_ids);
3261                 vnic->fw_grp_ids = NULL;
3262
3263                 kfree(vnic->uc_list);
3264                 vnic->uc_list = NULL;
3265
3266                 if (vnic->mc_list) {
3267                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3268                                           vnic->mc_list, vnic->mc_list_mapping);
3269                         vnic->mc_list = NULL;
3270                 }
3271
3272                 if (vnic->rss_table) {
3273                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
3274                                           vnic->rss_table,
3275                                           vnic->rss_table_dma_addr);
3276                         vnic->rss_table = NULL;
3277                 }
3278
3279                 vnic->rss_hash_key = NULL;
3280                 vnic->flags = 0;
3281         }
3282 }
3283
3284 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3285 {
3286         int i, rc = 0, size;
3287         struct bnxt_vnic_info *vnic;
3288         struct pci_dev *pdev = bp->pdev;
3289         int max_rings;
3290
3291         for (i = 0; i < bp->nr_vnics; i++) {
3292                 vnic = &bp->vnic_info[i];
3293
3294                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3295                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3296
3297                         if (mem_size > 0) {
3298                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3299                                 if (!vnic->uc_list) {
3300                                         rc = -ENOMEM;
3301                                         goto out;
3302                                 }
3303                         }
3304                 }
3305
3306                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3307                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3308                         vnic->mc_list =
3309                                 dma_alloc_coherent(&pdev->dev,
3310                                                    vnic->mc_list_size,
3311                                                    &vnic->mc_list_mapping,
3312                                                    GFP_KERNEL);
3313                         if (!vnic->mc_list) {
3314                                 rc = -ENOMEM;
3315                                 goto out;
3316                         }
3317                 }
3318
3319                 if (bp->flags & BNXT_FLAG_CHIP_P5)
3320                         goto vnic_skip_grps;
3321
3322                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3323                         max_rings = bp->rx_nr_rings;
3324                 else
3325                         max_rings = 1;
3326
3327                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3328                 if (!vnic->fw_grp_ids) {
3329                         rc = -ENOMEM;
3330                         goto out;
3331                 }
3332 vnic_skip_grps:
3333                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3334                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3335                         continue;
3336
3337                 /* Allocate rss table and hash key */
3338                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3339                                                      &vnic->rss_table_dma_addr,
3340                                                      GFP_KERNEL);
3341                 if (!vnic->rss_table) {
3342                         rc = -ENOMEM;
3343                         goto out;
3344                 }
3345
3346                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3347
3348                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3349                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3350         }
3351         return 0;
3352
3353 out:
3354         return rc;
3355 }
3356
3357 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3358 {
3359         struct pci_dev *pdev = bp->pdev;
3360
3361         if (bp->hwrm_cmd_resp_addr) {
3362                 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3363                                   bp->hwrm_cmd_resp_dma_addr);
3364                 bp->hwrm_cmd_resp_addr = NULL;
3365         }
3366
3367         if (bp->hwrm_cmd_kong_resp_addr) {
3368                 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3369                                   bp->hwrm_cmd_kong_resp_addr,
3370                                   bp->hwrm_cmd_kong_resp_dma_addr);
3371                 bp->hwrm_cmd_kong_resp_addr = NULL;
3372         }
3373 }
3374
3375 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3376 {
3377         struct pci_dev *pdev = bp->pdev;
3378
3379         bp->hwrm_cmd_kong_resp_addr =
3380                 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3381                                    &bp->hwrm_cmd_kong_resp_dma_addr,
3382                                    GFP_KERNEL);
3383         if (!bp->hwrm_cmd_kong_resp_addr)
3384                 return -ENOMEM;
3385
3386         return 0;
3387 }
3388
3389 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3390 {
3391         struct pci_dev *pdev = bp->pdev;
3392
3393         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3394                                                    &bp->hwrm_cmd_resp_dma_addr,
3395                                                    GFP_KERNEL);
3396         if (!bp->hwrm_cmd_resp_addr)
3397                 return -ENOMEM;
3398
3399         return 0;
3400 }
3401
3402 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3403 {
3404         if (bp->hwrm_short_cmd_req_addr) {
3405                 struct pci_dev *pdev = bp->pdev;
3406
3407                 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3408                                   bp->hwrm_short_cmd_req_addr,
3409                                   bp->hwrm_short_cmd_req_dma_addr);
3410                 bp->hwrm_short_cmd_req_addr = NULL;
3411         }
3412 }
3413
3414 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3415 {
3416         struct pci_dev *pdev = bp->pdev;
3417
3418         bp->hwrm_short_cmd_req_addr =
3419                 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3420                                    &bp->hwrm_short_cmd_req_dma_addr,
3421                                    GFP_KERNEL);
3422         if (!bp->hwrm_short_cmd_req_addr)
3423                 return -ENOMEM;
3424
3425         return 0;
3426 }
3427
3428 static void bnxt_free_port_stats(struct bnxt *bp)
3429 {
3430         struct pci_dev *pdev = bp->pdev;
3431
3432         bp->flags &= ~BNXT_FLAG_PORT_STATS;
3433         bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3434
3435         if (bp->hw_rx_port_stats) {
3436                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3437                                   bp->hw_rx_port_stats,
3438                                   bp->hw_rx_port_stats_map);
3439                 bp->hw_rx_port_stats = NULL;
3440         }
3441
3442         if (bp->hw_tx_port_stats_ext) {
3443                 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext),
3444                                   bp->hw_tx_port_stats_ext,
3445                                   bp->hw_tx_port_stats_ext_map);
3446                 bp->hw_tx_port_stats_ext = NULL;
3447         }
3448
3449         if (bp->hw_rx_port_stats_ext) {
3450                 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3451                                   bp->hw_rx_port_stats_ext,
3452                                   bp->hw_rx_port_stats_ext_map);
3453                 bp->hw_rx_port_stats_ext = NULL;
3454         }
3455
3456         if (bp->hw_pcie_stats) {
3457                 dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats),
3458                                   bp->hw_pcie_stats, bp->hw_pcie_stats_map);
3459                 bp->hw_pcie_stats = NULL;
3460         }
3461 }
3462
3463 static void bnxt_free_ring_stats(struct bnxt *bp)
3464 {
3465         struct pci_dev *pdev = bp->pdev;
3466         int size, i;
3467
3468         if (!bp->bnapi)
3469                 return;
3470
3471         size = sizeof(struct ctx_hw_stats);
3472
3473         for (i = 0; i < bp->cp_nr_rings; i++) {
3474                 struct bnxt_napi *bnapi = bp->bnapi[i];
3475                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3476
3477                 if (cpr->hw_stats) {
3478                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3479                                           cpr->hw_stats_map);
3480                         cpr->hw_stats = NULL;
3481                 }
3482         }
3483 }
3484
3485 static int bnxt_alloc_stats(struct bnxt *bp)
3486 {
3487         u32 size, i;
3488         struct pci_dev *pdev = bp->pdev;
3489
3490         size = sizeof(struct ctx_hw_stats);
3491
3492         for (i = 0; i < bp->cp_nr_rings; i++) {
3493                 struct bnxt_napi *bnapi = bp->bnapi[i];
3494                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3495
3496                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3497                                                    &cpr->hw_stats_map,
3498                                                    GFP_KERNEL);
3499                 if (!cpr->hw_stats)
3500                         return -ENOMEM;
3501
3502                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3503         }
3504
3505         if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
3506                 return 0;
3507
3508         if (bp->hw_rx_port_stats)
3509                 goto alloc_ext_stats;
3510
3511         bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3512                                  sizeof(struct tx_port_stats) + 1024;
3513
3514         bp->hw_rx_port_stats =
3515                 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3516                                    &bp->hw_rx_port_stats_map,
3517                                    GFP_KERNEL);
3518         if (!bp->hw_rx_port_stats)
3519                 return -ENOMEM;
3520
3521         bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512;
3522         bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3523                                    sizeof(struct rx_port_stats) + 512;
3524         bp->flags |= BNXT_FLAG_PORT_STATS;
3525
3526 alloc_ext_stats:
3527         /* Display extended statistics only if FW supports it */
3528         if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
3529                 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
3530                         return 0;
3531
3532         if (bp->hw_rx_port_stats_ext)
3533                 goto alloc_tx_ext_stats;
3534
3535         bp->hw_rx_port_stats_ext =
3536                 dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3537                                    &bp->hw_rx_port_stats_ext_map, GFP_KERNEL);
3538         if (!bp->hw_rx_port_stats_ext)
3539                 return 0;
3540
3541 alloc_tx_ext_stats:
3542         if (bp->hw_tx_port_stats_ext)
3543                 goto alloc_pcie_stats;
3544
3545         if (bp->hwrm_spec_code >= 0x10902 ||
3546             (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
3547                 bp->hw_tx_port_stats_ext =
3548                         dma_alloc_coherent(&pdev->dev,
3549                                            sizeof(struct tx_port_stats_ext),
3550                                            &bp->hw_tx_port_stats_ext_map,
3551                                            GFP_KERNEL);
3552         }
3553         bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3554
3555 alloc_pcie_stats:
3556         if (bp->hw_pcie_stats ||
3557             !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
3558                 return 0;
3559
3560         bp->hw_pcie_stats =
3561                 dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats),
3562                                    &bp->hw_pcie_stats_map, GFP_KERNEL);
3563         if (!bp->hw_pcie_stats)
3564                 return 0;
3565
3566         bp->flags |= BNXT_FLAG_PCIE_STATS;
3567         return 0;
3568 }
3569
3570 static void bnxt_clear_ring_indices(struct bnxt *bp)
3571 {
3572         int i;
3573
3574         if (!bp->bnapi)
3575                 return;
3576
3577         for (i = 0; i < bp->cp_nr_rings; i++) {
3578                 struct bnxt_napi *bnapi = bp->bnapi[i];
3579                 struct bnxt_cp_ring_info *cpr;
3580                 struct bnxt_rx_ring_info *rxr;
3581                 struct bnxt_tx_ring_info *txr;
3582
3583                 if (!bnapi)
3584                         continue;
3585
3586                 cpr = &bnapi->cp_ring;
3587                 cpr->cp_raw_cons = 0;
3588
3589                 txr = bnapi->tx_ring;
3590                 if (txr) {
3591                         txr->tx_prod = 0;
3592                         txr->tx_cons = 0;
3593                 }
3594
3595                 rxr = bnapi->rx_ring;
3596                 if (rxr) {
3597                         rxr->rx_prod = 0;
3598                         rxr->rx_agg_prod = 0;
3599                         rxr->rx_sw_agg_prod = 0;
3600                         rxr->rx_next_cons = 0;
3601                 }
3602         }
3603 }
3604
3605 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3606 {
3607 #ifdef CONFIG_RFS_ACCEL
3608         int i;
3609
3610         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
3611          * safe to delete the hash table.
3612          */
3613         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3614                 struct hlist_head *head;
3615                 struct hlist_node *tmp;
3616                 struct bnxt_ntuple_filter *fltr;
3617
3618                 head = &bp->ntp_fltr_hash_tbl[i];
3619                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3620                         hlist_del(&fltr->hash);
3621                         kfree(fltr);
3622                 }
3623         }
3624         if (irq_reinit) {
3625                 kfree(bp->ntp_fltr_bmap);
3626                 bp->ntp_fltr_bmap = NULL;
3627         }
3628         bp->ntp_fltr_count = 0;
3629 #endif
3630 }
3631
3632 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3633 {
3634 #ifdef CONFIG_RFS_ACCEL
3635         int i, rc = 0;
3636
3637         if (!(bp->flags & BNXT_FLAG_RFS))
3638                 return 0;
3639
3640         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3641                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3642
3643         bp->ntp_fltr_count = 0;
3644         bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3645                                     sizeof(long),
3646                                     GFP_KERNEL);
3647
3648         if (!bp->ntp_fltr_bmap)
3649                 rc = -ENOMEM;
3650
3651         return rc;
3652 #else
3653         return 0;
3654 #endif
3655 }
3656
3657 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3658 {
3659         bnxt_free_vnic_attributes(bp);
3660         bnxt_free_tx_rings(bp);
3661         bnxt_free_rx_rings(bp);
3662         bnxt_free_cp_rings(bp);
3663         bnxt_free_ntp_fltrs(bp, irq_re_init);
3664         if (irq_re_init) {
3665                 bnxt_free_ring_stats(bp);
3666                 bnxt_free_ring_grps(bp);
3667                 bnxt_free_vnics(bp);
3668                 kfree(bp->tx_ring_map);
3669                 bp->tx_ring_map = NULL;
3670                 kfree(bp->tx_ring);
3671                 bp->tx_ring = NULL;
3672                 kfree(bp->rx_ring);
3673                 bp->rx_ring = NULL;
3674                 kfree(bp->bnapi);
3675                 bp->bnapi = NULL;
3676         } else {
3677                 bnxt_clear_ring_indices(bp);
3678         }
3679 }
3680
3681 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3682 {
3683         int i, j, rc, size, arr_size;
3684         void *bnapi;
3685
3686         if (irq_re_init) {
3687                 /* Allocate bnapi mem pointer array and mem block for
3688                  * all queues
3689                  */
3690                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3691                                 bp->cp_nr_rings);
3692                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3693                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3694                 if (!bnapi)
3695                         return -ENOMEM;
3696
3697                 bp->bnapi = bnapi;
3698                 bnapi += arr_size;
3699                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3700                         bp->bnapi[i] = bnapi;
3701                         bp->bnapi[i]->index = i;
3702                         bp->bnapi[i]->bp = bp;
3703                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
3704                                 struct bnxt_cp_ring_info *cpr =
3705                                         &bp->bnapi[i]->cp_ring;
3706
3707                                 cpr->cp_ring_struct.ring_mem.flags =
3708                                         BNXT_RMEM_RING_PTE_FLAG;
3709                         }
3710                 }
3711
3712                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3713                                       sizeof(struct bnxt_rx_ring_info),
3714                                       GFP_KERNEL);
3715                 if (!bp->rx_ring)
3716                         return -ENOMEM;
3717
3718                 for (i = 0; i < bp->rx_nr_rings; i++) {
3719                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3720
3721                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
3722                                 rxr->rx_ring_struct.ring_mem.flags =
3723                                         BNXT_RMEM_RING_PTE_FLAG;
3724                                 rxr->rx_agg_ring_struct.ring_mem.flags =
3725                                         BNXT_RMEM_RING_PTE_FLAG;
3726                         }
3727                         rxr->bnapi = bp->bnapi[i];
3728                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3729                 }
3730
3731                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3732                                       sizeof(struct bnxt_tx_ring_info),
3733                                       GFP_KERNEL);
3734                 if (!bp->tx_ring)
3735                         return -ENOMEM;
3736
3737                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3738                                           GFP_KERNEL);
3739
3740                 if (!bp->tx_ring_map)
3741                         return -ENOMEM;
3742
3743                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3744                         j = 0;
3745                 else
3746                         j = bp->rx_nr_rings;
3747
3748                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3749                         struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3750
3751                         if (bp->flags & BNXT_FLAG_CHIP_P5)
3752                                 txr->tx_ring_struct.ring_mem.flags =
3753                                         BNXT_RMEM_RING_PTE_FLAG;
3754                         txr->bnapi = bp->bnapi[j];
3755                         bp->bnapi[j]->tx_ring = txr;
3756                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3757                         if (i >= bp->tx_nr_rings_xdp) {
3758                                 txr->txq_index = i - bp->tx_nr_rings_xdp;
3759                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
3760                         } else {
3761                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3762                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3763                         }
3764                 }
3765
3766                 rc = bnxt_alloc_stats(bp);
3767                 if (rc)
3768                         goto alloc_mem_err;
3769
3770                 rc = bnxt_alloc_ntp_fltrs(bp);
3771                 if (rc)
3772                         goto alloc_mem_err;
3773
3774                 rc = bnxt_alloc_vnics(bp);
3775                 if (rc)
3776                         goto alloc_mem_err;
3777         }
3778
3779         bnxt_init_ring_struct(bp);
3780
3781         rc = bnxt_alloc_rx_rings(bp);
3782         if (rc)
3783                 goto alloc_mem_err;
3784
3785         rc = bnxt_alloc_tx_rings(bp);
3786         if (rc)
3787                 goto alloc_mem_err;
3788
3789         rc = bnxt_alloc_cp_rings(bp);
3790         if (rc)
3791                 goto alloc_mem_err;
3792
3793         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3794                                   BNXT_VNIC_UCAST_FLAG;
3795         rc = bnxt_alloc_vnic_attributes(bp);
3796         if (rc)
3797                 goto alloc_mem_err;
3798         return 0;
3799
3800 alloc_mem_err:
3801         bnxt_free_mem(bp, true);
3802         return rc;
3803 }
3804
3805 static void bnxt_disable_int(struct bnxt *bp)
3806 {
3807         int i;
3808
3809         if (!bp->bnapi)
3810                 return;
3811
3812         for (i = 0; i < bp->cp_nr_rings; i++) {
3813                 struct bnxt_napi *bnapi = bp->bnapi[i];
3814                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3815                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3816
3817                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3818                         bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
3819         }
3820 }
3821
3822 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3823 {
3824         struct bnxt_napi *bnapi = bp->bnapi[n];
3825         struct bnxt_cp_ring_info *cpr;
3826
3827         cpr = &bnapi->cp_ring;
3828         return cpr->cp_ring_struct.map_idx;
3829 }
3830
3831 static void bnxt_disable_int_sync(struct bnxt *bp)
3832 {
3833         int i;
3834
3835         atomic_inc(&bp->intr_sem);
3836
3837         bnxt_disable_int(bp);
3838         for (i = 0; i < bp->cp_nr_rings; i++) {
3839                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3840
3841                 synchronize_irq(bp->irq_tbl[map_idx].vector);
3842         }
3843 }
3844
3845 static void bnxt_enable_int(struct bnxt *bp)
3846 {
3847         int i;
3848
3849         atomic_set(&bp->intr_sem, 0);
3850         for (i = 0; i < bp->cp_nr_rings; i++) {
3851                 struct bnxt_napi *bnapi = bp->bnapi[i];
3852                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3853
3854                 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
3855         }
3856 }
3857
3858 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3859                             u16 cmpl_ring, u16 target_id)
3860 {
3861         struct input *req = request;
3862
3863         req->req_type = cpu_to_le16(req_type);
3864         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3865         req->target_id = cpu_to_le16(target_id);
3866         if (bnxt_kong_hwrm_message(bp, req))
3867                 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
3868         else
3869                 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3870 }
3871
3872 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3873                                  int timeout, bool silent)
3874 {
3875         int i, intr_process, rc, tmo_count;
3876         struct input *req = msg;
3877         u32 *data = msg;
3878         __le32 *resp_len;
3879         u8 *valid;
3880         u16 cp_ring_id, len = 0;
3881         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3882         u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3883         struct hwrm_short_input short_input = {0};
3884         u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
3885         u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr;
3886         u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
3887         u16 dst = BNXT_HWRM_CHNL_CHIMP;
3888
3889         if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3890                 if (msg_len > bp->hwrm_max_ext_req_len ||
3891                     !bp->hwrm_short_cmd_req_addr)
3892                         return -EINVAL;
3893         }
3894
3895         if (bnxt_hwrm_kong_chnl(bp, req)) {
3896                 dst = BNXT_HWRM_CHNL_KONG;
3897                 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
3898                 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
3899                 resp = bp->hwrm_cmd_kong_resp_addr;
3900                 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr;
3901         }
3902
3903         memset(resp, 0, PAGE_SIZE);
3904         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3905         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3906
3907         req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
3908         /* currently supports only one outstanding message */
3909         if (intr_process)
3910                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3911
3912         if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
3913             msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3914                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3915                 u16 max_msg_len;
3916
3917                 /* Set boundary for maximum extended request length for short
3918                  * cmd format. If passed up from device use the max supported
3919                  * internal req length.
3920                  */
3921                 max_msg_len = bp->hwrm_max_ext_req_len;
3922
3923                 memcpy(short_cmd_req, req, msg_len);
3924                 if (msg_len < max_msg_len)
3925                         memset(short_cmd_req + msg_len, 0,
3926                                max_msg_len - msg_len);
3927
3928                 short_input.req_type = req->req_type;
3929                 short_input.signature =
3930                                 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3931                 short_input.size = cpu_to_le16(msg_len);
3932                 short_input.req_addr =
3933                         cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3934
3935                 data = (u32 *)&short_input;
3936                 msg_len = sizeof(short_input);
3937
3938                 /* Sync memory write before updating doorbell */
3939                 wmb();
3940
3941                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3942         }
3943
3944         /* Write request msg to hwrm channel */
3945         __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
3946
3947         for (i = msg_len; i < max_req_len; i += 4)
3948                 writel(0, bp->bar0 + bar_offset + i);
3949
3950         /* Ring channel doorbell */
3951         writel(1, bp->bar0 + doorbell_offset);
3952
3953         if (!timeout)
3954                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3955         /* convert timeout to usec */
3956         timeout *= 1000;
3957
3958         i = 0;
3959         /* Short timeout for the first few iterations:
3960          * number of loops = number of loops for short timeout +
3961          * number of loops for standard timeout.
3962          */
3963         tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3964         timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3965         tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3966         resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET);
3967
3968         if (intr_process) {
3969                 u16 seq_id = bp->hwrm_intr_seq_id;
3970
3971                 /* Wait until hwrm response cmpl interrupt is processed */
3972                 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
3973                        i++ < tmo_count) {
3974                         /* on first few passes, just barely sleep */
3975                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3976                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3977                                              HWRM_SHORT_MAX_TIMEOUT);
3978                         else
3979                                 usleep_range(HWRM_MIN_TIMEOUT,
3980                                              HWRM_MAX_TIMEOUT);
3981                 }
3982
3983                 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
3984                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3985                                    le16_to_cpu(req->req_type));
3986                         return -1;
3987                 }
3988                 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3989                       HWRM_RESP_LEN_SFT;
3990                 valid = resp_addr + len - 1;
3991         } else {
3992                 int j;
3993
3994                 /* Check if response len is updated */
3995                 for (i = 0; i < tmo_count; i++) {
3996                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3997                               HWRM_RESP_LEN_SFT;
3998                         if (len)
3999                                 break;
4000                         /* on first few passes, just barely sleep */
4001                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
4002                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
4003                                              HWRM_SHORT_MAX_TIMEOUT);
4004                         else
4005                                 usleep_range(HWRM_MIN_TIMEOUT,
4006                                              HWRM_MAX_TIMEOUT);
4007                 }
4008
4009                 if (i >= tmo_count) {
4010                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
4011                                    HWRM_TOTAL_TIMEOUT(i),
4012                                    le16_to_cpu(req->req_type),
4013                                    le16_to_cpu(req->seq_id), len);
4014                         return -1;
4015                 }
4016
4017                 /* Last byte of resp contains valid bit */
4018                 valid = resp_addr + len - 1;
4019                 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
4020                         /* make sure we read from updated DMA memory */
4021                         dma_rmb();
4022                         if (*valid)
4023                                 break;
4024                         usleep_range(1, 5);
4025                 }
4026
4027                 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
4028                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
4029                                    HWRM_TOTAL_TIMEOUT(i),
4030                                    le16_to_cpu(req->req_type),
4031                                    le16_to_cpu(req->seq_id), len, *valid);
4032                         return -1;
4033                 }
4034         }
4035
4036         /* Zero valid bit for compatibility.  Valid bit in an older spec
4037          * may become a new field in a newer spec.  We must make sure that
4038          * a new field not implemented by old spec will read zero.
4039          */
4040         *valid = 0;
4041         rc = le16_to_cpu(resp->error_code);
4042         if (rc && !silent)
4043                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
4044                            le16_to_cpu(resp->req_type),
4045                            le16_to_cpu(resp->seq_id), rc);
4046         return rc;
4047 }
4048
4049 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4050 {
4051         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
4052 }
4053
4054 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4055                               int timeout)
4056 {
4057         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4058 }
4059
4060 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4061 {
4062         int rc;
4063
4064         mutex_lock(&bp->hwrm_cmd_lock);
4065         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
4066         mutex_unlock(&bp->hwrm_cmd_lock);
4067         return rc;
4068 }
4069
4070 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4071                              int timeout)
4072 {
4073         int rc;
4074
4075         mutex_lock(&bp->hwrm_cmd_lock);
4076         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4077         mutex_unlock(&bp->hwrm_cmd_lock);
4078         return rc;
4079 }
4080
4081 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
4082                                      int bmap_size)
4083 {
4084         struct hwrm_func_drv_rgtr_input req = {0};
4085         DECLARE_BITMAP(async_events_bmap, 256);
4086         u32 *events = (u32 *)async_events_bmap;
4087         int i;
4088
4089         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4090
4091         req.enables =
4092                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4093
4094         memset(async_events_bmap, 0, sizeof(async_events_bmap));
4095         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
4096                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4097
4098         if (bmap && bmap_size) {
4099                 for (i = 0; i < bmap_size; i++) {
4100                         if (test_bit(i, bmap))
4101                                 __set_bit(i, async_events_bmap);
4102                 }
4103         }
4104
4105         for (i = 0; i < 8; i++)
4106                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4107
4108         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4109 }
4110
4111 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
4112 {
4113         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4114         struct hwrm_func_drv_rgtr_input req = {0};
4115         int rc;
4116
4117         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4118
4119         req.enables =
4120                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4121                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
4122
4123         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4124         req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
4125         req.ver_maj_8b = DRV_VER_MAJ;
4126         req.ver_min_8b = DRV_VER_MIN;
4127         req.ver_upd_8b = DRV_VER_UPD;
4128         req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4129         req.ver_min = cpu_to_le16(DRV_VER_MIN);
4130         req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4131
4132         if (BNXT_PF(bp)) {
4133                 u32 data[8];
4134                 int i;
4135
4136                 memset(data, 0, sizeof(data));
4137                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4138                         u16 cmd = bnxt_vf_req_snif[i];
4139                         unsigned int bit, idx;
4140
4141                         idx = cmd / 32;
4142                         bit = cmd % 32;
4143                         data[idx] |= 1 << bit;
4144                 }
4145
4146                 for (i = 0; i < 8; i++)
4147                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4148
4149                 req.enables |=
4150                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4151         }
4152
4153         if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4154                 req.flags |= cpu_to_le32(
4155                         FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4156
4157         mutex_lock(&bp->hwrm_cmd_lock);
4158         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4159         if (rc)
4160                 rc = -EIO;
4161         else if (resp->flags &
4162                  cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4163                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4164         mutex_unlock(&bp->hwrm_cmd_lock);
4165         return rc;
4166 }
4167
4168 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4169 {
4170         struct hwrm_func_drv_unrgtr_input req = {0};
4171
4172         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4173         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4174 }
4175
4176 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4177 {
4178         u32 rc = 0;
4179         struct hwrm_tunnel_dst_port_free_input req = {0};
4180
4181         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4182         req.tunnel_type = tunnel_type;
4183
4184         switch (tunnel_type) {
4185         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4186                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
4187                 break;
4188         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4189                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
4190                 break;
4191         default:
4192                 break;
4193         }
4194
4195         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4196         if (rc)
4197                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4198                            rc);
4199         return rc;
4200 }
4201
4202 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4203                                            u8 tunnel_type)
4204 {
4205         u32 rc = 0;
4206         struct hwrm_tunnel_dst_port_alloc_input req = {0};
4207         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4208
4209         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4210
4211         req.tunnel_type = tunnel_type;
4212         req.tunnel_dst_port_val = port;
4213
4214         mutex_lock(&bp->hwrm_cmd_lock);
4215         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4216         if (rc) {
4217                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4218                            rc);
4219                 goto err_out;
4220         }
4221
4222         switch (tunnel_type) {
4223         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4224                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
4225                 break;
4226         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4227                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
4228                 break;
4229         default:
4230                 break;
4231         }
4232
4233 err_out:
4234         mutex_unlock(&bp->hwrm_cmd_lock);
4235         return rc;
4236 }
4237
4238 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4239 {
4240         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
4241         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4242
4243         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
4244         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4245
4246         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4247         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4248         req.mask = cpu_to_le32(vnic->rx_mask);
4249         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4250 }
4251
4252 #ifdef CONFIG_RFS_ACCEL
4253 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4254                                             struct bnxt_ntuple_filter *fltr)
4255 {
4256         struct hwrm_cfa_ntuple_filter_free_input req = {0};
4257
4258         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
4259         req.ntuple_filter_id = fltr->filter_id;
4260         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4261 }
4262
4263 #define BNXT_NTP_FLTR_FLAGS                                     \
4264         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
4265          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
4266          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
4267          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
4268          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
4269          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
4270          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
4271          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
4272          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
4273          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
4274          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
4275          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
4276          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
4277          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4278
4279 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
4280                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4281
4282 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4283                                              struct bnxt_ntuple_filter *fltr)
4284 {
4285         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4286         struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4287         struct flow_keys *keys = &fltr->fkeys;
4288         struct bnxt_vnic_info *vnic;
4289         u32 dst_ena = 0;
4290         int rc = 0;
4291
4292         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
4293         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4294
4295         if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX) {
4296                 dst_ena = CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX;
4297                 req.rfs_ring_tbl_idx = cpu_to_le16(fltr->rxq);
4298                 vnic = &bp->vnic_info[0];
4299         } else {
4300                 vnic = &bp->vnic_info[fltr->rxq + 1];
4301         }
4302         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
4303         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS | dst_ena);
4304
4305         req.ethertype = htons(ETH_P_IP);
4306         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4307         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4308         req.ip_protocol = keys->basic.ip_proto;
4309
4310         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4311                 int i;
4312
4313                 req.ethertype = htons(ETH_P_IPV6);
4314                 req.ip_addr_type =
4315                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4316                 *(struct in6_addr *)&req.src_ipaddr[0] =
4317                         keys->addrs.v6addrs.src;
4318                 *(struct in6_addr *)&req.dst_ipaddr[0] =
4319                         keys->addrs.v6addrs.dst;
4320                 for (i = 0; i < 4; i++) {
4321                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4322                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4323                 }
4324         } else {
4325                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4326                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4327                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4328                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4329         }
4330         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4331                 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4332                 req.tunnel_type =
4333                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4334         }
4335
4336         req.src_port = keys->ports.src;
4337         req.src_port_mask = cpu_to_be16(0xffff);
4338         req.dst_port = keys->ports.dst;
4339         req.dst_port_mask = cpu_to_be16(0xffff);
4340
4341         mutex_lock(&bp->hwrm_cmd_lock);
4342         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4343         if (!rc) {
4344                 resp = bnxt_get_hwrm_resp_addr(bp, &req);
4345                 fltr->filter_id = resp->ntuple_filter_id;
4346         }
4347         mutex_unlock(&bp->hwrm_cmd_lock);
4348         return rc;
4349 }
4350 #endif
4351
4352 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4353                                      u8 *mac_addr)
4354 {
4355         u32 rc = 0;
4356         struct hwrm_cfa_l2_filter_alloc_input req = {0};
4357         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4358
4359         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
4360         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
4361         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
4362                 req.flags |=
4363                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
4364         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
4365         req.enables =
4366                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
4367                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
4368                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
4369         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
4370         req.l2_addr_mask[0] = 0xff;
4371         req.l2_addr_mask[1] = 0xff;
4372         req.l2_addr_mask[2] = 0xff;
4373         req.l2_addr_mask[3] = 0xff;
4374         req.l2_addr_mask[4] = 0xff;
4375         req.l2_addr_mask[5] = 0xff;
4376
4377         mutex_lock(&bp->hwrm_cmd_lock);
4378         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4379         if (!rc)
4380                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
4381                                                         resp->l2_filter_id;
4382         mutex_unlock(&bp->hwrm_cmd_lock);
4383         return rc;
4384 }
4385
4386 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
4387 {
4388         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
4389         int rc = 0;
4390
4391         /* Any associated ntuple filters will also be cleared by firmware. */
4392         mutex_lock(&bp->hwrm_cmd_lock);
4393         for (i = 0; i < num_of_vnics; i++) {
4394                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4395
4396                 for (j = 0; j < vnic->uc_filter_count; j++) {
4397                         struct hwrm_cfa_l2_filter_free_input req = {0};
4398
4399                         bnxt_hwrm_cmd_hdr_init(bp, &req,
4400                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
4401
4402                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
4403
4404                         rc = _hwrm_send_message(bp, &req, sizeof(req),
4405                                                 HWRM_CMD_TIMEOUT);
4406                 }
4407                 vnic->uc_filter_count = 0;
4408         }
4409         mutex_unlock(&bp->hwrm_cmd_lock);
4410
4411         return rc;
4412 }
4413
4414 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
4415 {
4416         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4417         struct hwrm_vnic_tpa_cfg_input req = {0};
4418
4419         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4420                 return 0;
4421
4422         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
4423
4424         if (tpa_flags) {
4425                 u16 mss = bp->dev->mtu - 40;
4426                 u32 nsegs, n, segs = 0, flags;
4427
4428                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4429                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4430                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4431                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4432                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4433                 if (tpa_flags & BNXT_FLAG_GRO)
4434                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4435
4436                 req.flags = cpu_to_le32(flags);
4437
4438                 req.enables =
4439                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
4440                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4441                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
4442
4443                 /* Number of segs are log2 units, and first packet is not
4444                  * included as part of this units.
4445                  */
4446                 if (mss <= BNXT_RX_PAGE_SIZE) {
4447                         n = BNXT_RX_PAGE_SIZE / mss;
4448                         nsegs = (MAX_SKB_FRAGS - 1) * n;
4449                 } else {
4450                         n = mss / BNXT_RX_PAGE_SIZE;
4451                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
4452                                 n++;
4453                         nsegs = (MAX_SKB_FRAGS - n) / n;
4454                 }
4455
4456                 segs = ilog2(nsegs);
4457                 req.max_agg_segs = cpu_to_le16(segs);
4458                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
4459
4460                 req.min_agg_len = cpu_to_le32(512);
4461         }
4462         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4463
4464         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4465 }
4466
4467 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
4468 {
4469         struct bnxt_ring_grp_info *grp_info;
4470
4471         grp_info = &bp->grp_info[ring->grp_idx];
4472         return grp_info->cp_fw_ring_id;
4473 }
4474
4475 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
4476 {
4477         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4478                 struct bnxt_napi *bnapi = rxr->bnapi;
4479                 struct bnxt_cp_ring_info *cpr;
4480
4481                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
4482                 return cpr->cp_ring_struct.fw_ring_id;
4483         } else {
4484                 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
4485         }
4486 }
4487
4488 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
4489 {
4490         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4491                 struct bnxt_napi *bnapi = txr->bnapi;
4492                 struct bnxt_cp_ring_info *cpr;
4493
4494                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
4495                 return cpr->cp_ring_struct.fw_ring_id;
4496         } else {
4497                 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
4498         }
4499 }
4500
4501 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4502 {
4503         u32 i, j, max_rings;
4504         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4505         struct hwrm_vnic_rss_cfg_input req = {0};
4506
4507         if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
4508             vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4509                 return 0;
4510
4511         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4512         if (set_rss) {
4513                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4514                 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4515                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4516                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4517                                 max_rings = bp->rx_nr_rings - 1;
4518                         else
4519                                 max_rings = bp->rx_nr_rings;
4520                 } else {
4521                         max_rings = 1;
4522                 }
4523
4524                 /* Fill the RSS indirection table with ring group ids */
4525                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4526                         if (j == max_rings)
4527                                 j = 0;
4528                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4529                 }
4530
4531                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4532                 req.hash_key_tbl_addr =
4533                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
4534         }
4535         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4536         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4537 }
4538
4539 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
4540 {
4541         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4542         u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings;
4543         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4544         struct hwrm_vnic_rss_cfg_input req = {0};
4545
4546         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4547         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4548         if (!set_rss) {
4549                 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4550                 return 0;
4551         }
4552         req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4553         req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4554         req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4555         req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
4556         nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
4557         for (i = 0, k = 0; i < nr_ctxs; i++) {
4558                 __le16 *ring_tbl = vnic->rss_table;
4559                 int rc;
4560
4561                 req.ring_table_pair_index = i;
4562                 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
4563                 for (j = 0; j < 64; j++) {
4564                         u16 ring_id;
4565
4566                         ring_id = rxr->rx_ring_struct.fw_ring_id;
4567                         *ring_tbl++ = cpu_to_le16(ring_id);
4568                         ring_id = bnxt_cp_ring_for_rx(bp, rxr);
4569                         *ring_tbl++ = cpu_to_le16(ring_id);
4570                         rxr++;
4571                         k++;
4572                         if (k == max_rings) {
4573                                 k = 0;
4574                                 rxr = &bp->rx_ring[0];
4575                         }
4576                 }
4577                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4578                 if (rc)
4579                         return -EIO;
4580         }
4581         return 0;
4582 }
4583
4584 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4585 {
4586         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4587         struct hwrm_vnic_plcmodes_cfg_input req = {0};
4588
4589         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4590         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4591                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4592                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4593         req.enables =
4594                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4595                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4596         /* thresholds not implemented in firmware yet */
4597         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4598         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4599         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4600         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4601 }
4602
4603 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4604                                         u16 ctx_idx)
4605 {
4606         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4607
4608         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4609         req.rss_cos_lb_ctx_id =
4610                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4611
4612         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4613         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4614 }
4615
4616 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4617 {
4618         int i, j;
4619
4620         for (i = 0; i < bp->nr_vnics; i++) {
4621                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4622
4623                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4624                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4625                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4626                 }
4627         }
4628         bp->rsscos_nr_ctxs = 0;
4629 }
4630
4631 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4632 {
4633         int rc;
4634         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4635         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4636                                                 bp->hwrm_cmd_resp_addr;
4637
4638         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4639                                -1);
4640
4641         mutex_lock(&bp->hwrm_cmd_lock);
4642         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4643         if (!rc)
4644                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4645                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
4646         mutex_unlock(&bp->hwrm_cmd_lock);
4647
4648         return rc;
4649 }
4650
4651 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4652 {
4653         if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4654                 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4655         return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4656 }
4657
4658 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4659 {
4660         unsigned int ring = 0, grp_idx;
4661         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4662         struct hwrm_vnic_cfg_input req = {0};
4663         u16 def_vlan = 0;
4664
4665         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4666
4667         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4668                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4669
4670                 req.default_rx_ring_id =
4671                         cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
4672                 req.default_cmpl_ring_id =
4673                         cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
4674                 req.enables =
4675                         cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
4676                                     VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
4677                 goto vnic_mru;
4678         }
4679         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4680         /* Only RSS support for now TBD: COS & LB */
4681         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4682                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4683                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4684                                            VNIC_CFG_REQ_ENABLES_MRU);
4685         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4686                 req.rss_rule =
4687                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4688                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4689                                            VNIC_CFG_REQ_ENABLES_MRU);
4690                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4691         } else {
4692                 req.rss_rule = cpu_to_le16(0xffff);
4693         }
4694
4695         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4696             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4697                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4698                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4699         } else {
4700                 req.cos_rule = cpu_to_le16(0xffff);
4701         }
4702
4703         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4704                 ring = 0;
4705         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4706                 ring = vnic_id - 1;
4707         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4708                 ring = bp->rx_nr_rings - 1;
4709
4710         grp_idx = bp->rx_ring[ring].bnapi->index;
4711         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4712         req.lb_rule = cpu_to_le16(0xffff);
4713 vnic_mru:
4714         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4715                               VLAN_HLEN);
4716
4717         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4718 #ifdef CONFIG_BNXT_SRIOV
4719         if (BNXT_VF(bp))
4720                 def_vlan = bp->vf.vlan;
4721 #endif
4722         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4723                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4724         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4725                 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4726
4727         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4728 }
4729
4730 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4731 {
4732         u32 rc = 0;
4733
4734         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4735                 struct hwrm_vnic_free_input req = {0};
4736
4737                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4738                 req.vnic_id =
4739                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4740
4741                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4742                 if (rc)
4743                         return rc;
4744                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4745         }
4746         return rc;
4747 }
4748
4749 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4750 {
4751         u16 i;
4752
4753         for (i = 0; i < bp->nr_vnics; i++)
4754                 bnxt_hwrm_vnic_free_one(bp, i);
4755 }
4756
4757 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4758                                 unsigned int start_rx_ring_idx,
4759                                 unsigned int nr_rings)
4760 {
4761         int rc = 0;
4762         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4763         struct hwrm_vnic_alloc_input req = {0};
4764         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4765         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4766
4767         if (bp->flags & BNXT_FLAG_CHIP_P5)
4768                 goto vnic_no_ring_grps;
4769
4770         /* map ring groups to this vnic */
4771         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4772                 grp_idx = bp->rx_ring[i].bnapi->index;
4773                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4774                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4775                                    j, nr_rings);
4776                         break;
4777                 }
4778                 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
4779         }
4780
4781 vnic_no_ring_grps:
4782         for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
4783                 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
4784         if (vnic_id == 0)
4785                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4786
4787         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4788
4789         mutex_lock(&bp->hwrm_cmd_lock);
4790         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4791         if (!rc)
4792                 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
4793         mutex_unlock(&bp->hwrm_cmd_lock);
4794         return rc;
4795 }
4796
4797 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4798 {
4799         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4800         struct hwrm_vnic_qcaps_input req = {0};
4801         int rc;
4802
4803         if (bp->hwrm_spec_code < 0x10600)
4804                 return 0;
4805
4806         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4807         mutex_lock(&bp->hwrm_cmd_lock);
4808         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4809         if (!rc) {
4810                 u32 flags = le32_to_cpu(resp->flags);
4811
4812                 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
4813                     (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4814                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4815                 if (flags &
4816                     VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4817                         bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4818         }
4819         mutex_unlock(&bp->hwrm_cmd_lock);
4820         return rc;
4821 }
4822
4823 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4824 {
4825         u16 i;
4826         u32 rc = 0;
4827
4828         if (bp->flags & BNXT_FLAG_CHIP_P5)
4829                 return 0;
4830
4831         mutex_lock(&bp->hwrm_cmd_lock);
4832         for (i = 0; i < bp->rx_nr_rings; i++) {
4833                 struct hwrm_ring_grp_alloc_input req = {0};
4834                 struct hwrm_ring_grp_alloc_output *resp =
4835                                         bp->hwrm_cmd_resp_addr;
4836                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4837
4838                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4839
4840                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4841                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4842                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4843                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4844
4845                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4846                                         HWRM_CMD_TIMEOUT);
4847                 if (rc)
4848                         break;
4849
4850                 bp->grp_info[grp_idx].fw_grp_id =
4851                         le32_to_cpu(resp->ring_group_id);
4852         }
4853         mutex_unlock(&bp->hwrm_cmd_lock);
4854         return rc;
4855 }
4856
4857 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4858 {
4859         u16 i;
4860         u32 rc = 0;
4861         struct hwrm_ring_grp_free_input req = {0};
4862
4863         if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
4864                 return 0;
4865
4866         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4867
4868         mutex_lock(&bp->hwrm_cmd_lock);
4869         for (i = 0; i < bp->cp_nr_rings; i++) {
4870                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4871                         continue;
4872                 req.ring_group_id =
4873                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
4874
4875                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4876                                         HWRM_CMD_TIMEOUT);
4877                 if (rc)
4878                         break;
4879                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4880         }
4881         mutex_unlock(&bp->hwrm_cmd_lock);
4882         return rc;
4883 }
4884
4885 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4886                                     struct bnxt_ring_struct *ring,
4887                                     u32 ring_type, u32 map_index)
4888 {
4889         int rc = 0, err = 0;
4890         struct hwrm_ring_alloc_input req = {0};
4891         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4892         struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
4893         struct bnxt_ring_grp_info *grp_info;
4894         u16 ring_id;
4895
4896         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4897
4898         req.enables = 0;
4899         if (rmem->nr_pages > 1) {
4900                 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
4901                 /* Page size is in log2 units */
4902                 req.page_size = BNXT_PAGE_SHIFT;
4903                 req.page_tbl_depth = 1;
4904         } else {
4905                 req.page_tbl_addr =  cpu_to_le64(rmem->dma_arr[0]);
4906         }
4907         req.fbo = 0;
4908         /* Association of ring index with doorbell index and MSIX number */
4909         req.logical_id = cpu_to_le16(map_index);
4910
4911         switch (ring_type) {
4912         case HWRM_RING_ALLOC_TX: {
4913                 struct bnxt_tx_ring_info *txr;
4914
4915                 txr = container_of(ring, struct bnxt_tx_ring_info,
4916                                    tx_ring_struct);
4917                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4918                 /* Association of transmit ring with completion ring */
4919                 grp_info = &bp->grp_info[ring->grp_idx];
4920                 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
4921                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4922                 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4923                 req.queue_id = cpu_to_le16(ring->queue_id);
4924                 break;
4925         }
4926         case HWRM_RING_ALLOC_RX:
4927                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4928                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4929                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4930                         u16 flags = 0;
4931
4932                         /* Association of rx ring with stats context */
4933                         grp_info = &bp->grp_info[ring->grp_idx];
4934                         req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
4935                         req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4936                         req.enables |= cpu_to_le32(
4937                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4938                         if (NET_IP_ALIGN == 2)
4939                                 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
4940                         req.flags = cpu_to_le16(flags);
4941                 }
4942                 break;
4943         case HWRM_RING_ALLOC_AGG:
4944                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4945                         req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
4946                         /* Association of agg ring with rx ring */
4947                         grp_info = &bp->grp_info[ring->grp_idx];
4948                         req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
4949                         req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
4950                         req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4951                         req.enables |= cpu_to_le32(
4952                                 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
4953                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4954                 } else {
4955                         req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4956                 }
4957                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4958                 break;
4959         case HWRM_RING_ALLOC_CMPL:
4960                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4961                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4962                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4963                         /* Association of cp ring with nq */
4964                         grp_info = &bp->grp_info[map_index];
4965                         req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4966                         req.cq_handle = cpu_to_le64(ring->handle);
4967                         req.enables |= cpu_to_le32(
4968                                 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
4969                 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
4970                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4971                 }
4972                 break;
4973         case HWRM_RING_ALLOC_NQ:
4974                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
4975                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4976                 if (bp->flags & BNXT_FLAG_USING_MSIX)
4977                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4978                 break;
4979         default:
4980                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4981                            ring_type);
4982                 return -1;
4983         }
4984
4985         mutex_lock(&bp->hwrm_cmd_lock);
4986         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4987         err = le16_to_cpu(resp->error_code);
4988         ring_id = le16_to_cpu(resp->ring_id);
4989         mutex_unlock(&bp->hwrm_cmd_lock);
4990
4991         if (rc || err) {
4992                 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4993                            ring_type, rc, err);
4994                 return -EIO;
4995         }
4996         ring->fw_ring_id = ring_id;
4997         return rc;
4998 }
4999
5000 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
5001 {
5002         int rc;
5003
5004         if (BNXT_PF(bp)) {
5005                 struct hwrm_func_cfg_input req = {0};
5006
5007                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5008                 req.fid = cpu_to_le16(0xffff);
5009                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5010                 req.async_event_cr = cpu_to_le16(idx);
5011                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5012         } else {
5013                 struct hwrm_func_vf_cfg_input req = {0};
5014
5015                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
5016                 req.enables =
5017                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5018                 req.async_event_cr = cpu_to_le16(idx);
5019                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5020         }
5021         return rc;
5022 }
5023
5024 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
5025                         u32 map_idx, u32 xid)
5026 {
5027         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5028                 if (BNXT_PF(bp))
5029                         db->doorbell = bp->bar1 + 0x10000;
5030                 else
5031                         db->doorbell = bp->bar1 + 0x4000;
5032                 switch (ring_type) {
5033                 case HWRM_RING_ALLOC_TX:
5034                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
5035                         break;
5036                 case HWRM_RING_ALLOC_RX:
5037                 case HWRM_RING_ALLOC_AGG:
5038                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
5039                         break;
5040                 case HWRM_RING_ALLOC_CMPL:
5041                         db->db_key64 = DBR_PATH_L2;
5042                         break;
5043                 case HWRM_RING_ALLOC_NQ:
5044                         db->db_key64 = DBR_PATH_L2;
5045                         break;
5046                 }
5047                 db->db_key64 |= (u64)xid << DBR_XID_SFT;
5048         } else {
5049                 db->doorbell = bp->bar1 + map_idx * 0x80;
5050                 switch (ring_type) {
5051                 case HWRM_RING_ALLOC_TX:
5052                         db->db_key32 = DB_KEY_TX;
5053                         break;
5054                 case HWRM_RING_ALLOC_RX:
5055                 case HWRM_RING_ALLOC_AGG:
5056                         db->db_key32 = DB_KEY_RX;
5057                         break;
5058                 case HWRM_RING_ALLOC_CMPL:
5059                         db->db_key32 = DB_KEY_CP;
5060                         break;
5061                 }
5062         }
5063 }
5064
5065 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
5066 {
5067         bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS);
5068         int i, rc = 0;
5069         u32 type;
5070
5071         if (bp->flags & BNXT_FLAG_CHIP_P5)
5072                 type = HWRM_RING_ALLOC_NQ;
5073         else
5074                 type = HWRM_RING_ALLOC_CMPL;
5075         for (i = 0; i < bp->cp_nr_rings; i++) {
5076                 struct bnxt_napi *bnapi = bp->bnapi[i];
5077                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5078                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5079                 u32 map_idx = ring->map_idx;
5080                 unsigned int vector;
5081
5082                 vector = bp->irq_tbl[map_idx].vector;
5083                 disable_irq_nosync(vector);
5084                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5085                 if (rc) {
5086                         enable_irq(vector);
5087                         goto err_out;
5088                 }
5089                 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5090                 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5091                 enable_irq(vector);
5092                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5093
5094                 if (!i) {
5095                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5096                         if (rc)
5097                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5098                 }
5099         }
5100
5101         type = HWRM_RING_ALLOC_TX;
5102         for (i = 0; i < bp->tx_nr_rings; i++) {
5103                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5104                 struct bnxt_ring_struct *ring;
5105                 u32 map_idx;
5106
5107                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5108                         struct bnxt_napi *bnapi = txr->bnapi;
5109                         struct bnxt_cp_ring_info *cpr, *cpr2;
5110                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5111
5112                         cpr = &bnapi->cp_ring;
5113                         cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5114                         ring = &cpr2->cp_ring_struct;
5115                         ring->handle = BNXT_TX_HDL;
5116                         map_idx = bnapi->index;
5117                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5118                         if (rc)
5119                                 goto err_out;
5120                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5121                                     ring->fw_ring_id);
5122                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5123                 }
5124                 ring = &txr->tx_ring_struct;
5125                 map_idx = i;
5126                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5127                 if (rc)
5128                         goto err_out;
5129                 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5130         }
5131
5132         type = HWRM_RING_ALLOC_RX;
5133         for (i = 0; i < bp->rx_nr_rings; i++) {
5134                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5135                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5136                 struct bnxt_napi *bnapi = rxr->bnapi;
5137                 u32 map_idx = bnapi->index;
5138
5139                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5140                 if (rc)
5141                         goto err_out;
5142                 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5143                 /* If we have agg rings, post agg buffers first. */
5144                 if (!agg_rings)
5145                         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5146                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5147                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5148                         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5149                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5150                         struct bnxt_cp_ring_info *cpr2;
5151
5152                         cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5153                         ring = &cpr2->cp_ring_struct;
5154                         ring->handle = BNXT_RX_HDL;
5155                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5156                         if (rc)
5157                                 goto err_out;
5158                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5159                                     ring->fw_ring_id);
5160                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5161                 }
5162         }
5163
5164         if (agg_rings) {
5165                 type = HWRM_RING_ALLOC_AGG;
5166                 for (i = 0; i < bp->rx_nr_rings; i++) {
5167                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5168                         struct bnxt_ring_struct *ring =
5169                                                 &rxr->rx_agg_ring_struct;
5170                         u32 grp_idx = ring->grp_idx;
5171                         u32 map_idx = grp_idx + bp->rx_nr_rings;
5172
5173                         rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5174                         if (rc)
5175                                 goto err_out;
5176
5177                         bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5178                                     ring->fw_ring_id);
5179                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
5180                         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5181                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
5182                 }
5183         }
5184 err_out:
5185         return rc;
5186 }
5187
5188 static int hwrm_ring_free_send_msg(struct bnxt *bp,
5189                                    struct bnxt_ring_struct *ring,
5190                                    u32 ring_type, int cmpl_ring_id)
5191 {
5192         int rc;
5193         struct hwrm_ring_free_input req = {0};
5194         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
5195         u16 error_code;
5196
5197         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
5198         req.ring_type = ring_type;
5199         req.ring_id = cpu_to_le16(ring->fw_ring_id);
5200
5201         mutex_lock(&bp->hwrm_cmd_lock);
5202         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5203         error_code = le16_to_cpu(resp->error_code);
5204         mutex_unlock(&bp->hwrm_cmd_lock);
5205
5206         if (rc || error_code) {
5207                 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5208                            ring_type, rc, error_code);
5209                 return -EIO;
5210         }
5211         return 0;
5212 }
5213
5214 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
5215 {
5216         u32 type;
5217         int i;
5218
5219         if (!bp->bnapi)
5220                 return;
5221
5222         for (i = 0; i < bp->tx_nr_rings; i++) {
5223                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5224                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
5225
5226                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5227                         u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
5228
5229                         hwrm_ring_free_send_msg(bp, ring,
5230                                                 RING_FREE_REQ_RING_TYPE_TX,
5231                                                 close_path ? cmpl_ring_id :
5232                                                 INVALID_HW_RING_ID);
5233                         ring->fw_ring_id = INVALID_HW_RING_ID;
5234                 }
5235         }
5236
5237         for (i = 0; i < bp->rx_nr_rings; i++) {
5238                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5239                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5240                 u32 grp_idx = rxr->bnapi->index;
5241
5242                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5243                         u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5244
5245                         hwrm_ring_free_send_msg(bp, ring,
5246                                                 RING_FREE_REQ_RING_TYPE_RX,
5247                                                 close_path ? cmpl_ring_id :
5248                                                 INVALID_HW_RING_ID);
5249                         ring->fw_ring_id = INVALID_HW_RING_ID;
5250                         bp->grp_info[grp_idx].rx_fw_ring_id =
5251                                 INVALID_HW_RING_ID;
5252                 }
5253         }
5254
5255         if (bp->flags & BNXT_FLAG_CHIP_P5)
5256                 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
5257         else
5258                 type = RING_FREE_REQ_RING_TYPE_RX;
5259         for (i = 0; i < bp->rx_nr_rings; i++) {
5260                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5261                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
5262                 u32 grp_idx = rxr->bnapi->index;
5263
5264                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5265                         u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5266
5267                         hwrm_ring_free_send_msg(bp, ring, type,
5268                                                 close_path ? cmpl_ring_id :
5269                                                 INVALID_HW_RING_ID);
5270                         ring->fw_ring_id = INVALID_HW_RING_ID;
5271                         bp->grp_info[grp_idx].agg_fw_ring_id =
5272                                 INVALID_HW_RING_ID;
5273                 }
5274         }
5275
5276         /* The completion rings are about to be freed.  After that the
5277          * IRQ doorbell will not work anymore.  So we need to disable
5278          * IRQ here.
5279          */
5280         bnxt_disable_int_sync(bp);
5281
5282         if (bp->flags & BNXT_FLAG_CHIP_P5)
5283                 type = RING_FREE_REQ_RING_TYPE_NQ;
5284         else
5285                 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
5286         for (i = 0; i < bp->cp_nr_rings; i++) {
5287                 struct bnxt_napi *bnapi = bp->bnapi[i];
5288                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5289                 struct bnxt_ring_struct *ring;
5290                 int j;
5291
5292                 for (j = 0; j < 2; j++) {
5293                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
5294
5295                         if (cpr2) {
5296                                 ring = &cpr2->cp_ring_struct;
5297                                 if (ring->fw_ring_id == INVALID_HW_RING_ID)
5298                                         continue;
5299                                 hwrm_ring_free_send_msg(bp, ring,
5300                                         RING_FREE_REQ_RING_TYPE_L2_CMPL,
5301                                         INVALID_HW_RING_ID);
5302                                 ring->fw_ring_id = INVALID_HW_RING_ID;
5303                         }
5304                 }
5305                 ring = &cpr->cp_ring_struct;
5306                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5307                         hwrm_ring_free_send_msg(bp, ring, type,
5308                                                 INVALID_HW_RING_ID);
5309                         ring->fw_ring_id = INVALID_HW_RING_ID;
5310                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
5311                 }
5312         }
5313 }
5314
5315 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5316                            bool shared);
5317
5318 static int bnxt_hwrm_get_rings(struct bnxt *bp)
5319 {
5320         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5321         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5322         struct hwrm_func_qcfg_input req = {0};
5323         int rc;
5324
5325         if (bp->hwrm_spec_code < 0x10601)
5326                 return 0;
5327
5328         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5329         req.fid = cpu_to_le16(0xffff);
5330         mutex_lock(&bp->hwrm_cmd_lock);
5331         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5332         if (rc) {
5333                 mutex_unlock(&bp->hwrm_cmd_lock);
5334                 return -EIO;
5335         }
5336
5337         hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5338         if (BNXT_NEW_RM(bp)) {
5339                 u16 cp, stats;
5340
5341                 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
5342                 hw_resc->resv_hw_ring_grps =
5343                         le32_to_cpu(resp->alloc_hw_ring_grps);
5344                 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
5345                 cp = le16_to_cpu(resp->alloc_cmpl_rings);
5346                 stats = le16_to_cpu(resp->alloc_stat_ctx);
5347                 hw_resc->resv_irqs = cp;
5348                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5349                         int rx = hw_resc->resv_rx_rings;
5350                         int tx = hw_resc->resv_tx_rings;
5351
5352                         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5353                                 rx >>= 1;
5354                         if (cp < (rx + tx)) {
5355                                 bnxt_trim_rings(bp, &rx, &tx, cp, false);
5356                                 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5357                                         rx <<= 1;
5358                                 hw_resc->resv_rx_rings = rx;
5359                                 hw_resc->resv_tx_rings = tx;
5360                         }
5361                         hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
5362                         hw_resc->resv_hw_ring_grps = rx;
5363                 }
5364                 hw_resc->resv_cp_rings = cp;
5365                 hw_resc->resv_stat_ctxs = stats;
5366         }
5367         mutex_unlock(&bp->hwrm_cmd_lock);
5368         return 0;
5369 }
5370
5371 /* Caller must hold bp->hwrm_cmd_lock */
5372 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
5373 {
5374         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5375         struct hwrm_func_qcfg_input req = {0};
5376         int rc;
5377
5378         if (bp->hwrm_spec_code < 0x10601)
5379                 return 0;
5380
5381         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5382         req.fid = cpu_to_le16(fid);
5383         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5384         if (!rc)
5385                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5386
5387         return rc;
5388 }
5389
5390 static bool bnxt_rfs_supported(struct bnxt *bp);
5391
5392 static void
5393 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
5394                              int tx_rings, int rx_rings, int ring_grps,
5395                              int cp_rings, int stats, int vnics)
5396 {
5397         u32 enables = 0;
5398
5399         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
5400         req->fid = cpu_to_le16(0xffff);
5401         enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5402         req->num_tx_rings = cpu_to_le16(tx_rings);
5403         if (BNXT_NEW_RM(bp)) {
5404                 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
5405                 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5406                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5407                         enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
5408                         enables |= tx_rings + ring_grps ?
5409                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5410                         enables |= rx_rings ?
5411                                 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5412                 } else {
5413                         enables |= cp_rings ?
5414                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5415                         enables |= ring_grps ?
5416                                    FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
5417                                    FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5418                 }
5419                 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
5420
5421                 req->num_rx_rings = cpu_to_le16(rx_rings);
5422                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5423                         req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5424                         req->num_msix = cpu_to_le16(cp_rings);
5425                         req->num_rsscos_ctxs =
5426                                 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5427                 } else {
5428                         req->num_cmpl_rings = cpu_to_le16(cp_rings);
5429                         req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5430                         req->num_rsscos_ctxs = cpu_to_le16(1);
5431                         if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
5432                             bnxt_rfs_supported(bp))
5433                                 req->num_rsscos_ctxs =
5434                                         cpu_to_le16(ring_grps + 1);
5435                 }
5436                 req->num_stat_ctxs = cpu_to_le16(stats);
5437                 req->num_vnics = cpu_to_le16(vnics);
5438         }
5439         req->enables = cpu_to_le32(enables);
5440 }
5441
5442 static void
5443 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
5444                              struct hwrm_func_vf_cfg_input *req, int tx_rings,
5445                              int rx_rings, int ring_grps, int cp_rings,
5446                              int stats, int vnics)
5447 {
5448         u32 enables = 0;
5449
5450         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
5451         enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5452         enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
5453                               FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5454         enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5455         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5456                 enables |= tx_rings + ring_grps ?
5457                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5458         } else {
5459                 enables |= cp_rings ?
5460                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5461                 enables |= ring_grps ?
5462                            FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
5463         }
5464         enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
5465         enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
5466
5467         req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
5468         req->num_tx_rings = cpu_to_le16(tx_rings);
5469         req->num_rx_rings = cpu_to_le16(rx_rings);
5470         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5471                 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5472                 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5473         } else {
5474                 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5475                 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5476                 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
5477         }
5478         req->num_stat_ctxs = cpu_to_le16(stats);
5479         req->num_vnics = cpu_to_le16(vnics);
5480
5481         req->enables = cpu_to_le32(enables);
5482 }
5483
5484 static int
5485 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5486                            int ring_grps, int cp_rings, int stats, int vnics)
5487 {
5488         struct hwrm_func_cfg_input req = {0};
5489         int rc;
5490
5491         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5492                                      cp_rings, stats, vnics);
5493         if (!req.enables)
5494                 return 0;
5495
5496         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5497         if (rc)
5498                 return -ENOMEM;
5499
5500         if (bp->hwrm_spec_code < 0x10601)
5501                 bp->hw_resc.resv_tx_rings = tx_rings;
5502
5503         rc = bnxt_hwrm_get_rings(bp);
5504         return rc;
5505 }
5506
5507 static int
5508 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5509                            int ring_grps, int cp_rings, int stats, int vnics)
5510 {
5511         struct hwrm_func_vf_cfg_input req = {0};
5512         int rc;
5513
5514         if (!BNXT_NEW_RM(bp)) {
5515                 bp->hw_resc.resv_tx_rings = tx_rings;
5516                 return 0;
5517         }
5518
5519         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5520                                      cp_rings, stats, vnics);
5521         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5522         if (rc)
5523                 return -ENOMEM;
5524
5525         rc = bnxt_hwrm_get_rings(bp);
5526         return rc;
5527 }
5528
5529 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
5530                                    int cp, int stat, int vnic)
5531 {
5532         if (BNXT_PF(bp))
5533                 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
5534                                                   vnic);
5535         else
5536                 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
5537                                                   vnic);
5538 }
5539
5540 int bnxt_nq_rings_in_use(struct bnxt *bp)
5541 {
5542         int cp = bp->cp_nr_rings;
5543         int ulp_msix, ulp_base;
5544
5545         ulp_msix = bnxt_get_ulp_msix_num(bp);
5546         if (ulp_msix) {
5547                 ulp_base = bnxt_get_ulp_msix_base(bp);
5548                 cp += ulp_msix;
5549                 if ((ulp_base + ulp_msix) > cp)
5550                         cp = ulp_base + ulp_msix;
5551         }
5552         return cp;
5553 }
5554
5555 static int bnxt_cp_rings_in_use(struct bnxt *bp)
5556 {
5557         int cp;
5558
5559         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5560                 return bnxt_nq_rings_in_use(bp);
5561
5562         cp = bp->tx_nr_rings + bp->rx_nr_rings;
5563         return cp;
5564 }
5565
5566 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
5567 {
5568         int ulp_stat = bnxt_get_ulp_stat_ctxs(bp);
5569         int cp = bp->cp_nr_rings;
5570
5571         if (!ulp_stat)
5572                 return cp;
5573
5574         if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp))
5575                 return bnxt_get_ulp_msix_base(bp) + ulp_stat;
5576
5577         return cp + ulp_stat;
5578 }
5579
5580 static bool bnxt_need_reserve_rings(struct bnxt *bp)
5581 {
5582         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5583         int cp = bnxt_cp_rings_in_use(bp);
5584         int nq = bnxt_nq_rings_in_use(bp);
5585         int rx = bp->rx_nr_rings, stat;
5586         int vnic = 1, grp = rx;
5587
5588         if (bp->hwrm_spec_code < 0x10601)
5589                 return false;
5590
5591         if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
5592                 return true;
5593
5594         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5595                 vnic = rx + 1;
5596         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5597                 rx <<= 1;
5598         stat = bnxt_get_func_stat_ctxs(bp);
5599         if (BNXT_NEW_RM(bp) &&
5600             (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
5601              hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
5602              (hw_resc->resv_hw_ring_grps != grp &&
5603               !(bp->flags & BNXT_FLAG_CHIP_P5))))
5604                 return true;
5605         if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
5606             hw_resc->resv_irqs != nq)
5607                 return true;
5608         return false;
5609 }
5610
5611 static int __bnxt_reserve_rings(struct bnxt *bp)
5612 {
5613         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5614         int cp = bnxt_nq_rings_in_use(bp);
5615         int tx = bp->tx_nr_rings;
5616         int rx = bp->rx_nr_rings;
5617         int grp, rx_rings, rc;
5618         int vnic = 1, stat;
5619         bool sh = false;
5620
5621         if (!bnxt_need_reserve_rings(bp))
5622                 return 0;
5623
5624         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5625                 sh = true;
5626         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5627                 vnic = rx + 1;
5628         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5629                 rx <<= 1;
5630         grp = bp->rx_nr_rings;
5631         stat = bnxt_get_func_stat_ctxs(bp);
5632
5633         rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
5634         if (rc)
5635                 return rc;
5636
5637         tx = hw_resc->resv_tx_rings;
5638         if (BNXT_NEW_RM(bp)) {
5639                 rx = hw_resc->resv_rx_rings;
5640                 cp = hw_resc->resv_irqs;
5641                 grp = hw_resc->resv_hw_ring_grps;
5642                 vnic = hw_resc->resv_vnics;
5643                 stat = hw_resc->resv_stat_ctxs;
5644         }
5645
5646         rx_rings = rx;
5647         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5648                 if (rx >= 2) {
5649                         rx_rings = rx >> 1;
5650                 } else {
5651                         if (netif_running(bp->dev))
5652                                 return -ENOMEM;
5653
5654                         bp->flags &= ~BNXT_FLAG_AGG_RINGS;
5655                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
5656                         bp->dev->hw_features &= ~NETIF_F_LRO;
5657                         bp->dev->features &= ~NETIF_F_LRO;
5658                         bnxt_set_ring_params(bp);
5659                 }
5660         }
5661         rx_rings = min_t(int, rx_rings, grp);
5662         cp = min_t(int, cp, bp->cp_nr_rings);
5663         if (stat > bnxt_get_ulp_stat_ctxs(bp))
5664                 stat -= bnxt_get_ulp_stat_ctxs(bp);
5665         cp = min_t(int, cp, stat);
5666         rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
5667         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5668                 rx = rx_rings << 1;
5669         cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
5670         bp->tx_nr_rings = tx;
5671         bp->rx_nr_rings = rx_rings;
5672         bp->cp_nr_rings = cp;
5673
5674         if (!tx || !rx || !cp || !grp || !vnic || !stat)
5675                 return -ENOMEM;
5676
5677         return rc;
5678 }
5679
5680 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5681                                     int ring_grps, int cp_rings, int stats,
5682                                     int vnics)
5683 {
5684         struct hwrm_func_vf_cfg_input req = {0};
5685         u32 flags;
5686         int rc;
5687
5688         if (!BNXT_NEW_RM(bp))
5689                 return 0;
5690
5691         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5692                                      cp_rings, stats, vnics);
5693         flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
5694                 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5695                 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5696                 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5697                 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
5698                 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
5699         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5700                 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5701
5702         req.flags = cpu_to_le32(flags);
5703         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5704         if (rc)
5705                 return -ENOMEM;
5706         return 0;
5707 }
5708
5709 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5710                                     int ring_grps, int cp_rings, int stats,
5711                                     int vnics)
5712 {
5713         struct hwrm_func_cfg_input req = {0};
5714         u32 flags;
5715         int rc;
5716
5717         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5718                                      cp_rings, stats, vnics);
5719         flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
5720         if (BNXT_NEW_RM(bp)) {
5721                 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5722                          FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5723                          FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5724                          FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
5725                 if (bp->flags & BNXT_FLAG_CHIP_P5)
5726                         flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
5727                                  FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
5728                 else
5729                         flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5730         }
5731
5732         req.flags = cpu_to_le32(flags);
5733         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5734         if (rc)
5735                 return -ENOMEM;
5736         return 0;
5737 }
5738
5739 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5740                                  int ring_grps, int cp_rings, int stats,
5741                                  int vnics)
5742 {
5743         if (bp->hwrm_spec_code < 0x10801)
5744                 return 0;
5745
5746         if (BNXT_PF(bp))
5747                 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
5748                                                 ring_grps, cp_rings, stats,
5749                                                 vnics);
5750
5751         return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
5752                                         cp_rings, stats, vnics);
5753 }
5754
5755 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
5756 {
5757         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5758         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5759         struct hwrm_ring_aggint_qcaps_input req = {0};
5760         int rc;
5761
5762         coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
5763         coal_cap->num_cmpl_dma_aggr_max = 63;
5764         coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
5765         coal_cap->cmpl_aggr_dma_tmr_max = 65535;
5766         coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
5767         coal_cap->int_lat_tmr_min_max = 65535;
5768         coal_cap->int_lat_tmr_max_max = 65535;
5769         coal_cap->num_cmpl_aggr_int_max = 65535;
5770         coal_cap->timer_units = 80;
5771
5772         if (bp->hwrm_spec_code < 0x10902)
5773                 return;
5774
5775         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
5776         mutex_lock(&bp->hwrm_cmd_lock);
5777         rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5778         if (!rc) {
5779                 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
5780                 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
5781                 coal_cap->num_cmpl_dma_aggr_max =
5782                         le16_to_cpu(resp->num_cmpl_dma_aggr_max);
5783                 coal_cap->num_cmpl_dma_aggr_during_int_max =
5784                         le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
5785                 coal_cap->cmpl_aggr_dma_tmr_max =
5786                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
5787                 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
5788                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
5789                 coal_cap->int_lat_tmr_min_max =
5790                         le16_to_cpu(resp->int_lat_tmr_min_max);
5791                 coal_cap->int_lat_tmr_max_max =
5792                         le16_to_cpu(resp->int_lat_tmr_max_max);
5793                 coal_cap->num_cmpl_aggr_int_max =
5794                         le16_to_cpu(resp->num_cmpl_aggr_int_max);
5795                 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
5796         }
5797         mutex_unlock(&bp->hwrm_cmd_lock);
5798 }
5799
5800 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
5801 {
5802         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5803
5804         return usec * 1000 / coal_cap->timer_units;
5805 }
5806
5807 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
5808         struct bnxt_coal *hw_coal,
5809         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5810 {
5811         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5812         u32 cmpl_params = coal_cap->cmpl_params;
5813         u16 val, tmr, max, flags = 0;
5814
5815         max = hw_coal->bufs_per_record * 128;
5816         if (hw_coal->budget)
5817                 max = hw_coal->bufs_per_record * hw_coal->budget;
5818         max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
5819
5820         val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
5821         req->num_cmpl_aggr_int = cpu_to_le16(val);
5822
5823         val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
5824         req->num_cmpl_dma_aggr = cpu_to_le16(val);
5825
5826         val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
5827                       coal_cap->num_cmpl_dma_aggr_during_int_max);
5828         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
5829
5830         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
5831         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
5832         req->int_lat_tmr_max = cpu_to_le16(tmr);
5833
5834         /* min timer set to 1/2 of interrupt timer */
5835         if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
5836                 val = tmr / 2;
5837                 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
5838                 req->int_lat_tmr_min = cpu_to_le16(val);
5839                 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5840         }
5841
5842         /* buf timer set to 1/4 of interrupt timer */
5843         val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
5844         req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
5845
5846         if (cmpl_params &
5847             RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
5848                 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
5849                 val = clamp_t(u16, tmr, 1,
5850                               coal_cap->cmpl_aggr_dma_tmr_during_int_max);
5851                 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
5852                 req->enables |=
5853                         cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
5854         }
5855
5856         if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
5857                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
5858         if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
5859             hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
5860                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
5861         req->flags = cpu_to_le16(flags);
5862         req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
5863 }
5864
5865 /* Caller holds bp->hwrm_cmd_lock */
5866 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
5867                                    struct bnxt_coal *hw_coal)
5868 {
5869         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5870         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5871         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5872         u32 nq_params = coal_cap->nq_params;
5873         u16 tmr;
5874
5875         if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
5876                 return 0;
5877
5878         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5879                                -1, -1);
5880         req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
5881         req.flags =
5882                 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
5883
5884         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
5885         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
5886         req.int_lat_tmr_min = cpu_to_le16(tmr);
5887         req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5888         return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5889 }
5890
5891 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
5892 {
5893         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
5894         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5895         struct bnxt_coal coal;
5896
5897         /* Tick values in micro seconds.
5898          * 1 coal_buf x bufs_per_record = 1 completion record.
5899          */
5900         memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
5901
5902         coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
5903         coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
5904
5905         if (!bnapi->rx_ring)
5906                 return -ENODEV;
5907
5908         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5909                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5910
5911         bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
5912
5913         req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
5914
5915         return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5916                                  HWRM_CMD_TIMEOUT);
5917 }
5918
5919 int bnxt_hwrm_set_coal(struct bnxt *bp)
5920 {
5921         int i, rc = 0;
5922         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
5923                                                            req_tx = {0}, *req;
5924
5925         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5926                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5927         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5928                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5929
5930         bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
5931         bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
5932
5933         mutex_lock(&bp->hwrm_cmd_lock);
5934         for (i = 0; i < bp->cp_nr_rings; i++) {
5935                 struct bnxt_napi *bnapi = bp->bnapi[i];
5936                 struct bnxt_coal *hw_coal;
5937                 u16 ring_id;
5938
5939                 req = &req_rx;
5940                 if (!bnapi->rx_ring) {
5941                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5942                         req = &req_tx;
5943                 } else {
5944                         ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
5945                 }
5946                 req->ring_id = cpu_to_le16(ring_id);
5947
5948                 rc = _hwrm_send_message(bp, req, sizeof(*req),
5949                                         HWRM_CMD_TIMEOUT);
5950                 if (rc)
5951                         break;
5952
5953                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5954                         continue;
5955
5956                 if (bnapi->rx_ring && bnapi->tx_ring) {
5957                         req = &req_tx;
5958                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5959                         req->ring_id = cpu_to_le16(ring_id);
5960                         rc = _hwrm_send_message(bp, req, sizeof(*req),
5961                                                 HWRM_CMD_TIMEOUT);
5962                         if (rc)
5963                                 break;
5964                 }
5965                 if (bnapi->rx_ring)
5966                         hw_coal = &bp->rx_coal;
5967                 else
5968                         hw_coal = &bp->tx_coal;
5969                 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
5970         }
5971         mutex_unlock(&bp->hwrm_cmd_lock);
5972         return rc;
5973 }
5974
5975 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5976 {
5977         int rc = 0, i;
5978         struct hwrm_stat_ctx_free_input req = {0};
5979
5980         if (!bp->bnapi)
5981                 return 0;
5982
5983         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5984                 return 0;
5985
5986         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5987
5988         mutex_lock(&bp->hwrm_cmd_lock);
5989         for (i = 0; i < bp->cp_nr_rings; i++) {
5990                 struct bnxt_napi *bnapi = bp->bnapi[i];
5991                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5992
5993                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5994                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5995
5996                         rc = _hwrm_send_message(bp, &req, sizeof(req),
5997                                                 HWRM_CMD_TIMEOUT);
5998                         if (rc)
5999                                 break;
6000
6001                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
6002                 }
6003         }
6004         mutex_unlock(&bp->hwrm_cmd_lock);
6005         return rc;
6006 }
6007
6008 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
6009 {
6010         int rc = 0, i;
6011         struct hwrm_stat_ctx_alloc_input req = {0};
6012         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6013
6014         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6015                 return 0;
6016
6017         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
6018
6019         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
6020
6021         mutex_lock(&bp->hwrm_cmd_lock);
6022         for (i = 0; i < bp->cp_nr_rings; i++) {
6023                 struct bnxt_napi *bnapi = bp->bnapi[i];
6024                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6025
6026                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
6027
6028                 rc = _hwrm_send_message(bp, &req, sizeof(req),
6029                                         HWRM_CMD_TIMEOUT);
6030                 if (rc)
6031                         break;
6032
6033                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
6034
6035                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
6036         }
6037         mutex_unlock(&bp->hwrm_cmd_lock);
6038         return rc;
6039 }
6040
6041 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
6042 {
6043         struct hwrm_func_qcfg_input req = {0};
6044         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6045         u16 flags;
6046         int rc;
6047
6048         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
6049         req.fid = cpu_to_le16(0xffff);
6050         mutex_lock(&bp->hwrm_cmd_lock);
6051         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6052         if (rc)
6053                 goto func_qcfg_exit;
6054
6055 #ifdef CONFIG_BNXT_SRIOV
6056         if (BNXT_VF(bp)) {
6057                 struct bnxt_vf_info *vf = &bp->vf;
6058
6059                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
6060         }
6061 #endif
6062         flags = le16_to_cpu(resp->flags);
6063         if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
6064                      FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
6065                 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
6066                 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
6067                         bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
6068         }
6069         if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
6070                 bp->flags |= BNXT_FLAG_MULTI_HOST;
6071
6072         switch (resp->port_partition_type) {
6073         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
6074         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
6075         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
6076                 bp->port_partition_type = resp->port_partition_type;
6077                 break;
6078         }
6079         if (bp->hwrm_spec_code < 0x10707 ||
6080             resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
6081                 bp->br_mode = BRIDGE_MODE_VEB;
6082         else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
6083                 bp->br_mode = BRIDGE_MODE_VEPA;
6084         else
6085                 bp->br_mode = BRIDGE_MODE_UNDEF;
6086
6087         bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
6088         if (!bp->max_mtu)
6089                 bp->max_mtu = BNXT_MAX_MTU;
6090
6091 func_qcfg_exit:
6092         mutex_unlock(&bp->hwrm_cmd_lock);
6093         return rc;
6094 }
6095
6096 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
6097 {
6098         struct hwrm_func_backing_store_qcaps_input req = {0};
6099         struct hwrm_func_backing_store_qcaps_output *resp =
6100                 bp->hwrm_cmd_resp_addr;
6101         int rc;
6102
6103         if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
6104                 return 0;
6105
6106         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
6107         mutex_lock(&bp->hwrm_cmd_lock);
6108         rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6109         if (!rc) {
6110                 struct bnxt_ctx_pg_info *ctx_pg;
6111                 struct bnxt_ctx_mem_info *ctx;
6112                 int i;
6113
6114                 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
6115                 if (!ctx) {
6116                         rc = -ENOMEM;
6117                         goto ctx_err;
6118                 }
6119                 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL);
6120                 if (!ctx_pg) {
6121                         kfree(ctx);
6122                         rc = -ENOMEM;
6123                         goto ctx_err;
6124                 }
6125                 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++)
6126                         ctx->tqm_mem[i] = ctx_pg;
6127
6128                 bp->ctx = ctx;
6129                 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
6130                 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
6131                 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
6132                 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
6133                 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
6134                 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
6135                 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
6136                 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
6137                 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
6138                 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
6139                 ctx->vnic_max_vnic_entries =
6140                         le16_to_cpu(resp->vnic_max_vnic_entries);
6141                 ctx->vnic_max_ring_table_entries =
6142                         le16_to_cpu(resp->vnic_max_ring_table_entries);
6143                 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
6144                 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
6145                 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
6146                 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
6147                 ctx->tqm_min_entries_per_ring =
6148                         le32_to_cpu(resp->tqm_min_entries_per_ring);
6149                 ctx->tqm_max_entries_per_ring =
6150                         le32_to_cpu(resp->tqm_max_entries_per_ring);
6151                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
6152                 if (!ctx->tqm_entries_multiple)
6153                         ctx->tqm_entries_multiple = 1;
6154                 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
6155                 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
6156                 ctx->mrav_num_entries_units =
6157                         le16_to_cpu(resp->mrav_num_entries_units);
6158                 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
6159                 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
6160         } else {
6161                 rc = 0;
6162         }
6163 ctx_err:
6164         mutex_unlock(&bp->hwrm_cmd_lock);
6165         return rc;
6166 }
6167
6168 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
6169                                   __le64 *pg_dir)
6170 {
6171         u8 pg_size = 0;
6172
6173         if (BNXT_PAGE_SHIFT == 13)
6174                 pg_size = 1 << 4;
6175         else if (BNXT_PAGE_SIZE == 16)
6176                 pg_size = 2 << 4;
6177
6178         *pg_attr = pg_size;
6179         if (rmem->depth >= 1) {
6180                 if (rmem->depth == 2)
6181                         *pg_attr |= 2;
6182                 else
6183                         *pg_attr |= 1;
6184                 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
6185         } else {
6186                 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
6187         }
6188 }
6189
6190 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES                 \
6191         (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP |                \
6192          FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ |               \
6193          FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ |                \
6194          FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC |              \
6195          FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
6196
6197 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
6198 {
6199         struct hwrm_func_backing_store_cfg_input req = {0};
6200         struct bnxt_ctx_mem_info *ctx = bp->ctx;
6201         struct bnxt_ctx_pg_info *ctx_pg;
6202         __le32 *num_entries;
6203         __le64 *pg_dir;
6204         u32 flags = 0;
6205         u8 *pg_attr;
6206         int i, rc;
6207         u32 ena;
6208
6209         if (!ctx)
6210                 return 0;
6211
6212         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
6213         req.enables = cpu_to_le32(enables);
6214
6215         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
6216                 ctx_pg = &ctx->qp_mem;
6217                 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
6218                 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
6219                 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
6220                 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
6221                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6222                                       &req.qpc_pg_size_qpc_lvl,
6223                                       &req.qpc_page_dir);
6224         }
6225         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
6226                 ctx_pg = &ctx->srq_mem;
6227                 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
6228                 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
6229                 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
6230                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6231                                       &req.srq_pg_size_srq_lvl,
6232                                       &req.srq_page_dir);
6233         }
6234         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
6235                 ctx_pg = &ctx->cq_mem;
6236                 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
6237                 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
6238                 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
6239                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
6240                                       &req.cq_page_dir);
6241         }
6242         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
6243                 ctx_pg = &ctx->vnic_mem;
6244                 req.vnic_num_vnic_entries =
6245                         cpu_to_le16(ctx->vnic_max_vnic_entries);
6246                 req.vnic_num_ring_table_entries =
6247                         cpu_to_le16(ctx->vnic_max_ring_table_entries);
6248                 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
6249                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6250                                       &req.vnic_pg_size_vnic_lvl,
6251                                       &req.vnic_page_dir);
6252         }
6253         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
6254                 ctx_pg = &ctx->stat_mem;
6255                 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
6256                 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
6257                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6258                                       &req.stat_pg_size_stat_lvl,
6259                                       &req.stat_page_dir);
6260         }
6261         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
6262                 ctx_pg = &ctx->mrav_mem;
6263                 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
6264                 if (ctx->mrav_num_entries_units)
6265                         flags |=
6266                         FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
6267                 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
6268                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6269                                       &req.mrav_pg_size_mrav_lvl,
6270                                       &req.mrav_page_dir);
6271         }
6272         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
6273                 ctx_pg = &ctx->tim_mem;
6274                 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
6275                 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
6276                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6277                                       &req.tim_pg_size_tim_lvl,
6278                                       &req.tim_page_dir);
6279         }
6280         for (i = 0, num_entries = &req.tqm_sp_num_entries,
6281              pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
6282              pg_dir = &req.tqm_sp_page_dir,
6283              ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
6284              i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
6285                 if (!(enables & ena))
6286                         continue;
6287
6288                 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
6289                 ctx_pg = ctx->tqm_mem[i];
6290                 *num_entries = cpu_to_le32(ctx_pg->entries);
6291                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
6292         }
6293         req.flags = cpu_to_le32(flags);
6294         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6295         if (rc)
6296                 rc = -EIO;
6297         return rc;
6298 }
6299
6300 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
6301                                   struct bnxt_ctx_pg_info *ctx_pg)
6302 {
6303         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6304
6305         rmem->page_size = BNXT_PAGE_SIZE;
6306         rmem->pg_arr = ctx_pg->ctx_pg_arr;
6307         rmem->dma_arr = ctx_pg->ctx_dma_arr;
6308         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
6309         if (rmem->depth >= 1)
6310                 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
6311         return bnxt_alloc_ring(bp, rmem);
6312 }
6313
6314 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
6315                                   struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
6316                                   u8 depth)
6317 {
6318         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6319         int rc;
6320
6321         if (!mem_size)
6322                 return 0;
6323
6324         ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6325         if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
6326                 ctx_pg->nr_pages = 0;
6327                 return -EINVAL;
6328         }
6329         if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
6330                 int nr_tbls, i;
6331
6332                 rmem->depth = 2;
6333                 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
6334                                              GFP_KERNEL);
6335                 if (!ctx_pg->ctx_pg_tbl)
6336                         return -ENOMEM;
6337                 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
6338                 rmem->nr_pages = nr_tbls;
6339                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6340                 if (rc)
6341                         return rc;
6342                 for (i = 0; i < nr_tbls; i++) {
6343                         struct bnxt_ctx_pg_info *pg_tbl;
6344
6345                         pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
6346                         if (!pg_tbl)
6347                                 return -ENOMEM;
6348                         ctx_pg->ctx_pg_tbl[i] = pg_tbl;
6349                         rmem = &pg_tbl->ring_mem;
6350                         rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
6351                         rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
6352                         rmem->depth = 1;
6353                         rmem->nr_pages = MAX_CTX_PAGES;
6354                         if (i == (nr_tbls - 1)) {
6355                                 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
6356
6357                                 if (rem)
6358                                         rmem->nr_pages = rem;
6359                         }
6360                         rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
6361                         if (rc)
6362                                 break;
6363                 }
6364         } else {
6365                 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6366                 if (rmem->nr_pages > 1 || depth)
6367                         rmem->depth = 1;
6368                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6369         }
6370         return rc;
6371 }
6372
6373 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
6374                                   struct bnxt_ctx_pg_info *ctx_pg)
6375 {
6376         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6377
6378         if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
6379             ctx_pg->ctx_pg_tbl) {
6380                 int i, nr_tbls = rmem->nr_pages;
6381
6382                 for (i = 0; i < nr_tbls; i++) {
6383                         struct bnxt_ctx_pg_info *pg_tbl;
6384                         struct bnxt_ring_mem_info *rmem2;
6385
6386                         pg_tbl = ctx_pg->ctx_pg_tbl[i];
6387                         if (!pg_tbl)
6388                                 continue;
6389                         rmem2 = &pg_tbl->ring_mem;
6390                         bnxt_free_ring(bp, rmem2);
6391                         ctx_pg->ctx_pg_arr[i] = NULL;
6392                         kfree(pg_tbl);
6393                         ctx_pg->ctx_pg_tbl[i] = NULL;
6394                 }
6395                 kfree(ctx_pg->ctx_pg_tbl);
6396                 ctx_pg->ctx_pg_tbl = NULL;
6397         }
6398         bnxt_free_ring(bp, rmem);
6399         ctx_pg->nr_pages = 0;
6400 }
6401
6402 static void bnxt_free_ctx_mem(struct bnxt *bp)
6403 {
6404         struct bnxt_ctx_mem_info *ctx = bp->ctx;
6405         int i;
6406
6407         if (!ctx)
6408                 return;
6409
6410         if (ctx->tqm_mem[0]) {
6411                 for (i = 0; i < bp->max_q + 1; i++)
6412                         bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
6413                 kfree(ctx->tqm_mem[0]);
6414                 ctx->tqm_mem[0] = NULL;
6415         }
6416
6417         bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
6418         bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
6419         bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
6420         bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
6421         bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
6422         bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
6423         bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
6424         ctx->flags &= ~BNXT_CTX_FLAG_INITED;
6425 }
6426
6427 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
6428 {
6429         struct bnxt_ctx_pg_info *ctx_pg;
6430         struct bnxt_ctx_mem_info *ctx;
6431         u32 mem_size, ena, entries;
6432         u32 num_mr, num_ah;
6433         u32 extra_srqs = 0;
6434         u32 extra_qps = 0;
6435         u8 pg_lvl = 1;
6436         int i, rc;
6437
6438         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
6439         if (rc) {
6440                 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
6441                            rc);
6442                 return rc;
6443         }
6444         ctx = bp->ctx;
6445         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
6446                 return 0;
6447
6448         if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
6449                 pg_lvl = 2;
6450                 extra_qps = 65536;
6451                 extra_srqs = 8192;
6452         }
6453
6454         ctx_pg = &ctx->qp_mem;
6455         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
6456                           extra_qps;
6457         mem_size = ctx->qp_entry_size * ctx_pg->entries;
6458         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6459         if (rc)
6460                 return rc;
6461
6462         ctx_pg = &ctx->srq_mem;
6463         ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
6464         mem_size = ctx->srq_entry_size * ctx_pg->entries;
6465         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6466         if (rc)
6467                 return rc;
6468
6469         ctx_pg = &ctx->cq_mem;
6470         ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
6471         mem_size = ctx->cq_entry_size * ctx_pg->entries;
6472         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6473         if (rc)
6474                 return rc;
6475
6476         ctx_pg = &ctx->vnic_mem;
6477         ctx_pg->entries = ctx->vnic_max_vnic_entries +
6478                           ctx->vnic_max_ring_table_entries;
6479         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
6480         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6481         if (rc)
6482                 return rc;
6483
6484         ctx_pg = &ctx->stat_mem;
6485         ctx_pg->entries = ctx->stat_max_entries;
6486         mem_size = ctx->stat_entry_size * ctx_pg->entries;
6487         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6488         if (rc)
6489                 return rc;
6490
6491         ena = 0;
6492         if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
6493                 goto skip_rdma;
6494
6495         ctx_pg = &ctx->mrav_mem;
6496         /* 128K extra is needed to accommodate static AH context
6497          * allocation by f/w.
6498          */
6499         num_mr = 1024 * 256;
6500         num_ah = 1024 * 128;
6501         ctx_pg->entries = num_mr + num_ah;
6502         mem_size = ctx->mrav_entry_size * ctx_pg->entries;
6503         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2);
6504         if (rc)
6505                 return rc;
6506         ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
6507         if (ctx->mrav_num_entries_units)
6508                 ctx_pg->entries =
6509                         ((num_mr / ctx->mrav_num_entries_units) << 16) |
6510                          (num_ah / ctx->mrav_num_entries_units);
6511
6512         ctx_pg = &ctx->tim_mem;
6513         ctx_pg->entries = ctx->qp_mem.entries;
6514         mem_size = ctx->tim_entry_size * ctx_pg->entries;
6515         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6516         if (rc)
6517                 return rc;
6518         ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
6519
6520 skip_rdma:
6521         entries = ctx->qp_max_l2_entries + extra_qps;
6522         entries = roundup(entries, ctx->tqm_entries_multiple);
6523         entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring,
6524                           ctx->tqm_max_entries_per_ring);
6525         for (i = 0; i < bp->max_q + 1; i++) {
6526                 ctx_pg = ctx->tqm_mem[i];
6527                 ctx_pg->entries = entries;
6528                 mem_size = ctx->tqm_entry_size * entries;
6529                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6530                 if (rc)
6531                         return rc;
6532                 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
6533         }
6534         ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
6535         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
6536         if (rc)
6537                 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
6538                            rc);
6539         else
6540                 ctx->flags |= BNXT_CTX_FLAG_INITED;
6541
6542         return 0;
6543 }
6544
6545 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
6546 {
6547         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6548         struct hwrm_func_resource_qcaps_input req = {0};
6549         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6550         int rc;
6551
6552         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
6553         req.fid = cpu_to_le16(0xffff);
6554
6555         mutex_lock(&bp->hwrm_cmd_lock);
6556         rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
6557                                        HWRM_CMD_TIMEOUT);
6558         if (rc) {
6559                 rc = -EIO;
6560                 goto hwrm_func_resc_qcaps_exit;
6561         }
6562
6563         hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
6564         if (!all)
6565                 goto hwrm_func_resc_qcaps_exit;
6566
6567         hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
6568         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6569         hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
6570         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6571         hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
6572         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6573         hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
6574         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6575         hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
6576         hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
6577         hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
6578         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6579         hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
6580         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6581         hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
6582         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6583
6584         if (bp->flags & BNXT_FLAG_CHIP_P5) {
6585                 u16 max_msix = le16_to_cpu(resp->max_msix);
6586
6587                 hw_resc->max_nqs = max_msix;
6588                 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
6589         }
6590
6591         if (BNXT_PF(bp)) {
6592                 struct bnxt_pf_info *pf = &bp->pf;
6593
6594                 pf->vf_resv_strategy =
6595                         le16_to_cpu(resp->vf_reservation_strategy);
6596                 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
6597                         pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
6598         }
6599 hwrm_func_resc_qcaps_exit:
6600         mutex_unlock(&bp->hwrm_cmd_lock);
6601         return rc;
6602 }
6603
6604 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
6605 {
6606         int rc = 0;
6607         struct hwrm_func_qcaps_input req = {0};
6608         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6609         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6610         u32 flags;
6611
6612         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
6613         req.fid = cpu_to_le16(0xffff);
6614
6615         mutex_lock(&bp->hwrm_cmd_lock);
6616         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6617         if (rc)
6618                 goto hwrm_func_qcaps_exit;
6619
6620         flags = le32_to_cpu(resp->flags);
6621         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
6622                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
6623         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
6624                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
6625         if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
6626                 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
6627         if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
6628                 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
6629
6630         bp->tx_push_thresh = 0;
6631         if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
6632                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
6633
6634         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6635         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6636         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6637         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6638         hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
6639         if (!hw_resc->max_hw_ring_grps)
6640                 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
6641         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6642         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6643         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6644
6645         if (BNXT_PF(bp)) {
6646                 struct bnxt_pf_info *pf = &bp->pf;
6647
6648                 pf->fw_fid = le16_to_cpu(resp->fid);
6649                 pf->port_id = le16_to_cpu(resp->port_id);
6650                 bp->dev->dev_port = pf->port_id;
6651                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
6652                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
6653                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
6654                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
6655                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
6656                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
6657                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
6658                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
6659                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
6660                 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
6661                         bp->flags |= BNXT_FLAG_WOL_CAP;
6662         } else {
6663 #ifdef CONFIG_BNXT_SRIOV
6664                 struct bnxt_vf_info *vf = &bp->vf;
6665
6666                 vf->fw_fid = le16_to_cpu(resp->fid);
6667                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
6668 #endif
6669         }
6670
6671 hwrm_func_qcaps_exit:
6672         mutex_unlock(&bp->hwrm_cmd_lock);
6673         return rc;
6674 }
6675
6676 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
6677
6678 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
6679 {
6680         int rc;
6681
6682         rc = __bnxt_hwrm_func_qcaps(bp);
6683         if (rc)
6684                 return rc;
6685         rc = bnxt_hwrm_queue_qportcfg(bp);
6686         if (rc) {
6687                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
6688                 return rc;
6689         }
6690         if (bp->hwrm_spec_code >= 0x10803) {
6691                 rc = bnxt_alloc_ctx_mem(bp);
6692                 if (rc)
6693                         return rc;
6694                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6695                 if (!rc)
6696                         bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
6697         }
6698         return 0;
6699 }
6700
6701 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
6702 {
6703         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6704         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
6705         int rc = 0;
6706         u32 flags;
6707
6708         if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
6709                 return 0;
6710
6711         resp = bp->hwrm_cmd_resp_addr;
6712         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1);
6713
6714         mutex_lock(&bp->hwrm_cmd_lock);
6715         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6716         if (rc)
6717                 goto hwrm_cfa_adv_qcaps_exit;
6718
6719         flags = le32_to_cpu(resp->flags);
6720         if (flags &
6721             CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED)
6722                 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX;
6723
6724 hwrm_cfa_adv_qcaps_exit:
6725         mutex_unlock(&bp->hwrm_cmd_lock);
6726         return rc;
6727 }
6728
6729 static int bnxt_hwrm_func_reset(struct bnxt *bp)
6730 {
6731         struct hwrm_func_reset_input req = {0};
6732
6733         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
6734         req.enables = 0;
6735
6736         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
6737 }
6738
6739 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
6740 {
6741         int rc = 0;
6742         struct hwrm_queue_qportcfg_input req = {0};
6743         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
6744         u8 i, j, *qptr;
6745         bool no_rdma;
6746
6747         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
6748
6749         mutex_lock(&bp->hwrm_cmd_lock);
6750         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6751         if (rc)
6752                 goto qportcfg_exit;
6753
6754         if (!resp->max_configurable_queues) {
6755                 rc = -EINVAL;
6756                 goto qportcfg_exit;
6757         }
6758         bp->max_tc = resp->max_configurable_queues;
6759         bp->max_lltc = resp->max_configurable_lossless_queues;
6760         if (bp->max_tc > BNXT_MAX_QUEUE)
6761                 bp->max_tc = BNXT_MAX_QUEUE;
6762
6763         no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
6764         qptr = &resp->queue_id0;
6765         for (i = 0, j = 0; i < bp->max_tc; i++) {
6766                 bp->q_info[j].queue_id = *qptr;
6767                 bp->q_ids[i] = *qptr++;
6768                 bp->q_info[j].queue_profile = *qptr++;
6769                 bp->tc_to_qidx[j] = j;
6770                 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
6771                     (no_rdma && BNXT_PF(bp)))
6772                         j++;
6773         }
6774         bp->max_q = bp->max_tc;
6775         bp->max_tc = max_t(u8, j, 1);
6776
6777         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
6778                 bp->max_tc = 1;
6779
6780         if (bp->max_lltc > bp->max_tc)
6781                 bp->max_lltc = bp->max_tc;
6782
6783 qportcfg_exit:
6784         mutex_unlock(&bp->hwrm_cmd_lock);
6785         return rc;
6786 }
6787
6788 static int bnxt_hwrm_ver_get(struct bnxt *bp)
6789 {
6790         int rc;
6791         struct hwrm_ver_get_input req = {0};
6792         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6793         u32 dev_caps_cfg;
6794
6795         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
6796         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
6797         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6798         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6799         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6800         mutex_lock(&bp->hwrm_cmd_lock);
6801         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6802         if (rc)
6803                 goto hwrm_ver_get_exit;
6804
6805         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
6806
6807         bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
6808                              resp->hwrm_intf_min_8b << 8 |
6809                              resp->hwrm_intf_upd_8b;
6810         if (resp->hwrm_intf_maj_8b < 1) {
6811                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
6812                             resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
6813                             resp->hwrm_intf_upd_8b);
6814                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
6815         }
6816         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
6817                  resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
6818                  resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
6819
6820         if (strlen(resp->active_pkg_name)) {
6821                 int fw_ver_len = strlen(bp->fw_ver_str);
6822
6823                 snprintf(bp->fw_ver_str + fw_ver_len,
6824                          FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
6825                          resp->active_pkg_name);
6826                 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
6827         }
6828
6829         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
6830         if (!bp->hwrm_cmd_timeout)
6831                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
6832
6833         if (resp->hwrm_intf_maj_8b >= 1) {
6834                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
6835                 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
6836         }
6837         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
6838                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
6839
6840         bp->chip_num = le16_to_cpu(resp->chip_num);
6841         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
6842             !resp->chip_metal)
6843                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
6844
6845         dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
6846         if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
6847             (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
6848                 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
6849
6850         if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
6851                 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
6852
6853         if (dev_caps_cfg &
6854             VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
6855                 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
6856
6857         if (dev_caps_cfg &
6858             VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
6859                 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
6860
6861         if (dev_caps_cfg &
6862             VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
6863                 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
6864
6865 hwrm_ver_get_exit:
6866         mutex_unlock(&bp->hwrm_cmd_lock);
6867         return rc;
6868 }
6869
6870 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
6871 {
6872         struct hwrm_fw_set_time_input req = {0};
6873         struct tm tm;
6874         time64_t now = ktime_get_real_seconds();
6875
6876         if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
6877             bp->hwrm_spec_code < 0x10400)
6878                 return -EOPNOTSUPP;
6879
6880         time64_to_tm(now, 0, &tm);
6881         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
6882         req.year = cpu_to_le16(1900 + tm.tm_year);
6883         req.month = 1 + tm.tm_mon;
6884         req.day = tm.tm_mday;
6885         req.hour = tm.tm_hour;
6886         req.minute = tm.tm_min;
6887         req.second = tm.tm_sec;
6888         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6889 }
6890
6891 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
6892 {
6893         int rc;
6894         struct bnxt_pf_info *pf = &bp->pf;
6895         struct hwrm_port_qstats_input req = {0};
6896
6897         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
6898                 return 0;
6899
6900         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
6901         req.port_id = cpu_to_le16(pf->port_id);
6902         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
6903         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
6904         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6905         return rc;
6906 }
6907
6908 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
6909 {
6910         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
6911         struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
6912         struct hwrm_port_qstats_ext_input req = {0};
6913         struct bnxt_pf_info *pf = &bp->pf;
6914         u32 tx_stat_size;
6915         int rc;
6916
6917         if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
6918                 return 0;
6919
6920         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
6921         req.port_id = cpu_to_le16(pf->port_id);
6922         req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
6923         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
6924         tx_stat_size = bp->hw_tx_port_stats_ext ?
6925                        sizeof(*bp->hw_tx_port_stats_ext) : 0;
6926         req.tx_stat_size = cpu_to_le16(tx_stat_size);
6927         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map);
6928         mutex_lock(&bp->hwrm_cmd_lock);
6929         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6930         if (!rc) {
6931                 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
6932                 bp->fw_tx_stats_ext_size = tx_stat_size ?
6933                         le16_to_cpu(resp->tx_stat_size) / 8 : 0;
6934         } else {
6935                 bp->fw_rx_stats_ext_size = 0;
6936                 bp->fw_tx_stats_ext_size = 0;
6937         }
6938         if (bp->fw_tx_stats_ext_size <=
6939             offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
6940                 mutex_unlock(&bp->hwrm_cmd_lock);
6941                 bp->pri2cos_valid = 0;
6942                 return rc;
6943         }
6944
6945         bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
6946         req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
6947
6948         rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
6949         if (!rc) {
6950                 struct hwrm_queue_pri2cos_qcfg_output *resp2;
6951                 u8 *pri2cos;
6952                 int i, j;
6953
6954                 resp2 = bp->hwrm_cmd_resp_addr;
6955                 pri2cos = &resp2->pri0_cos_queue_id;
6956                 for (i = 0; i < 8; i++) {
6957                         u8 queue_id = pri2cos[i];
6958
6959                         for (j = 0; j < bp->max_q; j++) {
6960                                 if (bp->q_ids[j] == queue_id)
6961                                         bp->pri2cos[i] = j;
6962                         }
6963                 }
6964                 bp->pri2cos_valid = 1;
6965         }
6966         mutex_unlock(&bp->hwrm_cmd_lock);
6967         return rc;
6968 }
6969
6970 static int bnxt_hwrm_pcie_qstats(struct bnxt *bp)
6971 {
6972         struct hwrm_pcie_qstats_input req = {0};
6973
6974         if (!(bp->flags & BNXT_FLAG_PCIE_STATS))
6975                 return 0;
6976
6977         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1);
6978         req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats));
6979         req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map);
6980         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6981 }
6982
6983 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
6984 {
6985         if (bp->vxlan_port_cnt) {
6986                 bnxt_hwrm_tunnel_dst_port_free(
6987                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6988         }
6989         bp->vxlan_port_cnt = 0;
6990         if (bp->nge_port_cnt) {
6991                 bnxt_hwrm_tunnel_dst_port_free(
6992                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6993         }
6994         bp->nge_port_cnt = 0;
6995 }
6996
6997 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
6998 {
6999         int rc, i;
7000         u32 tpa_flags = 0;
7001
7002         if (set_tpa)
7003                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
7004         for (i = 0; i < bp->nr_vnics; i++) {
7005                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
7006                 if (rc) {
7007                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
7008                                    i, rc);
7009                         return rc;
7010                 }
7011         }
7012         return 0;
7013 }
7014
7015 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
7016 {
7017         int i;
7018
7019         for (i = 0; i < bp->nr_vnics; i++)
7020                 bnxt_hwrm_vnic_set_rss(bp, i, false);
7021 }
7022
7023 static void bnxt_clear_vnic(struct bnxt *bp)
7024 {
7025         if (!bp->vnic_info)
7026                 return;
7027
7028         bnxt_hwrm_clear_vnic_filter(bp);
7029         if (!(bp->flags & BNXT_FLAG_CHIP_P5)) {
7030                 /* clear all RSS setting before free vnic ctx */
7031                 bnxt_hwrm_clear_vnic_rss(bp);
7032                 bnxt_hwrm_vnic_ctx_free(bp);
7033         }
7034         /* before free the vnic, undo the vnic tpa settings */
7035         if (bp->flags & BNXT_FLAG_TPA)
7036                 bnxt_set_tpa(bp, false);
7037         bnxt_hwrm_vnic_free(bp);
7038         if (bp->flags & BNXT_FLAG_CHIP_P5)
7039                 bnxt_hwrm_vnic_ctx_free(bp);
7040 }
7041
7042 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
7043                                     bool irq_re_init)
7044 {
7045         bnxt_clear_vnic(bp);
7046         bnxt_hwrm_ring_free(bp, close_path);
7047         bnxt_hwrm_ring_grp_free(bp);
7048         if (irq_re_init) {
7049                 bnxt_hwrm_stat_ctx_free(bp);
7050                 bnxt_hwrm_free_tunnel_ports(bp);
7051         }
7052 }
7053
7054 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
7055 {
7056         struct hwrm_func_cfg_input req = {0};
7057         int rc;
7058
7059         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
7060         req.fid = cpu_to_le16(0xffff);
7061         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
7062         if (br_mode == BRIDGE_MODE_VEB)
7063                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
7064         else if (br_mode == BRIDGE_MODE_VEPA)
7065                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
7066         else
7067                 return -EINVAL;
7068         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7069         if (rc)
7070                 rc = -EIO;
7071         return rc;
7072 }
7073
7074 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
7075 {
7076         struct hwrm_func_cfg_input req = {0};
7077         int rc;
7078
7079         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
7080                 return 0;
7081
7082         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
7083         req.fid = cpu_to_le16(0xffff);
7084         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
7085         req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
7086         if (size == 128)
7087                 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
7088
7089         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7090         if (rc)
7091                 rc = -EIO;
7092         return rc;
7093 }
7094
7095 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7096 {
7097         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
7098         int rc;
7099
7100         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
7101                 goto skip_rss_ctx;
7102
7103         /* allocate context for vnic */
7104         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
7105         if (rc) {
7106                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7107                            vnic_id, rc);
7108                 goto vnic_setup_err;
7109         }
7110         bp->rsscos_nr_ctxs++;
7111
7112         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7113                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
7114                 if (rc) {
7115                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
7116                                    vnic_id, rc);
7117                         goto vnic_setup_err;
7118                 }
7119                 bp->rsscos_nr_ctxs++;
7120         }
7121
7122 skip_rss_ctx:
7123         /* configure default vnic, ring grp */
7124         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
7125         if (rc) {
7126                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
7127                            vnic_id, rc);
7128                 goto vnic_setup_err;
7129         }
7130
7131         /* Enable RSS hashing on vnic */
7132         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
7133         if (rc) {
7134                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
7135                            vnic_id, rc);
7136                 goto vnic_setup_err;
7137         }
7138
7139         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
7140                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
7141                 if (rc) {
7142                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
7143                                    vnic_id, rc);
7144                 }
7145         }
7146
7147 vnic_setup_err:
7148         return rc;
7149 }
7150
7151 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
7152 {
7153         int rc, i, nr_ctxs;
7154
7155         nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
7156         for (i = 0; i < nr_ctxs; i++) {
7157                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
7158                 if (rc) {
7159                         netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
7160                                    vnic_id, i, rc);
7161                         break;
7162                 }
7163                 bp->rsscos_nr_ctxs++;
7164         }
7165         if (i < nr_ctxs)
7166                 return -ENOMEM;
7167
7168         rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
7169         if (rc) {
7170                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
7171                            vnic_id, rc);
7172                 return rc;
7173         }
7174         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
7175         if (rc) {
7176                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
7177                            vnic_id, rc);
7178                 return rc;
7179         }
7180         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
7181                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
7182                 if (rc) {
7183                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
7184                                    vnic_id, rc);
7185                 }
7186         }
7187         return rc;
7188 }
7189
7190 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7191 {
7192         if (bp->flags & BNXT_FLAG_CHIP_P5)
7193                 return __bnxt_setup_vnic_p5(bp, vnic_id);
7194         else
7195                 return __bnxt_setup_vnic(bp, vnic_id);
7196 }
7197
7198 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
7199 {
7200 #ifdef CONFIG_RFS_ACCEL
7201         int i, rc = 0;
7202
7203         if (bp->flags & BNXT_FLAG_CHIP_P5)
7204                 return 0;
7205
7206         for (i = 0; i < bp->rx_nr_rings; i++) {
7207                 struct bnxt_vnic_info *vnic;
7208                 u16 vnic_id = i + 1;
7209                 u16 ring_id = i;
7210
7211                 if (vnic_id >= bp->nr_vnics)
7212                         break;
7213
7214                 vnic = &bp->vnic_info[vnic_id];
7215                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
7216                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7217                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
7218                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
7219                 if (rc) {
7220                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7221                                    vnic_id, rc);
7222                         break;
7223                 }
7224                 rc = bnxt_setup_vnic(bp, vnic_id);
7225                 if (rc)
7226                         break;
7227         }
7228         return rc;
7229 #else
7230         return 0;
7231 #endif
7232 }
7233
7234 /* Allow PF and VF with default VLAN to be in promiscuous mode */
7235 static bool bnxt_promisc_ok(struct bnxt *bp)
7236 {
7237 #ifdef CONFIG_BNXT_SRIOV
7238         if (BNXT_VF(bp) && !bp->vf.vlan)
7239                 return false;
7240 #endif
7241         return true;
7242 }
7243
7244 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
7245 {
7246         unsigned int rc = 0;
7247
7248         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
7249         if (rc) {
7250                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7251                            rc);
7252                 return rc;
7253         }
7254
7255         rc = bnxt_hwrm_vnic_cfg(bp, 1);
7256         if (rc) {
7257                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7258                            rc);
7259                 return rc;
7260         }
7261         return rc;
7262 }
7263
7264 static int bnxt_cfg_rx_mode(struct bnxt *);
7265 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
7266
7267 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
7268 {
7269         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7270         int rc = 0;
7271         unsigned int rx_nr_rings = bp->rx_nr_rings;
7272
7273         if (irq_re_init) {
7274                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
7275                 if (rc) {
7276                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
7277                                    rc);
7278                         goto err_out;
7279                 }
7280         }
7281
7282         rc = bnxt_hwrm_ring_alloc(bp);
7283         if (rc) {
7284                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
7285                 goto err_out;
7286         }
7287
7288         rc = bnxt_hwrm_ring_grp_alloc(bp);
7289         if (rc) {
7290                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
7291                 goto err_out;
7292         }
7293
7294         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7295                 rx_nr_rings--;
7296
7297         /* default vnic 0 */
7298         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
7299         if (rc) {
7300                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
7301                 goto err_out;
7302         }
7303
7304         rc = bnxt_setup_vnic(bp, 0);
7305         if (rc)
7306                 goto err_out;
7307
7308         if (bp->flags & BNXT_FLAG_RFS) {
7309                 rc = bnxt_alloc_rfs_vnics(bp);
7310                 if (rc)
7311                         goto err_out;
7312         }
7313
7314         if (bp->flags & BNXT_FLAG_TPA) {
7315                 rc = bnxt_set_tpa(bp, true);
7316                 if (rc)
7317                         goto err_out;
7318         }
7319
7320         if (BNXT_VF(bp))
7321                 bnxt_update_vf_mac(bp);
7322
7323         /* Filter for default vnic 0 */
7324         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
7325         if (rc) {
7326                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
7327                 goto err_out;
7328         }
7329         vnic->uc_filter_count = 1;
7330
7331         vnic->rx_mask = 0;
7332         if (bp->dev->flags & IFF_BROADCAST)
7333                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7334
7335         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7336                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7337
7338         if (bp->dev->flags & IFF_ALLMULTI) {
7339                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7340                 vnic->mc_list_count = 0;
7341         } else {
7342                 u32 mask = 0;
7343
7344                 bnxt_mc_list_updated(bp, &mask);
7345                 vnic->rx_mask |= mask;
7346         }
7347
7348         rc = bnxt_cfg_rx_mode(bp);
7349         if (rc)
7350                 goto err_out;
7351
7352         rc = bnxt_hwrm_set_coal(bp);
7353         if (rc)
7354                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
7355                                 rc);
7356
7357         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7358                 rc = bnxt_setup_nitroa0_vnic(bp);
7359                 if (rc)
7360                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
7361                                    rc);
7362         }
7363
7364         if (BNXT_VF(bp)) {
7365                 bnxt_hwrm_func_qcfg(bp);
7366                 netdev_update_features(bp->dev);
7367         }
7368
7369         return 0;
7370
7371 err_out:
7372         bnxt_hwrm_resource_free(bp, 0, true);
7373
7374         return rc;
7375 }
7376
7377 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
7378 {
7379         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
7380         return 0;
7381 }
7382
7383 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
7384 {
7385         bnxt_init_cp_rings(bp);
7386         bnxt_init_rx_rings(bp);
7387         bnxt_init_tx_rings(bp);
7388         bnxt_init_ring_grps(bp, irq_re_init);
7389         bnxt_init_vnics(bp);
7390
7391         return bnxt_init_chip(bp, irq_re_init);
7392 }
7393
7394 static int bnxt_set_real_num_queues(struct bnxt *bp)
7395 {
7396         int rc;
7397         struct net_device *dev = bp->dev;
7398
7399         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
7400                                           bp->tx_nr_rings_xdp);
7401         if (rc)
7402                 return rc;
7403
7404         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
7405         if (rc)
7406                 return rc;
7407
7408 #ifdef CONFIG_RFS_ACCEL
7409         if (bp->flags & BNXT_FLAG_RFS)
7410                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
7411 #endif
7412
7413         return rc;
7414 }
7415
7416 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
7417                            bool shared)
7418 {
7419         int _rx = *rx, _tx = *tx;
7420
7421         if (shared) {
7422                 *rx = min_t(int, _rx, max);
7423                 *tx = min_t(int, _tx, max);
7424         } else {
7425                 if (max < 2)
7426                         return -ENOMEM;
7427
7428                 while (_rx + _tx > max) {
7429                         if (_rx > _tx && _rx > 1)
7430                                 _rx--;
7431                         else if (_tx > 1)
7432                                 _tx--;
7433                 }
7434                 *rx = _rx;
7435                 *tx = _tx;
7436         }
7437         return 0;
7438 }
7439
7440 static void bnxt_setup_msix(struct bnxt *bp)
7441 {
7442         const int len = sizeof(bp->irq_tbl[0].name);
7443         struct net_device *dev = bp->dev;
7444         int tcs, i;
7445
7446         tcs = netdev_get_num_tc(dev);
7447         if (tcs > 1) {
7448                 int i, off, count;
7449
7450                 for (i = 0; i < tcs; i++) {
7451                         count = bp->tx_nr_rings_per_tc;
7452                         off = i * count;
7453                         netdev_set_tc_queue(dev, i, count, off);
7454                 }
7455         }
7456
7457         for (i = 0; i < bp->cp_nr_rings; i++) {
7458                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7459                 char *attr;
7460
7461                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7462                         attr = "TxRx";
7463                 else if (i < bp->rx_nr_rings)
7464                         attr = "rx";
7465                 else
7466                         attr = "tx";
7467
7468                 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
7469                          attr, i);
7470                 bp->irq_tbl[map_idx].handler = bnxt_msix;
7471         }
7472 }
7473
7474 static void bnxt_setup_inta(struct bnxt *bp)
7475 {
7476         const int len = sizeof(bp->irq_tbl[0].name);
7477
7478         if (netdev_get_num_tc(bp->dev))
7479                 netdev_reset_tc(bp->dev);
7480
7481         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
7482                  0);
7483         bp->irq_tbl[0].handler = bnxt_inta;
7484 }
7485
7486 static int bnxt_setup_int_mode(struct bnxt *bp)
7487 {
7488         int rc;
7489
7490         if (bp->flags & BNXT_FLAG_USING_MSIX)
7491                 bnxt_setup_msix(bp);
7492         else
7493                 bnxt_setup_inta(bp);
7494
7495         rc = bnxt_set_real_num_queues(bp);
7496         return rc;
7497 }
7498
7499 #ifdef CONFIG_RFS_ACCEL
7500 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
7501 {
7502         return bp->hw_resc.max_rsscos_ctxs;
7503 }
7504
7505 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
7506 {
7507         return bp->hw_resc.max_vnics;
7508 }
7509 #endif
7510
7511 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
7512 {
7513         return bp->hw_resc.max_stat_ctxs;
7514 }
7515
7516 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
7517 {
7518         return bp->hw_resc.max_cp_rings;
7519 }
7520
7521 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
7522 {
7523         unsigned int cp = bp->hw_resc.max_cp_rings;
7524
7525         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7526                 cp -= bnxt_get_ulp_msix_num(bp);
7527
7528         return cp;
7529 }
7530
7531 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
7532 {
7533         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7534
7535         if (bp->flags & BNXT_FLAG_CHIP_P5)
7536                 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
7537
7538         return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
7539 }
7540
7541 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
7542 {
7543         bp->hw_resc.max_irqs = max_irqs;
7544 }
7545
7546 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
7547 {
7548         unsigned int cp;
7549
7550         cp = bnxt_get_max_func_cp_rings_for_en(bp);
7551         if (bp->flags & BNXT_FLAG_CHIP_P5)
7552                 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
7553         else
7554                 return cp - bp->cp_nr_rings;
7555 }
7556
7557 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
7558 {
7559         return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp);
7560 }
7561
7562 int bnxt_get_avail_msix(struct bnxt *bp, int num)
7563 {
7564         int max_cp = bnxt_get_max_func_cp_rings(bp);
7565         int max_irq = bnxt_get_max_func_irqs(bp);
7566         int total_req = bp->cp_nr_rings + num;
7567         int max_idx, avail_msix;
7568
7569         max_idx = bp->total_irqs;
7570         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7571                 max_idx = min_t(int, bp->total_irqs, max_cp);
7572         avail_msix = max_idx - bp->cp_nr_rings;
7573         if (!BNXT_NEW_RM(bp) || avail_msix >= num)
7574                 return avail_msix;
7575
7576         if (max_irq < total_req) {
7577                 num = max_irq - bp->cp_nr_rings;
7578                 if (num <= 0)
7579                         return 0;
7580         }
7581         return num;
7582 }
7583
7584 static int bnxt_get_num_msix(struct bnxt *bp)
7585 {
7586         if (!BNXT_NEW_RM(bp))
7587                 return bnxt_get_max_func_irqs(bp);
7588
7589         return bnxt_nq_rings_in_use(bp);
7590 }
7591
7592 static int bnxt_init_msix(struct bnxt *bp)
7593 {
7594         int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
7595         struct msix_entry *msix_ent;
7596
7597         total_vecs = bnxt_get_num_msix(bp);
7598         max = bnxt_get_max_func_irqs(bp);
7599         if (total_vecs > max)
7600                 total_vecs = max;
7601
7602         if (!total_vecs)
7603                 return 0;
7604
7605         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
7606         if (!msix_ent)
7607                 return -ENOMEM;
7608
7609         for (i = 0; i < total_vecs; i++) {
7610                 msix_ent[i].entry = i;
7611                 msix_ent[i].vector = 0;
7612         }
7613
7614         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
7615                 min = 2;
7616
7617         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
7618         ulp_msix = bnxt_get_ulp_msix_num(bp);
7619         if (total_vecs < 0 || total_vecs < ulp_msix) {
7620                 rc = -ENODEV;
7621                 goto msix_setup_exit;
7622         }
7623
7624         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
7625         if (bp->irq_tbl) {
7626                 for (i = 0; i < total_vecs; i++)
7627                         bp->irq_tbl[i].vector = msix_ent[i].vector;
7628
7629                 bp->total_irqs = total_vecs;
7630                 /* Trim rings based upon num of vectors allocated */
7631                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
7632                                      total_vecs - ulp_msix, min == 1);
7633                 if (rc)
7634                         goto msix_setup_exit;
7635
7636                 bp->cp_nr_rings = (min == 1) ?
7637                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7638                                   bp->tx_nr_rings + bp->rx_nr_rings;
7639
7640         } else {
7641                 rc = -ENOMEM;
7642                 goto msix_setup_exit;
7643         }
7644         bp->flags |= BNXT_FLAG_USING_MSIX;
7645         kfree(msix_ent);
7646         return 0;
7647
7648 msix_setup_exit:
7649         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
7650         kfree(bp->irq_tbl);
7651         bp->irq_tbl = NULL;
7652         pci_disable_msix(bp->pdev);
7653         kfree(msix_ent);
7654         return rc;
7655 }
7656
7657 static int bnxt_init_inta(struct bnxt *bp)
7658 {
7659         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7660         if (!bp->irq_tbl)
7661                 return -ENOMEM;
7662
7663         bp->total_irqs = 1;
7664         bp->rx_nr_rings = 1;
7665         bp->tx_nr_rings = 1;
7666         bp->cp_nr_rings = 1;
7667         bp->flags |= BNXT_FLAG_SHARED_RINGS;
7668         bp->irq_tbl[0].vector = bp->pdev->irq;
7669         return 0;
7670 }
7671
7672 static int bnxt_init_int_mode(struct bnxt *bp)
7673 {
7674         int rc = 0;
7675
7676         if (bp->flags & BNXT_FLAG_MSIX_CAP)
7677                 rc = bnxt_init_msix(bp);
7678
7679         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
7680                 /* fallback to INTA */
7681                 rc = bnxt_init_inta(bp);
7682         }
7683         return rc;
7684 }
7685
7686 static void bnxt_clear_int_mode(struct bnxt *bp)
7687 {
7688         if (bp->flags & BNXT_FLAG_USING_MSIX)
7689                 pci_disable_msix(bp->pdev);
7690
7691         kfree(bp->irq_tbl);
7692         bp->irq_tbl = NULL;
7693         bp->flags &= ~BNXT_FLAG_USING_MSIX;
7694 }
7695
7696 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
7697 {
7698         int tcs = netdev_get_num_tc(bp->dev);
7699         bool irq_cleared = false;
7700         int rc;
7701
7702         if (!bnxt_need_reserve_rings(bp))
7703                 return 0;
7704
7705         if (irq_re_init && BNXT_NEW_RM(bp) &&
7706             bnxt_get_num_msix(bp) != bp->total_irqs) {
7707                 bnxt_ulp_irq_stop(bp);
7708                 bnxt_clear_int_mode(bp);
7709                 irq_cleared = true;
7710         }
7711         rc = __bnxt_reserve_rings(bp);
7712         if (irq_cleared) {
7713                 if (!rc)
7714                         rc = bnxt_init_int_mode(bp);
7715                 bnxt_ulp_irq_restart(bp, rc);
7716         }
7717         if (rc) {
7718                 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
7719                 return rc;
7720         }
7721         if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
7722                 netdev_err(bp->dev, "tx ring reservation failure\n");
7723                 netdev_reset_tc(bp->dev);
7724                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7725                 return -ENOMEM;
7726         }
7727         return 0;
7728 }
7729
7730 static void bnxt_free_irq(struct bnxt *bp)
7731 {
7732         struct bnxt_irq *irq;
7733         int i;
7734
7735 #ifdef CONFIG_RFS_ACCEL
7736         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
7737         bp->dev->rx_cpu_rmap = NULL;
7738 #endif
7739         if (!bp->irq_tbl || !bp->bnapi)
7740                 return;
7741
7742         for (i = 0; i < bp->cp_nr_rings; i++) {
7743                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7744
7745                 irq = &bp->irq_tbl[map_idx];
7746                 if (irq->requested) {
7747                         if (irq->have_cpumask) {
7748                                 irq_set_affinity_hint(irq->vector, NULL);
7749                                 free_cpumask_var(irq->cpu_mask);
7750                                 irq->have_cpumask = 0;
7751                         }
7752                         free_irq(irq->vector, bp->bnapi[i]);
7753                 }
7754
7755                 irq->requested = 0;
7756         }
7757 }
7758
7759 static int bnxt_request_irq(struct bnxt *bp)
7760 {
7761         int i, j, rc = 0;
7762         unsigned long flags = 0;
7763 #ifdef CONFIG_RFS_ACCEL
7764         struct cpu_rmap *rmap;
7765 #endif
7766
7767         rc = bnxt_setup_int_mode(bp);
7768         if (rc) {
7769                 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
7770                            rc);
7771                 return rc;
7772         }
7773 #ifdef CONFIG_RFS_ACCEL
7774         rmap = bp->dev->rx_cpu_rmap;
7775 #endif
7776         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
7777                 flags = IRQF_SHARED;
7778
7779         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
7780                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7781                 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
7782
7783 #ifdef CONFIG_RFS_ACCEL
7784                 if (rmap && bp->bnapi[i]->rx_ring) {
7785                         rc = irq_cpu_rmap_add(rmap, irq->vector);
7786                         if (rc)
7787                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
7788                                             j);
7789                         j++;
7790                 }
7791 #endif
7792                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
7793                                  bp->bnapi[i]);
7794                 if (rc)
7795                         break;
7796
7797                 irq->requested = 1;
7798
7799                 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
7800                         int numa_node = dev_to_node(&bp->pdev->dev);
7801
7802                         irq->have_cpumask = 1;
7803                         cpumask_set_cpu(cpumask_local_spread(i, numa_node),
7804                                         irq->cpu_mask);
7805                         rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
7806                         if (rc) {
7807                                 netdev_warn(bp->dev,
7808                                             "Set affinity failed, IRQ = %d\n",
7809                                             irq->vector);
7810                                 break;
7811                         }
7812                 }
7813         }
7814         return rc;
7815 }
7816
7817 static void bnxt_del_napi(struct bnxt *bp)
7818 {
7819         int i;
7820
7821         if (!bp->bnapi)
7822                 return;
7823
7824         for (i = 0; i < bp->cp_nr_rings; i++) {
7825                 struct bnxt_napi *bnapi = bp->bnapi[i];
7826
7827                 napi_hash_del(&bnapi->napi);
7828                 netif_napi_del(&bnapi->napi);
7829         }
7830         /* We called napi_hash_del() before netif_napi_del(), we need
7831          * to respect an RCU grace period before freeing napi structures.
7832          */
7833         synchronize_net();
7834 }
7835
7836 static void bnxt_init_napi(struct bnxt *bp)
7837 {
7838         int i;
7839         unsigned int cp_nr_rings = bp->cp_nr_rings;
7840         struct bnxt_napi *bnapi;
7841
7842         if (bp->flags & BNXT_FLAG_USING_MSIX) {
7843                 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
7844
7845                 if (bp->flags & BNXT_FLAG_CHIP_P5)
7846                         poll_fn = bnxt_poll_p5;
7847                 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7848                         cp_nr_rings--;
7849                 for (i = 0; i < cp_nr_rings; i++) {
7850                         bnapi = bp->bnapi[i];
7851                         netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
7852                 }
7853                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7854                         bnapi = bp->bnapi[cp_nr_rings];
7855                         netif_napi_add(bp->dev, &bnapi->napi,
7856                                        bnxt_poll_nitroa0, 64);
7857                 }
7858         } else {
7859                 bnapi = bp->bnapi[0];
7860                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
7861         }
7862 }
7863
7864 static void bnxt_disable_napi(struct bnxt *bp)
7865 {
7866         int i;
7867
7868         if (!bp->bnapi)
7869                 return;
7870
7871         for (i = 0; i < bp->cp_nr_rings; i++) {
7872                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7873
7874                 if (bp->bnapi[i]->rx_ring)
7875                         cancel_work_sync(&cpr->dim.work);
7876
7877                 napi_disable(&bp->bnapi[i]->napi);
7878         }
7879 }
7880
7881 static void bnxt_enable_napi(struct bnxt *bp)
7882 {
7883         int i;
7884
7885         for (i = 0; i < bp->cp_nr_rings; i++) {
7886                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7887                 bp->bnapi[i]->in_reset = false;
7888
7889                 if (bp->bnapi[i]->rx_ring) {
7890                         INIT_WORK(&cpr->dim.work, bnxt_dim_work);
7891                         cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
7892                 }
7893                 napi_enable(&bp->bnapi[i]->napi);
7894         }
7895 }
7896
7897 void bnxt_tx_disable(struct bnxt *bp)
7898 {
7899         int i;
7900         struct bnxt_tx_ring_info *txr;
7901
7902         if (bp->tx_ring) {
7903                 for (i = 0; i < bp->tx_nr_rings; i++) {
7904                         txr = &bp->tx_ring[i];
7905                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
7906                 }
7907         }
7908         /* Stop all TX queues */
7909         netif_tx_disable(bp->dev);
7910         netif_carrier_off(bp->dev);
7911 }
7912
7913 void bnxt_tx_enable(struct bnxt *bp)
7914 {
7915         int i;
7916         struct bnxt_tx_ring_info *txr;
7917
7918         for (i = 0; i < bp->tx_nr_rings; i++) {
7919                 txr = &bp->tx_ring[i];
7920                 txr->dev_state = 0;
7921         }
7922         netif_tx_wake_all_queues(bp->dev);
7923         if (bp->link_info.link_up)
7924                 netif_carrier_on(bp->dev);
7925 }
7926
7927 static void bnxt_report_link(struct bnxt *bp)
7928 {
7929         if (bp->link_info.link_up) {
7930                 const char *duplex;
7931                 const char *flow_ctrl;
7932                 u32 speed;
7933                 u16 fec;
7934
7935                 netif_carrier_on(bp->dev);
7936                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
7937                         duplex = "full";
7938                 else
7939                         duplex = "half";
7940                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
7941                         flow_ctrl = "ON - receive & transmit";
7942                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
7943                         flow_ctrl = "ON - transmit";
7944                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
7945                         flow_ctrl = "ON - receive";
7946                 else
7947                         flow_ctrl = "none";
7948                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
7949                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
7950                             speed, duplex, flow_ctrl);
7951                 if (bp->flags & BNXT_FLAG_EEE_CAP)
7952                         netdev_info(bp->dev, "EEE is %s\n",
7953                                     bp->eee.eee_active ? "active" :
7954                                                          "not active");
7955                 fec = bp->link_info.fec_cfg;
7956                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
7957                         netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
7958                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
7959                                     (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
7960                                      (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
7961         } else {
7962                 netif_carrier_off(bp->dev);
7963                 netdev_err(bp->dev, "NIC Link is Down\n");
7964         }
7965 }
7966
7967 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
7968 {
7969         int rc = 0;
7970         struct hwrm_port_phy_qcaps_input req = {0};
7971         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7972         struct bnxt_link_info *link_info = &bp->link_info;
7973
7974         if (bp->hwrm_spec_code < 0x10201)
7975                 return 0;
7976
7977         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
7978
7979         mutex_lock(&bp->hwrm_cmd_lock);
7980         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7981         if (rc)
7982                 goto hwrm_phy_qcaps_exit;
7983
7984         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
7985                 struct ethtool_eee *eee = &bp->eee;
7986                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
7987
7988                 bp->flags |= BNXT_FLAG_EEE_CAP;
7989                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7990                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
7991                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
7992                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
7993                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
7994         }
7995         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
7996                 if (bp->test_info)
7997                         bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
7998         }
7999         if (resp->supported_speeds_auto_mode)
8000                 link_info->support_auto_speeds =
8001                         le16_to_cpu(resp->supported_speeds_auto_mode);
8002
8003         bp->port_count = resp->port_cnt;
8004
8005 hwrm_phy_qcaps_exit:
8006         mutex_unlock(&bp->hwrm_cmd_lock);
8007         return rc;
8008 }
8009
8010 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
8011 {
8012         int rc = 0;
8013         struct bnxt_link_info *link_info = &bp->link_info;
8014         struct hwrm_port_phy_qcfg_input req = {0};
8015         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8016         u8 link_up = link_info->link_up;
8017         u16 diff;
8018
8019         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
8020
8021         mutex_lock(&bp->hwrm_cmd_lock);
8022         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8023         if (rc) {
8024                 mutex_unlock(&bp->hwrm_cmd_lock);
8025                 return rc;
8026         }
8027
8028         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
8029         link_info->phy_link_status = resp->link;
8030         link_info->duplex = resp->duplex_cfg;
8031         if (bp->hwrm_spec_code >= 0x10800)
8032                 link_info->duplex = resp->duplex_state;
8033         link_info->pause = resp->pause;
8034         link_info->auto_mode = resp->auto_mode;
8035         link_info->auto_pause_setting = resp->auto_pause;
8036         link_info->lp_pause = resp->link_partner_adv_pause;
8037         link_info->force_pause_setting = resp->force_pause;
8038         link_info->duplex_setting = resp->duplex_cfg;
8039         if (link_info->phy_link_status == BNXT_LINK_LINK)
8040                 link_info->link_speed = le16_to_cpu(resp->link_speed);
8041         else
8042                 link_info->link_speed = 0;
8043         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
8044         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
8045         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
8046         link_info->lp_auto_link_speeds =
8047                 le16_to_cpu(resp->link_partner_adv_speeds);
8048         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
8049         link_info->phy_ver[0] = resp->phy_maj;
8050         link_info->phy_ver[1] = resp->phy_min;
8051         link_info->phy_ver[2] = resp->phy_bld;
8052         link_info->media_type = resp->media_type;
8053         link_info->phy_type = resp->phy_type;
8054         link_info->transceiver = resp->xcvr_pkg_type;
8055         link_info->phy_addr = resp->eee_config_phy_addr &
8056                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
8057         link_info->module_status = resp->module_status;
8058
8059         if (bp->flags & BNXT_FLAG_EEE_CAP) {
8060                 struct ethtool_eee *eee = &bp->eee;
8061                 u16 fw_speeds;
8062
8063                 eee->eee_active = 0;
8064                 if (resp->eee_config_phy_addr &
8065                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
8066                         eee->eee_active = 1;
8067                         fw_speeds = le16_to_cpu(
8068                                 resp->link_partner_adv_eee_link_speed_mask);
8069                         eee->lp_advertised =
8070                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
8071                 }
8072
8073                 /* Pull initial EEE config */
8074                 if (!chng_link_state) {
8075                         if (resp->eee_config_phy_addr &
8076                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
8077                                 eee->eee_enabled = 1;
8078
8079                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
8080                         eee->advertised =
8081                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
8082
8083                         if (resp->eee_config_phy_addr &
8084                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
8085                                 __le32 tmr;
8086
8087                                 eee->tx_lpi_enabled = 1;
8088                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
8089                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
8090                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
8091                         }
8092                 }
8093         }
8094
8095         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
8096         if (bp->hwrm_spec_code >= 0x10504)
8097                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
8098
8099         /* TODO: need to add more logic to report VF link */
8100         if (chng_link_state) {
8101                 if (link_info->phy_link_status == BNXT_LINK_LINK)
8102                         link_info->link_up = 1;
8103                 else
8104                         link_info->link_up = 0;
8105                 if (link_up != link_info->link_up)
8106                         bnxt_report_link(bp);
8107         } else {
8108                 /* alwasy link down if not require to update link state */
8109                 link_info->link_up = 0;
8110         }
8111         mutex_unlock(&bp->hwrm_cmd_lock);
8112
8113         if (!BNXT_SINGLE_PF(bp))
8114                 return 0;
8115
8116         diff = link_info->support_auto_speeds ^ link_info->advertising;
8117         if ((link_info->support_auto_speeds | diff) !=
8118             link_info->support_auto_speeds) {
8119                 /* An advertised speed is no longer supported, so we need to
8120                  * update the advertisement settings.  Caller holds RTNL
8121                  * so we can modify link settings.
8122                  */
8123                 link_info->advertising = link_info->support_auto_speeds;
8124                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
8125                         bnxt_hwrm_set_link_setting(bp, true, false);
8126         }
8127         return 0;
8128 }
8129
8130 static void bnxt_get_port_module_status(struct bnxt *bp)
8131 {
8132         struct bnxt_link_info *link_info = &bp->link_info;
8133         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
8134         u8 module_status;
8135
8136         if (bnxt_update_link(bp, true))
8137                 return;
8138
8139         module_status = link_info->module_status;
8140         switch (module_status) {
8141         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
8142         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
8143         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
8144                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
8145                             bp->pf.port_id);
8146                 if (bp->hwrm_spec_code >= 0x10201) {
8147                         netdev_warn(bp->dev, "Module part number %s\n",
8148                                     resp->phy_vendor_partnumber);
8149                 }
8150                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
8151                         netdev_warn(bp->dev, "TX is disabled\n");
8152                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
8153                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
8154         }
8155 }
8156
8157 static void
8158 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
8159 {
8160         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
8161                 if (bp->hwrm_spec_code >= 0x10201)
8162                         req->auto_pause =
8163                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
8164                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
8165                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
8166                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
8167                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
8168                 req->enables |=
8169                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
8170         } else {
8171                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
8172                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
8173                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
8174                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
8175                 req->enables |=
8176                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
8177                 if (bp->hwrm_spec_code >= 0x10201) {
8178                         req->auto_pause = req->force_pause;
8179                         req->enables |= cpu_to_le32(
8180                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
8181                 }
8182         }
8183 }
8184
8185 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
8186                                       struct hwrm_port_phy_cfg_input *req)
8187 {
8188         u8 autoneg = bp->link_info.autoneg;
8189         u16 fw_link_speed = bp->link_info.req_link_speed;
8190         u16 advertising = bp->link_info.advertising;
8191
8192         if (autoneg & BNXT_AUTONEG_SPEED) {
8193                 req->auto_mode |=
8194                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
8195
8196                 req->enables |= cpu_to_le32(
8197                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
8198                 req->auto_link_speed_mask = cpu_to_le16(advertising);
8199
8200                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
8201                 req->flags |=
8202                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
8203         } else {
8204                 req->force_link_speed = cpu_to_le16(fw_link_speed);
8205                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
8206         }
8207
8208         /* tell chimp that the setting takes effect immediately */
8209         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
8210 }
8211
8212 int bnxt_hwrm_set_pause(struct bnxt *bp)
8213 {
8214         struct hwrm_port_phy_cfg_input req = {0};
8215         int rc;
8216
8217         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8218         bnxt_hwrm_set_pause_common(bp, &req);
8219
8220         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
8221             bp->link_info.force_link_chng)
8222                 bnxt_hwrm_set_link_common(bp, &req);
8223
8224         mutex_lock(&bp->hwrm_cmd_lock);
8225         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8226         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
8227                 /* since changing of pause setting doesn't trigger any link
8228                  * change event, the driver needs to update the current pause
8229                  * result upon successfully return of the phy_cfg command
8230                  */
8231                 bp->link_info.pause =
8232                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
8233                 bp->link_info.auto_pause_setting = 0;
8234                 if (!bp->link_info.force_link_chng)
8235                         bnxt_report_link(bp);
8236         }
8237         bp->link_info.force_link_chng = false;
8238         mutex_unlock(&bp->hwrm_cmd_lock);
8239         return rc;
8240 }
8241
8242 static void bnxt_hwrm_set_eee(struct bnxt *bp,
8243                               struct hwrm_port_phy_cfg_input *req)
8244 {
8245         struct ethtool_eee *eee = &bp->eee;
8246
8247         if (eee->eee_enabled) {
8248                 u16 eee_speeds;
8249                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
8250
8251                 if (eee->tx_lpi_enabled)
8252                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
8253                 else
8254                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
8255
8256                 req->flags |= cpu_to_le32(flags);
8257                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
8258                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
8259                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
8260         } else {
8261                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
8262         }
8263 }
8264
8265 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
8266 {
8267         struct hwrm_port_phy_cfg_input req = {0};
8268
8269         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8270         if (set_pause)
8271                 bnxt_hwrm_set_pause_common(bp, &req);
8272
8273         bnxt_hwrm_set_link_common(bp, &req);
8274
8275         if (set_eee)
8276                 bnxt_hwrm_set_eee(bp, &req);
8277         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8278 }
8279
8280 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
8281 {
8282         struct hwrm_port_phy_cfg_input req = {0};
8283
8284         if (!BNXT_SINGLE_PF(bp))
8285                 return 0;
8286
8287         if (pci_num_vf(bp->pdev))
8288                 return 0;
8289
8290         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8291         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
8292         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8293 }
8294
8295 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
8296 {
8297         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
8298         struct hwrm_func_drv_if_change_input req = {0};
8299         bool resc_reinit = false;
8300         int rc;
8301
8302         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
8303                 return 0;
8304
8305         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
8306         if (up)
8307                 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
8308         mutex_lock(&bp->hwrm_cmd_lock);
8309         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8310         if (!rc && (resp->flags &
8311                     cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
8312                 resc_reinit = true;
8313         mutex_unlock(&bp->hwrm_cmd_lock);
8314
8315         if (up && resc_reinit && BNXT_NEW_RM(bp)) {
8316                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8317
8318                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
8319                 hw_resc->resv_cp_rings = 0;
8320                 hw_resc->resv_stat_ctxs = 0;
8321                 hw_resc->resv_irqs = 0;
8322                 hw_resc->resv_tx_rings = 0;
8323                 hw_resc->resv_rx_rings = 0;
8324                 hw_resc->resv_hw_ring_grps = 0;
8325                 hw_resc->resv_vnics = 0;
8326                 bp->tx_nr_rings = 0;
8327                 bp->rx_nr_rings = 0;
8328         }
8329         return rc;
8330 }
8331
8332 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
8333 {
8334         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
8335         struct hwrm_port_led_qcaps_input req = {0};
8336         struct bnxt_pf_info *pf = &bp->pf;
8337         int rc;
8338
8339         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
8340                 return 0;
8341
8342         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
8343         req.port_id = cpu_to_le16(pf->port_id);
8344         mutex_lock(&bp->hwrm_cmd_lock);
8345         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8346         if (rc) {
8347                 mutex_unlock(&bp->hwrm_cmd_lock);
8348                 return rc;
8349         }
8350         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
8351                 int i;
8352
8353                 bp->num_leds = resp->num_leds;
8354                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
8355                                                  bp->num_leds);
8356                 for (i = 0; i < bp->num_leds; i++) {
8357                         struct bnxt_led_info *led = &bp->leds[i];
8358                         __le16 caps = led->led_state_caps;
8359
8360                         if (!led->led_group_id ||
8361                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
8362                                 bp->num_leds = 0;
8363                                 break;
8364                         }
8365                 }
8366         }
8367         mutex_unlock(&bp->hwrm_cmd_lock);
8368         return 0;
8369 }
8370
8371 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
8372 {
8373         struct hwrm_wol_filter_alloc_input req = {0};
8374         struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
8375         int rc;
8376
8377         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
8378         req.port_id = cpu_to_le16(bp->pf.port_id);
8379         req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
8380         req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
8381         memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
8382         mutex_lock(&bp->hwrm_cmd_lock);
8383         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8384         if (!rc)
8385                 bp->wol_filter_id = resp->wol_filter_id;
8386         mutex_unlock(&bp->hwrm_cmd_lock);
8387         return rc;
8388 }
8389
8390 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
8391 {
8392         struct hwrm_wol_filter_free_input req = {0};
8393         int rc;
8394
8395         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
8396         req.port_id = cpu_to_le16(bp->pf.port_id);
8397         req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
8398         req.wol_filter_id = bp->wol_filter_id;
8399         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8400         return rc;
8401 }
8402
8403 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
8404 {
8405         struct hwrm_wol_filter_qcfg_input req = {0};
8406         struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8407         u16 next_handle = 0;
8408         int rc;
8409
8410         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
8411         req.port_id = cpu_to_le16(bp->pf.port_id);
8412         req.handle = cpu_to_le16(handle);
8413         mutex_lock(&bp->hwrm_cmd_lock);
8414         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8415         if (!rc) {
8416                 next_handle = le16_to_cpu(resp->next_handle);
8417                 if (next_handle != 0) {
8418                         if (resp->wol_type ==
8419                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
8420                                 bp->wol = 1;
8421                                 bp->wol_filter_id = resp->wol_filter_id;
8422                         }
8423                 }
8424         }
8425         mutex_unlock(&bp->hwrm_cmd_lock);
8426         return next_handle;
8427 }
8428
8429 static void bnxt_get_wol_settings(struct bnxt *bp)
8430 {
8431         u16 handle = 0;
8432
8433         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
8434                 return;
8435
8436         do {
8437                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
8438         } while (handle && handle != 0xffff);
8439 }
8440
8441 #ifdef CONFIG_BNXT_HWMON
8442 static ssize_t bnxt_show_temp(struct device *dev,
8443                               struct device_attribute *devattr, char *buf)
8444 {
8445         struct hwrm_temp_monitor_query_input req = {0};
8446         struct hwrm_temp_monitor_query_output *resp;
8447         struct bnxt *bp = dev_get_drvdata(dev);
8448         u32 temp = 0;
8449
8450         resp = bp->hwrm_cmd_resp_addr;
8451         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
8452         mutex_lock(&bp->hwrm_cmd_lock);
8453         if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
8454                 temp = resp->temp * 1000; /* display millidegree */
8455         mutex_unlock(&bp->hwrm_cmd_lock);
8456
8457         return sprintf(buf, "%u\n", temp);
8458 }
8459 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
8460
8461 static struct attribute *bnxt_attrs[] = {
8462         &sensor_dev_attr_temp1_input.dev_attr.attr,
8463         NULL
8464 };
8465 ATTRIBUTE_GROUPS(bnxt);
8466
8467 static void bnxt_hwmon_close(struct bnxt *bp)
8468 {
8469         if (bp->hwmon_dev) {
8470                 hwmon_device_unregister(bp->hwmon_dev);
8471                 bp->hwmon_dev = NULL;
8472         }
8473 }
8474
8475 static void bnxt_hwmon_open(struct bnxt *bp)
8476 {
8477         struct pci_dev *pdev = bp->pdev;
8478
8479         bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
8480                                                           DRV_MODULE_NAME, bp,
8481                                                           bnxt_groups);
8482         if (IS_ERR(bp->hwmon_dev)) {
8483                 bp->hwmon_dev = NULL;
8484                 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
8485         }
8486 }
8487 #else
8488 static void bnxt_hwmon_close(struct bnxt *bp)
8489 {
8490 }
8491
8492 static void bnxt_hwmon_open(struct bnxt *bp)
8493 {
8494 }
8495 #endif
8496
8497 static bool bnxt_eee_config_ok(struct bnxt *bp)
8498 {
8499         struct ethtool_eee *eee = &bp->eee;
8500         struct bnxt_link_info *link_info = &bp->link_info;
8501
8502         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
8503                 return true;
8504
8505         if (eee->eee_enabled) {
8506                 u32 advertising =
8507                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
8508
8509                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8510                         eee->eee_enabled = 0;
8511                         return false;
8512                 }
8513                 if (eee->advertised & ~advertising) {
8514                         eee->advertised = advertising & eee->supported;
8515                         return false;
8516                 }
8517         }
8518         return true;
8519 }
8520
8521 static int bnxt_update_phy_setting(struct bnxt *bp)
8522 {
8523         int rc;
8524         bool update_link = false;
8525         bool update_pause = false;
8526         bool update_eee = false;
8527         struct bnxt_link_info *link_info = &bp->link_info;
8528
8529         rc = bnxt_update_link(bp, true);
8530         if (rc) {
8531                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
8532                            rc);
8533                 return rc;
8534         }
8535         if (!BNXT_SINGLE_PF(bp))
8536                 return 0;
8537
8538         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8539             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
8540             link_info->req_flow_ctrl)
8541                 update_pause = true;
8542         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8543             link_info->force_pause_setting != link_info->req_flow_ctrl)
8544                 update_pause = true;
8545         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8546                 if (BNXT_AUTO_MODE(link_info->auto_mode))
8547                         update_link = true;
8548                 if (link_info->req_link_speed != link_info->force_link_speed)
8549                         update_link = true;
8550                 if (link_info->req_duplex != link_info->duplex_setting)
8551                         update_link = true;
8552         } else {
8553                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
8554                         update_link = true;
8555                 if (link_info->advertising != link_info->auto_link_speeds)
8556                         update_link = true;
8557         }
8558
8559         /* The last close may have shutdown the link, so need to call
8560          * PHY_CFG to bring it back up.
8561          */
8562         if (!netif_carrier_ok(bp->dev))
8563                 update_link = true;
8564
8565         if (!bnxt_eee_config_ok(bp))
8566                 update_eee = true;
8567
8568         if (update_link)
8569                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
8570         else if (update_pause)
8571                 rc = bnxt_hwrm_set_pause(bp);
8572         if (rc) {
8573                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
8574                            rc);
8575                 return rc;
8576         }
8577
8578         return rc;
8579 }
8580
8581 /* Common routine to pre-map certain register block to different GRC window.
8582  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
8583  * in PF and 3 windows in VF that can be customized to map in different
8584  * register blocks.
8585  */
8586 static void bnxt_preset_reg_win(struct bnxt *bp)
8587 {
8588         if (BNXT_PF(bp)) {
8589                 /* CAG registers map to GRC window #4 */
8590                 writel(BNXT_CAG_REG_BASE,
8591                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
8592         }
8593 }
8594
8595 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
8596
8597 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8598 {
8599         int rc = 0;
8600
8601         bnxt_preset_reg_win(bp);
8602         netif_carrier_off(bp->dev);
8603         if (irq_re_init) {
8604                 /* Reserve rings now if none were reserved at driver probe. */
8605                 rc = bnxt_init_dflt_ring_mode(bp);
8606                 if (rc) {
8607                         netdev_err(bp->dev, "Failed to reserve default rings at open\n");
8608                         return rc;
8609                 }
8610         }
8611         rc = bnxt_reserve_rings(bp, irq_re_init);
8612         if (rc)
8613                 return rc;
8614         if ((bp->flags & BNXT_FLAG_RFS) &&
8615             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
8616                 /* disable RFS if falling back to INTA */
8617                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
8618                 bp->flags &= ~BNXT_FLAG_RFS;
8619         }
8620
8621         rc = bnxt_alloc_mem(bp, irq_re_init);
8622         if (rc) {
8623                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8624                 goto open_err_free_mem;
8625         }
8626
8627         if (irq_re_init) {
8628                 bnxt_init_napi(bp);
8629                 rc = bnxt_request_irq(bp);
8630                 if (rc) {
8631                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
8632                         goto open_err_irq;
8633                 }
8634         }
8635
8636         bnxt_enable_napi(bp);
8637         bnxt_debug_dev_init(bp);
8638
8639         rc = bnxt_init_nic(bp, irq_re_init);
8640         if (rc) {
8641                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8642                 goto open_err;
8643         }
8644
8645         if (link_re_init) {
8646                 mutex_lock(&bp->link_lock);
8647                 rc = bnxt_update_phy_setting(bp);
8648                 mutex_unlock(&bp->link_lock);
8649                 if (rc) {
8650                         netdev_warn(bp->dev, "failed to update phy settings\n");
8651                         if (BNXT_SINGLE_PF(bp)) {
8652                                 bp->link_info.phy_retry = true;
8653                                 bp->link_info.phy_retry_expires =
8654                                         jiffies + 5 * HZ;
8655                         }
8656                 }
8657         }
8658
8659         if (irq_re_init)
8660                 udp_tunnel_get_rx_info(bp->dev);
8661
8662         set_bit(BNXT_STATE_OPEN, &bp->state);
8663         bnxt_enable_int(bp);
8664         /* Enable TX queues */
8665         bnxt_tx_enable(bp);
8666         mod_timer(&bp->timer, jiffies + bp->current_interval);
8667         /* Poll link status and check for SFP+ module status */
8668         bnxt_get_port_module_status(bp);
8669
8670         /* VF-reps may need to be re-opened after the PF is re-opened */
8671         if (BNXT_PF(bp))
8672                 bnxt_vf_reps_open(bp);
8673         return 0;
8674
8675 open_err:
8676         bnxt_debug_dev_exit(bp);
8677         bnxt_disable_napi(bp);
8678
8679 open_err_irq:
8680         bnxt_del_napi(bp);
8681
8682 open_err_free_mem:
8683         bnxt_free_skbs(bp);
8684         bnxt_free_irq(bp);
8685         bnxt_free_mem(bp, true);
8686         return rc;
8687 }
8688
8689 /* rtnl_lock held */
8690 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8691 {
8692         int rc = 0;
8693
8694         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
8695         if (rc) {
8696                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
8697                 dev_close(bp->dev);
8698         }
8699         return rc;
8700 }
8701
8702 /* rtnl_lock held, open the NIC half way by allocating all resources, but
8703  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
8704  * self tests.
8705  */
8706 int bnxt_half_open_nic(struct bnxt *bp)
8707 {
8708         int rc = 0;
8709
8710         rc = bnxt_alloc_mem(bp, false);
8711         if (rc) {
8712                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8713                 goto half_open_err;
8714         }
8715         rc = bnxt_init_nic(bp, false);
8716         if (rc) {
8717                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8718                 goto half_open_err;
8719         }
8720         return 0;
8721
8722 half_open_err:
8723         bnxt_free_skbs(bp);
8724         bnxt_free_mem(bp, false);
8725         dev_close(bp->dev);
8726         return rc;
8727 }
8728
8729 /* rtnl_lock held, this call can only be made after a previous successful
8730  * call to bnxt_half_open_nic().
8731  */
8732 void bnxt_half_close_nic(struct bnxt *bp)
8733 {
8734         bnxt_hwrm_resource_free(bp, false, false);
8735         bnxt_free_skbs(bp);
8736         bnxt_free_mem(bp, false);
8737 }
8738
8739 static int bnxt_open(struct net_device *dev)
8740 {
8741         struct bnxt *bp = netdev_priv(dev);
8742         int rc;
8743
8744         bnxt_hwrm_if_change(bp, true);
8745         rc = __bnxt_open_nic(bp, true, true);
8746         if (rc)
8747                 bnxt_hwrm_if_change(bp, false);
8748
8749         bnxt_hwmon_open(bp);
8750
8751         return rc;
8752 }
8753
8754 static bool bnxt_drv_busy(struct bnxt *bp)
8755 {
8756         return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
8757                 test_bit(BNXT_STATE_READ_STATS, &bp->state));
8758 }
8759
8760 static void bnxt_get_ring_stats(struct bnxt *bp,
8761                                 struct rtnl_link_stats64 *stats);
8762
8763 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
8764                              bool link_re_init)
8765 {
8766         /* Close the VF-reps before closing PF */
8767         if (BNXT_PF(bp))
8768                 bnxt_vf_reps_close(bp);
8769
8770         /* Change device state to avoid TX queue wake up's */
8771         bnxt_tx_disable(bp);
8772
8773         clear_bit(BNXT_STATE_OPEN, &bp->state);
8774         smp_mb__after_atomic();
8775         while (bnxt_drv_busy(bp))
8776                 msleep(20);
8777
8778         /* Flush rings and and disable interrupts */
8779         bnxt_shutdown_nic(bp, irq_re_init);
8780
8781         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
8782
8783         bnxt_debug_dev_exit(bp);
8784         bnxt_disable_napi(bp);
8785         del_timer_sync(&bp->timer);
8786         bnxt_free_skbs(bp);
8787
8788         /* Save ring stats before shutdown */
8789         if (bp->bnapi)
8790                 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
8791         if (irq_re_init) {
8792                 bnxt_free_irq(bp);
8793                 bnxt_del_napi(bp);
8794         }
8795         bnxt_free_mem(bp, irq_re_init);
8796 }
8797
8798 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8799 {
8800         int rc = 0;
8801
8802 #ifdef CONFIG_BNXT_SRIOV
8803         if (bp->sriov_cfg) {
8804                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
8805                                                       !bp->sriov_cfg,
8806                                                       BNXT_SRIOV_CFG_WAIT_TMO);
8807                 if (rc)
8808                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
8809         }
8810 #endif
8811         __bnxt_close_nic(bp, irq_re_init, link_re_init);
8812         return rc;
8813 }
8814
8815 static int bnxt_close(struct net_device *dev)
8816 {
8817         struct bnxt *bp = netdev_priv(dev);
8818
8819         bnxt_hwmon_close(bp);
8820         bnxt_close_nic(bp, true, true);
8821         bnxt_hwrm_shutdown_link(bp);
8822         bnxt_hwrm_if_change(bp, false);
8823         return 0;
8824 }
8825
8826 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
8827                                    u16 *val)
8828 {
8829         struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
8830         struct hwrm_port_phy_mdio_read_input req = {0};
8831         int rc;
8832
8833         if (bp->hwrm_spec_code < 0x10a00)
8834                 return -EOPNOTSUPP;
8835
8836         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
8837         req.port_id = cpu_to_le16(bp->pf.port_id);
8838         req.phy_addr = phy_addr;
8839         req.reg_addr = cpu_to_le16(reg & 0x1f);
8840         if (mdio_phy_id_is_c45(phy_addr)) {
8841                 req.cl45_mdio = 1;
8842                 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8843                 req.dev_addr = mdio_phy_id_devad(phy_addr);
8844                 req.reg_addr = cpu_to_le16(reg);
8845         }
8846
8847         mutex_lock(&bp->hwrm_cmd_lock);
8848         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8849         if (!rc)
8850                 *val = le16_to_cpu(resp->reg_data);
8851         mutex_unlock(&bp->hwrm_cmd_lock);
8852         return rc;
8853 }
8854
8855 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
8856                                     u16 val)
8857 {
8858         struct hwrm_port_phy_mdio_write_input req = {0};
8859
8860         if (bp->hwrm_spec_code < 0x10a00)
8861                 return -EOPNOTSUPP;
8862
8863         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
8864         req.port_id = cpu_to_le16(bp->pf.port_id);
8865         req.phy_addr = phy_addr;
8866         req.reg_addr = cpu_to_le16(reg & 0x1f);
8867         if (mdio_phy_id_is_c45(phy_addr)) {
8868                 req.cl45_mdio = 1;
8869                 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8870                 req.dev_addr = mdio_phy_id_devad(phy_addr);
8871                 req.reg_addr = cpu_to_le16(reg);
8872         }
8873         req.reg_data = cpu_to_le16(val);
8874
8875         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8876 }
8877
8878 /* rtnl_lock held */
8879 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8880 {
8881         struct mii_ioctl_data *mdio = if_mii(ifr);
8882         struct bnxt *bp = netdev_priv(dev);
8883         int rc;
8884
8885         switch (cmd) {
8886         case SIOCGMIIPHY:
8887                 mdio->phy_id = bp->link_info.phy_addr;
8888
8889                 /* fallthru */
8890         case SIOCGMIIREG: {
8891                 u16 mii_regval = 0;
8892
8893                 if (!netif_running(dev))
8894                         return -EAGAIN;
8895
8896                 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
8897                                              &mii_regval);
8898                 mdio->val_out = mii_regval;
8899                 return rc;
8900         }
8901
8902         case SIOCSMIIREG:
8903                 if (!netif_running(dev))
8904                         return -EAGAIN;
8905
8906                 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
8907                                                 mdio->val_in);
8908
8909         default:
8910                 /* do nothing */
8911                 break;
8912         }
8913         return -EOPNOTSUPP;
8914 }
8915
8916 static void bnxt_get_ring_stats(struct bnxt *bp,
8917                                 struct rtnl_link_stats64 *stats)
8918 {
8919         int i;
8920
8921
8922         for (i = 0; i < bp->cp_nr_rings; i++) {
8923                 struct bnxt_napi *bnapi = bp->bnapi[i];
8924                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8925                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
8926
8927                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
8928                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
8929                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
8930
8931                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
8932                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
8933                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
8934
8935                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
8936                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
8937                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
8938
8939                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
8940                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
8941                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
8942
8943                 stats->rx_missed_errors +=
8944                         le64_to_cpu(hw_stats->rx_discard_pkts);
8945
8946                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
8947
8948                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
8949         }
8950 }
8951
8952 static void bnxt_add_prev_stats(struct bnxt *bp,
8953                                 struct rtnl_link_stats64 *stats)
8954 {
8955         struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
8956
8957         stats->rx_packets += prev_stats->rx_packets;
8958         stats->tx_packets += prev_stats->tx_packets;
8959         stats->rx_bytes += prev_stats->rx_bytes;
8960         stats->tx_bytes += prev_stats->tx_bytes;
8961         stats->rx_missed_errors += prev_stats->rx_missed_errors;
8962         stats->multicast += prev_stats->multicast;
8963         stats->tx_dropped += prev_stats->tx_dropped;
8964 }
8965
8966 static void
8967 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
8968 {
8969         struct bnxt *bp = netdev_priv(dev);
8970
8971         set_bit(BNXT_STATE_READ_STATS, &bp->state);
8972         /* Make sure bnxt_close_nic() sees that we are reading stats before
8973          * we check the BNXT_STATE_OPEN flag.
8974          */
8975         smp_mb__after_atomic();
8976         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
8977                 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8978                 *stats = bp->net_stats_prev;
8979                 return;
8980         }
8981
8982         bnxt_get_ring_stats(bp, stats);
8983         bnxt_add_prev_stats(bp, stats);
8984
8985         if (bp->flags & BNXT_FLAG_PORT_STATS) {
8986                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
8987                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
8988
8989                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
8990                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
8991                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
8992                                           le64_to_cpu(rx->rx_ovrsz_frames) +
8993                                           le64_to_cpu(rx->rx_runt_frames);
8994                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
8995                                    le64_to_cpu(rx->rx_jbr_frames);
8996                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
8997                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
8998                 stats->tx_errors = le64_to_cpu(tx->tx_err);
8999         }
9000         clear_bit(BNXT_STATE_READ_STATS, &bp->state);
9001 }
9002
9003 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
9004 {
9005         struct net_device *dev = bp->dev;
9006         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9007         struct netdev_hw_addr *ha;
9008         u8 *haddr;
9009         int mc_count = 0;
9010         bool update = false;
9011         int off = 0;
9012
9013         netdev_for_each_mc_addr(ha, dev) {
9014                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
9015                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9016                         vnic->mc_list_count = 0;
9017                         return false;
9018                 }
9019                 haddr = ha->addr;
9020                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
9021                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
9022                         update = true;
9023                 }
9024                 off += ETH_ALEN;
9025                 mc_count++;
9026         }
9027         if (mc_count)
9028                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
9029
9030         if (mc_count != vnic->mc_list_count) {
9031                 vnic->mc_list_count = mc_count;
9032                 update = true;
9033         }
9034         return update;
9035 }
9036
9037 static bool bnxt_uc_list_updated(struct bnxt *bp)
9038 {
9039         struct net_device *dev = bp->dev;
9040         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9041         struct netdev_hw_addr *ha;
9042         int off = 0;
9043
9044         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
9045                 return true;
9046
9047         netdev_for_each_uc_addr(ha, dev) {
9048                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
9049                         return true;
9050
9051                 off += ETH_ALEN;
9052         }
9053         return false;
9054 }
9055
9056 static void bnxt_set_rx_mode(struct net_device *dev)
9057 {
9058         struct bnxt *bp = netdev_priv(dev);
9059         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9060         u32 mask = vnic->rx_mask;
9061         bool mc_update = false;
9062         bool uc_update;
9063
9064         if (!netif_running(dev))
9065                 return;
9066
9067         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
9068                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
9069                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
9070                   CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
9071
9072         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
9073                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
9074
9075         uc_update = bnxt_uc_list_updated(bp);
9076
9077         if (dev->flags & IFF_BROADCAST)
9078                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
9079         if (dev->flags & IFF_ALLMULTI) {
9080                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9081                 vnic->mc_list_count = 0;
9082         } else {
9083                 mc_update = bnxt_mc_list_updated(bp, &mask);
9084         }
9085
9086         if (mask != vnic->rx_mask || uc_update || mc_update) {
9087                 vnic->rx_mask = mask;
9088
9089                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
9090                 bnxt_queue_sp_work(bp);
9091         }
9092 }
9093
9094 static int bnxt_cfg_rx_mode(struct bnxt *bp)
9095 {
9096         struct net_device *dev = bp->dev;
9097         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9098         struct netdev_hw_addr *ha;
9099         int i, off = 0, rc;
9100         bool uc_update;
9101
9102         netif_addr_lock_bh(dev);
9103         uc_update = bnxt_uc_list_updated(bp);
9104         netif_addr_unlock_bh(dev);
9105
9106         if (!uc_update)
9107                 goto skip_uc;
9108
9109         mutex_lock(&bp->hwrm_cmd_lock);
9110         for (i = 1; i < vnic->uc_filter_count; i++) {
9111                 struct hwrm_cfa_l2_filter_free_input req = {0};
9112
9113                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
9114                                        -1);
9115
9116                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
9117
9118                 rc = _hwrm_send_message(bp, &req, sizeof(req),
9119                                         HWRM_CMD_TIMEOUT);
9120         }
9121         mutex_unlock(&bp->hwrm_cmd_lock);
9122
9123         vnic->uc_filter_count = 1;
9124
9125         netif_addr_lock_bh(dev);
9126         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
9127                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
9128         } else {
9129                 netdev_for_each_uc_addr(ha, dev) {
9130                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
9131                         off += ETH_ALEN;
9132                         vnic->uc_filter_count++;
9133                 }
9134         }
9135         netif_addr_unlock_bh(dev);
9136
9137         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
9138                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
9139                 if (rc) {
9140                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
9141                                    rc);
9142                         vnic->uc_filter_count = i;
9143                         return rc;
9144                 }
9145         }
9146
9147 skip_uc:
9148         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
9149         if (rc && vnic->mc_list_count) {
9150                 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
9151                             rc);
9152                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9153                 vnic->mc_list_count = 0;
9154                 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
9155         }
9156         if (rc)
9157                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
9158                            rc);
9159
9160         return rc;
9161 }
9162
9163 static bool bnxt_can_reserve_rings(struct bnxt *bp)
9164 {
9165 #ifdef CONFIG_BNXT_SRIOV
9166         if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
9167                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9168
9169                 /* No minimum rings were provisioned by the PF.  Don't
9170                  * reserve rings by default when device is down.
9171                  */
9172                 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
9173                         return true;
9174
9175                 if (!netif_running(bp->dev))
9176                         return false;
9177         }
9178 #endif
9179         return true;
9180 }
9181
9182 /* If the chip and firmware supports RFS */
9183 static bool bnxt_rfs_supported(struct bnxt *bp)
9184 {
9185         if (bp->flags & BNXT_FLAG_CHIP_P5) {
9186                 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX)
9187                         return true;
9188                 return false;
9189         }
9190         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
9191                 return true;
9192         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9193                 return true;
9194         return false;
9195 }
9196
9197 /* If runtime conditions support RFS */
9198 static bool bnxt_rfs_capable(struct bnxt *bp)
9199 {
9200 #ifdef CONFIG_RFS_ACCEL
9201         int vnics, max_vnics, max_rss_ctxs;
9202
9203         if (bp->flags & BNXT_FLAG_CHIP_P5)
9204                 return bnxt_rfs_supported(bp);
9205         if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
9206                 return false;
9207
9208         vnics = 1 + bp->rx_nr_rings;
9209         max_vnics = bnxt_get_max_func_vnics(bp);
9210         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
9211
9212         /* RSS contexts not a limiting factor */
9213         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9214                 max_rss_ctxs = max_vnics;
9215         if (vnics > max_vnics || vnics > max_rss_ctxs) {
9216                 if (bp->rx_nr_rings > 1)
9217                         netdev_warn(bp->dev,
9218                                     "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
9219                                     min(max_rss_ctxs - 1, max_vnics - 1));
9220                 return false;
9221         }
9222
9223         if (!BNXT_NEW_RM(bp))
9224                 return true;
9225
9226         if (vnics == bp->hw_resc.resv_vnics)
9227                 return true;
9228
9229         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
9230         if (vnics <= bp->hw_resc.resv_vnics)
9231                 return true;
9232
9233         netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
9234         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
9235         return false;
9236 #else
9237         return false;
9238 #endif
9239 }
9240
9241 static netdev_features_t bnxt_fix_features(struct net_device *dev,
9242                                            netdev_features_t features)
9243 {
9244         struct bnxt *bp = netdev_priv(dev);
9245
9246         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
9247                 features &= ~NETIF_F_NTUPLE;
9248
9249         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9250                 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
9251
9252         if (!(features & NETIF_F_GRO))
9253                 features &= ~NETIF_F_GRO_HW;
9254
9255         if (features & NETIF_F_GRO_HW)
9256                 features &= ~NETIF_F_LRO;
9257
9258         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
9259          * turned on or off together.
9260          */
9261         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
9262             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
9263                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
9264                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9265                                       NETIF_F_HW_VLAN_STAG_RX);
9266                 else
9267                         features |= NETIF_F_HW_VLAN_CTAG_RX |
9268                                     NETIF_F_HW_VLAN_STAG_RX;
9269         }
9270 #ifdef CONFIG_BNXT_SRIOV
9271         if (BNXT_VF(bp)) {
9272                 if (bp->vf.vlan) {
9273                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9274                                       NETIF_F_HW_VLAN_STAG_RX);
9275                 }
9276         }
9277 #endif
9278         return features;
9279 }
9280
9281 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
9282 {
9283         struct bnxt *bp = netdev_priv(dev);
9284         u32 flags = bp->flags;
9285         u32 changes;
9286         int rc = 0;
9287         bool re_init = false;
9288         bool update_tpa = false;
9289
9290         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
9291         if (features & NETIF_F_GRO_HW)
9292                 flags |= BNXT_FLAG_GRO;
9293         else if (features & NETIF_F_LRO)
9294                 flags |= BNXT_FLAG_LRO;
9295
9296         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9297                 flags &= ~BNXT_FLAG_TPA;
9298
9299         if (features & NETIF_F_HW_VLAN_CTAG_RX)
9300                 flags |= BNXT_FLAG_STRIP_VLAN;
9301
9302         if (features & NETIF_F_NTUPLE)
9303                 flags |= BNXT_FLAG_RFS;
9304
9305         changes = flags ^ bp->flags;
9306         if (changes & BNXT_FLAG_TPA) {
9307                 update_tpa = true;
9308                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
9309                     (flags & BNXT_FLAG_TPA) == 0)
9310                         re_init = true;
9311         }
9312
9313         if (changes & ~BNXT_FLAG_TPA)
9314                 re_init = true;
9315
9316         if (flags != bp->flags) {
9317                 u32 old_flags = bp->flags;
9318
9319                 bp->flags = flags;
9320
9321                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9322                         if (update_tpa)
9323                                 bnxt_set_ring_params(bp);
9324                         return rc;
9325                 }
9326
9327                 if (re_init) {
9328                         bnxt_close_nic(bp, false, false);
9329                         if (update_tpa)
9330                                 bnxt_set_ring_params(bp);
9331
9332                         return bnxt_open_nic(bp, false, false);
9333                 }
9334                 if (update_tpa) {
9335                         rc = bnxt_set_tpa(bp,
9336                                           (flags & BNXT_FLAG_TPA) ?
9337                                           true : false);
9338                         if (rc)
9339                                 bp->flags = old_flags;
9340                 }
9341         }
9342         return rc;
9343 }
9344
9345 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
9346                                        u32 ring_id, u32 *prod, u32 *cons)
9347 {
9348         struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
9349         struct hwrm_dbg_ring_info_get_input req = {0};
9350         int rc;
9351
9352         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
9353         req.ring_type = ring_type;
9354         req.fw_ring_id = cpu_to_le32(ring_id);
9355         mutex_lock(&bp->hwrm_cmd_lock);
9356         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9357         if (!rc) {
9358                 *prod = le32_to_cpu(resp->producer_index);
9359                 *cons = le32_to_cpu(resp->consumer_index);
9360         }
9361         mutex_unlock(&bp->hwrm_cmd_lock);
9362         return rc;
9363 }
9364
9365 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
9366 {
9367         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9368         int i = bnapi->index;
9369
9370         if (!txr)
9371                 return;
9372
9373         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
9374                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
9375                     txr->tx_cons);
9376 }
9377
9378 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
9379 {
9380         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9381         int i = bnapi->index;
9382
9383         if (!rxr)
9384                 return;
9385
9386         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
9387                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
9388                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
9389                     rxr->rx_sw_agg_prod);
9390 }
9391
9392 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
9393 {
9394         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
9395         int i = bnapi->index;
9396
9397         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
9398                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
9399 }
9400
9401 static void bnxt_dbg_dump_states(struct bnxt *bp)
9402 {
9403         int i;
9404         struct bnxt_napi *bnapi;
9405
9406         for (i = 0; i < bp->cp_nr_rings; i++) {
9407                 bnapi = bp->bnapi[i];
9408                 if (netif_msg_drv(bp)) {
9409                         bnxt_dump_tx_sw_state(bnapi);
9410                         bnxt_dump_rx_sw_state(bnapi);
9411                         bnxt_dump_cp_sw_state(bnapi);
9412                 }
9413         }
9414 }
9415
9416 static void bnxt_reset_task(struct bnxt *bp, bool silent)
9417 {
9418         if (!silent)
9419                 bnxt_dbg_dump_states(bp);
9420         if (netif_running(bp->dev)) {
9421                 int rc;
9422
9423                 if (!silent)
9424                         bnxt_ulp_stop(bp);
9425                 bnxt_close_nic(bp, false, false);
9426                 rc = bnxt_open_nic(bp, false, false);
9427                 if (!silent && !rc)
9428                         bnxt_ulp_start(bp);
9429         }
9430 }
9431
9432 static void bnxt_tx_timeout(struct net_device *dev)
9433 {
9434         struct bnxt *bp = netdev_priv(dev);
9435
9436         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
9437         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
9438         bnxt_queue_sp_work(bp);
9439 }
9440
9441 static void bnxt_timer(struct timer_list *t)
9442 {
9443         struct bnxt *bp = from_timer(bp, t, timer);
9444         struct net_device *dev = bp->dev;
9445
9446         if (!netif_running(dev))
9447                 return;
9448
9449         if (atomic_read(&bp->intr_sem) != 0)
9450                 goto bnxt_restart_timer;
9451
9452         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
9453             bp->stats_coal_ticks) {
9454                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
9455                 bnxt_queue_sp_work(bp);
9456         }
9457
9458         if (bnxt_tc_flower_enabled(bp)) {
9459                 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
9460                 bnxt_queue_sp_work(bp);
9461         }
9462
9463         if (bp->link_info.phy_retry) {
9464                 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
9465                         bp->link_info.phy_retry = 0;
9466                         netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
9467                 } else {
9468                         set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
9469                         bnxt_queue_sp_work(bp);
9470                 }
9471         }
9472
9473         if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) {
9474                 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
9475                 bnxt_queue_sp_work(bp);
9476         }
9477 bnxt_restart_timer:
9478         mod_timer(&bp->timer, jiffies + bp->current_interval);
9479 }
9480
9481 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
9482 {
9483         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
9484          * set.  If the device is being closed, bnxt_close() may be holding
9485          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
9486          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
9487          */
9488         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9489         rtnl_lock();
9490 }
9491
9492 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
9493 {
9494         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9495         rtnl_unlock();
9496 }
9497
9498 /* Only called from bnxt_sp_task() */
9499 static void bnxt_reset(struct bnxt *bp, bool silent)
9500 {
9501         bnxt_rtnl_lock_sp(bp);
9502         if (test_bit(BNXT_STATE_OPEN, &bp->state))
9503                 bnxt_reset_task(bp, silent);
9504         bnxt_rtnl_unlock_sp(bp);
9505 }
9506
9507 static void bnxt_chk_missed_irq(struct bnxt *bp)
9508 {
9509         int i;
9510
9511         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9512                 return;
9513
9514         for (i = 0; i < bp->cp_nr_rings; i++) {
9515                 struct bnxt_napi *bnapi = bp->bnapi[i];
9516                 struct bnxt_cp_ring_info *cpr;
9517                 u32 fw_ring_id;
9518                 int j;
9519
9520                 if (!bnapi)
9521                         continue;
9522
9523                 cpr = &bnapi->cp_ring;
9524                 for (j = 0; j < 2; j++) {
9525                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
9526                         u32 val[2];
9527
9528                         if (!cpr2 || cpr2->has_more_work ||
9529                             !bnxt_has_work(bp, cpr2))
9530                                 continue;
9531
9532                         if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
9533                                 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
9534                                 continue;
9535                         }
9536                         fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
9537                         bnxt_dbg_hwrm_ring_info_get(bp,
9538                                 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
9539                                 fw_ring_id, &val[0], &val[1]);
9540                         cpr->missed_irqs++;
9541                 }
9542         }
9543 }
9544
9545 static void bnxt_cfg_ntp_filters(struct bnxt *);
9546
9547 static void bnxt_sp_task(struct work_struct *work)
9548 {
9549         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
9550
9551         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9552         smp_mb__after_atomic();
9553         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9554                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9555                 return;
9556         }
9557
9558         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
9559                 bnxt_cfg_rx_mode(bp);
9560
9561         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
9562                 bnxt_cfg_ntp_filters(bp);
9563         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
9564                 bnxt_hwrm_exec_fwd_req(bp);
9565         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9566                 bnxt_hwrm_tunnel_dst_port_alloc(
9567                         bp, bp->vxlan_port,
9568                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9569         }
9570         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9571                 bnxt_hwrm_tunnel_dst_port_free(
9572                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9573         }
9574         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9575                 bnxt_hwrm_tunnel_dst_port_alloc(
9576                         bp, bp->nge_port,
9577                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9578         }
9579         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9580                 bnxt_hwrm_tunnel_dst_port_free(
9581                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9582         }
9583         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
9584                 bnxt_hwrm_port_qstats(bp);
9585                 bnxt_hwrm_port_qstats_ext(bp);
9586                 bnxt_hwrm_pcie_qstats(bp);
9587         }
9588
9589         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
9590                 int rc;
9591
9592                 mutex_lock(&bp->link_lock);
9593                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
9594                                        &bp->sp_event))
9595                         bnxt_hwrm_phy_qcaps(bp);
9596
9597                 rc = bnxt_update_link(bp, true);
9598                 mutex_unlock(&bp->link_lock);
9599                 if (rc)
9600                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
9601                                    rc);
9602         }
9603         if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
9604                 int rc;
9605
9606                 mutex_lock(&bp->link_lock);
9607                 rc = bnxt_update_phy_setting(bp);
9608                 mutex_unlock(&bp->link_lock);
9609                 if (rc) {
9610                         netdev_warn(bp->dev, "update phy settings retry failed\n");
9611                 } else {
9612                         bp->link_info.phy_retry = false;
9613                         netdev_info(bp->dev, "update phy settings retry succeeded\n");
9614                 }
9615         }
9616         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
9617                 mutex_lock(&bp->link_lock);
9618                 bnxt_get_port_module_status(bp);
9619                 mutex_unlock(&bp->link_lock);
9620         }
9621
9622         if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
9623                 bnxt_tc_flow_stats_work(bp);
9624
9625         if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
9626                 bnxt_chk_missed_irq(bp);
9627
9628         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
9629          * must be the last functions to be called before exiting.
9630          */
9631         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
9632                 bnxt_reset(bp, false);
9633
9634         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
9635                 bnxt_reset(bp, true);
9636
9637         smp_mb__before_atomic();
9638         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9639 }
9640
9641 /* Under rtnl_lock */
9642 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
9643                      int tx_xdp)
9644 {
9645         int max_rx, max_tx, tx_sets = 1;
9646         int tx_rings_needed, stats;
9647         int rx_rings = rx;
9648         int cp, vnics, rc;
9649
9650         if (tcs)
9651                 tx_sets = tcs;
9652
9653         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
9654         if (rc)
9655                 return rc;
9656
9657         if (max_rx < rx)
9658                 return -ENOMEM;
9659
9660         tx_rings_needed = tx * tx_sets + tx_xdp;
9661         if (max_tx < tx_rings_needed)
9662                 return -ENOMEM;
9663
9664         vnics = 1;
9665         if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
9666                 vnics += rx_rings;
9667
9668         if (bp->flags & BNXT_FLAG_AGG_RINGS)
9669                 rx_rings <<= 1;
9670         cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
9671         stats = cp;
9672         if (BNXT_NEW_RM(bp)) {
9673                 cp += bnxt_get_ulp_msix_num(bp);
9674                 stats += bnxt_get_ulp_stat_ctxs(bp);
9675         }
9676         return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
9677                                      stats, vnics);
9678 }
9679
9680 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
9681 {
9682         if (bp->bar2) {
9683                 pci_iounmap(pdev, bp->bar2);
9684                 bp->bar2 = NULL;
9685         }
9686
9687         if (bp->bar1) {
9688                 pci_iounmap(pdev, bp->bar1);
9689                 bp->bar1 = NULL;
9690         }
9691
9692         if (bp->bar0) {
9693                 pci_iounmap(pdev, bp->bar0);
9694                 bp->bar0 = NULL;
9695         }
9696 }
9697
9698 static void bnxt_cleanup_pci(struct bnxt *bp)
9699 {
9700         bnxt_unmap_bars(bp, bp->pdev);
9701         pci_release_regions(bp->pdev);
9702         pci_disable_device(bp->pdev);
9703 }
9704
9705 static void bnxt_init_dflt_coal(struct bnxt *bp)
9706 {
9707         struct bnxt_coal *coal;
9708
9709         /* Tick values in micro seconds.
9710          * 1 coal_buf x bufs_per_record = 1 completion record.
9711          */
9712         coal = &bp->rx_coal;
9713         coal->coal_ticks = 10;
9714         coal->coal_bufs = 30;
9715         coal->coal_ticks_irq = 1;
9716         coal->coal_bufs_irq = 2;
9717         coal->idle_thresh = 50;
9718         coal->bufs_per_record = 2;
9719         coal->budget = 64;              /* NAPI budget */
9720
9721         coal = &bp->tx_coal;
9722         coal->coal_ticks = 28;
9723         coal->coal_bufs = 30;
9724         coal->coal_ticks_irq = 2;
9725         coal->coal_bufs_irq = 2;
9726         coal->bufs_per_record = 1;
9727
9728         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
9729 }
9730
9731 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
9732 {
9733         int rc;
9734         struct bnxt *bp = netdev_priv(dev);
9735
9736         SET_NETDEV_DEV(dev, &pdev->dev);
9737
9738         /* enable device (incl. PCI PM wakeup), and bus-mastering */
9739         rc = pci_enable_device(pdev);
9740         if (rc) {
9741                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9742                 goto init_err;
9743         }
9744
9745         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9746                 dev_err(&pdev->dev,
9747                         "Cannot find PCI device base address, aborting\n");
9748                 rc = -ENODEV;
9749                 goto init_err_disable;
9750         }
9751
9752         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9753         if (rc) {
9754                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9755                 goto init_err_disable;
9756         }
9757
9758         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
9759             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9760                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
9761                 goto init_err_disable;
9762         }
9763
9764         pci_set_master(pdev);
9765
9766         bp->dev = dev;
9767         bp->pdev = pdev;
9768
9769         bp->bar0 = pci_ioremap_bar(pdev, 0);
9770         if (!bp->bar0) {
9771                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9772                 rc = -ENOMEM;
9773                 goto init_err_release;
9774         }
9775
9776         bp->bar1 = pci_ioremap_bar(pdev, 2);
9777         if (!bp->bar1) {
9778                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
9779                 rc = -ENOMEM;
9780                 goto init_err_release;
9781         }
9782
9783         bp->bar2 = pci_ioremap_bar(pdev, 4);
9784         if (!bp->bar2) {
9785                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
9786                 rc = -ENOMEM;
9787                 goto init_err_release;
9788         }
9789
9790         pci_enable_pcie_error_reporting(pdev);
9791
9792         INIT_WORK(&bp->sp_task, bnxt_sp_task);
9793
9794         spin_lock_init(&bp->ntp_fltr_lock);
9795 #if BITS_PER_LONG == 32
9796         spin_lock_init(&bp->db_lock);
9797 #endif
9798
9799         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
9800         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
9801
9802         bnxt_init_dflt_coal(bp);
9803
9804         timer_setup(&bp->timer, bnxt_timer, 0);
9805         bp->current_interval = BNXT_TIMER_INTERVAL;
9806
9807         clear_bit(BNXT_STATE_OPEN, &bp->state);
9808         return 0;
9809
9810 init_err_release:
9811         bnxt_unmap_bars(bp, pdev);
9812         pci_release_regions(pdev);
9813
9814 init_err_disable:
9815         pci_disable_device(pdev);
9816
9817 init_err:
9818         return rc;
9819 }
9820
9821 /* rtnl_lock held */
9822 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
9823 {
9824         struct sockaddr *addr = p;
9825         struct bnxt *bp = netdev_priv(dev);
9826         int rc = 0;
9827
9828         if (!is_valid_ether_addr(addr->sa_data))
9829                 return -EADDRNOTAVAIL;
9830
9831         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
9832                 return 0;
9833
9834         rc = bnxt_approve_mac(bp, addr->sa_data, true);
9835         if (rc)
9836                 return rc;
9837
9838         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9839         if (netif_running(dev)) {
9840                 bnxt_close_nic(bp, false, false);
9841                 rc = bnxt_open_nic(bp, false, false);
9842         }
9843
9844         return rc;
9845 }
9846
9847 /* rtnl_lock held */
9848 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
9849 {
9850         struct bnxt *bp = netdev_priv(dev);
9851
9852         if (netif_running(dev))
9853                 bnxt_close_nic(bp, false, false);
9854
9855         dev->mtu = new_mtu;
9856         bnxt_set_ring_params(bp);
9857
9858         if (netif_running(dev))
9859                 return bnxt_open_nic(bp, false, false);
9860
9861         return 0;
9862 }
9863
9864 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
9865 {
9866         struct bnxt *bp = netdev_priv(dev);
9867         bool sh = false;
9868         int rc;
9869
9870         if (tc > bp->max_tc) {
9871                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
9872                            tc, bp->max_tc);
9873                 return -EINVAL;
9874         }
9875
9876         if (netdev_get_num_tc(dev) == tc)
9877                 return 0;
9878
9879         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
9880                 sh = true;
9881
9882         rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
9883                               sh, tc, bp->tx_nr_rings_xdp);
9884         if (rc)
9885                 return rc;
9886
9887         /* Needs to close the device and do hw resource re-allocations */
9888         if (netif_running(bp->dev))
9889                 bnxt_close_nic(bp, true, false);
9890
9891         if (tc) {
9892                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
9893                 netdev_set_num_tc(dev, tc);
9894         } else {
9895                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
9896                 netdev_reset_tc(dev);
9897         }
9898         bp->tx_nr_rings += bp->tx_nr_rings_xdp;
9899         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9900                                bp->tx_nr_rings + bp->rx_nr_rings;
9901
9902         if (netif_running(bp->dev))
9903                 return bnxt_open_nic(bp, true, false);
9904
9905         return 0;
9906 }
9907
9908 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9909                                   void *cb_priv)
9910 {
9911         struct bnxt *bp = cb_priv;
9912
9913         if (!bnxt_tc_flower_enabled(bp) ||
9914             !tc_cls_can_offload_and_chain0(bp->dev, type_data))
9915                 return -EOPNOTSUPP;
9916
9917         switch (type) {
9918         case TC_SETUP_CLSFLOWER:
9919                 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
9920         default:
9921                 return -EOPNOTSUPP;
9922         }
9923 }
9924
9925 static LIST_HEAD(bnxt_block_cb_list);
9926
9927 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
9928                          void *type_data)
9929 {
9930         struct bnxt *bp = netdev_priv(dev);
9931
9932         switch (type) {
9933         case TC_SETUP_BLOCK:
9934                 return flow_block_cb_setup_simple(type_data,
9935                                                   &bnxt_block_cb_list,
9936                                                   bnxt_setup_tc_block_cb,
9937                                                   bp, bp, true);
9938         case TC_SETUP_QDISC_MQPRIO: {
9939                 struct tc_mqprio_qopt *mqprio = type_data;
9940
9941                 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9942
9943                 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
9944         }
9945         default:
9946                 return -EOPNOTSUPP;
9947         }
9948 }
9949
9950 #ifdef CONFIG_RFS_ACCEL
9951 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
9952                             struct bnxt_ntuple_filter *f2)
9953 {
9954         struct flow_keys *keys1 = &f1->fkeys;
9955         struct flow_keys *keys2 = &f2->fkeys;
9956
9957         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
9958             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
9959             keys1->ports.ports == keys2->ports.ports &&
9960             keys1->basic.ip_proto == keys2->basic.ip_proto &&
9961             keys1->basic.n_proto == keys2->basic.n_proto &&
9962             keys1->control.flags == keys2->control.flags &&
9963             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
9964             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
9965                 return true;
9966
9967         return false;
9968 }
9969
9970 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
9971                               u16 rxq_index, u32 flow_id)
9972 {
9973         struct bnxt *bp = netdev_priv(dev);
9974         struct bnxt_ntuple_filter *fltr, *new_fltr;
9975         struct flow_keys *fkeys;
9976         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
9977         int rc = 0, idx, bit_id, l2_idx = 0;
9978         struct hlist_head *head;
9979
9980         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
9981                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9982                 int off = 0, j;
9983
9984                 netif_addr_lock_bh(dev);
9985                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
9986                         if (ether_addr_equal(eth->h_dest,
9987                                              vnic->uc_list + off)) {
9988                                 l2_idx = j + 1;
9989                                 break;
9990                         }
9991                 }
9992                 netif_addr_unlock_bh(dev);
9993                 if (!l2_idx)
9994                         return -EINVAL;
9995         }
9996         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
9997         if (!new_fltr)
9998                 return -ENOMEM;
9999
10000         fkeys = &new_fltr->fkeys;
10001         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
10002                 rc = -EPROTONOSUPPORT;
10003                 goto err_free;
10004         }
10005
10006         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
10007              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
10008             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
10009              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
10010                 rc = -EPROTONOSUPPORT;
10011                 goto err_free;
10012         }
10013         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
10014             bp->hwrm_spec_code < 0x10601) {
10015                 rc = -EPROTONOSUPPORT;
10016                 goto err_free;
10017         }
10018         if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
10019             bp->hwrm_spec_code < 0x10601) {
10020                 rc = -EPROTONOSUPPORT;
10021                 goto err_free;
10022         }
10023
10024         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
10025         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
10026
10027         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
10028         head = &bp->ntp_fltr_hash_tbl[idx];
10029         rcu_read_lock();
10030         hlist_for_each_entry_rcu(fltr, head, hash) {
10031                 if (bnxt_fltr_match(fltr, new_fltr)) {
10032                         rcu_read_unlock();
10033                         rc = 0;
10034                         goto err_free;
10035                 }
10036         }
10037         rcu_read_unlock();
10038
10039         spin_lock_bh(&bp->ntp_fltr_lock);
10040         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
10041                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
10042         if (bit_id < 0) {
10043                 spin_unlock_bh(&bp->ntp_fltr_lock);
10044                 rc = -ENOMEM;
10045                 goto err_free;
10046         }
10047
10048         new_fltr->sw_id = (u16)bit_id;
10049         new_fltr->flow_id = flow_id;
10050         new_fltr->l2_fltr_idx = l2_idx;
10051         new_fltr->rxq = rxq_index;
10052         hlist_add_head_rcu(&new_fltr->hash, head);
10053         bp->ntp_fltr_count++;
10054         spin_unlock_bh(&bp->ntp_fltr_lock);
10055
10056         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
10057         bnxt_queue_sp_work(bp);
10058
10059         return new_fltr->sw_id;
10060
10061 err_free:
10062         kfree(new_fltr);
10063         return rc;
10064 }
10065
10066 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
10067 {
10068         int i;
10069
10070         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
10071                 struct hlist_head *head;
10072                 struct hlist_node *tmp;
10073                 struct bnxt_ntuple_filter *fltr;
10074                 int rc;
10075
10076                 head = &bp->ntp_fltr_hash_tbl[i];
10077                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
10078                         bool del = false;
10079
10080                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
10081                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
10082                                                         fltr->flow_id,
10083                                                         fltr->sw_id)) {
10084                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
10085                                                                          fltr);
10086                                         del = true;
10087                                 }
10088                         } else {
10089                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
10090                                                                        fltr);
10091                                 if (rc)
10092                                         del = true;
10093                                 else
10094                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
10095                         }
10096
10097                         if (del) {
10098                                 spin_lock_bh(&bp->ntp_fltr_lock);
10099                                 hlist_del_rcu(&fltr->hash);
10100                                 bp->ntp_fltr_count--;
10101                                 spin_unlock_bh(&bp->ntp_fltr_lock);
10102                                 synchronize_rcu();
10103                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
10104                                 kfree(fltr);
10105                         }
10106                 }
10107         }
10108         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
10109                 netdev_info(bp->dev, "Receive PF driver unload event!");
10110 }
10111
10112 #else
10113
10114 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
10115 {
10116 }
10117
10118 #endif /* CONFIG_RFS_ACCEL */
10119
10120 static void bnxt_udp_tunnel_add(struct net_device *dev,
10121                                 struct udp_tunnel_info *ti)
10122 {
10123         struct bnxt *bp = netdev_priv(dev);
10124
10125         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
10126                 return;
10127
10128         if (!netif_running(dev))
10129                 return;
10130
10131         switch (ti->type) {
10132         case UDP_TUNNEL_TYPE_VXLAN:
10133                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
10134                         return;
10135
10136                 bp->vxlan_port_cnt++;
10137                 if (bp->vxlan_port_cnt == 1) {
10138                         bp->vxlan_port = ti->port;
10139                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
10140                         bnxt_queue_sp_work(bp);
10141                 }
10142                 break;
10143         case UDP_TUNNEL_TYPE_GENEVE:
10144                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
10145                         return;
10146
10147                 bp->nge_port_cnt++;
10148                 if (bp->nge_port_cnt == 1) {
10149                         bp->nge_port = ti->port;
10150                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
10151                 }
10152                 break;
10153         default:
10154                 return;
10155         }
10156
10157         bnxt_queue_sp_work(bp);
10158 }
10159
10160 static void bnxt_udp_tunnel_del(struct net_device *dev,
10161                                 struct udp_tunnel_info *ti)
10162 {
10163         struct bnxt *bp = netdev_priv(dev);
10164
10165         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
10166                 return;
10167
10168         if (!netif_running(dev))
10169                 return;
10170
10171         switch (ti->type) {
10172         case UDP_TUNNEL_TYPE_VXLAN:
10173                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
10174                         return;
10175                 bp->vxlan_port_cnt--;
10176
10177                 if (bp->vxlan_port_cnt != 0)
10178                         return;
10179
10180                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
10181                 break;
10182         case UDP_TUNNEL_TYPE_GENEVE:
10183                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
10184                         return;
10185                 bp->nge_port_cnt--;
10186
10187                 if (bp->nge_port_cnt != 0)
10188                         return;
10189
10190                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
10191                 break;
10192         default:
10193                 return;
10194         }
10195
10196         bnxt_queue_sp_work(bp);
10197 }
10198
10199 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
10200                                struct net_device *dev, u32 filter_mask,
10201                                int nlflags)
10202 {
10203         struct bnxt *bp = netdev_priv(dev);
10204
10205         return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
10206                                        nlflags, filter_mask, NULL);
10207 }
10208
10209 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
10210                                u16 flags, struct netlink_ext_ack *extack)
10211 {
10212         struct bnxt *bp = netdev_priv(dev);
10213         struct nlattr *attr, *br_spec;
10214         int rem, rc = 0;
10215
10216         if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
10217                 return -EOPNOTSUPP;
10218
10219         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
10220         if (!br_spec)
10221                 return -EINVAL;
10222
10223         nla_for_each_nested(attr, br_spec, rem) {
10224                 u16 mode;
10225
10226                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
10227                         continue;
10228
10229                 if (nla_len(attr) < sizeof(mode))
10230                         return -EINVAL;
10231
10232                 mode = nla_get_u16(attr);
10233                 if (mode == bp->br_mode)
10234                         break;
10235
10236                 rc = bnxt_hwrm_set_br_mode(bp, mode);
10237                 if (!rc)
10238                         bp->br_mode = mode;
10239                 break;
10240         }
10241         return rc;
10242 }
10243
10244 int bnxt_get_port_parent_id(struct net_device *dev,
10245                             struct netdev_phys_item_id *ppid)
10246 {
10247         struct bnxt *bp = netdev_priv(dev);
10248
10249         if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
10250                 return -EOPNOTSUPP;
10251
10252         /* The PF and it's VF-reps only support the switchdev framework */
10253         if (!BNXT_PF(bp))
10254                 return -EOPNOTSUPP;
10255
10256         ppid->id_len = sizeof(bp->switch_id);
10257         memcpy(ppid->id, bp->switch_id, ppid->id_len);
10258
10259         return 0;
10260 }
10261
10262 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev)
10263 {
10264         struct bnxt *bp = netdev_priv(dev);
10265
10266         return &bp->dl_port;
10267 }
10268
10269 static const struct net_device_ops bnxt_netdev_ops = {
10270         .ndo_open               = bnxt_open,
10271         .ndo_start_xmit         = bnxt_start_xmit,
10272         .ndo_stop               = bnxt_close,
10273         .ndo_get_stats64        = bnxt_get_stats64,
10274         .ndo_set_rx_mode        = bnxt_set_rx_mode,
10275         .ndo_do_ioctl           = bnxt_ioctl,
10276         .ndo_validate_addr      = eth_validate_addr,
10277         .ndo_set_mac_address    = bnxt_change_mac_addr,
10278         .ndo_change_mtu         = bnxt_change_mtu,
10279         .ndo_fix_features       = bnxt_fix_features,
10280         .ndo_set_features       = bnxt_set_features,
10281         .ndo_tx_timeout         = bnxt_tx_timeout,
10282 #ifdef CONFIG_BNXT_SRIOV
10283         .ndo_get_vf_config      = bnxt_get_vf_config,
10284         .ndo_set_vf_mac         = bnxt_set_vf_mac,
10285         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
10286         .ndo_set_vf_rate        = bnxt_set_vf_bw,
10287         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
10288         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
10289         .ndo_set_vf_trust       = bnxt_set_vf_trust,
10290 #endif
10291         .ndo_setup_tc           = bnxt_setup_tc,
10292 #ifdef CONFIG_RFS_ACCEL
10293         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
10294 #endif
10295         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
10296         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
10297         .ndo_bpf                = bnxt_xdp,
10298         .ndo_xdp_xmit           = bnxt_xdp_xmit,
10299         .ndo_bridge_getlink     = bnxt_bridge_getlink,
10300         .ndo_bridge_setlink     = bnxt_bridge_setlink,
10301         .ndo_get_devlink_port   = bnxt_get_devlink_port,
10302 };
10303
10304 static void bnxt_remove_one(struct pci_dev *pdev)
10305 {
10306         struct net_device *dev = pci_get_drvdata(pdev);
10307         struct bnxt *bp = netdev_priv(dev);
10308
10309         if (BNXT_PF(bp)) {
10310                 bnxt_sriov_disable(bp);
10311                 bnxt_dl_unregister(bp);
10312         }
10313
10314         pci_disable_pcie_error_reporting(pdev);
10315         unregister_netdev(dev);
10316         bnxt_shutdown_tc(bp);
10317         bnxt_cancel_sp_work(bp);
10318         bp->sp_event = 0;
10319
10320         bnxt_clear_int_mode(bp);
10321         bnxt_hwrm_func_drv_unrgtr(bp);
10322         bnxt_free_hwrm_resources(bp);
10323         bnxt_free_hwrm_short_cmd_req(bp);
10324         bnxt_ethtool_free(bp);
10325         bnxt_dcb_free(bp);
10326         kfree(bp->edev);
10327         bp->edev = NULL;
10328         bnxt_cleanup_pci(bp);
10329         bnxt_free_ctx_mem(bp);
10330         kfree(bp->ctx);
10331         bp->ctx = NULL;
10332         bnxt_free_port_stats(bp);
10333         free_netdev(dev);
10334 }
10335
10336 static int bnxt_probe_phy(struct bnxt *bp)
10337 {
10338         int rc = 0;
10339         struct bnxt_link_info *link_info = &bp->link_info;
10340
10341         rc = bnxt_hwrm_phy_qcaps(bp);
10342         if (rc) {
10343                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
10344                            rc);
10345                 return rc;
10346         }
10347         mutex_init(&bp->link_lock);
10348
10349         rc = bnxt_update_link(bp, false);
10350         if (rc) {
10351                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
10352                            rc);
10353                 return rc;
10354         }
10355
10356         /* Older firmware does not have supported_auto_speeds, so assume
10357          * that all supported speeds can be autonegotiated.
10358          */
10359         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
10360                 link_info->support_auto_speeds = link_info->support_speeds;
10361
10362         /*initialize the ethool setting copy with NVM settings */
10363         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
10364                 link_info->autoneg = BNXT_AUTONEG_SPEED;
10365                 if (bp->hwrm_spec_code >= 0x10201) {
10366                         if (link_info->auto_pause_setting &
10367                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
10368                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10369                 } else {
10370                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10371                 }
10372                 link_info->advertising = link_info->auto_link_speeds;
10373         } else {
10374                 link_info->req_link_speed = link_info->force_link_speed;
10375                 link_info->req_duplex = link_info->duplex_setting;
10376         }
10377         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
10378                 link_info->req_flow_ctrl =
10379                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
10380         else
10381                 link_info->req_flow_ctrl = link_info->force_pause_setting;
10382         return rc;
10383 }
10384
10385 static int bnxt_get_max_irq(struct pci_dev *pdev)
10386 {
10387         u16 ctrl;
10388
10389         if (!pdev->msix_cap)
10390                 return 1;
10391
10392         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
10393         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
10394 }
10395
10396 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10397                                 int *max_cp)
10398 {
10399         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10400         int max_ring_grps = 0, max_irq;
10401
10402         *max_tx = hw_resc->max_tx_rings;
10403         *max_rx = hw_resc->max_rx_rings;
10404         *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
10405         max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
10406                         bnxt_get_ulp_msix_num(bp),
10407                         hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
10408         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
10409                 *max_cp = min_t(int, *max_cp, max_irq);
10410         max_ring_grps = hw_resc->max_hw_ring_grps;
10411         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
10412                 *max_cp -= 1;
10413                 *max_rx -= 2;
10414         }
10415         if (bp->flags & BNXT_FLAG_AGG_RINGS)
10416                 *max_rx >>= 1;
10417         if (bp->flags & BNXT_FLAG_CHIP_P5) {
10418                 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
10419                 /* On P5 chips, max_cp output param should be available NQs */
10420                 *max_cp = max_irq;
10421         }
10422         *max_rx = min_t(int, *max_rx, max_ring_grps);
10423 }
10424
10425 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
10426 {
10427         int rx, tx, cp;
10428
10429         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
10430         *max_rx = rx;
10431         *max_tx = tx;
10432         if (!rx || !tx || !cp)
10433                 return -ENOMEM;
10434
10435         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
10436 }
10437
10438 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10439                                bool shared)
10440 {
10441         int rc;
10442
10443         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10444         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
10445                 /* Not enough rings, try disabling agg rings. */
10446                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
10447                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10448                 if (rc) {
10449                         /* set BNXT_FLAG_AGG_RINGS back for consistency */
10450                         bp->flags |= BNXT_FLAG_AGG_RINGS;
10451                         return rc;
10452                 }
10453                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
10454                 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10455                 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10456                 bnxt_set_ring_params(bp);
10457         }
10458
10459         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
10460                 int max_cp, max_stat, max_irq;
10461
10462                 /* Reserve minimum resources for RoCE */
10463                 max_cp = bnxt_get_max_func_cp_rings(bp);
10464                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
10465                 max_irq = bnxt_get_max_func_irqs(bp);
10466                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
10467                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
10468                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
10469                         return 0;
10470
10471                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
10472                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
10473                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
10474                 max_cp = min_t(int, max_cp, max_irq);
10475                 max_cp = min_t(int, max_cp, max_stat);
10476                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
10477                 if (rc)
10478                         rc = 0;
10479         }
10480         return rc;
10481 }
10482
10483 /* In initial default shared ring setting, each shared ring must have a
10484  * RX/TX ring pair.
10485  */
10486 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
10487 {
10488         bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
10489         bp->rx_nr_rings = bp->cp_nr_rings;
10490         bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
10491         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10492 }
10493
10494 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
10495 {
10496         int dflt_rings, max_rx_rings, max_tx_rings, rc;
10497
10498         if (!bnxt_can_reserve_rings(bp))
10499                 return 0;
10500
10501         if (sh)
10502                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
10503         dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues();
10504         /* Reduce default rings on multi-port cards so that total default
10505          * rings do not exceed CPU count.
10506          */
10507         if (bp->port_count > 1) {
10508                 int max_rings =
10509                         max_t(int, num_online_cpus() / bp->port_count, 1);
10510
10511                 dflt_rings = min_t(int, dflt_rings, max_rings);
10512         }
10513         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
10514         if (rc)
10515                 return rc;
10516         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
10517         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
10518         if (sh)
10519                 bnxt_trim_dflt_sh_rings(bp);
10520         else
10521                 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
10522         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10523
10524         rc = __bnxt_reserve_rings(bp);
10525         if (rc)
10526                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
10527         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10528         if (sh)
10529                 bnxt_trim_dflt_sh_rings(bp);
10530
10531         /* Rings may have been trimmed, re-reserve the trimmed rings. */
10532         if (bnxt_need_reserve_rings(bp)) {
10533                 rc = __bnxt_reserve_rings(bp);
10534                 if (rc)
10535                         netdev_warn(bp->dev, "2nd rings reservation failed.\n");
10536                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10537         }
10538         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
10539                 bp->rx_nr_rings++;
10540                 bp->cp_nr_rings++;
10541         }
10542         return rc;
10543 }
10544
10545 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
10546 {
10547         int rc;
10548
10549         if (bp->tx_nr_rings)
10550                 return 0;
10551
10552         bnxt_ulp_irq_stop(bp);
10553         bnxt_clear_int_mode(bp);
10554         rc = bnxt_set_dflt_rings(bp, true);
10555         if (rc) {
10556                 netdev_err(bp->dev, "Not enough rings available.\n");
10557                 goto init_dflt_ring_err;
10558         }
10559         rc = bnxt_init_int_mode(bp);
10560         if (rc)
10561                 goto init_dflt_ring_err;
10562
10563         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10564         if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
10565                 bp->flags |= BNXT_FLAG_RFS;
10566                 bp->dev->features |= NETIF_F_NTUPLE;
10567         }
10568 init_dflt_ring_err:
10569         bnxt_ulp_irq_restart(bp, rc);
10570         return rc;
10571 }
10572
10573 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
10574 {
10575         int rc;
10576
10577         ASSERT_RTNL();
10578         bnxt_hwrm_func_qcaps(bp);
10579
10580         if (netif_running(bp->dev))
10581                 __bnxt_close_nic(bp, true, false);
10582
10583         bnxt_ulp_irq_stop(bp);
10584         bnxt_clear_int_mode(bp);
10585         rc = bnxt_init_int_mode(bp);
10586         bnxt_ulp_irq_restart(bp, rc);
10587
10588         if (netif_running(bp->dev)) {
10589                 if (rc)
10590                         dev_close(bp->dev);
10591                 else
10592                         rc = bnxt_open_nic(bp, true, false);
10593         }
10594
10595         return rc;
10596 }
10597
10598 static int bnxt_init_mac_addr(struct bnxt *bp)
10599 {
10600         int rc = 0;
10601
10602         if (BNXT_PF(bp)) {
10603                 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
10604         } else {
10605 #ifdef CONFIG_BNXT_SRIOV
10606                 struct bnxt_vf_info *vf = &bp->vf;
10607                 bool strict_approval = true;
10608
10609                 if (is_valid_ether_addr(vf->mac_addr)) {
10610                         /* overwrite netdev dev_addr with admin VF MAC */
10611                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
10612                         /* Older PF driver or firmware may not approve this
10613                          * correctly.
10614                          */
10615                         strict_approval = false;
10616                 } else {
10617                         eth_hw_addr_random(bp->dev);
10618                 }
10619                 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
10620 #endif
10621         }
10622         return rc;
10623 }
10624
10625 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
10626 {
10627         struct pci_dev *pdev = bp->pdev;
10628         int pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN);
10629         u32 dw;
10630
10631         if (!pos) {
10632                 netdev_info(bp->dev, "Unable do read adapter's DSN");
10633                 return -EOPNOTSUPP;
10634         }
10635
10636         /* DSN (two dw) is at an offset of 4 from the cap pos */
10637         pos += 4;
10638         pci_read_config_dword(pdev, pos, &dw);
10639         put_unaligned_le32(dw, &dsn[0]);
10640         pci_read_config_dword(pdev, pos + 4, &dw);
10641         put_unaligned_le32(dw, &dsn[4]);
10642         return 0;
10643 }
10644
10645 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
10646 {
10647         static int version_printed;
10648         struct net_device *dev;
10649         struct bnxt *bp;
10650         int rc, max_irqs;
10651
10652         if (pci_is_bridge(pdev))
10653                 return -ENODEV;
10654
10655         if (version_printed++ == 0)
10656                 pr_info("%s", version);
10657
10658         max_irqs = bnxt_get_max_irq(pdev);
10659         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
10660         if (!dev)
10661                 return -ENOMEM;
10662
10663         bp = netdev_priv(dev);
10664         bnxt_set_max_func_irqs(bp, max_irqs);
10665
10666         if (bnxt_vf_pciid(ent->driver_data))
10667                 bp->flags |= BNXT_FLAG_VF;
10668
10669         if (pdev->msix_cap)
10670                 bp->flags |= BNXT_FLAG_MSIX_CAP;
10671
10672         rc = bnxt_init_board(pdev, dev);
10673         if (rc < 0)
10674                 goto init_err_free;
10675
10676         dev->netdev_ops = &bnxt_netdev_ops;
10677         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
10678         dev->ethtool_ops = &bnxt_ethtool_ops;
10679         pci_set_drvdata(pdev, dev);
10680
10681         rc = bnxt_alloc_hwrm_resources(bp);
10682         if (rc)
10683                 goto init_err_pci_clean;
10684
10685         mutex_init(&bp->hwrm_cmd_lock);
10686         rc = bnxt_hwrm_ver_get(bp);
10687         if (rc)
10688                 goto init_err_pci_clean;
10689
10690         if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
10691                 rc = bnxt_alloc_kong_hwrm_resources(bp);
10692                 if (rc)
10693                         bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
10694         }
10695
10696         if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
10697             bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
10698                 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
10699                 if (rc)
10700                         goto init_err_pci_clean;
10701         }
10702
10703         if (BNXT_CHIP_P5(bp))
10704                 bp->flags |= BNXT_FLAG_CHIP_P5;
10705
10706         rc = bnxt_hwrm_func_reset(bp);
10707         if (rc)
10708                 goto init_err_pci_clean;
10709
10710         bnxt_hwrm_fw_set_time(bp);
10711
10712         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10713                            NETIF_F_TSO | NETIF_F_TSO6 |
10714                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10715                            NETIF_F_GSO_IPXIP4 |
10716                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10717                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
10718                            NETIF_F_RXCSUM | NETIF_F_GRO;
10719
10720         if (BNXT_SUPPORTS_TPA(bp))
10721                 dev->hw_features |= NETIF_F_LRO;
10722
10723         dev->hw_enc_features =
10724                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10725                         NETIF_F_TSO | NETIF_F_TSO6 |
10726                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10727                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10728                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
10729         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
10730                                     NETIF_F_GSO_GRE_CSUM;
10731         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
10732         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
10733                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
10734         if (BNXT_SUPPORTS_TPA(bp))
10735                 dev->hw_features |= NETIF_F_GRO_HW;
10736         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
10737         if (dev->features & NETIF_F_GRO_HW)
10738                 dev->features &= ~NETIF_F_LRO;
10739         dev->priv_flags |= IFF_UNICAST_FLT;
10740
10741 #ifdef CONFIG_BNXT_SRIOV
10742         init_waitqueue_head(&bp->sriov_cfg_wait);
10743         mutex_init(&bp->sriov_lock);
10744 #endif
10745         if (BNXT_SUPPORTS_TPA(bp)) {
10746                 bp->gro_func = bnxt_gro_func_5730x;
10747                 if (BNXT_CHIP_P4(bp))
10748                         bp->gro_func = bnxt_gro_func_5731x;
10749         }
10750         if (!BNXT_CHIP_P4_PLUS(bp))
10751                 bp->flags |= BNXT_FLAG_DOUBLE_DB;
10752
10753         rc = bnxt_hwrm_func_drv_rgtr(bp);
10754         if (rc)
10755                 goto init_err_pci_clean;
10756
10757         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
10758         if (rc)
10759                 goto init_err_pci_clean;
10760
10761         bp->ulp_probe = bnxt_ulp_probe;
10762
10763         rc = bnxt_hwrm_queue_qportcfg(bp);
10764         if (rc) {
10765                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
10766                            rc);
10767                 rc = -1;
10768                 goto init_err_pci_clean;
10769         }
10770         /* Get the MAX capabilities for this function */
10771         rc = bnxt_hwrm_func_qcaps(bp);
10772         if (rc) {
10773                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
10774                            rc);
10775                 rc = -1;
10776                 goto init_err_pci_clean;
10777         }
10778
10779         rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
10780         if (rc)
10781                 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
10782                             rc);
10783
10784         rc = bnxt_init_mac_addr(bp);
10785         if (rc) {
10786                 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
10787                 rc = -EADDRNOTAVAIL;
10788                 goto init_err_pci_clean;
10789         }
10790
10791         if (BNXT_PF(bp)) {
10792                 /* Read the adapter's DSN to use as the eswitch switch_id */
10793                 rc = bnxt_pcie_dsn_get(bp, bp->switch_id);
10794                 if (rc)
10795                         goto init_err_pci_clean;
10796         }
10797         bnxt_hwrm_func_qcfg(bp);
10798         bnxt_hwrm_vnic_qcaps(bp);
10799         bnxt_hwrm_port_led_qcaps(bp);
10800         bnxt_ethtool_init(bp);
10801         bnxt_dcb_init(bp);
10802
10803         /* MTU range: 60 - FW defined max */
10804         dev->min_mtu = ETH_ZLEN;
10805         dev->max_mtu = bp->max_mtu;
10806
10807         rc = bnxt_probe_phy(bp);
10808         if (rc)
10809                 goto init_err_pci_clean;
10810
10811         bnxt_set_rx_skb_mode(bp, false);
10812         bnxt_set_tpa_flags(bp);
10813         bnxt_set_ring_params(bp);
10814         rc = bnxt_set_dflt_rings(bp, true);
10815         if (rc) {
10816                 netdev_err(bp->dev, "Not enough rings available.\n");
10817                 rc = -ENOMEM;
10818                 goto init_err_pci_clean;
10819         }
10820
10821         /* Default RSS hash cfg. */
10822         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
10823                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
10824                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
10825                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
10826         if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) {
10827                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
10828                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
10829                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
10830         }
10831
10832         if (bnxt_rfs_supported(bp)) {
10833                 dev->hw_features |= NETIF_F_NTUPLE;
10834                 if (bnxt_rfs_capable(bp)) {
10835                         bp->flags |= BNXT_FLAG_RFS;
10836                         dev->features |= NETIF_F_NTUPLE;
10837                 }
10838         }
10839
10840         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
10841                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
10842
10843         rc = bnxt_init_int_mode(bp);
10844         if (rc)
10845                 goto init_err_pci_clean;
10846
10847         /* No TC has been set yet and rings may have been trimmed due to
10848          * limited MSIX, so we re-initialize the TX rings per TC.
10849          */
10850         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10851
10852         bnxt_get_wol_settings(bp);
10853         if (bp->flags & BNXT_FLAG_WOL_CAP)
10854                 device_set_wakeup_enable(&pdev->dev, bp->wol);
10855         else
10856                 device_set_wakeup_capable(&pdev->dev, false);
10857
10858         bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
10859
10860         bnxt_hwrm_coal_params_qcaps(bp);
10861
10862         if (BNXT_PF(bp)) {
10863                 if (!bnxt_pf_wq) {
10864                         bnxt_pf_wq =
10865                                 create_singlethread_workqueue("bnxt_pf_wq");
10866                         if (!bnxt_pf_wq) {
10867                                 dev_err(&pdev->dev, "Unable to create workqueue.\n");
10868                                 goto init_err_pci_clean;
10869                         }
10870                 }
10871                 bnxt_init_tc(bp);
10872         }
10873
10874         rc = register_netdev(dev);
10875         if (rc)
10876                 goto init_err_cleanup_tc;
10877
10878         if (BNXT_PF(bp))
10879                 bnxt_dl_register(bp);
10880
10881         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
10882                     board_info[ent->driver_data].name,
10883                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
10884         pcie_print_link_status(pdev);
10885
10886         return 0;
10887
10888 init_err_cleanup_tc:
10889         bnxt_shutdown_tc(bp);
10890         bnxt_clear_int_mode(bp);
10891
10892 init_err_pci_clean:
10893         bnxt_free_hwrm_short_cmd_req(bp);
10894         bnxt_free_hwrm_resources(bp);
10895         bnxt_free_ctx_mem(bp);
10896         kfree(bp->ctx);
10897         bp->ctx = NULL;
10898         bnxt_cleanup_pci(bp);
10899
10900 init_err_free:
10901         free_netdev(dev);
10902         return rc;
10903 }
10904
10905 static void bnxt_shutdown(struct pci_dev *pdev)
10906 {
10907         struct net_device *dev = pci_get_drvdata(pdev);
10908         struct bnxt *bp;
10909
10910         if (!dev)
10911                 return;
10912
10913         rtnl_lock();
10914         bp = netdev_priv(dev);
10915         if (!bp)
10916                 goto shutdown_exit;
10917
10918         if (netif_running(dev))
10919                 dev_close(dev);
10920
10921         bnxt_ulp_shutdown(bp);
10922
10923         if (system_state == SYSTEM_POWER_OFF) {
10924                 bnxt_clear_int_mode(bp);
10925                 pci_disable_device(pdev);
10926                 pci_wake_from_d3(pdev, bp->wol);
10927                 pci_set_power_state(pdev, PCI_D3hot);
10928         }
10929
10930 shutdown_exit:
10931         rtnl_unlock();
10932 }
10933
10934 #ifdef CONFIG_PM_SLEEP
10935 static int bnxt_suspend(struct device *device)
10936 {
10937         struct pci_dev *pdev = to_pci_dev(device);
10938         struct net_device *dev = pci_get_drvdata(pdev);
10939         struct bnxt *bp = netdev_priv(dev);
10940         int rc = 0;
10941
10942         rtnl_lock();
10943         if (netif_running(dev)) {
10944                 netif_device_detach(dev);
10945                 rc = bnxt_close(dev);
10946         }
10947         bnxt_hwrm_func_drv_unrgtr(bp);
10948         rtnl_unlock();
10949         return rc;
10950 }
10951
10952 static int bnxt_resume(struct device *device)
10953 {
10954         struct pci_dev *pdev = to_pci_dev(device);
10955         struct net_device *dev = pci_get_drvdata(pdev);
10956         struct bnxt *bp = netdev_priv(dev);
10957         int rc = 0;
10958
10959         rtnl_lock();
10960         if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
10961                 rc = -ENODEV;
10962                 goto resume_exit;
10963         }
10964         rc = bnxt_hwrm_func_reset(bp);
10965         if (rc) {
10966                 rc = -EBUSY;
10967                 goto resume_exit;
10968         }
10969         bnxt_get_wol_settings(bp);
10970         if (netif_running(dev)) {
10971                 rc = bnxt_open(dev);
10972                 if (!rc)
10973                         netif_device_attach(dev);
10974         }
10975
10976 resume_exit:
10977         rtnl_unlock();
10978         return rc;
10979 }
10980
10981 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
10982 #define BNXT_PM_OPS (&bnxt_pm_ops)
10983
10984 #else
10985
10986 #define BNXT_PM_OPS NULL
10987
10988 #endif /* CONFIG_PM_SLEEP */
10989
10990 /**
10991  * bnxt_io_error_detected - called when PCI error is detected
10992  * @pdev: Pointer to PCI device
10993  * @state: The current pci connection state
10994  *
10995  * This function is called after a PCI bus error affecting
10996  * this device has been detected.
10997  */
10998 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
10999                                                pci_channel_state_t state)
11000 {
11001         struct net_device *netdev = pci_get_drvdata(pdev);
11002         struct bnxt *bp = netdev_priv(netdev);
11003
11004         netdev_info(netdev, "PCI I/O error detected\n");
11005
11006         rtnl_lock();
11007         netif_device_detach(netdev);
11008
11009         bnxt_ulp_stop(bp);
11010
11011         if (state == pci_channel_io_perm_failure) {
11012                 rtnl_unlock();
11013                 return PCI_ERS_RESULT_DISCONNECT;
11014         }
11015
11016         if (netif_running(netdev))
11017                 bnxt_close(netdev);
11018
11019         pci_disable_device(pdev);
11020         rtnl_unlock();
11021
11022         /* Request a slot slot reset. */
11023         return PCI_ERS_RESULT_NEED_RESET;
11024 }
11025
11026 /**
11027  * bnxt_io_slot_reset - called after the pci bus has been reset.
11028  * @pdev: Pointer to PCI device
11029  *
11030  * Restart the card from scratch, as if from a cold-boot.
11031  * At this point, the card has exprienced a hard reset,
11032  * followed by fixups by BIOS, and has its config space
11033  * set up identically to what it was at cold boot.
11034  */
11035 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
11036 {
11037         struct net_device *netdev = pci_get_drvdata(pdev);
11038         struct bnxt *bp = netdev_priv(netdev);
11039         int err = 0;
11040         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
11041
11042         netdev_info(bp->dev, "PCI Slot Reset\n");
11043
11044         rtnl_lock();
11045
11046         if (pci_enable_device(pdev)) {
11047                 dev_err(&pdev->dev,
11048                         "Cannot re-enable PCI device after reset.\n");
11049         } else {
11050                 pci_set_master(pdev);
11051
11052                 err = bnxt_hwrm_func_reset(bp);
11053                 if (!err && netif_running(netdev))
11054                         err = bnxt_open(netdev);
11055
11056                 if (!err) {
11057                         result = PCI_ERS_RESULT_RECOVERED;
11058                         bnxt_ulp_start(bp);
11059                 }
11060         }
11061
11062         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
11063                 dev_close(netdev);
11064
11065         rtnl_unlock();
11066
11067         return PCI_ERS_RESULT_RECOVERED;
11068 }
11069
11070 /**
11071  * bnxt_io_resume - called when traffic can start flowing again.
11072  * @pdev: Pointer to PCI device
11073  *
11074  * This callback is called when the error recovery driver tells
11075  * us that its OK to resume normal operation.
11076  */
11077 static void bnxt_io_resume(struct pci_dev *pdev)
11078 {
11079         struct net_device *netdev = pci_get_drvdata(pdev);
11080
11081         rtnl_lock();
11082
11083         netif_device_attach(netdev);
11084
11085         rtnl_unlock();
11086 }
11087
11088 static const struct pci_error_handlers bnxt_err_handler = {
11089         .error_detected = bnxt_io_error_detected,
11090         .slot_reset     = bnxt_io_slot_reset,
11091         .resume         = bnxt_io_resume
11092 };
11093
11094 static struct pci_driver bnxt_pci_driver = {
11095         .name           = DRV_MODULE_NAME,
11096         .id_table       = bnxt_pci_tbl,
11097         .probe          = bnxt_init_one,
11098         .remove         = bnxt_remove_one,
11099         .shutdown       = bnxt_shutdown,
11100         .driver.pm      = BNXT_PM_OPS,
11101         .err_handler    = &bnxt_err_handler,
11102 #if defined(CONFIG_BNXT_SRIOV)
11103         .sriov_configure = bnxt_sriov_configure,
11104 #endif
11105 };
11106
11107 static int __init bnxt_init(void)
11108 {
11109         bnxt_debug_init();
11110         return pci_register_driver(&bnxt_pci_driver);
11111 }
11112
11113 static void __exit bnxt_exit(void)
11114 {
11115         pci_unregister_driver(&bnxt_pci_driver);
11116         if (bnxt_pf_wq)
11117                 destroy_workqueue(bnxt_pf_wq);
11118         bnxt_debug_exit();
11119 }
11120
11121 module_init(bnxt_init);
11122 module_exit(bnxt_exit);