3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 /* Ethernet chip registers.
35 #define SCBStatus 0 /* Rx/Command Unit Status *Word* */
36 #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
37 #define SCBCmd 2 /* Rx/Command Unit Command *Word* */
38 #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
39 #define SCBPointer 4 /* General purpose pointer. */
40 #define SCBPort 8 /* Misc. commands and operands. */
41 #define SCBflash 12 /* Flash memory control. */
42 #define SCBeeprom 14 /* EEPROM memory control. */
43 #define SCBCtrlMDI 16 /* MDI interface control. */
44 #define SCBEarlyRx 20 /* Early receive byte count. */
45 #define SCBGenControl 28 /* 82559 General Control Register */
46 #define SCBGenStatus 29 /* 82559 General Status register */
48 /* 82559 SCB status word defnitions
50 #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
51 #define SCB_STATUS_FR 0x4000 /* frame received */
52 #define SCB_STATUS_CNA 0x2000 /* CU left active state */
53 #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
54 #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
55 #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
56 #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
58 #define SCB_INTACK_MASK 0xFD00 /* all the above */
60 #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
61 #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
63 /* System control block commands
67 #define CU_START 0x0010
68 #define CU_RESUME 0x0020
69 #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
70 #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
71 #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
72 #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
75 #define RUC_NOP 0x0000
76 #define RUC_START 0x0001
77 #define RUC_RESUME 0x0002
78 #define RUC_ABORT 0x0004
79 #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
80 #define RUC_RESUMENR 0x0007
82 #define CU_CMD_MASK 0x00f0
83 #define RU_CMD_MASK 0x0007
85 #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
86 #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
88 #define CU_STATUS_MASK 0x00C0
89 #define RU_STATUS_MASK 0x003C
91 #define RU_STATUS_IDLE (0<<2)
92 #define RU_STATUS_SUS (1<<2)
93 #define RU_STATUS_NORES (2<<2)
94 #define RU_STATUS_READY (4<<2)
95 #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
96 #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
97 #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
99 /* 82559 Port interface commands.
101 #define I82559_RESET 0x00000000 /* Software reset */
102 #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
103 #define I82559_SELECTIVE_RESET 0x00000002
104 #define I82559_DUMP 0x00000003
105 #define I82559_DUMP_WAKEUP 0x00000007
107 /* 82559 Eeprom interface.
109 #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
110 #define EE_CS 0x02 /* EEPROM chip select. */
111 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
112 #define EE_WRITE_0 0x01
113 #define EE_WRITE_1 0x05
114 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
115 #define EE_ENB (0x4800 | EE_CS)
116 #define EE_CMD_BITS 3
117 #define EE_DATA_BITS 16
119 /* The EEPROM commands include the alway-set leading bit.
121 #define EE_EWENB_CMD (4 << addr_len)
122 #define EE_WRITE_CMD (5 << addr_len)
123 #define EE_READ_CMD (6 << addr_len)
124 #define EE_ERASE_CMD (7 << addr_len)
126 /* Receive frame descriptors.
130 volatile u16 control;
131 volatile u32 link; /* struct RxFD * */
132 volatile u32 rx_buf_addr; /* void * */
135 volatile u8 data[PKTSIZE_ALIGN];
138 #define RFD_STATUS_C 0x8000 /* completion of received frame */
139 #define RFD_STATUS_OK 0x2000 /* frame received with no errors */
141 #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
142 #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
143 #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
144 #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
146 #define RFD_COUNT_MASK 0x3fff
147 #define RFD_COUNT_F 0x4000
148 #define RFD_COUNT_EOF 0x8000
150 #define RFD_RX_CRC 0x0800 /* crc error */
151 #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
152 #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
153 #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
154 #define RFD_RX_SHORT 0x0080 /* short frame error */
155 #define RFD_RX_LENGTH 0x0020
156 #define RFD_RX_ERROR 0x0010 /* receive error */
157 #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
158 #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
159 #define RFD_RX_TCO 0x0001 /* TCO indication */
161 /* Transmit frame descriptors
163 struct TxFD { /* Transmit frame descriptor set. */
165 volatile u16 command;
166 volatile u32 link; /* void * */
167 volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
170 volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */
171 volatile s32 tx_buf_size0; /* Length of Tx frame. */
172 volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */
173 volatile s32 tx_buf_size1; /* Length of Tx frame. */
176 #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
177 #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
178 #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
179 #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
180 #define TxCB_CMD_S 0x4000 /* suspend on completion */
181 #define TxCB_CMD_EL 0x8000 /* last command block in CBL */
183 #define TxCB_COUNT_MASK 0x3fff
184 #define TxCB_COUNT_EOF 0x8000
186 /* The Speedo3 Rx and Tx frame/buffer descriptors.
188 struct descriptor { /* A generic descriptor. */
190 volatile u16 command;
191 volatile u32 link; /* struct descriptor * */
193 unsigned char params[0];
196 #define CFG_CMD_EL 0x8000
197 #define CFG_CMD_SUSPEND 0x4000
198 #define CFG_CMD_INT 0x2000
199 #define CFG_CMD_IAS 0x0001 /* individual address setup */
200 #define CFG_CMD_CONFIGURE 0x0002 /* configure */
202 #define CFG_STATUS_C 0x8000
203 #define CFG_STATUS_OK 0x2000
207 #define NUM_RX_DESC PKTBUFSRX
208 #define NUM_TX_DESC 1 /* Number of TX descriptors */
210 #define TOUT_LOOP 1000000
214 static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
215 static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
216 static int rx_next; /* RX descriptor ring pointer */
217 static int tx_next; /* TX descriptor ring pointer */
218 static int tx_threshold;
221 * The parameters for a CmdConfigure operation.
222 * There are so many options that it would be difficult to document
223 * each bit. We mostly use the default or recommended settings.
225 static const char i82557_config_cmd[] = {
226 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */
228 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */
231 static const char i82558_config_cmd[] = {
232 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
233 0, 0x2E, 0, 0x60, 0x08, 0x88,
234 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
238 static void init_rx_ring (struct eth_device *dev);
239 static void purge_tx_ring (struct eth_device *dev);
241 static void read_hw_addr (struct eth_device *dev, bd_t * bis);
243 static int eepro100_init (struct eth_device *dev, bd_t * bis);
244 static int eepro100_send (struct eth_device *dev, volatile void *packet,
246 static int eepro100_recv (struct eth_device *dev);
247 static void eepro100_halt (struct eth_device *dev);
249 #if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460)
250 #define bus_to_phys(a) (a)
251 #define phys_to_bus(a) (a)
253 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
254 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
257 static inline int INW (struct eth_device *dev, u_long addr)
259 return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase));
262 static inline void OUTW (struct eth_device *dev, int command, u_long addr)
264 *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command);
267 static inline void OUTL (struct eth_device *dev, int command, u_long addr)
269 *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command);
272 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
273 static inline int INL (struct eth_device *dev, u_long addr)
275 return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase));
278 static int get_phyreg (struct eth_device *dev, unsigned char addr,
279 unsigned char reg, unsigned short *value)
284 /* read requested data */
285 cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
286 OUTL (dev, cmd, SCBCtrlMDI);
290 cmd = INL (dev, SCBCtrlMDI);
291 } while (!(cmd & (1 << 28)) && (--timeout));
296 *value = (unsigned short) (cmd & 0xffff);
301 static int set_phyreg (struct eth_device *dev, unsigned char addr,
302 unsigned char reg, unsigned short value)
307 /* write requested data */
308 cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
309 OUTL (dev, cmd | value, SCBCtrlMDI);
311 while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout))
320 /* Check if given phyaddr is valid, i.e. there is a PHY connected.
321 * Do this by checking model value field from ID2 register.
323 static struct eth_device* verify_phyaddr (char *devname, unsigned char addr)
325 struct eth_device *dev;
326 unsigned short value;
329 dev = eth_get_dev_by_name(devname);
331 printf("%s: no such device\n", devname);
335 /* read id2 register */
336 if (get_phyreg(dev, addr, PHY_PHYIDR2, &value) != 0) {
337 printf("%s: mii read timeout!\n", devname);
342 model = (unsigned char)((value >> 4) & 0x003f);
345 printf("%s: no PHY at address %d\n", devname, addr);
352 static int eepro100_miiphy_read (char *devname, unsigned char addr,
353 unsigned char reg, unsigned short *value)
355 struct eth_device *dev;
357 dev = verify_phyaddr(devname, addr);
361 if (get_phyreg(dev, addr, reg, value) != 0) {
362 printf("%s: mii read timeout!\n", devname);
369 static int eepro100_miiphy_write (char *devname, unsigned char addr,
370 unsigned char reg, unsigned short value)
372 struct eth_device *dev;
374 dev = verify_phyaddr(devname, addr);
378 if (set_phyreg(dev, addr, reg, value) != 0) {
379 printf("%s: mii write timeout!\n", devname);
388 /* Wait for the chip get the command.
390 static int wait_for_eepro100 (struct eth_device *dev)
394 for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
395 if (i >= TOUT_LOOP) {
403 static struct pci_device_id supported[] = {
404 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
405 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
406 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
410 int eepro100_initialize (bd_t * bis)
414 struct eth_device *dev;
421 if ((devno = pci_find_devices (supported, idx++)) < 0) {
425 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
429 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
433 pci_write_config_dword (devno,
435 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
437 /* Check if I/O accesses and Bus Mastering are enabled.
439 pci_read_config_dword (devno, PCI_COMMAND, &status);
440 if (!(status & PCI_COMMAND_MEMORY)) {
441 printf ("Error: Can not enable MEM access.\n");
445 if (!(status & PCI_COMMAND_MASTER)) {
446 printf ("Error: Can not enable Bus Mastering.\n");
450 dev = (struct eth_device *) malloc (sizeof *dev);
452 sprintf (dev->name, "i82559#%d", card_number);
453 dev->priv = (void *) devno; /* this have to come before bus_to_phys() */
454 dev->iobase = bus_to_phys (iobase);
455 dev->init = eepro100_init;
456 dev->halt = eepro100_halt;
457 dev->send = eepro100_send;
458 dev->recv = eepro100_recv;
462 #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
463 /* register mii command access routines */
464 miiphy_register(dev->name,
465 eepro100_miiphy_read, eepro100_miiphy_write);
470 /* Set the latency timer for value.
472 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
476 read_hw_addr (dev, bis);
483 static int eepro100_init (struct eth_device *dev, bd_t * bis)
487 struct descriptor *ias_cmd, *cfg_cmd;
489 /* Reset the ethernet controller
491 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
494 OUTL (dev, I82559_RESET, SCBPort);
497 if (!wait_for_eepro100 (dev)) {
498 printf ("Error: Can not reset ethernet controller.\n");
501 OUTL (dev, 0, SCBPointer);
502 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
504 if (!wait_for_eepro100 (dev)) {
505 printf ("Error: Can not reset ethernet controller.\n");
508 OUTL (dev, 0, SCBPointer);
509 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
511 /* Initialize Rx and Tx rings.
516 /* Tell the adapter where the RX ring is located.
518 if (!wait_for_eepro100 (dev)) {
519 printf ("Error: Can not reset ethernet controller.\n");
523 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
524 OUTW (dev, SCB_M | RUC_START, SCBCmd);
526 /* Send the Configure frame */
528 tx_next = ((tx_next + 1) % NUM_TX_DESC);
530 cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
531 cfg_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_CONFIGURE));
533 cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
535 memcpy (cfg_cmd->params, i82558_config_cmd,
536 sizeof (i82558_config_cmd));
538 if (!wait_for_eepro100 (dev)) {
539 printf ("Error---CFG_CMD_CONFIGURE: Can not reset ethernet controller.\n");
543 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
544 OUTW (dev, SCB_M | CU_START, SCBCmd);
547 !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
549 if (i >= TOUT_LOOP) {
550 printf ("%s: Tx error buffer not ready\n", dev->name);
555 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
556 printf ("TX error status = 0x%08X\n",
557 le16_to_cpu (tx_ring[tx_cur].status));
561 /* Send the Individual Address Setup frame
564 tx_next = ((tx_next + 1) % NUM_TX_DESC);
566 ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
567 ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS));
569 ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
571 memcpy (ias_cmd->params, dev->enetaddr, 6);
573 /* Tell the adapter where the TX ring is located.
575 if (!wait_for_eepro100 (dev)) {
576 printf ("Error: Can not reset ethernet controller.\n");
580 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
581 OUTW (dev, SCB_M | CU_START, SCBCmd);
583 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
585 if (i >= TOUT_LOOP) {
586 printf ("%s: Tx error buffer not ready\n",
592 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
593 printf ("TX error status = 0x%08X\n",
594 le16_to_cpu (tx_ring[tx_cur].status));
604 static int eepro100_send (struct eth_device *dev, volatile void *packet, int length)
610 printf ("%s: bad packet size: %d\n", dev->name, length);
615 tx_next = (tx_next + 1) % NUM_TX_DESC;
617 tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
621 tx_ring[tx_cur].status = 0;
622 tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
623 tx_ring[tx_cur].link =
624 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
625 tx_ring[tx_cur].tx_desc_addr =
626 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
627 tx_ring[tx_cur].tx_buf_addr0 =
628 cpu_to_le32 (phys_to_bus ((u_long) packet));
629 tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
631 if (!wait_for_eepro100 (dev)) {
632 printf ("%s: Tx error ethernet controller not ready.\n",
639 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
640 OUTW (dev, SCB_M | CU_START, SCBCmd);
642 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
644 if (i >= TOUT_LOOP) {
645 printf ("%s: Tx error buffer not ready\n", dev->name);
650 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
651 printf ("TX error status = 0x%08X\n",
652 le16_to_cpu (tx_ring[tx_cur].status));
662 static int eepro100_recv (struct eth_device *dev)
665 int rx_prev, length = 0;
667 stat = INW (dev, SCBStatus);
668 OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
671 status = le16_to_cpu (rx_ring[rx_next].status);
673 if (!(status & RFD_STATUS_C)) {
677 /* Valid frame status.
679 if ((status & RFD_STATUS_OK)) {
680 /* A valid frame received.
682 length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
684 /* Pass the packet up to the protocol
687 NetReceive (rx_ring[rx_next].data, length);
689 /* There was an error.
691 printf ("RX error status = 0x%08X\n", status);
694 rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
695 rx_ring[rx_next].status = 0;
696 rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
698 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
699 rx_ring[rx_prev].control = 0;
701 /* Update entry information.
703 rx_next = (rx_next + 1) % NUM_RX_DESC;
706 if (stat & SCB_STATUS_RNR) {
708 printf ("%s: Receiver is not ready, restart it !\n", dev->name);
710 /* Reinitialize Rx ring.
714 if (!wait_for_eepro100 (dev)) {
715 printf ("Error: Can not restart ethernet controller.\n");
719 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
720 OUTW (dev, SCB_M | RUC_START, SCBCmd);
727 static void eepro100_halt (struct eth_device *dev)
729 /* Reset the ethernet controller
731 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
734 OUTL (dev, I82559_RESET, SCBPort);
737 if (!wait_for_eepro100 (dev)) {
738 printf ("Error: Can not reset ethernet controller.\n");
741 OUTL (dev, 0, SCBPointer);
742 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
744 if (!wait_for_eepro100 (dev)) {
745 printf ("Error: Can not reset ethernet controller.\n");
748 OUTL (dev, 0, SCBPointer);
749 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
757 static int read_eeprom (struct eth_device *dev, int location, int addr_len)
759 unsigned short retval = 0;
760 int read_cmd = location | EE_READ_CMD;
763 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
764 OUTW (dev, EE_ENB, SCBeeprom);
766 /* Shift the read command bits out. */
767 for (i = 12; i >= 0; i--) {
768 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
770 OUTW (dev, EE_ENB | dataval, SCBeeprom);
772 OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
775 OUTW (dev, EE_ENB, SCBeeprom);
777 for (i = 15; i >= 0; i--) {
778 OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
780 retval = (retval << 1) |
781 ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
782 OUTW (dev, EE_ENB, SCBeeprom);
786 /* Terminate the EEPROM access. */
787 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
791 #ifdef CONFIG_EEPRO100_SROM_WRITE
792 int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
794 unsigned short dataval;
795 int enable_cmd = 0x3f | EE_EWENB_CMD;
796 int write_cmd = location | EE_WRITE_CMD;
798 unsigned long datalong, tmplong;
800 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
802 OUTW(dev, EE_ENB, SCBeeprom);
804 /* Shift the enable command bits out. */
805 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
807 dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
808 OUTW(dev, EE_ENB | dataval, SCBeeprom);
810 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
814 OUTW(dev, EE_ENB, SCBeeprom);
816 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
818 OUTW(dev, EE_ENB, SCBeeprom);
821 /* Shift the write command bits out. */
822 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
824 dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
825 OUTW(dev, EE_ENB | dataval, SCBeeprom);
827 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
832 datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
834 for (i = 0; i< EE_DATA_BITS; i++)
836 /* Extract and move data bit to bit DI */
837 dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
839 OUTW(dev, EE_ENB | dataval, SCBeeprom);
841 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
843 OUTW(dev, EE_ENB | dataval, SCBeeprom);
846 datalong = datalong << 1; /* Adjust significant data bit*/
849 /* Finish up command (toggle CS) */
850 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
851 udelay(1); /* delay for more than 250 ns */
852 OUTW(dev, EE_ENB, SCBeeprom);
854 /* Wait for programming ready (D0 = 1) */
858 dataval = INW(dev, SCBeeprom);
859 if (dataval & EE_DATA_READ)
867 printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
871 /* Terminate the EEPROM access. */
872 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
878 static void init_rx_ring (struct eth_device *dev)
882 for (i = 0; i < NUM_RX_DESC; i++) {
883 rx_ring[i].status = 0;
885 (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
887 cpu_to_le32 (phys_to_bus
888 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
889 rx_ring[i].rx_buf_addr = 0xffffffff;
890 rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
896 static void purge_tx_ring (struct eth_device *dev)
901 tx_threshold = 0x01208000;
903 for (i = 0; i < NUM_TX_DESC; i++) {
904 tx_ring[i].status = 0;
905 tx_ring[i].command = 0;
907 tx_ring[i].tx_desc_addr = 0;
908 tx_ring[i].count = 0;
910 tx_ring[i].tx_buf_addr0 = 0;
911 tx_ring[i].tx_buf_size0 = 0;
912 tx_ring[i].tx_buf_addr1 = 0;
913 tx_ring[i].tx_buf_size1 = 0;
917 static void read_hw_addr (struct eth_device *dev, bd_t * bis)
922 int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
924 for (j = 0, i = 0; i < 0x40; i++) {
925 u16 value = read_eeprom (dev, i, addr_len);
930 dev->enetaddr[j++] = value;
931 dev->enetaddr[j++] = value >> 8;
936 memset (dev->enetaddr, 0, ETH_ALEN);
938 printf ("%s: Invalid EEPROM checksum %#4.4x, "
939 "check settings before activating this device!\n",