1 /**************************************************************************
2 Intel Pro 1000 for ppcboot/das-u-boot
3 Drivers are port from Intel's Linux driver e1000-4.3.15
4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
5 tested on both gig copper and gig fiber boards
6 ***************************************************************************/
7 /*******************************************************************************
10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
12 This program is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published by the Free
14 Software Foundation; either version 2 of the License, or (at your option)
17 This program is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 You should have received a copy of the GNU General Public License along with
23 this program; if not, write to the Free Software Foundation, Inc., 59
24 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 The full GNU General Public License is included in this distribution in the
30 Linux NICS <linux.nics@intel.com>
31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 *******************************************************************************/
35 * Copyright (C) Archway Digital Solutions.
37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
40 * Copyright (C) Linux Networx.
41 * Massive upgrade to work with the new intel gigabit NICs.
42 * <ebiederman at lnxi dot com>
47 #define TOUT_LOOP 100000
50 #define virt_to_bus(x) ((unsigned long)x)
51 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
52 #define mdelay(n) udelay((n)*1000)
54 #define E1000_DEFAULT_PBA 0x00000030
56 /* NIC specific static variables go here */
58 static char tx_pool[128 + 16];
59 static char rx_pool[128 + 16];
60 static char packet[2096];
62 static struct e1000_tx_desc *tx_base;
63 static struct e1000_rx_desc *rx_base;
66 static int rx_tail, rx_last;
68 static struct pci_device_id supported[] = {
69 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
72 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
86 /* Function forward declarations */
87 static int e1000_setup_link(struct eth_device *nic);
88 static int e1000_setup_fiber_link(struct eth_device *nic);
89 static int e1000_setup_copper_link(struct eth_device *nic);
90 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
91 static void e1000_config_collision_dist(struct e1000_hw *hw);
92 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
93 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
94 static int e1000_check_for_link(struct eth_device *nic);
95 static int e1000_wait_autoneg(struct e1000_hw *hw);
96 static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
98 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
100 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
102 static void e1000_phy_hw_reset(struct e1000_hw *hw);
103 static int e1000_phy_reset(struct e1000_hw *hw);
104 static int e1000_detect_gig_phy(struct e1000_hw *hw);
106 #define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg)))
107 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg))
108 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\
109 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))))
110 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
111 readl((a)->hw_addr + E1000_##reg + ((offset) << 2)))
112 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
114 #ifndef CONFIG_AP1000 /* remove for warnings */
115 /******************************************************************************
116 * Raises the EEPROM's clock input.
118 * hw - Struct containing variables accessed by shared code
119 * eecd - EECD's current value
120 *****************************************************************************/
122 e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
124 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
125 * wait 50 microseconds.
127 *eecd = *eecd | E1000_EECD_SK;
128 E1000_WRITE_REG(hw, EECD, *eecd);
129 E1000_WRITE_FLUSH(hw);
133 /******************************************************************************
134 * Lowers the EEPROM's clock input.
136 * hw - Struct containing variables accessed by shared code
137 * eecd - EECD's current value
138 *****************************************************************************/
140 e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
142 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
143 * wait 50 microseconds.
145 *eecd = *eecd & ~E1000_EECD_SK;
146 E1000_WRITE_REG(hw, EECD, *eecd);
147 E1000_WRITE_FLUSH(hw);
151 /******************************************************************************
152 * Shift data bits out to the EEPROM.
154 * hw - Struct containing variables accessed by shared code
155 * data - data to send to the EEPROM
156 * count - number of bits to shift out
157 *****************************************************************************/
159 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
164 /* We need to shift "count" bits out to the EEPROM. So, value in the
165 * "data" parameter will be shifted out to the EEPROM one bit at a time.
166 * In order to do this, "data" must be broken down into bits.
168 mask = 0x01 << (count - 1);
169 eecd = E1000_READ_REG(hw, EECD);
170 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
172 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
173 * and then raising and then lowering the clock (the SK bit controls
174 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
175 * by setting "DI" to "0" and then raising and then lowering the clock.
177 eecd &= ~E1000_EECD_DI;
180 eecd |= E1000_EECD_DI;
182 E1000_WRITE_REG(hw, EECD, eecd);
183 E1000_WRITE_FLUSH(hw);
187 e1000_raise_ee_clk(hw, &eecd);
188 e1000_lower_ee_clk(hw, &eecd);
194 /* We leave the "DI" bit set to "0" when we leave this routine. */
195 eecd &= ~E1000_EECD_DI;
196 E1000_WRITE_REG(hw, EECD, eecd);
199 /******************************************************************************
200 * Shift data bits in from the EEPROM
202 * hw - Struct containing variables accessed by shared code
203 *****************************************************************************/
205 e1000_shift_in_ee_bits(struct e1000_hw *hw)
211 /* In order to read a register from the EEPROM, we need to shift 16 bits
212 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
213 * the EEPROM (setting the SK bit), and then reading the value of the "DO"
214 * bit. During this "shifting in" process the "DI" bit should always be
218 eecd = E1000_READ_REG(hw, EECD);
220 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
223 for (i = 0; i < 16; i++) {
225 e1000_raise_ee_clk(hw, &eecd);
227 eecd = E1000_READ_REG(hw, EECD);
229 eecd &= ~(E1000_EECD_DI);
230 if (eecd & E1000_EECD_DO)
233 e1000_lower_ee_clk(hw, &eecd);
239 /******************************************************************************
240 * Prepares EEPROM for access
242 * hw - Struct containing variables accessed by shared code
244 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
245 * function should be called before issuing a command to the EEPROM.
246 *****************************************************************************/
248 e1000_setup_eeprom(struct e1000_hw *hw)
252 eecd = E1000_READ_REG(hw, EECD);
254 /* Clear SK and DI */
255 eecd &= ~(E1000_EECD_SK | E1000_EECD_DI);
256 E1000_WRITE_REG(hw, EECD, eecd);
259 eecd |= E1000_EECD_CS;
260 E1000_WRITE_REG(hw, EECD, eecd);
263 /******************************************************************************
264 * Returns EEPROM to a "standby" state
266 * hw - Struct containing variables accessed by shared code
267 *****************************************************************************/
269 e1000_standby_eeprom(struct e1000_hw *hw)
273 eecd = E1000_READ_REG(hw, EECD);
276 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
277 E1000_WRITE_REG(hw, EECD, eecd);
278 E1000_WRITE_FLUSH(hw);
282 eecd |= E1000_EECD_SK;
283 E1000_WRITE_REG(hw, EECD, eecd);
284 E1000_WRITE_FLUSH(hw);
288 eecd |= E1000_EECD_CS;
289 E1000_WRITE_REG(hw, EECD, eecd);
290 E1000_WRITE_FLUSH(hw);
294 eecd &= ~E1000_EECD_SK;
295 E1000_WRITE_REG(hw, EECD, eecd);
296 E1000_WRITE_FLUSH(hw);
300 /******************************************************************************
301 * Reads a 16 bit word from the EEPROM.
303 * hw - Struct containing variables accessed by shared code
304 * offset - offset of word in the EEPROM to read
305 * data - word read from the EEPROM
306 *****************************************************************************/
308 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t * data)
312 int large_eeprom = FALSE;
314 /* Request EEPROM Access */
315 if (hw->mac_type > e1000_82544) {
316 eecd = E1000_READ_REG(hw, EECD);
317 if (eecd & E1000_EECD_SIZE)
319 eecd |= E1000_EECD_REQ;
320 E1000_WRITE_REG(hw, EECD, eecd);
321 eecd = E1000_READ_REG(hw, EECD);
322 while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
325 eecd = E1000_READ_REG(hw, EECD);
327 if (!(eecd & E1000_EECD_GNT)) {
328 eecd &= ~E1000_EECD_REQ;
329 E1000_WRITE_REG(hw, EECD, eecd);
330 DEBUGOUT("Could not acquire EEPROM grant\n");
331 return -E1000_ERR_EEPROM;
335 /* Prepare the EEPROM for reading */
336 e1000_setup_eeprom(hw);
338 /* Send the READ command (opcode + addr) */
339 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3);
340 e1000_shift_out_ee_bits(hw, offset, (large_eeprom) ? 8 : 6);
343 *data = e1000_shift_in_ee_bits(hw);
345 /* End this read operation */
346 e1000_standby_eeprom(hw);
348 /* Stop requesting EEPROM access */
349 if (hw->mac_type > e1000_82544) {
350 eecd = E1000_READ_REG(hw, EECD);
351 eecd &= ~E1000_EECD_REQ;
352 E1000_WRITE_REG(hw, EECD, eecd);
360 e1000_eeprom_cleanup(struct e1000_hw *hw)
364 eecd = E1000_READ_REG(hw, EECD);
365 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
366 E1000_WRITE_REG(hw, EECD, eecd);
367 e1000_raise_ee_clk(hw, &eecd);
368 e1000_lower_ee_clk(hw, &eecd);
372 e1000_wait_eeprom_done(struct e1000_hw *hw)
377 e1000_standby_eeprom(hw);
378 for (i = 0; i < 200; i++) {
379 eecd = E1000_READ_REG(hw, EECD);
380 if (eecd & E1000_EECD_DO)
388 e1000_write_eeprom(struct e1000_hw *hw, uint16_t Reg, uint16_t Data)
391 int large_eeprom = FALSE;
394 /* Request EEPROM Access */
395 if (hw->mac_type > e1000_82544) {
396 eecd = E1000_READ_REG(hw, EECD);
397 if (eecd & E1000_EECD_SIZE)
399 eecd |= E1000_EECD_REQ;
400 E1000_WRITE_REG(hw, EECD, eecd);
401 eecd = E1000_READ_REG(hw, EECD);
402 while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
405 eecd = E1000_READ_REG(hw, EECD);
407 if (!(eecd & E1000_EECD_GNT)) {
408 eecd &= ~E1000_EECD_REQ;
409 E1000_WRITE_REG(hw, EECD, eecd);
410 DEBUGOUT("Could not acquire EEPROM grant\n");
414 e1000_setup_eeprom(hw);
415 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE, 5);
416 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4);
417 e1000_standby_eeprom(hw);
418 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE, 3);
419 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 8 : 6);
420 e1000_shift_out_ee_bits(hw, Data, 16);
421 if (!e1000_wait_eeprom_done(hw)) {
424 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE, 5);
425 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4);
426 e1000_eeprom_cleanup(hw);
428 /* Stop requesting EEPROM access */
429 if (hw->mac_type > e1000_82544) {
430 eecd = E1000_READ_REG(hw, EECD);
431 eecd &= ~E1000_EECD_REQ;
432 E1000_WRITE_REG(hw, EECD, eecd);
435 eecd = E1000_READ_REG(hw, EECD);
436 while (((eecd & E1000_EECD_GNT)) && (i < 500)) {
439 eecd = E1000_READ_REG(hw, EECD);
441 if ((eecd & E1000_EECD_GNT)) {
442 DEBUGOUT("Could not release EEPROM grant\n");
448 /******************************************************************************
449 * Verifies that the EEPROM has a valid checksum
451 * hw - Struct containing variables accessed by shared code
453 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
454 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
456 *****************************************************************************/
458 e1000_validate_eeprom_checksum(struct eth_device *nic)
460 struct e1000_hw *hw = nic->priv;
461 uint16_t checksum = 0;
462 uint16_t i, eeprom_data;
466 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
467 if (e1000_read_eeprom(hw, i, &eeprom_data) < 0) {
468 DEBUGOUT("EEPROM Read Error\n");
469 return -E1000_ERR_EEPROM;
471 checksum += eeprom_data;
474 if (checksum == (uint16_t) EEPROM_SUM) {
477 DEBUGOUT("EEPROM Checksum Invalid\n");
478 return -E1000_ERR_EEPROM;
481 #endif /* #ifndef CONFIG_AP1000 */
483 /******************************************************************************
484 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
485 * second function of dual function devices
487 * nic - Struct containing variables accessed by shared code
488 *****************************************************************************/
490 e1000_read_mac_addr(struct eth_device *nic)
492 #ifndef CONFIG_AP1000
493 struct e1000_hw *hw = nic->priv;
495 uint16_t eeprom_data;
500 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
502 if (e1000_read_eeprom(hw, offset, &eeprom_data) < 0) {
503 DEBUGOUT("EEPROM Read Error\n");
504 return -E1000_ERR_EEPROM;
506 nic->enetaddr[i] = eeprom_data & 0xff;
507 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
509 if ((hw->mac_type == e1000_82546) &&
510 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
511 /* Invert the last bit if this is the second device */
512 nic->enetaddr[5] += 1;
514 #ifdef CONFIG_E1000_FALLBACK_MAC
515 if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 )
516 for ( i=0; i < NODE_ADDRESS_SIZE; i++ )
517 nic->enetaddr[i] = (CONFIG_E1000_FALLBACK_MAC >> (8*(5-i))) & 0xff;
521 * The AP1000's e1000 has no eeprom; the MAC address is stored in the
522 * environment variables. Currently this does not support the addition
523 * of a PMC e1000 card, which is certainly a possibility, so this should
524 * be updated to properly use the env variable only for the onboard e1000
532 s = getenv ("ethaddr");
534 return -E1000_ERR_EEPROM;
537 for(ii = 0; ii < 6; ii++) {
538 nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
540 s = (*e) ? e + 1 : e;
548 /******************************************************************************
549 * Initializes receive address filters.
551 * hw - Struct containing variables accessed by shared code
553 * Places the MAC address in receive address register 0 and clears the rest
554 * of the receive addresss registers. Clears the multicast table. Assumes
555 * the receiver is in reset when the routine is called.
556 *****************************************************************************/
558 e1000_init_rx_addrs(struct eth_device *nic)
560 struct e1000_hw *hw = nic->priv;
567 /* Setup the receive address. */
568 DEBUGOUT("Programming MAC Address into RAR[0]\n");
569 addr_low = (nic->enetaddr[0] |
570 (nic->enetaddr[1] << 8) |
571 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
573 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
575 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
576 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
578 /* Zero out the other 15 receive addresses. */
579 DEBUGOUT("Clearing RAR[1-15]\n");
580 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
581 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
582 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
586 /******************************************************************************
587 * Clears the VLAN filer table
589 * hw - Struct containing variables accessed by shared code
590 *****************************************************************************/
592 e1000_clear_vfta(struct e1000_hw *hw)
596 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
597 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
600 /******************************************************************************
601 * Set the mac type member in the hw struct.
603 * hw - Struct containing variables accessed by shared code
604 *****************************************************************************/
606 e1000_set_mac_type(struct e1000_hw *hw)
610 switch (hw->device_id) {
611 case E1000_DEV_ID_82542:
612 switch (hw->revision_id) {
613 case E1000_82542_2_0_REV_ID:
614 hw->mac_type = e1000_82542_rev2_0;
616 case E1000_82542_2_1_REV_ID:
617 hw->mac_type = e1000_82542_rev2_1;
620 /* Invalid 82542 revision ID */
621 return -E1000_ERR_MAC_TYPE;
624 case E1000_DEV_ID_82543GC_FIBER:
625 case E1000_DEV_ID_82543GC_COPPER:
626 hw->mac_type = e1000_82543;
628 case E1000_DEV_ID_82544EI_COPPER:
629 case E1000_DEV_ID_82544EI_FIBER:
630 case E1000_DEV_ID_82544GC_COPPER:
631 case E1000_DEV_ID_82544GC_LOM:
632 hw->mac_type = e1000_82544;
634 case E1000_DEV_ID_82540EM:
635 case E1000_DEV_ID_82540EM_LOM:
636 hw->mac_type = e1000_82540;
638 case E1000_DEV_ID_82545EM_COPPER:
639 case E1000_DEV_ID_82545EM_FIBER:
640 hw->mac_type = e1000_82545;
642 case E1000_DEV_ID_82546EB_COPPER:
643 case E1000_DEV_ID_82546EB_FIBER:
644 hw->mac_type = e1000_82546;
646 case E1000_DEV_ID_82541ER:
647 case E1000_DEV_ID_82541GI_LF:
648 hw->mac_type = e1000_82541_rev_2;
651 /* Should never have loaded on this device */
652 return -E1000_ERR_MAC_TYPE;
654 return E1000_SUCCESS;
657 /******************************************************************************
658 * Reset the transmit and receive units; mask and clear all interrupts.
660 * hw - Struct containing variables accessed by shared code
661 *****************************************************************************/
663 e1000_reset_hw(struct e1000_hw *hw)
672 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
673 if (hw->mac_type == e1000_82542_rev2_0) {
674 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
675 pci_write_config_word(hw->pdev, PCI_COMMAND,
677 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
680 /* Clear interrupt mask to stop board from generating interrupts */
681 DEBUGOUT("Masking off all interrupts\n");
682 E1000_WRITE_REG(hw, IMC, 0xffffffff);
684 /* Disable the Transmit and Receive units. Then delay to allow
685 * any pending transactions to complete before we hit the MAC with
688 E1000_WRITE_REG(hw, RCTL, 0);
689 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
690 E1000_WRITE_FLUSH(hw);
692 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
693 hw->tbi_compatibility_on = FALSE;
695 /* Delay to allow any outstanding PCI transactions to complete before
696 * resetting the device
700 /* Issue a global reset to the MAC. This will reset the chip's
701 * transmit, receive, DMA, and link units. It will not effect
702 * the current PCI configuration. The global reset bit is self-
703 * clearing, and should clear within a microsecond.
705 DEBUGOUT("Issuing a global reset to MAC\n");
706 ctrl = E1000_READ_REG(hw, CTRL);
709 if (hw->mac_type > e1000_82543)
710 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
713 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
715 /* Force a reload from the EEPROM if necessary */
716 if (hw->mac_type < e1000_82540) {
717 /* Wait for reset to complete */
719 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
720 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
721 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
722 E1000_WRITE_FLUSH(hw);
723 /* Wait for EEPROM reload */
726 /* Wait for EEPROM reload (it happens automatically) */
728 /* Dissable HW ARPs on ASF enabled adapters */
729 manc = E1000_READ_REG(hw, MANC);
730 manc &= ~(E1000_MANC_ARP_EN);
731 E1000_WRITE_REG(hw, MANC, manc);
734 /* Clear interrupt mask to stop board from generating interrupts */
735 DEBUGOUT("Masking off all interrupts\n");
736 E1000_WRITE_REG(hw, IMC, 0xffffffff);
738 /* Clear any pending interrupt events. */
739 icr = E1000_READ_REG(hw, ICR);
741 /* If MWI was previously enabled, reenable it. */
742 if (hw->mac_type == e1000_82542_rev2_0) {
743 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
747 /******************************************************************************
748 * Performs basic configuration of the adapter.
750 * hw - Struct containing variables accessed by shared code
752 * Assumes that the controller has previously been reset and is in a
753 * post-reset uninitialized state. Initializes the receive address registers,
754 * multicast table, and VLAN filter table. Calls routines to setup link
755 * configuration and flow control settings. Clears all on-chip counters. Leaves
756 * the transmit and receive units disabled and uninitialized.
757 *****************************************************************************/
759 e1000_init_hw(struct eth_device *nic)
761 struct e1000_hw *hw = nic->priv;
762 uint32_t ctrl, status;
765 uint16_t pcix_cmd_word;
766 uint16_t pcix_stat_hi_word;
769 e1000_bus_type bus_type = e1000_bus_type_unknown;
773 /* Initialize Identification LED */
774 ret_val = e1000_id_led_init(hw);
776 DEBUGOUT("Error Initializing Identification LED\n");
780 /* Set the Media Type and exit with error if it is not valid. */
781 if (hw->mac_type != e1000_82543) {
782 /* tbi_compatibility is only valid on 82543 */
783 hw->tbi_compatibility_en = FALSE;
786 if (hw->mac_type >= e1000_82543) {
787 status = E1000_READ_REG(hw, STATUS);
788 if (status & E1000_STATUS_TBIMODE) {
789 hw->media_type = e1000_media_type_fiber;
790 /* tbi_compatibility not valid on fiber */
791 hw->tbi_compatibility_en = FALSE;
793 hw->media_type = e1000_media_type_copper;
796 /* This is an 82542 (fiber only) */
797 hw->media_type = e1000_media_type_fiber;
800 /* Disabling VLAN filtering. */
801 DEBUGOUT("Initializing the IEEE VLAN\n");
802 E1000_WRITE_REG(hw, VET, 0);
804 e1000_clear_vfta(hw);
806 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
807 if (hw->mac_type == e1000_82542_rev2_0) {
808 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
809 pci_write_config_word(hw->pdev, PCI_COMMAND,
811 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
812 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
813 E1000_WRITE_FLUSH(hw);
817 /* Setup the receive address. This involves initializing all of the Receive
818 * Address Registers (RARs 0 - 15).
820 e1000_init_rx_addrs(nic);
822 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
823 if (hw->mac_type == e1000_82542_rev2_0) {
824 E1000_WRITE_REG(hw, RCTL, 0);
825 E1000_WRITE_FLUSH(hw);
827 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
830 /* Zero out the Multicast HASH table */
831 DEBUGOUT("Zeroing the MTA\n");
832 for (i = 0; i < E1000_MC_TBL_SIZE; i++)
833 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
836 /* Set the PCI priority bit correctly in the CTRL register. This
837 * determines if the adapter gives priority to receives, or if it
838 * gives equal priority to transmits and receives.
840 if (hw->dma_fairness) {
841 ctrl = E1000_READ_REG(hw, CTRL);
842 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
845 if (hw->mac_type >= e1000_82543) {
846 status = E1000_READ_REG(hw, STATUS);
847 bus_type = (status & E1000_STATUS_PCIX_MODE) ?
848 e1000_bus_type_pcix : e1000_bus_type_pci;
850 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
851 if (bus_type == e1000_bus_type_pcix) {
852 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
854 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
857 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
858 PCIX_COMMAND_MMRBC_SHIFT;
860 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
861 PCIX_STATUS_HI_MMRBC_SHIFT;
862 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
863 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
864 if (cmd_mmrbc > stat_mmrbc) {
865 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
866 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
867 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
872 /* Call a subroutine to configure the link and setup flow control. */
873 ret_val = e1000_setup_link(nic);
875 /* Set the transmit descriptor write-back policy */
876 if (hw->mac_type > e1000_82544) {
877 ctrl = E1000_READ_REG(hw, TXDCTL);
879 (ctrl & ~E1000_TXDCTL_WTHRESH) |
880 E1000_TXDCTL_FULL_TX_DESC_WB;
881 E1000_WRITE_REG(hw, TXDCTL, ctrl);
884 /* Clear all of the statistics registers (clear on read). It is
885 * important that we do this after we have tried to establish link
886 * because the symbol error count will increment wildly if there
889 e1000_clear_hw_cntrs(hw);
895 /******************************************************************************
896 * Configures flow control and link settings.
898 * hw - Struct containing variables accessed by shared code
900 * Determines which flow control settings to use. Calls the apropriate media-
901 * specific link configuration function. Configures the flow control settings.
902 * Assuming the adapter has a valid link partner, a valid link should be
903 * established. Assumes the hardware has previously been reset and the
904 * transmitter and receiver are not enabled.
905 *****************************************************************************/
907 e1000_setup_link(struct eth_device *nic)
909 struct e1000_hw *hw = nic->priv;
912 uint16_t eeprom_data;
916 #ifndef CONFIG_AP1000
917 /* Read and store word 0x0F of the EEPROM. This word contains bits
918 * that determine the hardware's default PAUSE (flow control) mode,
919 * a bit that determines whether the HW defaults to enabling or
920 * disabling auto-negotiation, and the direction of the
921 * SW defined pins. If there is no SW over-ride of the flow
922 * control setting, then the variable hw->fc will
923 * be initialized based on a value in the EEPROM.
925 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) {
926 DEBUGOUT("EEPROM Read Error\n");
927 return -E1000_ERR_EEPROM;
930 /* we have to hardcode the proper value for our hardware. */
931 /* this value is for the 82540EM pci card used for prototyping, and it works. */
932 eeprom_data = 0xb220;
935 if (hw->fc == e1000_fc_default) {
936 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
937 hw->fc = e1000_fc_none;
938 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
939 EEPROM_WORD0F_ASM_DIR)
940 hw->fc = e1000_fc_tx_pause;
942 hw->fc = e1000_fc_full;
945 /* We want to save off the original Flow Control configuration just
946 * in case we get disconnected and then reconnected into a different
947 * hub or switch with different Flow Control capabilities.
949 if (hw->mac_type == e1000_82542_rev2_0)
950 hw->fc &= (~e1000_fc_tx_pause);
952 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
953 hw->fc &= (~e1000_fc_rx_pause);
955 hw->original_fc = hw->fc;
957 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
959 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
960 * polarity value for the SW controlled pins, and setup the
961 * Extended Device Control reg with that info.
962 * This is needed because one of the SW controlled pins is used for
963 * signal detection. So this should be done before e1000_setup_pcs_link()
964 * or e1000_phy_setup() is called.
966 if (hw->mac_type == e1000_82543) {
967 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
969 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
972 /* Call the necessary subroutine to configure the link. */
973 ret_val = (hw->media_type == e1000_media_type_fiber) ?
974 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
979 /* Initialize the flow control address, type, and PAUSE timer
980 * registers to their default values. This is done even if flow
981 * control is disabled, because it does not hurt anything to
982 * initialize these registers.
985 ("Initializing the Flow Control address, type and timer regs\n");
987 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
988 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
989 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
990 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
992 /* Set the flow control receive threshold registers. Normally,
993 * these registers will be set to a default threshold that may be
994 * adjusted later by the driver's runtime code. However, if the
995 * ability to transmit pause frames in not enabled, then these
996 * registers will be set to 0.
998 if (!(hw->fc & e1000_fc_tx_pause)) {
999 E1000_WRITE_REG(hw, FCRTL, 0);
1000 E1000_WRITE_REG(hw, FCRTH, 0);
1002 /* We need to set up the Receive Threshold high and low water marks
1003 * as well as (optionally) enabling the transmission of XON frames.
1005 if (hw->fc_send_xon) {
1006 E1000_WRITE_REG(hw, FCRTL,
1007 (hw->fc_low_water | E1000_FCRTL_XONE));
1008 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1010 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1011 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1017 /******************************************************************************
1018 * Sets up link for a fiber based adapter
1020 * hw - Struct containing variables accessed by shared code
1022 * Manipulates Physical Coding Sublayer functions in order to configure
1023 * link. Assumes the hardware has been previously reset and the transmitter
1024 * and receiver are not enabled.
1025 *****************************************************************************/
1027 e1000_setup_fiber_link(struct eth_device *nic)
1029 struct e1000_hw *hw = nic->priv;
1038 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1039 * set when the optics detect a signal. On older adapters, it will be
1040 * cleared when there is a signal
1042 ctrl = E1000_READ_REG(hw, CTRL);
1043 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1044 signal = E1000_CTRL_SWDPIN1;
1048 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
1050 /* Take the link out of reset */
1051 ctrl &= ~(E1000_CTRL_LRST);
1053 e1000_config_collision_dist(hw);
1055 /* Check for a software override of the flow control settings, and setup
1056 * the device accordingly. If auto-negotiation is enabled, then software
1057 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1058 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1059 * auto-negotiation is disabled, then software will have to manually
1060 * configure the two flow control enable bits in the CTRL register.
1062 * The possible values of the "fc" parameter are:
1063 * 0: Flow control is completely disabled
1064 * 1: Rx flow control is enabled (we can receive pause frames, but
1065 * not send pause frames).
1066 * 2: Tx flow control is enabled (we can send pause frames but we do
1067 * not support receiving pause frames).
1068 * 3: Both Rx and TX flow control (symmetric) are enabled.
1072 /* Flow control is completely disabled by a software over-ride. */
1073 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1075 case e1000_fc_rx_pause:
1076 /* RX Flow control is enabled and TX Flow control is disabled by a
1077 * software over-ride. Since there really isn't a way to advertise
1078 * that we are capable of RX Pause ONLY, we will advertise that we
1079 * support both symmetric and asymmetric RX PAUSE. Later, we will
1080 * disable the adapter's ability to send PAUSE frames.
1082 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1084 case e1000_fc_tx_pause:
1085 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1086 * software over-ride.
1088 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1091 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1092 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1095 DEBUGOUT("Flow control param set incorrectly\n");
1096 return -E1000_ERR_CONFIG;
1100 /* Since auto-negotiation is enabled, take the link out of reset (the link
1101 * will be in reset, because we previously reset the chip). This will
1102 * restart auto-negotiation. If auto-neogtiation is successful then the
1103 * link-up status bit will be set and the flow control enable bits (RFCE
1104 * and TFCE) will be set according to their negotiated value.
1106 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
1108 E1000_WRITE_REG(hw, TXCW, txcw);
1109 E1000_WRITE_REG(hw, CTRL, ctrl);
1110 E1000_WRITE_FLUSH(hw);
1115 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1116 * indication in the Device Status Register. Time-out if a link isn't
1117 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1118 * less than 500 milliseconds even if the other end is doing it in SW).
1120 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1121 DEBUGOUT("Looking for Link\n");
1122 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1124 status = E1000_READ_REG(hw, STATUS);
1125 if (status & E1000_STATUS_LU)
1128 if (i == (LINK_UP_TIMEOUT / 10)) {
1129 /* AutoNeg failed to achieve a link, so we'll call
1130 * e1000_check_for_link. This routine will force the link up if we
1131 * detect a signal. This will allow us to communicate with
1132 * non-autonegotiating link partners.
1134 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1135 hw->autoneg_failed = 1;
1136 ret_val = e1000_check_for_link(nic);
1138 DEBUGOUT("Error while checking for link\n");
1141 hw->autoneg_failed = 0;
1143 hw->autoneg_failed = 0;
1144 DEBUGOUT("Valid Link Found\n");
1147 DEBUGOUT("No Signal Detected\n");
1148 return -E1000_ERR_NOLINK;
1153 /******************************************************************************
1154 * Detects which PHY is present and the speed and duplex
1156 * hw - Struct containing variables accessed by shared code
1157 ******************************************************************************/
1159 e1000_setup_copper_link(struct eth_device *nic)
1161 struct e1000_hw *hw = nic->priv;
1169 ctrl = E1000_READ_REG(hw, CTRL);
1170 /* With 82543, we need to force speed and duplex on the MAC equal to what
1171 * the PHY speed and duplex configuration is. In addition, we need to
1172 * perform a hardware reset on the PHY to take it out of reset.
1174 if (hw->mac_type > e1000_82543) {
1175 ctrl |= E1000_CTRL_SLU;
1176 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1177 E1000_WRITE_REG(hw, CTRL, ctrl);
1180 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1181 E1000_WRITE_REG(hw, CTRL, ctrl);
1182 e1000_phy_hw_reset(hw);
1185 /* Make sure we have a valid PHY */
1186 ret_val = e1000_detect_gig_phy(hw);
1188 DEBUGOUT("Error, did not detect valid phy.\n");
1191 DEBUGOUT("Phy ID = %x \n", hw->phy_id);
1193 /* Enable CRS on TX. This must be set for half-duplex operation. */
1194 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
1195 DEBUGOUT("PHY Read Error\n");
1196 return -E1000_ERR_PHY;
1198 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1202 * MDI/MDI-X = 0 (default)
1203 * 0 - Auto for all speeds
1206 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1208 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1211 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1214 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1217 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1221 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1225 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1230 * disable_polarity_correction = 0 (default)
1231 * Automatic Correction for Reversed Cable Polarity
1235 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1236 if (hw->disable_polarity_correction == 1)
1237 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1239 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1241 if (e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
1242 DEBUGOUT("PHY Write Error\n");
1243 return -E1000_ERR_PHY;
1246 /* Force TX_CLK in the Extended PHY Specific Control Register
1249 if (e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
1250 DEBUGOUT("PHY Read Error\n");
1251 return -E1000_ERR_PHY;
1253 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1254 /* Configure Master and Slave downshift values */
1255 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1256 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1257 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1258 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1259 if (e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
1260 DEBUGOUT("PHY Write Error\n");
1261 return -E1000_ERR_PHY;
1264 /* SW Reset the PHY so all changes take effect */
1265 ret_val = e1000_phy_reset(hw);
1267 DEBUGOUT("Error Resetting the PHY\n");
1272 * autoneg = 1 (default)
1273 * PHY will advertise value(s) parsed from
1274 * autoneg_advertised and fc
1276 * PHY will be set to 10H, 10F, 100H, or 100F
1277 * depending on value parsed from forced_speed_duplex.
1280 /* Is autoneg enabled? This is enabled by default or by software override.
1281 * If so, call e1000_phy_setup_autoneg routine to parse the
1282 * autoneg_advertised and fc options. If autoneg is NOT enabled, then the
1283 * user should have provided a speed/duplex override. If so, then call
1284 * e1000_phy_force_speed_duplex to parse and set this up.
1286 /* Perform some bounds checking on the hw->autoneg_advertised
1287 * parameter. If this variable is zero, then set it to the default.
1289 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1291 /* If autoneg_advertised is zero, we assume it was not defaulted
1292 * by the calling code so we set to advertise full capability.
1294 if (hw->autoneg_advertised == 0)
1295 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1297 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1298 ret_val = e1000_phy_setup_autoneg(hw);
1300 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1303 DEBUGOUT("Restarting Auto-Neg\n");
1305 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1306 * the Auto Neg Restart bit in the PHY control register.
1308 if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
1309 DEBUGOUT("PHY Read Error\n");
1310 return -E1000_ERR_PHY;
1312 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1313 if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
1314 DEBUGOUT("PHY Write Error\n");
1315 return -E1000_ERR_PHY;
1318 /* Does the user want to wait for Auto-Neg to complete here, or
1319 * check at a later time (for example, callback routine).
1321 if (hw->wait_autoneg_complete) {
1322 ret_val = e1000_wait_autoneg(hw);
1325 ("Error while waiting for autoneg to complete\n");
1330 /* If we do not wait for autonegtation to complete I
1331 * do not see a valid link status.
1333 ret_val = e1000_wait_autoneg(hw);
1335 DEBUGOUT("Error while waiting for autoneg to complete\n");
1340 /* Check link status. Wait up to 100 microseconds for link to become
1343 for (i = 0; i < 10; i++) {
1344 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1345 DEBUGOUT("PHY Read Error\n");
1346 return -E1000_ERR_PHY;
1348 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1349 DEBUGOUT("PHY Read Error\n");
1350 return -E1000_ERR_PHY;
1352 if (phy_data & MII_SR_LINK_STATUS) {
1353 /* We have link, so we need to finish the config process:
1354 * 1) Set up the MAC to the current PHY speed/duplex
1355 * if we are on 82543. If we
1356 * are on newer silicon, we only need to configure
1357 * collision distance in the Transmit Control Register.
1358 * 2) Set up flow control on the MAC to that established with
1361 if (hw->mac_type >= e1000_82544) {
1362 e1000_config_collision_dist(hw);
1364 ret_val = e1000_config_mac_to_phy(hw);
1367 ("Error configuring MAC to PHY settings\n");
1371 ret_val = e1000_config_fc_after_link_up(hw);
1373 DEBUGOUT("Error Configuring Flow Control\n");
1376 DEBUGOUT("Valid link established!!!\n");
1382 DEBUGOUT("Unable to establish link!!!\n");
1383 return -E1000_ERR_NOLINK;
1386 /******************************************************************************
1387 * Configures PHY autoneg and flow control advertisement settings
1389 * hw - Struct containing variables accessed by shared code
1390 ******************************************************************************/
1392 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1394 uint16_t mii_autoneg_adv_reg;
1395 uint16_t mii_1000t_ctrl_reg;
1399 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1400 if (e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) {
1401 DEBUGOUT("PHY Read Error\n");
1402 return -E1000_ERR_PHY;
1405 /* Read the MII 1000Base-T Control Register (Address 9). */
1406 if (e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) {
1407 DEBUGOUT("PHY Read Error\n");
1408 return -E1000_ERR_PHY;
1411 /* Need to parse both autoneg_advertised and fc and set up
1412 * the appropriate PHY registers. First we will parse for
1413 * autoneg_advertised software override. Since we can advertise
1414 * a plethora of combinations, we need to check each bit
1418 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1419 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1420 * the 1000Base-T Control Register (Address 9).
1422 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1423 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1425 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
1427 /* Do we want to advertise 10 Mb Half Duplex? */
1428 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1429 DEBUGOUT("Advertise 10mb Half duplex\n");
1430 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1433 /* Do we want to advertise 10 Mb Full Duplex? */
1434 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1435 DEBUGOUT("Advertise 10mb Full duplex\n");
1436 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1439 /* Do we want to advertise 100 Mb Half Duplex? */
1440 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1441 DEBUGOUT("Advertise 100mb Half duplex\n");
1442 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1445 /* Do we want to advertise 100 Mb Full Duplex? */
1446 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1447 DEBUGOUT("Advertise 100mb Full duplex\n");
1448 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1451 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1452 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1454 ("Advertise 1000mb Half duplex requested, request denied!\n");
1457 /* Do we want to advertise 1000 Mb Full Duplex? */
1458 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1459 DEBUGOUT("Advertise 1000mb Full duplex\n");
1460 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1463 /* Check for a software override of the flow control settings, and
1464 * setup the PHY advertisement registers accordingly. If
1465 * auto-negotiation is enabled, then software will have to set the
1466 * "PAUSE" bits to the correct value in the Auto-Negotiation
1467 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1469 * The possible values of the "fc" parameter are:
1470 * 0: Flow control is completely disabled
1471 * 1: Rx flow control is enabled (we can receive pause frames
1472 * but not send pause frames).
1473 * 2: Tx flow control is enabled (we can send pause frames
1474 * but we do not support receiving pause frames).
1475 * 3: Both Rx and TX flow control (symmetric) are enabled.
1476 * other: No software override. The flow control configuration
1477 * in the EEPROM is used.
1480 case e1000_fc_none: /* 0 */
1481 /* Flow control (RX & TX) is completely disabled by a
1482 * software over-ride.
1484 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1486 case e1000_fc_rx_pause: /* 1 */
1487 /* RX Flow control is enabled, and TX Flow control is
1488 * disabled, by a software over-ride.
1490 /* Since there really isn't a way to advertise that we are
1491 * capable of RX Pause ONLY, we will advertise that we
1492 * support both symmetric and asymmetric RX PAUSE. Later
1493 * (in e1000_config_fc_after_link_up) we will disable the
1494 *hw's ability to send PAUSE frames.
1496 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1498 case e1000_fc_tx_pause: /* 2 */
1499 /* TX Flow control is enabled, and RX Flow control is
1500 * disabled, by a software over-ride.
1502 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1503 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1505 case e1000_fc_full: /* 3 */
1506 /* Flow control (both RX and TX) is enabled by a software
1509 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1512 DEBUGOUT("Flow control param set incorrectly\n");
1513 return -E1000_ERR_CONFIG;
1516 if (e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) {
1517 DEBUGOUT("PHY Write Error\n");
1518 return -E1000_ERR_PHY;
1521 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1523 if (e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) {
1524 DEBUGOUT("PHY Write Error\n");
1525 return -E1000_ERR_PHY;
1530 /******************************************************************************
1531 * Sets the collision distance in the Transmit Control register
1533 * hw - Struct containing variables accessed by shared code
1535 * Link should have been established previously. Reads the speed and duplex
1536 * information from the Device Status register.
1537 ******************************************************************************/
1539 e1000_config_collision_dist(struct e1000_hw *hw)
1543 tctl = E1000_READ_REG(hw, TCTL);
1545 tctl &= ~E1000_TCTL_COLD;
1546 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1548 E1000_WRITE_REG(hw, TCTL, tctl);
1549 E1000_WRITE_FLUSH(hw);
1552 /******************************************************************************
1553 * Sets MAC speed and duplex settings to reflect the those in the PHY
1555 * hw - Struct containing variables accessed by shared code
1556 * mii_reg - data to write to the MII control register
1558 * The contents of the PHY register containing the needed information need to
1560 ******************************************************************************/
1562 e1000_config_mac_to_phy(struct e1000_hw *hw)
1569 /* Read the Device Control Register and set the bits to Force Speed
1572 ctrl = E1000_READ_REG(hw, CTRL);
1573 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1574 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1576 /* Set up duplex in the Device Control and Transmit Control
1577 * registers depending on negotiated values.
1579 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
1580 DEBUGOUT("PHY Read Error\n");
1581 return -E1000_ERR_PHY;
1583 if (phy_data & M88E1000_PSSR_DPLX)
1584 ctrl |= E1000_CTRL_FD;
1586 ctrl &= ~E1000_CTRL_FD;
1588 e1000_config_collision_dist(hw);
1590 /* Set up speed in the Device Control register depending on
1591 * negotiated values.
1593 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1594 ctrl |= E1000_CTRL_SPD_1000;
1595 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1596 ctrl |= E1000_CTRL_SPD_100;
1597 /* Write the configured values back to the Device Control Reg. */
1598 E1000_WRITE_REG(hw, CTRL, ctrl);
1602 /******************************************************************************
1603 * Forces the MAC's flow control settings.
1605 * hw - Struct containing variables accessed by shared code
1607 * Sets the TFCE and RFCE bits in the device control register to reflect
1608 * the adapter settings. TFCE and RFCE need to be explicitly set by
1609 * software when a Copper PHY is used because autonegotiation is managed
1610 * by the PHY rather than the MAC. Software must also configure these
1611 * bits when link is forced on a fiber connection.
1612 *****************************************************************************/
1614 e1000_force_mac_fc(struct e1000_hw *hw)
1620 /* Get the current configuration of the Device Control Register */
1621 ctrl = E1000_READ_REG(hw, CTRL);
1623 /* Because we didn't get link via the internal auto-negotiation
1624 * mechanism (we either forced link or we got link via PHY
1625 * auto-neg), we have to manually enable/disable transmit an
1626 * receive flow control.
1628 * The "Case" statement below enables/disable flow control
1629 * according to the "hw->fc" parameter.
1631 * The possible values of the "fc" parameter are:
1632 * 0: Flow control is completely disabled
1633 * 1: Rx flow control is enabled (we can receive pause
1634 * frames but not send pause frames).
1635 * 2: Tx flow control is enabled (we can send pause frames
1636 * frames but we do not receive pause frames).
1637 * 3: Both Rx and TX flow control (symmetric) is enabled.
1638 * other: No other values should be possible at this point.
1643 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1645 case e1000_fc_rx_pause:
1646 ctrl &= (~E1000_CTRL_TFCE);
1647 ctrl |= E1000_CTRL_RFCE;
1649 case e1000_fc_tx_pause:
1650 ctrl &= (~E1000_CTRL_RFCE);
1651 ctrl |= E1000_CTRL_TFCE;
1654 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1657 DEBUGOUT("Flow control param set incorrectly\n");
1658 return -E1000_ERR_CONFIG;
1661 /* Disable TX Flow Control for 82542 (rev 2.0) */
1662 if (hw->mac_type == e1000_82542_rev2_0)
1663 ctrl &= (~E1000_CTRL_TFCE);
1665 E1000_WRITE_REG(hw, CTRL, ctrl);
1669 /******************************************************************************
1670 * Configures flow control settings after link is established
1672 * hw - Struct containing variables accessed by shared code
1674 * Should be called immediately after a valid link has been established.
1675 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1676 * and autonegotiation is enabled, the MAC flow control settings will be set
1677 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1678 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1679 *****************************************************************************/
1681 e1000_config_fc_after_link_up(struct e1000_hw *hw)
1684 uint16_t mii_status_reg;
1685 uint16_t mii_nway_adv_reg;
1686 uint16_t mii_nway_lp_ability_reg;
1692 /* Check for the case where we have fiber media and auto-neg failed
1693 * so we had to force link. In this case, we need to force the
1694 * configuration of the MAC to match the "fc" parameter.
1696 if ((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) {
1697 ret_val = e1000_force_mac_fc(hw);
1699 DEBUGOUT("Error forcing flow control settings\n");
1704 /* Check for the case where we have copper media and auto-neg is
1705 * enabled. In this case, we need to check and see if Auto-Neg
1706 * has completed, and if so, how the PHY and link partner has
1707 * flow control configured.
1709 if (hw->media_type == e1000_media_type_copper) {
1710 /* Read the MII Status Register and check to see if AutoNeg
1711 * has completed. We read this twice because this reg has
1712 * some "sticky" (latched) bits.
1714 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1715 DEBUGOUT("PHY Read Error \n");
1716 return -E1000_ERR_PHY;
1718 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1719 DEBUGOUT("PHY Read Error \n");
1720 return -E1000_ERR_PHY;
1723 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1724 /* The AutoNeg process has completed, so we now need to
1725 * read both the Auto Negotiation Advertisement Register
1726 * (Address 4) and the Auto_Negotiation Base Page Ability
1727 * Register (Address 5) to determine how flow control was
1730 if (e1000_read_phy_reg
1731 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
1732 DEBUGOUT("PHY Read Error\n");
1733 return -E1000_ERR_PHY;
1735 if (e1000_read_phy_reg
1736 (hw, PHY_LP_ABILITY,
1737 &mii_nway_lp_ability_reg) < 0) {
1738 DEBUGOUT("PHY Read Error\n");
1739 return -E1000_ERR_PHY;
1742 /* Two bits in the Auto Negotiation Advertisement Register
1743 * (Address 4) and two bits in the Auto Negotiation Base
1744 * Page Ability Register (Address 5) determine flow control
1745 * for both the PHY and the link partner. The following
1746 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1747 * 1999, describes these PAUSE resolution bits and how flow
1748 * control is determined based upon these settings.
1749 * NOTE: DC = Don't Care
1751 * LOCAL DEVICE | LINK PARTNER
1752 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1753 *-------|---------|-------|---------|--------------------
1754 * 0 | 0 | DC | DC | e1000_fc_none
1755 * 0 | 1 | 0 | DC | e1000_fc_none
1756 * 0 | 1 | 1 | 0 | e1000_fc_none
1757 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1758 * 1 | 0 | 0 | DC | e1000_fc_none
1759 * 1 | DC | 1 | DC | e1000_fc_full
1760 * 1 | 1 | 0 | 0 | e1000_fc_none
1761 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1764 /* Are both PAUSE bits set to 1? If so, this implies
1765 * Symmetric Flow Control is enabled at both ends. The
1766 * ASM_DIR bits are irrelevant per the spec.
1768 * For Symmetric Flow Control:
1770 * LOCAL DEVICE | LINK PARTNER
1771 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1772 *-------|---------|-------|---------|--------------------
1773 * 1 | DC | 1 | DC | e1000_fc_full
1776 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1777 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1778 /* Now we need to check if the user selected RX ONLY
1779 * of pause frames. In this case, we had to advertise
1780 * FULL flow control because we could not advertise RX
1781 * ONLY. Hence, we must now check to see if we need to
1782 * turn OFF the TRANSMISSION of PAUSE frames.
1784 if (hw->original_fc == e1000_fc_full) {
1785 hw->fc = e1000_fc_full;
1786 DEBUGOUT("Flow Control = FULL.\r\n");
1788 hw->fc = e1000_fc_rx_pause;
1790 ("Flow Control = RX PAUSE frames only.\r\n");
1793 /* For receiving PAUSE frames ONLY.
1795 * LOCAL DEVICE | LINK PARTNER
1796 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1797 *-------|---------|-------|---------|--------------------
1798 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1801 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1802 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1803 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1804 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
1806 hw->fc = e1000_fc_tx_pause;
1808 ("Flow Control = TX PAUSE frames only.\r\n");
1810 /* For transmitting PAUSE frames ONLY.
1812 * LOCAL DEVICE | LINK PARTNER
1813 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1814 *-------|---------|-------|---------|--------------------
1815 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1818 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1819 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1820 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1821 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
1823 hw->fc = e1000_fc_rx_pause;
1825 ("Flow Control = RX PAUSE frames only.\r\n");
1827 /* Per the IEEE spec, at this point flow control should be
1828 * disabled. However, we want to consider that we could
1829 * be connected to a legacy switch that doesn't advertise
1830 * desired flow control, but can be forced on the link
1831 * partner. So if we advertised no flow control, that is
1832 * what we will resolve to. If we advertised some kind of
1833 * receive capability (Rx Pause Only or Full Flow Control)
1834 * and the link partner advertised none, we will configure
1835 * ourselves to enable Rx Flow Control only. We can do
1836 * this safely for two reasons: If the link partner really
1837 * didn't want flow control enabled, and we enable Rx, no
1838 * harm done since we won't be receiving any PAUSE frames
1839 * anyway. If the intent on the link partner was to have
1840 * flow control enabled, then by us enabling RX only, we
1841 * can at least receive pause frames and process them.
1842 * This is a good idea because in most cases, since we are
1843 * predominantly a server NIC, more times than not we will
1844 * be asked to delay transmission of packets than asking
1845 * our link partner to pause transmission of frames.
1847 else if (hw->original_fc == e1000_fc_none ||
1848 hw->original_fc == e1000_fc_tx_pause) {
1849 hw->fc = e1000_fc_none;
1850 DEBUGOUT("Flow Control = NONE.\r\n");
1852 hw->fc = e1000_fc_rx_pause;
1854 ("Flow Control = RX PAUSE frames only.\r\n");
1857 /* Now we need to do one last check... If we auto-
1858 * negotiated to HALF DUPLEX, flow control should not be
1859 * enabled per IEEE 802.3 spec.
1861 e1000_get_speed_and_duplex(hw, &speed, &duplex);
1863 if (duplex == HALF_DUPLEX)
1864 hw->fc = e1000_fc_none;
1866 /* Now we call a subroutine to actually force the MAC
1867 * controller to use the correct flow control settings.
1869 ret_val = e1000_force_mac_fc(hw);
1872 ("Error forcing flow control settings\n");
1877 ("Copper PHY and Auto Neg has not completed.\r\n");
1883 /******************************************************************************
1884 * Checks to see if the link status of the hardware has changed.
1886 * hw - Struct containing variables accessed by shared code
1888 * Called by any function that needs to check the link status of the adapter.
1889 *****************************************************************************/
1891 e1000_check_for_link(struct eth_device *nic)
1893 struct e1000_hw *hw = nic->priv;
1901 uint16_t lp_capability;
1905 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1906 * set when the optics detect a signal. On older adapters, it will be
1907 * cleared when there is a signal
1909 ctrl = E1000_READ_REG(hw, CTRL);
1910 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1911 signal = E1000_CTRL_SWDPIN1;
1915 status = E1000_READ_REG(hw, STATUS);
1916 rxcw = E1000_READ_REG(hw, RXCW);
1917 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
1919 /* If we have a copper PHY then we only want to go out to the PHY
1920 * registers to see if Auto-Neg has completed and/or if our link
1921 * status has changed. The get_link_status flag will be set if we
1922 * receive a Link Status Change interrupt or we have Rx Sequence
1925 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
1926 /* First we want to see if the MII Status Register reports
1927 * link. If so, then we want to get the current speed/duplex
1929 * Read the register twice since the link bit is sticky.
1931 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1932 DEBUGOUT("PHY Read Error\n");
1933 return -E1000_ERR_PHY;
1935 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1936 DEBUGOUT("PHY Read Error\n");
1937 return -E1000_ERR_PHY;
1940 if (phy_data & MII_SR_LINK_STATUS) {
1941 hw->get_link_status = FALSE;
1943 /* No link detected */
1944 return -E1000_ERR_NOLINK;
1947 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
1948 * have Si on board that is 82544 or newer, Auto
1949 * Speed Detection takes care of MAC speed/duplex
1950 * configuration. So we only need to configure Collision
1951 * Distance in the MAC. Otherwise, we need to force
1952 * speed/duplex on the MAC to the current PHY speed/duplex
1955 if (hw->mac_type >= e1000_82544)
1956 e1000_config_collision_dist(hw);
1958 ret_val = e1000_config_mac_to_phy(hw);
1961 ("Error configuring MAC to PHY settings\n");
1966 /* Configure Flow Control now that Auto-Neg has completed. First, we
1967 * need to restore the desired flow control settings because we may
1968 * have had to re-autoneg with a different link partner.
1970 ret_val = e1000_config_fc_after_link_up(hw);
1972 DEBUGOUT("Error configuring flow control\n");
1976 /* At this point we know that we are on copper and we have
1977 * auto-negotiated link. These are conditions for checking the link
1978 * parter capability register. We use the link partner capability to
1979 * determine if TBI Compatibility needs to be turned on or off. If
1980 * the link partner advertises any speed in addition to Gigabit, then
1981 * we assume that they are GMII-based, and TBI compatibility is not
1982 * needed. If no other speeds are advertised, we assume the link
1983 * partner is TBI-based, and we turn on TBI Compatibility.
1985 if (hw->tbi_compatibility_en) {
1986 if (e1000_read_phy_reg
1987 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
1988 DEBUGOUT("PHY Read Error\n");
1989 return -E1000_ERR_PHY;
1991 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
1992 NWAY_LPAR_10T_FD_CAPS |
1993 NWAY_LPAR_100TX_HD_CAPS |
1994 NWAY_LPAR_100TX_FD_CAPS |
1995 NWAY_LPAR_100T4_CAPS)) {
1996 /* If our link partner advertises anything in addition to
1997 * gigabit, we do not need to enable TBI compatibility.
1999 if (hw->tbi_compatibility_on) {
2000 /* If we previously were in the mode, turn it off. */
2001 rctl = E1000_READ_REG(hw, RCTL);
2002 rctl &= ~E1000_RCTL_SBP;
2003 E1000_WRITE_REG(hw, RCTL, rctl);
2004 hw->tbi_compatibility_on = FALSE;
2007 /* If TBI compatibility is was previously off, turn it on. For
2008 * compatibility with a TBI link partner, we will store bad
2009 * packets. Some frames have an additional byte on the end and
2010 * will look like CRC errors to to the hardware.
2012 if (!hw->tbi_compatibility_on) {
2013 hw->tbi_compatibility_on = TRUE;
2014 rctl = E1000_READ_REG(hw, RCTL);
2015 rctl |= E1000_RCTL_SBP;
2016 E1000_WRITE_REG(hw, RCTL, rctl);
2021 /* If we don't have link (auto-negotiation failed or link partner cannot
2022 * auto-negotiate), the cable is plugged in (we have signal), and our
2023 * link partner is not trying to auto-negotiate with us (we are receiving
2024 * idles or data), we need to force link up. We also need to give
2025 * auto-negotiation time to complete, in case the cable was just plugged
2026 * in. The autoneg_failed flag does this.
2028 else if ((hw->media_type == e1000_media_type_fiber) &&
2029 (!(status & E1000_STATUS_LU)) &&
2030 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
2031 (!(rxcw & E1000_RXCW_C))) {
2032 if (hw->autoneg_failed == 0) {
2033 hw->autoneg_failed = 1;
2036 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2038 /* Disable auto-negotiation in the TXCW register */
2039 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2041 /* Force link-up and also force full-duplex. */
2042 ctrl = E1000_READ_REG(hw, CTRL);
2043 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2044 E1000_WRITE_REG(hw, CTRL, ctrl);
2046 /* Configure Flow Control after forcing link up. */
2047 ret_val = e1000_config_fc_after_link_up(hw);
2049 DEBUGOUT("Error configuring flow control\n");
2053 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2054 * auto-negotiation in the TXCW register and disable forced link in the
2055 * Device Control register in an attempt to auto-negotiate with our link
2058 else if ((hw->media_type == e1000_media_type_fiber) &&
2059 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2061 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2062 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2063 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2068 /******************************************************************************
2069 * Detects the current speed and duplex settings of the hardware.
2071 * hw - Struct containing variables accessed by shared code
2072 * speed - Speed of the connection
2073 * duplex - Duplex setting of the connection
2074 *****************************************************************************/
2076 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2077 uint16_t * speed, uint16_t * duplex)
2083 if (hw->mac_type >= e1000_82543) {
2084 status = E1000_READ_REG(hw, STATUS);
2085 if (status & E1000_STATUS_SPEED_1000) {
2086 *speed = SPEED_1000;
2087 DEBUGOUT("1000 Mbs, ");
2088 } else if (status & E1000_STATUS_SPEED_100) {
2090 DEBUGOUT("100 Mbs, ");
2093 DEBUGOUT("10 Mbs, ");
2096 if (status & E1000_STATUS_FD) {
2097 *duplex = FULL_DUPLEX;
2098 DEBUGOUT("Full Duplex\r\n");
2100 *duplex = HALF_DUPLEX;
2101 DEBUGOUT(" Half Duplex\r\n");
2104 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2105 *speed = SPEED_1000;
2106 *duplex = FULL_DUPLEX;
2110 /******************************************************************************
2111 * Blocks until autoneg completes or times out (~4.5 seconds)
2113 * hw - Struct containing variables accessed by shared code
2114 ******************************************************************************/
2116 e1000_wait_autoneg(struct e1000_hw *hw)
2122 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2124 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2125 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2126 /* Read the MII Status Register and wait for Auto-Neg
2127 * Complete bit to be set.
2129 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
2130 DEBUGOUT("PHY Read Error\n");
2131 return -E1000_ERR_PHY;
2133 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
2134 DEBUGOUT("PHY Read Error\n");
2135 return -E1000_ERR_PHY;
2137 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
2138 DEBUGOUT("Auto-Neg complete.\n");
2143 DEBUGOUT("Auto-Neg timedout.\n");
2144 return -E1000_ERR_TIMEOUT;
2147 /******************************************************************************
2148 * Raises the Management Data Clock
2150 * hw - Struct containing variables accessed by shared code
2151 * ctrl - Device control register's current value
2152 ******************************************************************************/
2154 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
2156 /* Raise the clock input to the Management Data Clock (by setting the MDC
2157 * bit), and then delay 2 microseconds.
2159 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2160 E1000_WRITE_FLUSH(hw);
2164 /******************************************************************************
2165 * Lowers the Management Data Clock
2167 * hw - Struct containing variables accessed by shared code
2168 * ctrl - Device control register's current value
2169 ******************************************************************************/
2171 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
2173 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2174 * bit), and then delay 2 microseconds.
2176 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2177 E1000_WRITE_FLUSH(hw);
2181 /******************************************************************************
2182 * Shifts data bits out to the PHY
2184 * hw - Struct containing variables accessed by shared code
2185 * data - Data to send out to the PHY
2186 * count - Number of bits to shift out
2188 * Bits are shifted out in MSB to LSB order.
2189 ******************************************************************************/
2191 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
2196 /* We need to shift "count" number of bits out to the PHY. So, the value
2197 * in the "data" parameter will be shifted out to the PHY one bit at a
2198 * time. In order to do this, "data" must be broken down into bits.
2201 mask <<= (count - 1);
2203 ctrl = E1000_READ_REG(hw, CTRL);
2205 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2206 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2209 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2210 * then raising and lowering the Management Data Clock. A "0" is
2211 * shifted out to the PHY by setting the MDIO bit to "0" and then
2212 * raising and lowering the clock.
2215 ctrl |= E1000_CTRL_MDIO;
2217 ctrl &= ~E1000_CTRL_MDIO;
2219 E1000_WRITE_REG(hw, CTRL, ctrl);
2220 E1000_WRITE_FLUSH(hw);
2224 e1000_raise_mdi_clk(hw, &ctrl);
2225 e1000_lower_mdi_clk(hw, &ctrl);
2231 /******************************************************************************
2232 * Shifts data bits in from the PHY
2234 * hw - Struct containing variables accessed by shared code
2236 * Bits are shifted in in MSB to LSB order.
2237 ******************************************************************************/
2239 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2245 /* In order to read a register from the PHY, we need to shift in a total
2246 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2247 * to avoid contention on the MDIO pin when a read operation is performed.
2248 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2249 * by raising the input to the Management Data Clock (setting the MDC bit),
2250 * and then reading the value of the MDIO bit.
2252 ctrl = E1000_READ_REG(hw, CTRL);
2254 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2255 ctrl &= ~E1000_CTRL_MDIO_DIR;
2256 ctrl &= ~E1000_CTRL_MDIO;
2258 E1000_WRITE_REG(hw, CTRL, ctrl);
2259 E1000_WRITE_FLUSH(hw);
2261 /* Raise and Lower the clock before reading in the data. This accounts for
2262 * the turnaround bits. The first clock occurred when we clocked out the
2263 * last bit of the Register Address.
2265 e1000_raise_mdi_clk(hw, &ctrl);
2266 e1000_lower_mdi_clk(hw, &ctrl);
2268 for (data = 0, i = 0; i < 16; i++) {
2270 e1000_raise_mdi_clk(hw, &ctrl);
2271 ctrl = E1000_READ_REG(hw, CTRL);
2272 /* Check to see if we shifted in a "1". */
2273 if (ctrl & E1000_CTRL_MDIO)
2275 e1000_lower_mdi_clk(hw, &ctrl);
2278 e1000_raise_mdi_clk(hw, &ctrl);
2279 e1000_lower_mdi_clk(hw, &ctrl);
2284 /*****************************************************************************
2285 * Reads the value from a PHY register
2287 * hw - Struct containing variables accessed by shared code
2288 * reg_addr - address of the PHY register to read
2289 ******************************************************************************/
2291 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
2295 const uint32_t phy_addr = 1;
2297 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2298 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
2299 return -E1000_ERR_PARAM;
2302 if (hw->mac_type > e1000_82543) {
2303 /* Set up Op-code, Phy Address, and register address in the MDI
2304 * Control register. The MAC will take care of interfacing with the
2305 * PHY to retrieve the desired data.
2307 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2308 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2309 (E1000_MDIC_OP_READ));
2311 E1000_WRITE_REG(hw, MDIC, mdic);
2313 /* Poll the ready bit to see if the MDI read completed */
2314 for (i = 0; i < 64; i++) {
2316 mdic = E1000_READ_REG(hw, MDIC);
2317 if (mdic & E1000_MDIC_READY)
2320 if (!(mdic & E1000_MDIC_READY)) {
2321 DEBUGOUT("MDI Read did not complete\n");
2322 return -E1000_ERR_PHY;
2324 if (mdic & E1000_MDIC_ERROR) {
2325 DEBUGOUT("MDI Error\n");
2326 return -E1000_ERR_PHY;
2328 *phy_data = (uint16_t) mdic;
2330 /* We must first send a preamble through the MDIO pin to signal the
2331 * beginning of an MII instruction. This is done by sending 32
2332 * consecutive "1" bits.
2334 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2336 /* Now combine the next few fields that are required for a read
2337 * operation. We use this method instead of calling the
2338 * e1000_shift_out_mdi_bits routine five different times. The format of
2339 * a MII read instruction consists of a shift out of 14 bits and is
2340 * defined as follows:
2341 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2342 * followed by a shift in of 18 bits. This first two bits shifted in
2343 * are TurnAround bits used to avoid contention on the MDIO pin when a
2344 * READ operation is performed. These two bits are thrown away
2345 * followed by a shift in of 16 bits which contains the desired data.
2347 mdic = ((reg_addr) | (phy_addr << 5) |
2348 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2350 e1000_shift_out_mdi_bits(hw, mdic, 14);
2352 /* Now that we've shifted out the read command to the MII, we need to
2353 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2356 *phy_data = e1000_shift_in_mdi_bits(hw);
2361 /******************************************************************************
2362 * Writes a value to a PHY register
2364 * hw - Struct containing variables accessed by shared code
2365 * reg_addr - address of the PHY register to write
2366 * data - data to write to the PHY
2367 ******************************************************************************/
2369 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
2373 const uint32_t phy_addr = 1;
2375 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2376 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
2377 return -E1000_ERR_PARAM;
2380 if (hw->mac_type > e1000_82543) {
2381 /* Set up Op-code, Phy Address, register address, and data intended
2382 * for the PHY register in the MDI Control register. The MAC will take
2383 * care of interfacing with the PHY to send the desired data.
2385 mdic = (((uint32_t) phy_data) |
2386 (reg_addr << E1000_MDIC_REG_SHIFT) |
2387 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2388 (E1000_MDIC_OP_WRITE));
2390 E1000_WRITE_REG(hw, MDIC, mdic);
2392 /* Poll the ready bit to see if the MDI read completed */
2393 for (i = 0; i < 64; i++) {
2395 mdic = E1000_READ_REG(hw, MDIC);
2396 if (mdic & E1000_MDIC_READY)
2399 if (!(mdic & E1000_MDIC_READY)) {
2400 DEBUGOUT("MDI Write did not complete\n");
2401 return -E1000_ERR_PHY;
2404 /* We'll need to use the SW defined pins to shift the write command
2405 * out to the PHY. We first send a preamble to the PHY to signal the
2406 * beginning of the MII instruction. This is done by sending 32
2407 * consecutive "1" bits.
2409 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2411 /* Now combine the remaining required fields that will indicate a
2412 * write operation. We use this method instead of calling the
2413 * e1000_shift_out_mdi_bits routine for each field in the command. The
2414 * format of a MII write instruction is as follows:
2415 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2417 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2418 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2420 mdic |= (uint32_t) phy_data;
2422 e1000_shift_out_mdi_bits(hw, mdic, 32);
2427 /******************************************************************************
2428 * Returns the PHY to the power-on reset state
2430 * hw - Struct containing variables accessed by shared code
2431 ******************************************************************************/
2433 e1000_phy_hw_reset(struct e1000_hw *hw)
2440 DEBUGOUT("Resetting Phy...\n");
2442 if (hw->mac_type > e1000_82543) {
2443 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2444 * bit. Then, take it out of reset.
2446 ctrl = E1000_READ_REG(hw, CTRL);
2447 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2448 E1000_WRITE_FLUSH(hw);
2450 E1000_WRITE_REG(hw, CTRL, ctrl);
2451 E1000_WRITE_FLUSH(hw);
2453 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2454 * bit to put the PHY into reset. Then, take it out of reset.
2456 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2457 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2458 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2459 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2460 E1000_WRITE_FLUSH(hw);
2462 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2463 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2464 E1000_WRITE_FLUSH(hw);
2469 /******************************************************************************
2472 * hw - Struct containing variables accessed by shared code
2474 * Sets bit 15 of the MII Control regiser
2475 ******************************************************************************/
2477 e1000_phy_reset(struct e1000_hw *hw)
2483 if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
2484 DEBUGOUT("PHY Read Error\n");
2485 return -E1000_ERR_PHY;
2487 phy_data |= MII_CR_RESET;
2488 if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
2489 DEBUGOUT("PHY Write Error\n");
2490 return -E1000_ERR_PHY;
2496 static int e1000_set_phy_type (struct e1000_hw *hw)
2500 if (hw->mac_type == e1000_undefined)
2501 return -E1000_ERR_PHY_TYPE;
2503 switch (hw->phy_id) {
2504 case M88E1000_E_PHY_ID:
2505 case M88E1000_I_PHY_ID:
2506 case M88E1011_I_PHY_ID:
2507 hw->phy_type = e1000_phy_m88;
2509 case IGP01E1000_I_PHY_ID:
2510 if (hw->mac_type == e1000_82541 ||
2511 hw->mac_type == e1000_82541_rev_2) {
2512 hw->phy_type = e1000_phy_igp;
2517 /* Should never have loaded on this device */
2518 hw->phy_type = e1000_phy_undefined;
2519 return -E1000_ERR_PHY_TYPE;
2522 return E1000_SUCCESS;
2525 /******************************************************************************
2526 * Probes the expected PHY address for known PHY IDs
2528 * hw - Struct containing variables accessed by shared code
2529 ******************************************************************************/
2531 e1000_detect_gig_phy(struct e1000_hw *hw)
2533 int32_t phy_init_status;
2534 uint16_t phy_id_high, phy_id_low;
2539 /* Read the PHY ID Registers to identify which PHY is onboard. */
2540 if (e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) {
2541 DEBUGOUT("PHY Read Error\n");
2542 return -E1000_ERR_PHY;
2544 hw->phy_id = (uint32_t) (phy_id_high << 16);
2546 if (e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) {
2547 DEBUGOUT("PHY Read Error\n");
2548 return -E1000_ERR_PHY;
2550 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2552 switch (hw->mac_type) {
2554 if (hw->phy_id == M88E1000_E_PHY_ID)
2558 if (hw->phy_id == M88E1000_I_PHY_ID)
2564 if (hw->phy_id == M88E1011_I_PHY_ID)
2567 case e1000_82541_rev_2:
2568 if(hw->phy_id == IGP01E1000_I_PHY_ID)
2573 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
2574 return -E1000_ERR_CONFIG;
2577 phy_init_status = e1000_set_phy_type(hw);
2579 if ((match) && (phy_init_status == E1000_SUCCESS)) {
2580 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
2583 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
2584 return -E1000_ERR_PHY;
2588 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
2590 * e1000_sw_init initializes the Adapter private data structure.
2591 * Fields are initialized based on PCI device information and
2592 * OS network device settings (MTU size).
2596 e1000_sw_init(struct eth_device *nic, int cardnum)
2598 struct e1000_hw *hw = (typeof(hw)) nic->priv;
2601 /* PCI config space info */
2602 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
2603 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
2604 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
2605 &hw->subsystem_vendor_id);
2606 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
2608 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
2609 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
2611 /* identify the MAC */
2612 result = e1000_set_mac_type(hw);
2614 E1000_ERR("Unknown MAC Type\n");
2618 /* lan a vs. lan b settings */
2619 if (hw->mac_type == e1000_82546)
2620 /*this also works w/ multiple 82546 cards */
2621 /*but not if they're intermingled /w other e1000s */
2622 hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a;
2624 hw->lan_loc = e1000_lan_a;
2626 /* flow control settings */
2627 hw->fc_high_water = E1000_FC_HIGH_THRESH;
2628 hw->fc_low_water = E1000_FC_LOW_THRESH;
2629 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
2630 hw->fc_send_xon = 1;
2632 /* Media type - copper or fiber */
2634 if (hw->mac_type >= e1000_82543) {
2635 uint32_t status = E1000_READ_REG(hw, STATUS);
2637 if (status & E1000_STATUS_TBIMODE) {
2638 DEBUGOUT("fiber interface\n");
2639 hw->media_type = e1000_media_type_fiber;
2641 DEBUGOUT("copper interface\n");
2642 hw->media_type = e1000_media_type_copper;
2645 hw->media_type = e1000_media_type_fiber;
2648 if (hw->mac_type < e1000_82543)
2649 hw->report_tx_early = 0;
2651 hw->report_tx_early = 1;
2653 hw->tbi_compatibility_en = TRUE;
2655 hw->wait_autoneg_complete = FALSE;
2656 hw->adaptive_ifs = TRUE;
2658 /* Copper options */
2659 if (hw->media_type == e1000_media_type_copper) {
2660 hw->mdix = AUTO_ALL_MODES;
2661 hw->disable_polarity_correction = FALSE;
2664 return E1000_SUCCESS;
2668 fill_rx(struct e1000_hw *hw)
2670 struct e1000_rx_desc *rd;
2673 rd = rx_base + rx_tail;
2674 rx_tail = (rx_tail + 1) % 8;
2676 rd->buffer_addr = cpu_to_le64((u32) & packet);
2677 E1000_WRITE_REG(hw, RDT, rx_tail);
2681 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
2682 * @adapter: board private structure
2684 * Configure the Tx unit of the MAC after a reset.
2688 e1000_configure_tx(struct e1000_hw *hw)
2694 ptr = (u32) tx_pool;
2696 ptr = (ptr + 0x10) & (~0xf);
2698 tx_base = (typeof(tx_base)) ptr;
2700 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
2701 E1000_WRITE_REG(hw, TDBAH, 0);
2703 E1000_WRITE_REG(hw, TDLEN, 128);
2705 /* Setup the HW Tx Head and Tail descriptor pointers */
2706 E1000_WRITE_REG(hw, TDH, 0);
2707 E1000_WRITE_REG(hw, TDT, 0);
2710 /* Set the default values for the Tx Inter Packet Gap timer */
2711 switch (hw->mac_type) {
2712 case e1000_82542_rev2_0:
2713 case e1000_82542_rev2_1:
2714 tipg = DEFAULT_82542_TIPG_IPGT;
2715 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2716 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2719 if (hw->media_type == e1000_media_type_fiber)
2720 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2722 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2723 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2724 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2726 E1000_WRITE_REG(hw, TIPG, tipg);
2728 /* Set the Tx Interrupt Delay register */
2729 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
2730 if (hw->mac_type >= e1000_82540)
2731 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
2733 /* Program the Transmit Control Register */
2734 tctl = E1000_READ_REG(hw, TCTL);
2735 tctl &= ~E1000_TCTL_CT;
2736 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
2737 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2738 E1000_WRITE_REG(hw, TCTL, tctl);
2740 e1000_config_collision_dist(hw);
2742 /* Setup Transmit Descriptor Settings for this adapter */
2743 adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_IDE;
2745 if (adapter->hw.report_tx_early == 1)
2746 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2748 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
2753 * e1000_setup_rctl - configure the receive control register
2754 * @adapter: Board private structure
2757 e1000_setup_rctl(struct e1000_hw *hw)
2761 rctl = E1000_READ_REG(hw, RCTL);
2763 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2765 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF; /* |
2766 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
2768 if (hw->tbi_compatibility_on == 1)
2769 rctl |= E1000_RCTL_SBP;
2771 rctl &= ~E1000_RCTL_SBP;
2773 rctl &= ~(E1000_RCTL_SZ_4096);
2775 switch (adapter->rx_buffer_len) {
2776 case E1000_RXBUFFER_2048:
2779 rctl |= E1000_RCTL_SZ_2048;
2780 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
2783 case E1000_RXBUFFER_4096:
2784 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
2786 case E1000_RXBUFFER_8192:
2787 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
2789 case E1000_RXBUFFER_16384:
2790 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
2794 E1000_WRITE_REG(hw, RCTL, rctl);
2798 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
2799 * @adapter: board private structure
2801 * Configure the Rx unit of the MAC after a reset.
2804 e1000_configure_rx(struct e1000_hw *hw)
2809 unsigned long rxcsum;
2812 /* make sure receives are disabled while setting up the descriptors */
2813 rctl = E1000_READ_REG(hw, RCTL);
2814 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
2816 /* set the Receive Delay Timer Register */
2818 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
2820 if (hw->mac_type >= e1000_82540) {
2822 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
2824 /* Set the interrupt throttling rate. Value is calculated
2825 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
2826 #define MAX_INTS_PER_SEC 8000
2827 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
2828 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
2831 /* Setup the Base and Length of the Rx Descriptor Ring */
2832 ptr = (u32) rx_pool;
2834 ptr = (ptr + 0x10) & (~0xf);
2835 rx_base = (typeof(rx_base)) ptr;
2836 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
2837 E1000_WRITE_REG(hw, RDBAH, 0);
2839 E1000_WRITE_REG(hw, RDLEN, 128);
2841 /* Setup the HW Rx Head and Tail Descriptor Pointers */
2842 E1000_WRITE_REG(hw, RDH, 0);
2843 E1000_WRITE_REG(hw, RDT, 0);
2845 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
2846 if ((adapter->hw.mac_type >= e1000_82543) && (adapter->rx_csum == TRUE)) {
2847 rxcsum = E1000_READ_REG(hw, RXCSUM);
2848 rxcsum |= E1000_RXCSUM_TUOFL;
2849 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
2852 /* Enable Receives */
2854 E1000_WRITE_REG(hw, RCTL, rctl);
2858 /**************************************************************************
2859 POLL - Wait for a frame
2860 ***************************************************************************/
2862 e1000_poll(struct eth_device *nic)
2864 struct e1000_hw *hw = nic->priv;
2865 struct e1000_rx_desc *rd;
2866 /* return true if there's an ethernet packet ready to read */
2867 rd = rx_base + rx_last;
2868 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
2870 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
2871 NetReceive((uchar *)packet, le32_to_cpu(rd->length));
2876 /**************************************************************************
2877 TRANSMIT - Transmit a frame
2878 ***************************************************************************/
2880 e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
2882 struct e1000_hw *hw = nic->priv;
2883 struct e1000_tx_desc *txp;
2886 txp = tx_base + tx_tail;
2887 tx_tail = (tx_tail + 1) % 8;
2889 txp->buffer_addr = cpu_to_le64(virt_to_bus(packet));
2890 txp->lower.data = cpu_to_le32(E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP |
2891 E1000_TXD_CMD_IFCS | length);
2892 txp->upper.data = 0;
2893 E1000_WRITE_REG(hw, TDT, tx_tail);
2895 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
2896 if (i++ > TOUT_LOOP) {
2897 DEBUGOUT("e1000: tx timeout\n");
2900 udelay(10); /* give the nic a chance to write to the register */
2907 e1000_reset(struct eth_device *nic)
2909 struct e1000_hw *hw = nic->priv;
2912 if (hw->mac_type >= e1000_82544) {
2913 E1000_WRITE_REG(hw, WUC, 0);
2915 return e1000_init_hw(nic);
2918 /**************************************************************************
2919 DISABLE - Turn off ethernet interface
2920 ***************************************************************************/
2922 e1000_disable(struct eth_device *nic)
2924 struct e1000_hw *hw = nic->priv;
2926 /* Turn off the ethernet interface */
2927 E1000_WRITE_REG(hw, RCTL, 0);
2928 E1000_WRITE_REG(hw, TCTL, 0);
2930 /* Clear the transmit ring */
2931 E1000_WRITE_REG(hw, TDH, 0);
2932 E1000_WRITE_REG(hw, TDT, 0);
2934 /* Clear the receive ring */
2935 E1000_WRITE_REG(hw, RDH, 0);
2936 E1000_WRITE_REG(hw, RDT, 0);
2938 /* put the card in its initial state */
2940 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
2946 /**************************************************************************
2947 INIT - set up ethernet interface(s)
2948 ***************************************************************************/
2950 e1000_init(struct eth_device *nic, bd_t * bis)
2952 struct e1000_hw *hw = nic->priv;
2955 ret_val = e1000_reset(nic);
2957 if ((ret_val == -E1000_ERR_NOLINK) ||
2958 (ret_val == -E1000_ERR_TIMEOUT)) {
2959 E1000_ERR("Valid Link not detected\n");
2961 E1000_ERR("Hardware Initialization Failed\n");
2965 e1000_configure_tx(hw);
2966 e1000_setup_rctl(hw);
2967 e1000_configure_rx(hw);
2971 /**************************************************************************
2972 PROBE - Look for an adapter, this routine's visible to the outside
2973 You should omit the last argument struct pci_device * for a non-PCI NIC
2974 ***************************************************************************/
2976 e1000_initialize(bd_t * bis)
2979 int card_number = 0;
2980 struct eth_device *nic = NULL;
2981 struct e1000_hw *hw = NULL;
2986 while (1) { /* Find PCI device(s) */
2987 if ((devno = pci_find_devices(supported, idx++)) < 0) {
2991 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
2992 iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */
2993 DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase);
2995 pci_write_config_dword(devno, PCI_COMMAND,
2996 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
2997 /* Check if I/O accesses and Bus Mastering are enabled. */
2998 pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord);
2999 if (!(PciCommandWord & PCI_COMMAND_MEMORY)) {
3000 printf("Error: Can not enable MEM access.\n");
3002 } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) {
3003 printf("Error: Can not enable Bus Mastering.\n");
3007 nic = (struct eth_device *) malloc(sizeof (*nic));
3008 hw = (struct e1000_hw *) malloc(sizeof (*hw));
3011 nic->iobase = bus_to_phys(devno, iobase);
3013 sprintf(nic->name, "e1000#%d", card_number);
3015 /* Are these variables needed? */
3017 hw->fc = e1000_fc_none;
3018 hw->original_fc = e1000_fc_none;
3020 hw->fc = e1000_fc_default;
3021 hw->original_fc = e1000_fc_default;
3023 hw->autoneg_failed = 0;
3024 hw->get_link_status = TRUE;
3025 hw->hw_addr = (typeof(hw->hw_addr)) iobase;
3026 hw->mac_type = e1000_undefined;
3028 /* MAC and Phy settings */
3029 if (e1000_sw_init(nic, card_number) < 0) {
3034 #if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
3035 if (e1000_validate_eeprom_checksum(nic) < 0) {
3036 printf("The EEPROM Checksum Is Not Valid\n");
3042 e1000_read_mac_addr(nic);
3044 E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA);
3046 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n",
3047 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
3048 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
3050 nic->init = e1000_init;
3051 nic->recv = e1000_poll;
3052 nic->send = e1000_transmit;
3053 nic->halt = e1000_disable;