2 dm9000.c: Version 1.2 12/15/2003
4 A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
5 Copyright (C) 1997 Sten Wang
7 This program is free software; you can redistribute it and/or
8 modify it under the terms of the GNU General Public License
9 as published by the Free Software Foundation; either version 2
10 of the License, or (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
19 V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
20 06/22/2001 Support DM9801 progrmming
21 E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
22 E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
23 R17 = (R17 & 0xfff0) | NF + 3
24 E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
25 R17 = (R17 & 0xfff0) | NF
27 v1.00 modify by simon 2001.9.5
28 change for kernel 2.4.x
30 v1.1 11/09/2001 fix force mode bug
32 v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
34 Added tx/rx 32 bit mode.
35 Cleaned up for kernel merge.
37 --------------------------------------
39 12/15/2003 Initial port to u-boot by
40 Sascha Hauer <saschahauer@web.de>
42 06/03/2008 Remy Bohmer <linux@bohmer.net>
43 - Added autodetect of databus width.
44 - Made debug code compile again.
45 - Adapt eth_send such that it matches the DM9000*
46 application notes. Needed to make it work properly
48 - Adapted reset procedure to match DM9000 application
49 notes (i.e. double reset)
50 These changes are tested with DM9000{A,EP,E} together
51 with a 200MHz Atmel AT91SAM92161 core
53 TODO: Homerun NIC and longrun NIC are not functional, only internal at the
62 #ifdef CONFIG_DRIVER_DM9000
66 /* Board/System/Debug information/definition ---------------- */
68 #define DM9801_NOISE_FLOOR 0x08
69 #define DM9802_NOISE_FLOOR 0x05
71 /* #define CONFIG_DM9000_DEBUG */
73 #ifdef CONFIG_DM9000_DEBUG
74 #define DM9000_DBG(fmt,args...) printf(fmt, ##args)
75 #define DM9000_DMP_PACKET(func,packet,length) \
78 printf(func ": length: %d\n", length); \
79 for (i = 0; i < length; i++) { \
81 printf("\n%s: %02x: ", func, i); \
82 printf("%02x ", ((unsigned char *) packet)[i]); \
86 #define DM9000_DBG(fmt,args...)
87 #define DM9000_DMP_PACKET(func,packet,length)
90 enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD =
91 1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO =
92 8, DM9000_1M_HPNA = 0x10
94 enum DM9000_NIC_TYPE { FASTETHER_NIC = 0, HOMERUN_NIC = 1, LONGRUN_NIC = 2
97 /* Structure/enum declaration ------------------------------- */
98 typedef struct board_info {
99 u32 runt_length_counter; /* counter: RX length < 64byte */
100 u32 long_length_counter; /* counter: RX length > 1514byte */
101 u32 reset_counter; /* counter: RESET */
102 u32 reset_tx_timeout; /* RESET caused by TX Timeout */
103 u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
105 u16 queue_start_addr;
108 u8 device_wait_reset; /* device state */
109 u8 nic_type; /* NIC type */
110 unsigned char srom[128];
111 void (*outblk)(void *data_ptr, int count);
112 void (*inblk)(void *data_ptr, int count);
113 void (*rx_status)(u16 *RxStatus, u16 *RxLen);
115 static board_info_t dm9000_info;
117 /* For module input parameter */
118 static int media_mode = DM9000_AUTO;
119 static u8 nfloor = 0;
121 /* function declaration ------------------------------------- */
122 int eth_init(bd_t * bd);
123 int eth_send(volatile void *, int);
126 static int dm9000_probe(void);
127 static u16 phy_read(int);
128 static void phy_write(int, u16);
129 u16 read_srom_word(int);
130 static u8 DM9000_ior(int);
131 static void DM9000_iow(int reg, u8 value);
133 /* DM9000 network board routine ---------------------------- */
135 #define DM9000_outb(d,r) ( *(volatile u8 *)r = d )
136 #define DM9000_outw(d,r) ( *(volatile u16 *)r = d )
137 #define DM9000_outl(d,r) ( *(volatile u32 *)r = d )
138 #define DM9000_inb(r) (*(volatile u8 *)r)
139 #define DM9000_inw(r) (*(volatile u16 *)r)
140 #define DM9000_inl(r) (*(volatile u32 *)r)
142 #ifdef CONFIG_DM9000_DEBUG
147 DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
148 DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
149 DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
150 DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
151 DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
152 DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
153 DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
154 DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
159 static void dm9000_outblk_8bit(void *data_ptr, int count)
162 for (i = 0; i < count; i++)
163 DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
166 static void dm9000_outblk_16bit(void *data_ptr, int count)
169 u32 tmplen = (count + 1) / 2;
171 for (i = 0; i < tmplen; i++)
172 DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
174 static void dm9000_outblk_32bit(void *data_ptr, int count)
177 u32 tmplen = (count + 3) / 4;
179 for (i = 0; i < tmplen; i++)
180 DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
183 static void dm9000_inblk_8bit(void *data_ptr, int count)
186 for (i = 0; i < count; i++)
187 ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
190 static void dm9000_inblk_16bit(void *data_ptr, int count)
193 u32 tmplen = (count + 1) / 2;
195 for (i = 0; i < tmplen; i++)
196 ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
198 static void dm9000_inblk_32bit(void *data_ptr, int count)
201 u32 tmplen = (count + 3) / 4;
203 for (i = 0; i < tmplen; i++)
204 ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
207 static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
209 u32 tmpdata = DM9000_inl(DM9000_DATA);
211 DM9000_outb(DM9000_MRCMD, DM9000_IO);
214 *RxLen = tmpdata >> 16;
217 static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
219 DM9000_outb(DM9000_MRCMD, DM9000_IO);
221 *RxStatus = DM9000_inw(DM9000_DATA);
222 *RxLen = DM9000_inw(DM9000_DATA);
225 static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
227 DM9000_outb(DM9000_MRCMD, DM9000_IO);
229 *RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
230 *RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
234 Search DM9000 board, allocate space and register it
240 id_val = DM9000_ior(DM9000_VIDL);
241 id_val |= DM9000_ior(DM9000_VIDH) << 8;
242 id_val |= DM9000_ior(DM9000_PIDL) << 16;
243 id_val |= DM9000_ior(DM9000_PIDH) << 24;
244 if (id_val == DM9000_ID) {
245 printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
249 printf("dm9000 not found at 0x%08x id: 0x%08x\n",
250 CONFIG_DM9000_BASE, id_val);
255 /* Set PHY operationg mode
260 u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
261 if (!(media_mode & DM9000_AUTO)) {
262 switch (media_mode) {
280 phy_write(4, phy_reg4); /* Set PHY media mode */
281 phy_write(0, phy_reg0); /* Tmp */
283 DM9000_iow(DM9000_GPCR, 0x01); /* Let GPIO0 output */
284 DM9000_iow(DM9000_GPR, 0x00); /* Enable PHY */
291 program_dm9801(u16 HPNA_rev)
293 __u16 reg16, reg17, reg24, reg25;
295 nfloor = DM9801_NOISE_FLOOR;
296 reg16 = phy_read(16);
297 reg17 = phy_read(17);
298 reg24 = phy_read(24);
299 reg25 = phy_read(25);
301 case 0xb900: /* DM9801 E3 */
303 reg25 = ((reg24 + nfloor) & 0x00ff) | 0xf000;
305 case 0xb901: /* DM9801 E4 */
306 reg25 = ((reg24 + nfloor) & 0x00ff) | 0xc200;
307 reg17 = (reg17 & 0xfff0) + nfloor + 3;
309 case 0xb902: /* DM9801 E5 */
310 case 0xb903: /* DM9801 E6 */
313 reg25 = ((reg24 + nfloor - 3) & 0x00ff) | 0xc200;
314 reg17 = (reg17 & 0xfff0) + nfloor;
316 phy_write(16, reg16);
317 phy_write(17, reg17);
318 phy_write(25, reg25);
329 nfloor = DM9802_NOISE_FLOOR;
330 reg25 = phy_read(25);
331 reg25 = (reg25 & 0xff00) + nfloor;
332 phy_write(25, reg25);
340 struct board_info *db = &dm9000_info;
342 DM9000_iow(DM9000_NCR, NCR_EXT_PHY);
343 phy_reg3 = phy_read(3);
344 switch (phy_reg3 & 0xfff0) {
346 if (phy_read(31) == 0x4404) {
347 db->nic_type = HOMERUN_NIC;
348 program_dm9801(phy_reg3);
349 DM9000_DBG("found homerun NIC\n");
351 db->nic_type = LONGRUN_NIC;
352 DM9000_DBG("found longrun NIC\n");
357 db->nic_type = FASTETHER_NIC;
360 DM9000_iow(DM9000_NCR, 0);
363 /* General Purpose dm9000 reset routine */
367 DM9000_DBG("resetting DM9000\n");
370 see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
372 /* DEBUG: Make all GPIO pins outputs */
373 DM9000_iow(DM9000_GPCR, 0x0F);
374 /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
375 DM9000_iow(DM9000_GPR, 0);
376 /* Step 2: Software reset */
377 DM9000_iow(DM9000_NCR, 3);
380 DM9000_DBG("resetting the DM9000, 1st reset\n");
381 udelay(25); /* Wait at least 20 us */
382 } while (DM9000_ior(DM9000_NCR) & 1);
384 DM9000_iow(DM9000_NCR, 0);
385 DM9000_iow(DM9000_NCR, 3); /* Issue a second reset */
388 DM9000_DBG("resetting the DM9000, 2nd reset\n");
389 udelay(25); /* Wait at least 20 us */
390 } while (DM9000_ior(DM9000_NCR) & 1);
392 /* Check whether the ethernet controller is present */
393 if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
394 (DM9000_ior(DM9000_PIDH) != 0x90))
395 printf("ERROR: resetting DM9000 -> not responding\n");
398 /* Initilize dm9000 board
405 struct board_info *db = &dm9000_info;
407 DM9000_DBG("eth_init()\n");
413 /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
414 io_mode = DM9000_ior(DM9000_ISR) >> 6;
417 case 0x0: /* 16-bit mode */
418 printf("DM9000: running in 16 bit mode\n");
419 db->outblk = dm9000_outblk_16bit;
420 db->inblk = dm9000_inblk_16bit;
421 db->rx_status = dm9000_rx_status_16bit;
423 case 0x01: /* 32-bit mode */
424 printf("DM9000: running in 32 bit mode\n");
425 db->outblk = dm9000_outblk_32bit;
426 db->inblk = dm9000_inblk_32bit;
427 db->rx_status = dm9000_rx_status_32bit;
429 case 0x02: /* 8 bit mode */
430 printf("DM9000: running in 8 bit mode\n");
431 db->outblk = dm9000_outblk_8bit;
432 db->inblk = dm9000_inblk_8bit;
433 db->rx_status = dm9000_rx_status_8bit;
436 /* Assume 8 bit mode, will probably not work anyway */
437 printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
438 db->outblk = dm9000_outblk_8bit;
439 db->inblk = dm9000_inblk_8bit;
440 db->rx_status = dm9000_rx_status_8bit;
444 /* NIC Type: FASTETHER, HOMERUN, LONGRUN */
447 /* GPIO0 on pre-activate PHY */
448 DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */
453 /* Program operating register */
454 DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */
455 DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */
456 DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
457 DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
458 DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
459 DM9000_iow(DM9000_SMCR, 0); /* Special Mode */
460 DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
461 DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */
463 /* Set Node address */
464 for (i = 0; i < 6; i++)
465 ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
467 if (is_zero_ether_addr(bd->bi_enetaddr) ||
468 is_multicast_ether_addr(bd->bi_enetaddr)) {
469 /* try reading from environment */
472 s = getenv ("ethaddr");
473 for (i = 0; i < 6; ++i) {
474 bd->bi_enetaddr[i] = s ?
475 simple_strtoul (s, &e, 16) : 0;
477 s = (*e) ? e + 1 : e;
481 printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
482 bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
483 bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
484 for (i = 0, oft = 0x10; i < 6; i++, oft++)
485 DM9000_iow(oft, bd->bi_enetaddr[i]);
486 for (i = 0, oft = 0x16; i < 8; i++, oft++)
487 DM9000_iow(oft, 0xff);
489 /* read back mac, just to be sure */
490 for (i = 0, oft = 0x10; i < 6; i++, oft++)
491 DM9000_DBG("%02x:", DM9000_ior(oft));
494 /* Activate DM9000 */
495 DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
496 DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */
498 while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
502 printf("could not establish link\n");
507 /* see what we've got */
508 lnk = phy_read(17) >> 12;
509 printf("operating at ");
512 printf("10M half duplex ");
515 printf("10M full duplex ");
518 printf("100M half duplex ");
521 printf("100M full duplex ");
524 printf("unknown: %d ", lnk);
532 Hardware start transmission.
533 Send a packet to media from the upper layer.
536 eth_send(volatile void *packet, int length)
540 struct board_info *db = &dm9000_info;
542 DM9000_DMP_PACKET("eth_send", packet, length);
544 DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
546 /* Move data to DM9000 TX RAM */
547 data_ptr = (char *) packet;
548 DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
550 /* push the data to the TX-fifo */
551 (db->outblk)(data_ptr, length);
553 /* Set TX length to DM9000 */
554 DM9000_iow(DM9000_TXPLL, length & 0xff);
555 DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
557 /* Issue TX polling command */
558 DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
560 /* wait for end of transmission */
561 tmo = get_timer(0) + 5 * CFG_HZ;
562 while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
563 !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
564 if (get_timer(0) >= tmo) {
565 printf("transmission timeout\n");
569 DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
571 DM9000_DBG("transmit done\n\n");
577 The interface is stopped when it is brought.
582 DM9000_DBG("eth_halt\n");
585 phy_write(0, 0x8000); /* PHY RESET */
586 DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
587 DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
588 DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
592 Received a packet and pass to upper layer
597 u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
598 u16 RxStatus, RxLen = 0;
599 struct board_info *db = &dm9000_info;
601 /* Check packet ready or not */
602 DM9000_ior(DM9000_MRCMDX); /* Dummy read */
603 rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */
607 /* Status check: this byte must be 0 or 1 */
609 DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
610 DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
611 DM9000_DBG("rx status check: %d\n", rxbyte);
613 DM9000_DBG("receiving packet\n");
615 /* A packet ready now & Get status/length */
616 DM9000_outb(DM9000_MRCMD, DM9000_IO);
618 (db->rx_status)(&RxStatus, &RxLen);
620 DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
622 /* Move data from DM9000 */
623 /* Read received packet from RX SRAM */
624 (db->inblk)(rdptr, RxLen);
626 if ((RxStatus & 0xbf00) || (RxLen < 0x40)
627 || (RxLen > DM9000_PKT_MAX)) {
628 if (RxStatus & 0x100) {
629 printf("rx fifo error\n");
631 if (RxStatus & 0x200) {
632 printf("rx crc error\n");
634 if (RxStatus & 0x8000) {
635 printf("rx length error\n");
637 if (RxLen > DM9000_PKT_MAX) {
638 printf("rx length too big\n");
642 DM9000_DMP_PACKET("eth_rx", rdptr, RxLen);
644 /* Pass to upper layer */
645 DM9000_DBG("passing packet to upper layer\n");
646 NetReceive(NetRxPackets[0], RxLen);
653 Read a word data from SROM
656 read_srom_word(int offset)
658 DM9000_iow(DM9000_EPAR, offset);
659 DM9000_iow(DM9000_EPCR, 0x4);
661 DM9000_iow(DM9000_EPCR, 0x0);
662 return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
666 write_srom_word(int offset, u16 val)
668 DM9000_iow(DM9000_EPAR, offset);
669 DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
670 DM9000_iow(DM9000_EPDRL, (val & 0xff));
671 DM9000_iow(DM9000_EPCR, 0x12);
673 DM9000_iow(DM9000_EPCR, 0);
678 Read a byte from I/O port
683 DM9000_outb(reg, DM9000_IO);
684 return DM9000_inb(DM9000_DATA);
688 Write a byte to I/O port
691 DM9000_iow(int reg, u8 value)
693 DM9000_outb(reg, DM9000_IO);
694 DM9000_outb(value, DM9000_DATA);
698 Read a word from phyxcer
705 /* Fill the phyxcer register into REG_0C */
706 DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
707 DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
708 udelay(100); /* Wait read complete */
709 DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
710 val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
712 /* The read data keeps on REG_0D & REG_0E */
713 DM9000_DBG("phy_read(0x%x): 0x%x\n", reg, val);
718 Write a word to phyxcer
721 phy_write(int reg, u16 value)
724 /* Fill the phyxcer register into REG_0C */
725 DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
727 /* Fill the written data into REG_0D & REG_0E */
728 DM9000_iow(DM9000_EPDRL, (value & 0xff));
729 DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
730 DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
731 udelay(500); /* Wait write complete */
732 DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
733 DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value);
735 #endif /* CONFIG_DRIVER_DM9000 */