3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
9 * Designware ethernet IP driver for U-Boot
18 #include <linux/compiler.h>
19 #include <linux/err.h>
21 #include "designware.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
27 struct eth_mac_regs *mac_p = bus->priv;
30 int timeout = CONFIG_MDIO_TIMEOUT;
32 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
33 ((reg << MIIREGSHIFT) & MII_REGMSK);
35 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
38 while (get_timer(start) < timeout) {
39 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
40 return readl(&mac_p->miidata);
47 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
50 struct eth_mac_regs *mac_p = bus->priv;
53 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
55 writel(val, &mac_p->miidata);
56 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
57 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
59 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
62 while (get_timer(start) < timeout) {
63 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
73 static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p)
75 struct mii_dev *bus = mdio_alloc();
78 printf("Failed to allocate MDIO bus\n");
82 bus->read = dw_mdio_read;
83 bus->write = dw_mdio_write;
84 snprintf(bus->name, sizeof(bus->name), name);
86 bus->priv = (void *)mac_regs_p;
88 return mdio_register(bus);
91 static void tx_descs_init(struct dw_eth_dev *priv)
93 struct eth_dma_regs *dma_p = priv->dma_regs_p;
94 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
95 char *txbuffs = &priv->txbuffs[0];
96 struct dmamacdescr *desc_p;
99 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
100 desc_p = &desc_table_p[idx];
101 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
102 desc_p->dmamac_next = &desc_table_p[idx + 1];
104 #if defined(CONFIG_DW_ALTDESCRIPTOR)
105 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
106 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
107 DESC_TXSTS_TXCHECKINSCTRL |
108 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
110 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
111 desc_p->dmamac_cntl = 0;
112 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
114 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
115 desc_p->txrx_status = 0;
119 /* Correcting the last pointer of the chain */
120 desc_p->dmamac_next = &desc_table_p[0];
122 /* Flush all Tx buffer descriptors at once */
123 flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
124 (unsigned int)priv->tx_mac_descrtable +
125 sizeof(priv->tx_mac_descrtable));
127 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
128 priv->tx_currdescnum = 0;
131 static void rx_descs_init(struct dw_eth_dev *priv)
133 struct eth_dma_regs *dma_p = priv->dma_regs_p;
134 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
135 char *rxbuffs = &priv->rxbuffs[0];
136 struct dmamacdescr *desc_p;
139 /* Before passing buffers to GMAC we need to make sure zeros
140 * written there right after "priv" structure allocation were
142 * Otherwise there's a chance to get some of them flushed in RAM when
143 * GMAC is already pushing data to RAM via DMA. This way incoming from
144 * GMAC data will be corrupted. */
145 flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
148 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
149 desc_p = &desc_table_p[idx];
150 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
151 desc_p->dmamac_next = &desc_table_p[idx + 1];
153 desc_p->dmamac_cntl =
154 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
157 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
160 /* Correcting the last pointer of the chain */
161 desc_p->dmamac_next = &desc_table_p[0];
163 /* Flush all Rx buffer descriptors at once */
164 flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
165 (unsigned int)priv->rx_mac_descrtable +
166 sizeof(priv->rx_mac_descrtable));
168 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
169 priv->rx_currdescnum = 0;
172 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
174 struct eth_mac_regs *mac_p = priv->mac_regs_p;
175 u32 macid_lo, macid_hi;
177 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
179 macid_hi = mac_id[4] + (mac_id[5] << 8);
181 writel(macid_hi, &mac_p->macaddr0hi);
182 writel(macid_lo, &mac_p->macaddr0lo);
187 static void dw_adjust_link(struct eth_mac_regs *mac_p,
188 struct phy_device *phydev)
190 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
193 printf("%s: No link.\n", phydev->dev->name);
197 if (phydev->speed != 1000)
198 conf |= MII_PORTSELECT;
200 conf &= ~MII_PORTSELECT;
202 if (phydev->speed == 100)
206 conf |= FULLDPLXMODE;
208 writel(conf, &mac_p->conf);
210 printf("Speed: %d, %s duplex%s\n", phydev->speed,
211 (phydev->duplex) ? "full" : "half",
212 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
215 static void _dw_eth_halt(struct dw_eth_dev *priv)
217 struct eth_mac_regs *mac_p = priv->mac_regs_p;
218 struct eth_dma_regs *dma_p = priv->dma_regs_p;
220 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
221 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
223 phy_shutdown(priv->phydev);
226 static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
228 struct eth_mac_regs *mac_p = priv->mac_regs_p;
229 struct eth_dma_regs *dma_p = priv->dma_regs_p;
233 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
235 start = get_timer(0);
236 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
237 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
238 printf("DMA reset timeout\n");
246 * Soft reset above clears HW address registers.
247 * So we have to set it here once again.
249 _dw_write_hwaddr(priv, enetaddr);
254 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
256 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
257 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
260 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
264 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
266 #ifdef CONFIG_DW_AXI_BURST_LEN
267 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
270 /* Start up the PHY */
271 ret = phy_startup(priv->phydev);
273 printf("Could not initialize PHY %s\n",
274 priv->phydev->dev->name);
278 dw_adjust_link(mac_p, priv->phydev);
280 if (!priv->phydev->link)
283 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
288 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
290 struct eth_dma_regs *dma_p = priv->dma_regs_p;
291 u32 desc_num = priv->tx_currdescnum;
292 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
293 uint32_t desc_start = (uint32_t)desc_p;
294 uint32_t desc_end = desc_start +
295 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
296 uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
297 uint32_t data_end = data_start +
298 roundup(length, ARCH_DMA_MINALIGN);
300 * Strictly we only need to invalidate the "txrx_status" field
301 * for the following check, but on some platforms we cannot
302 * invalidate only 4 bytes, so we flush the entire descriptor,
303 * which is 16 bytes in total. This is safe because the
304 * individual descriptors in the array are each aligned to
305 * ARCH_DMA_MINALIGN and padded appropriately.
307 invalidate_dcache_range(desc_start, desc_end);
309 /* Check if the descriptor is owned by CPU */
310 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
311 printf("CPU not owner of tx frame\n");
315 memcpy(desc_p->dmamac_addr, packet, length);
317 /* Flush data to be sent */
318 flush_dcache_range(data_start, data_end);
320 #if defined(CONFIG_DW_ALTDESCRIPTOR)
321 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
322 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) &
323 DESC_TXCTRL_SIZE1MASK;
325 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
326 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
328 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
329 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
332 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
335 /* Flush modified buffer descriptor */
336 flush_dcache_range(desc_start, desc_end);
338 /* Test the wrap-around condition. */
339 if (++desc_num >= CONFIG_TX_DESCR_NUM)
342 priv->tx_currdescnum = desc_num;
344 /* Start the transmission */
345 writel(POLL_DATA, &dma_p->txpolldemand);
350 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
352 u32 status, desc_num = priv->rx_currdescnum;
353 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
354 int length = -EAGAIN;
355 uint32_t desc_start = (uint32_t)desc_p;
356 uint32_t desc_end = desc_start +
357 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
358 uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
361 /* Invalidate entire buffer descriptor */
362 invalidate_dcache_range(desc_start, desc_end);
364 status = desc_p->txrx_status;
366 /* Check if the owner is the CPU */
367 if (!(status & DESC_RXSTS_OWNBYDMA)) {
369 length = (status & DESC_RXSTS_FRMLENMSK) >>
370 DESC_RXSTS_FRMLENSHFT;
372 /* Invalidate received data */
373 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
374 invalidate_dcache_range(data_start, data_end);
375 *packetp = desc_p->dmamac_addr;
381 static int _dw_free_pkt(struct dw_eth_dev *priv)
383 u32 desc_num = priv->rx_currdescnum;
384 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
385 uint32_t desc_start = (uint32_t)desc_p;
386 uint32_t desc_end = desc_start +
387 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
390 * Make the current descriptor valid again and go to
393 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
395 /* Flush only status field - others weren't changed */
396 flush_dcache_range(desc_start, desc_end);
398 /* Test the wrap-around condition. */
399 if (++desc_num >= CONFIG_RX_DESCR_NUM)
401 priv->rx_currdescnum = desc_num;
406 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
408 struct phy_device *phydev;
409 int mask = 0xffffffff, ret;
411 #ifdef CONFIG_PHY_ADDR
412 mask = 1 << CONFIG_PHY_ADDR;
415 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
419 phy_connect_dev(phydev, dev);
421 phydev->supported &= PHY_GBIT_FEATURES;
422 if (priv->max_speed) {
423 ret = phy_set_supported(phydev, priv->max_speed);
427 phydev->advertising = phydev->supported;
429 priv->phydev = phydev;
435 #ifndef CONFIG_DM_ETH
436 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
438 return _dw_eth_init(dev->priv, dev->enetaddr);
441 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
443 return _dw_eth_send(dev->priv, packet, length);
446 static int dw_eth_recv(struct eth_device *dev)
451 length = _dw_eth_recv(dev->priv, &packet);
452 if (length == -EAGAIN)
454 net_process_received_packet(packet, length);
456 _dw_free_pkt(dev->priv);
461 static void dw_eth_halt(struct eth_device *dev)
463 return _dw_eth_halt(dev->priv);
466 static int dw_write_hwaddr(struct eth_device *dev)
468 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
471 int designware_initialize(ulong base_addr, u32 interface)
473 struct eth_device *dev;
474 struct dw_eth_dev *priv;
476 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
481 * Since the priv structure contains the descriptors which need a strict
482 * buswidth alignment, memalign is used to allocate memory
484 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
485 sizeof(struct dw_eth_dev));
491 memset(dev, 0, sizeof(struct eth_device));
492 memset(priv, 0, sizeof(struct dw_eth_dev));
494 sprintf(dev->name, "dwmac.%lx", base_addr);
495 dev->iobase = (int)base_addr;
499 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
500 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
503 dev->init = dw_eth_init;
504 dev->send = dw_eth_send;
505 dev->recv = dw_eth_recv;
506 dev->halt = dw_eth_halt;
507 dev->write_hwaddr = dw_write_hwaddr;
511 priv->interface = interface;
513 dw_mdio_init(dev->name, priv->mac_regs_p);
514 priv->bus = miiphy_get_dev_by_name(dev->name);
516 return dw_phy_init(priv, dev);
521 static int designware_eth_start(struct udevice *dev)
523 struct eth_pdata *pdata = dev_get_platdata(dev);
525 return _dw_eth_init(dev->priv, pdata->enetaddr);
528 static int designware_eth_send(struct udevice *dev, void *packet, int length)
530 struct dw_eth_dev *priv = dev_get_priv(dev);
532 return _dw_eth_send(priv, packet, length);
535 static int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
537 struct dw_eth_dev *priv = dev_get_priv(dev);
539 return _dw_eth_recv(priv, packetp);
542 static int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
545 struct dw_eth_dev *priv = dev_get_priv(dev);
547 return _dw_free_pkt(priv);
550 static void designware_eth_stop(struct udevice *dev)
552 struct dw_eth_dev *priv = dev_get_priv(dev);
554 return _dw_eth_halt(priv);
557 static int designware_eth_write_hwaddr(struct udevice *dev)
559 struct eth_pdata *pdata = dev_get_platdata(dev);
560 struct dw_eth_dev *priv = dev_get_priv(dev);
562 return _dw_write_hwaddr(priv, pdata->enetaddr);
565 static int designware_eth_bind(struct udevice *dev)
568 static int num_cards;
571 /* Create a unique device name for PCI type devices */
572 if (device_is_on_pci_bus(dev)) {
573 sprintf(name, "eth_designware#%u", num_cards++);
574 device_set_name(dev, name);
581 static int designware_eth_probe(struct udevice *dev)
583 struct eth_pdata *pdata = dev_get_platdata(dev);
584 struct dw_eth_dev *priv = dev_get_priv(dev);
585 u32 iobase = pdata->iobase;
590 * If we are on PCI bus, either directly attached to a PCI root port,
591 * or via a PCI bridge, fill in platdata before we probe the hardware.
593 if (device_is_on_pci_bus(dev)) {
594 pci_dev_t bdf = dm_pci_get_bdf(dev);
596 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
597 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
598 iobase = pci_mem_to_phys(bdf, iobase);
600 pdata->iobase = iobase;
601 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
605 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
606 priv->mac_regs_p = (struct eth_mac_regs *)iobase;
607 priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET);
608 priv->interface = pdata->phy_interface;
609 priv->max_speed = pdata->max_speed;
611 dw_mdio_init(dev->name, priv->mac_regs_p);
612 priv->bus = miiphy_get_dev_by_name(dev->name);
614 ret = dw_phy_init(priv, dev);
615 debug("%s, ret=%d\n", __func__, ret);
620 static int designware_eth_remove(struct udevice *dev)
622 struct dw_eth_dev *priv = dev_get_priv(dev);
625 mdio_unregister(priv->bus);
626 mdio_free(priv->bus);
631 static const struct eth_ops designware_eth_ops = {
632 .start = designware_eth_start,
633 .send = designware_eth_send,
634 .recv = designware_eth_recv,
635 .free_pkt = designware_eth_free_pkt,
636 .stop = designware_eth_stop,
637 .write_hwaddr = designware_eth_write_hwaddr,
640 static int designware_eth_ofdata_to_platdata(struct udevice *dev)
642 struct eth_pdata *pdata = dev_get_platdata(dev);
643 const char *phy_mode;
646 pdata->iobase = dev_get_addr(dev);
647 pdata->phy_interface = -1;
648 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
650 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
651 if (pdata->phy_interface == -1) {
652 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
656 pdata->max_speed = 0;
657 cell = fdt_getprop(gd->fdt_blob, dev->of_offset, "max-speed", NULL);
659 pdata->max_speed = fdt32_to_cpu(*cell);
664 static const struct udevice_id designware_eth_ids[] = {
665 { .compatible = "allwinner,sun7i-a20-gmac" },
666 { .compatible = "altr,socfpga-stmmac" },
670 U_BOOT_DRIVER(eth_designware) = {
671 .name = "eth_designware",
673 .of_match = designware_eth_ids,
674 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
675 .bind = designware_eth_bind,
676 .probe = designware_eth_probe,
677 .remove = designware_eth_remove,
678 .ops = &designware_eth_ops,
679 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
680 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
681 .flags = DM_FLAG_ALLOC_PRIV_DMA,
684 static struct pci_device_id supported[] = {
685 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
689 U_BOOT_PCI_DEVICE(eth_designware, supported);